274 lines
6.9 KiB
C
274 lines
6.9 KiB
C
#include <grub/dl.h>
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#include <grub/cache.h>
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#include <grub/arm/system.h>
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#ifdef GRUB_MACHINE_UBOOT
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#include <grub/uboot/uboot.h>
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#include <grub/uboot/api_public.h>
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#include <grub/mm.h>
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#endif
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/* This is only about cache architecture. It doesn't imply
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the CPU architecture. */
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static enum
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{
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ARCH_UNKNOWN,
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ARCH_ARMV5_WRITE_THROUGH,
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ARCH_ARMV6,
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ARCH_ARMV6_UNIFIED,
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ARCH_ARMV7
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} type = ARCH_UNKNOWN;
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static int is_v6_mmu;
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static grub_uint32_t grub_arch_cache_dlinesz;
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static grub_uint32_t grub_arch_cache_ilinesz;
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static grub_uint32_t grub_arch_cache_max_linesz;
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/* Prototypes for asm functions. */
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void grub_arm_clean_dcache_range_armv6 (grub_addr_t start, grub_addr_t end,
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grub_addr_t dlinesz);
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void grub_arm_clean_dcache_range_armv7 (grub_addr_t start, grub_addr_t end,
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grub_addr_t dlinesz);
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void grub_arm_invalidate_icache_range_armv6 (grub_addr_t start, grub_addr_t end,
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grub_addr_t dlinesz);
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void grub_arm_invalidate_icache_range_armv7 (grub_addr_t start, grub_addr_t end,
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grub_addr_t dlinesz);
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void grub_arm_disable_caches_mmu_armv6 (void);
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void grub_arm_disable_caches_mmu_armv7 (void);
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grub_uint32_t grub_arm_main_id (void);
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grub_uint32_t grub_arm_cache_type (void);
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static void
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probe_caches (void)
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{
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grub_uint32_t main_id, cache_type;
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/* Read main ID Register */
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main_id = grub_arm_main_id ();
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switch ((main_id >> 16) & 0xf)
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{
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case 0x3:
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case 0x4:
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case 0x5:
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case 0x6:
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is_v6_mmu = 0;
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break;
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case 0x7:
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case 0xf:
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is_v6_mmu = 1;
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break;
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default:
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grub_fatal ("Unsupported ARM ID 0x%x", main_id);
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}
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/* Read Cache Type Register */
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cache_type = grub_arm_cache_type ();
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switch (cache_type >> 24)
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{
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case 0x00:
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case 0x01:
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grub_arch_cache_dlinesz = 8 << ((cache_type >> 12) & 3);
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grub_arch_cache_ilinesz = 8 << (cache_type & 3);
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type = ARCH_ARMV5_WRITE_THROUGH;
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break;
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case 0x04:
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case 0x0a:
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case 0x0c:
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case 0x0e:
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case 0x1c:
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grub_arch_cache_dlinesz = 8 << ((cache_type >> 12) & 3);
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grub_arch_cache_ilinesz = 8 << (cache_type & 3);
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type = ARCH_ARMV6_UNIFIED;
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break;
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case 0x05:
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case 0x0b:
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case 0x0d:
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case 0x0f:
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case 0x1d:
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grub_arch_cache_dlinesz = 8 << ((cache_type >> 12) & 3);
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grub_arch_cache_ilinesz = 8 << (cache_type & 3);
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type = ARCH_ARMV6;
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break;
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case 0x80 ... 0x8f:
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grub_arch_cache_dlinesz = 4 << ((cache_type >> 16) & 0xf);
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grub_arch_cache_ilinesz = 4 << (cache_type & 0xf);
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type = ARCH_ARMV7;
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break;
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default:
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grub_fatal ("Unsupported cache type 0x%x", cache_type);
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}
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if (grub_arch_cache_dlinesz > grub_arch_cache_ilinesz)
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grub_arch_cache_max_linesz = grub_arch_cache_dlinesz;
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else
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grub_arch_cache_max_linesz = grub_arch_cache_ilinesz;
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}
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#ifdef GRUB_MACHINE_UBOOT
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static void subdivide (grub_uint32_t *table, grub_uint32_t *subtable,
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grub_uint32_t addr)
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{
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grub_uint32_t j;
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addr = addr >> 20 << 20;
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table[addr >> 20] = (grub_addr_t) subtable | 1;
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for (j = 0; j < 256; j++)
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subtable[j] = addr | (j << 12)
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| (3 << 4) | (3 << 6) | (3 << 8) | (3 << 10)
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| (0 << 3) | (1 << 2) | 2;
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}
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void
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grub_arm_enable_caches_mmu (void)
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{
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grub_uint32_t *table;
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grub_uint32_t i;
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grub_uint32_t border_crossing = 0;
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grub_uint32_t *subtable;
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struct sys_info *si = grub_uboot_get_sys_info ();
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if (!si || (si->mr_no == 0))
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{
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grub_printf ("couldn't get memory map, not enabling caches");
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grub_errno = GRUB_ERR_NONE;
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return;
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}
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if (type == ARCH_UNKNOWN)
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probe_caches ();
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for (i = 0; (signed) i < si->mr_no; i++)
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{
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if (si->mr[i].start & ((1 << 20) - 1))
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border_crossing++;
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if ((si->mr[i].start + si->mr[i].size) & ((1 << 20) - 1))
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border_crossing++;
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}
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grub_printf ("%d crossers\n", border_crossing);
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table = grub_memalign (1 << 14, (1 << 14) + (border_crossing << 10));
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if (!table)
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{
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grub_printf ("couldn't allocate place for MMU table, not enabling caches");
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grub_errno = GRUB_ERR_NONE;
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return;
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}
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subtable = table + (1 << 12);
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/* Map all unknown as device. */
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for (i = 0; i < (1 << 12); i++)
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table[i] = (i << 20) | (3 << 10) | (0 << 3) | (1 << 2) | 2;
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/*
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Device: TEX= 0, C=0, B=1
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normal: TEX= 0, C=1, B=1
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AP = 3
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IMP = 0
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Domain = 0
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*/
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for (i = 0; (signed) i < si->mr_no; i++)
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{
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if (si->mr[i].start & ((1 << 20) - 1))
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{
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subdivide (table, subtable, si->mr[i].start);
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subtable += (1 << 8);
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}
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if ((si->mr[i].start + si->mr[i].size) & ((1 << 20) - 1))
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{
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subdivide (table, subtable, si->mr[i].start + si->mr[i].size);
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subtable += (1 << 8);
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}
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}
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for (i = 0; (signed) i < si->mr_no; i++)
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if ((si->mr[i].flags & MR_ATTR_MASK) == MR_ATTR_DRAM
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|| (si->mr[i].flags & MR_ATTR_MASK) == MR_ATTR_SRAM
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|| (si->mr[i].flags & MR_ATTR_MASK) == MR_ATTR_FLASH)
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{
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grub_uint32_t cur, end;
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cur = si->mr[i].start;
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end = si->mr[i].start + si->mr[i].size;
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while (cur < end)
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{
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grub_uint32_t *st;
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if ((table[cur >> 20] & 3) == 2)
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{
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cur = cur >> 20 << 20;
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table[cur >> 20] = cur | (3 << 10) | (1 << 3) | (1 << 2) | 2;
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cur += (1 << 20);
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continue;
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}
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cur = cur >> 12 << 12;
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st = (grub_uint32_t *) (table[cur >> 20] & ~0x3ff);
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st[(cur >> 12) & 0xff] = cur | (3 << 4) | (3 << 6)
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| (3 << 8) | (3 << 10)
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| (1 << 3) | (1 << 2) | 2;
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cur += (1 << 12);
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}
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}
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grub_printf ("MMU tables generated\n");
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if (is_v6_mmu)
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grub_arm_clear_mmu_v6 ();
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grub_printf ("enabling MMU\n");
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grub_arm_enable_mmu (table);
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grub_printf ("MMU enabled\n");
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}
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#endif
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void
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grub_arch_sync_caches (void *address, grub_size_t len)
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{
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grub_addr_t start = (grub_addr_t) address;
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grub_addr_t end = start + len;
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if (type == ARCH_UNKNOWN)
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probe_caches ();
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start = ALIGN_DOWN (start, grub_arch_cache_max_linesz);
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end = ALIGN_UP (end, grub_arch_cache_max_linesz);
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switch (type)
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{
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case ARCH_ARMV6:
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grub_arm_clean_dcache_range_armv6 (start, end, grub_arch_cache_dlinesz);
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grub_arm_invalidate_icache_range_armv6 (start, end,
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grub_arch_cache_ilinesz);
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break;
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case ARCH_ARMV7:
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grub_arm_clean_dcache_range_armv7 (start, end, grub_arch_cache_dlinesz);
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grub_arm_invalidate_icache_range_armv7 (start, end,
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grub_arch_cache_ilinesz);
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break;
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/* Nothing to do. */
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case ARCH_ARMV5_WRITE_THROUGH:
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case ARCH_ARMV6_UNIFIED:
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break;
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/* Pacify GCC. */
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case ARCH_UNKNOWN:
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break;
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}
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}
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void
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grub_arm_disable_caches_mmu (void)
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{
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if (type == ARCH_UNKNOWN)
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probe_caches ();
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switch (type)
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{
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case ARCH_ARMV5_WRITE_THROUGH:
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case ARCH_ARMV6_UNIFIED:
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case ARCH_ARMV6:
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grub_arm_disable_caches_mmu_armv6 ();
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break;
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case ARCH_ARMV7:
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grub_arm_disable_caches_mmu_armv7 ();
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break;
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/* Pacify GCC. */
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case ARCH_UNKNOWN:
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break;
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}
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}
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