631 lines
No EOL
19 KiB
ArmAsm
631 lines
No EOL
19 KiB
ArmAsm
/*
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* GRUB -- GRand Unified Bootloader
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* Copyright (C) 2000,2001,2002,2003,2004,2005,2007,2008,2009,2010 Free Software Foundation, Inc.
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*
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* GRUB is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* GRUB is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <grub/mips/yeeloong/serial.h>
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#include <grub/mips/yeeloong/pci.h>
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#include <grub/mips/loongson.h>
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#include <grub/pci.h>
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#include <grub/machine/serial.h>
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#include <grub/ns8250.h>
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#include <grub/cs5536.h>
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#include <grub/smbus.h>
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.set noreorder
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.set noat
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.set nomacro
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.global start,_start,__start
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start:
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_start:
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__start:
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bal serial_hw_init
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nop
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/* Find CS5536 controller. */
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/* $t4 chooses device in priority encoding. */
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/* Resulting value is kept in GRUB_MACHINE_PCI_CONF_CTRL_REG.
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This way we don't need to sacrifice a register for it. */
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/* We have only one bus (0). Function is 0. */
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lui $t0, %hi(GRUB_MACHINE_PCI_CONF_CTRL_REG_ADDR)
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lui $t1, %hi(GRUB_MACHINE_PCI_CONFSPACE)
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lui $t3, %hi(GRUB_CS5536_PCIID)
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addiu $t3, $t3, %lo(GRUB_CS5536_PCIID)
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ori $t4, $zero, 1
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lui $a0, %hi(no_cs5536)
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1:
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andi $t4, $t4, ((1 << GRUB_PCI_NUM_DEVICES) - 1)
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beql $t4, $zero, fatal
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addiu $a0, $a0, %lo(no_cs5536)
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sw $t4, %lo(GRUB_MACHINE_PCI_CONF_CTRL_REG_ADDR) ($t0)
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lw $t2, (%lo(GRUB_MACHINE_PCI_CONFSPACE) + GRUB_PCI_REG_PCI_ID) ($t1)
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bnel $t2, $t3, 1b
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sll $t4, $t4, 1
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bal message
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addiu $a0, $a0, %lo(cs5536_found)
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bal printhex
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move $a0, $t4
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/* Initialise SMBus controller. */
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/* Set GPIO LBAR. */
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lui $a0, %hi(GRUB_CS5536_MSR_GPIO_BAR)
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addiu $a0, $a0, %lo(GRUB_CS5536_MSR_GPIO_BAR)
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ori $a1, $zero, GRUB_CS5536_LBAR_GPIO
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/* Set mask to 0xf and enabled bit to 1. */
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bal wrmsr
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ori $a2, $zero, ((GRUB_CS5536_LBAR_MASK_MASK \
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| GRUB_CS5536_LBAR_ENABLE) >> 32)
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/* Set SMBUS LBAR. */
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lui $a0, %hi(GRUB_CS5536_MSR_SMB_BAR)
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addiu $a0, $a0, %lo(GRUB_CS5536_MSR_SMB_BAR)
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ori $a1, $zero, GRUB_CS5536_LBAR_SMBUS
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/* Set mask to 0xf and enabled bit to 1. */
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bal wrmsr
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ori $a2, $zero, ((GRUB_CS5536_LBAR_MASK_MASK \
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| GRUB_CS5536_LBAR_ENABLE) >> 32)
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lui $a0, %hi(smbus_enabled)
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bal message
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addiu $a0, $a0, %lo(smbus_enabled)
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/* Enable SMBus controller pins. */
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lui $t0, %hi(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_GPIO)
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ori $t1, $zero, GRUB_GPIO_SMBUS_PINS
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sw $t1, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_GPIO + GRUB_GPIO_REG_OUT_EN) ($t0)
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sw $t1, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_GPIO + GRUB_GPIO_REG_OUT_AUX1) ($t0)
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sw $t1, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_GPIO + GRUB_GPIO_REG_IN_EN) ($t0)
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sw $t1, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_GPIO + GRUB_GPIO_REG_IN_AUX1) ($t0)
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lui $t0, %hi(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS)
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/* Disable SMB. */
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sb $zero, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL2) ($t0)
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/* Disable interrupts. */
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sb $zero, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1) ($t0)
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/* Set as master. */
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sb $zero, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_ADDR) ($t0)
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/* Launch SMBus controller at slowest speed possible. */
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ori $t1, $zero, 0xff
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sb $t1, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL3) ($t0)
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sb $t1, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL2) ($t0)
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/* Yeeloong has only one memory slot. */
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/* Output first byte on serial for debugging. */
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ori $a1, $zero, GRUB_SMB_RAM_START_ADDR
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bal read_spd
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move $a0, $zero
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bal printhex
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move $a0, $v0
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bal read_spd
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ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_TYPE_ADDR
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ori $t0, $zero, GRUB_SMBUS_SPD_MEMORY_TYPE_DDR2
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lui $a0, %hi(unimplemented_memory_type)
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bne $t0, $v0, fatal
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addiu $a0, $a0, %lo(unimplemented_memory_type)
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/* And here is our goal: DDR2 controller initialisation. */
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lui $t0, %hi(GRUB_CPU_LOONGSON_CORECFG)
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ld $t1, %lo(GRUB_CPU_LOONGSON_CORECFG) ($t0)
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/* Use addiu for sign-extension. */
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addiu $t2, $zero, ~(GRUB_CPU_LOONGSON_CORECFG_DISABLE_DDR2_SPACE|GRUB_CPU_LOONGSON_CORECFG_BUFFER_CPU)
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and $t1, $t1, $t2
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sd $t1, %lo (GRUB_CPU_LOONGSON_CORECFG) ($t0)
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b continue
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. = start + GRUB_CPU_LOONGSON_FLASH_TLB_REFILL - GRUB_CPU_LOONGSON_FLASH_START
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tlb_refill:
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mfc0 $s1, GRUB_CPU_LOONGSON_COP0_EPC
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mfc0 $s2, GRUB_CPU_LOONGSON_COP0_BADVADDR
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move $s3, $ra
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lui $a0, %hi(epc)
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bal message
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addiu $a0, $a0, %lo(epc)
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bal printhex
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move $a0, $s1
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lui $a0, %hi(badvaddr)
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bal message
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addiu $a0, $a0, %lo(badvaddr)
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bal printhex
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move $a0, $s2
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lui $a0, %hi(return_msg)
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bal message
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addiu $a0, $a0, %lo(return_msg)
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bal printhex
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move $a0, $s3
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lui $a0, %hi(newline)
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bal message
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addiu $a0, $a0, %lo(newline)
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lui $a0, %hi(unhandled_tlb_refill)
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b fatal
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addiu $a0, $a0, %lo(unhandled_tlb_refill)
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. = start + GRUB_CPU_LOONGSON_FLASH_CACHE_ERROR - GRUB_CPU_LOONGSON_FLASH_START
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cache_error:
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lui $a0, %hi(unhandled_cache_error)
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b fatal
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addiu $a0, $a0, %lo(unhandled_cache_error)
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. = start + GRUB_CPU_LOONGSON_FLASH_OTHER_EXCEPTION - GRUB_CPU_LOONGSON_FLASH_START
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other_exception:
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mfc0 $s0, GRUB_CPU_LOONGSON_COP0_CAUSE
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mfc0 $s1, GRUB_CPU_LOONGSON_COP0_EPC
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mfc0 $s2, GRUB_CPU_LOONGSON_COP0_BADVADDR
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lui $a0, %hi(cause)
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bal message
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addiu $a0, $a0, %lo(cause)
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bal printhex
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move $a0, $s0
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lui $a0, %hi(epc)
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bal message
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addiu $a0, $a0, %lo(epc)
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bal printhex
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move $a0, $s1
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lui $a0, %hi(badvaddr)
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bal message
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addiu $a0, $a0, %lo(badvaddr)
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bal printhex
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move $a0, $s2
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lui $a0, %hi(newline)
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bal message
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addiu $a0, $a0, %lo(newline)
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lui $a0, %hi(unhandled_exception)
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b fatal
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addiu $a0, $a0, %lo(unhandled_exception)
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/* Same as similarly named C function but in asm since
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we need it early. */
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/* In: none. Out: none. Clobbered: $t0, $t1, $a0. */
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serial_hw_init:
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lui $t0, %hi (GRUB_MACHINE_SERIAL_PORT)
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/* Turn off the interrupt. */
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sb $zero, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_IER)($t0)
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/* Set DLAB. */
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ori $t1, $zero, UART_DLAB
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sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_LCR)($t0)
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/* Set the baud rate 115200. */
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ori $t1, $zero, GRUB_MACHINE_SERIAL_DIVISOR_115200
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sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_DLL)($t0)
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sb $zero, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_DLH)($t0)
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/* Set the line status. */
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ori $t1, $zero, (UART_NO_PARITY | UART_8BITS_WORD | UART_1_STOP_BIT)
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sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_LCR)($t0)
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/* Enable the FIFO. */
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ori $t1, $zero, UART_ENABLE_FIFO_TRIGGER1
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sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_FCR)($t0)
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/* Turn on DTR and RTS. */
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ori $t1, $zero, UART_ENABLE_DTRRTS
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sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_MCR)($t0)
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/* Let message return to original caller. */
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lui $a0, %hi(notification_string)
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addiu $a0, $a0, %lo(notification_string)
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/* Print message on serial console. */
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/* In: $a0 = asciiz message. Out: none. Clobbered: $t0, $t1, $a0. */
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message:
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lui $t0, %hi (GRUB_MACHINE_SERIAL_PORT)
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1:
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lb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_LSR)($t0)
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andi $t1, $t1, UART_EMPTY_TRANSMITTER
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beq $t1, $zero, 1b
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nop
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lb $t1, 0($a0)
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sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_TX)($t0)
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bne $t1, $zero, 1b
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addiu $a0, $a0, 1
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jr $ra
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nop
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/* Print 32-bit hexadecimal on serial.
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In: $a0. Out: None. Clobbered: $a0, $t0, $t1, $t2
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*/
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printhex:
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lui $t0, %hi (GRUB_MACHINE_SERIAL_PORT)
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ori $t2, $zero, 8
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1:
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lb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_LSR)($t0)
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andi $t1, $t1, UART_EMPTY_TRANSMITTER
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beq $t1, $zero, 1b
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nop
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srl $t1, $a0, 28
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addiu $t1, $t1, -10
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blt $t1, $zero, 2f
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sll $a0, $a0, 4
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addiu $t1, $t1, 'A'-10-'0'
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2: addiu $t1, $t1, '0'+10
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sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_TX)($t0)
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addiu $t2, $t2, -1
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bne $t2, $zero, 1b
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nop
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jr $ra
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nop
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fatal:
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bal message
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nop
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self:
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b self
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nop
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/* Write CS5536 MSR.
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In: $a0 address, $a1 lower word, $a2 upper word.
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Out: None
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Clobbered: $t0
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*/
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wrmsr:
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lui $t0, %hi(GRUB_MACHINE_PCI_CONFSPACE)
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sw $a0, (%lo(GRUB_MACHINE_PCI_CONFSPACE) + GRUB_CS5536_MSR_MAILBOX_ADDR) ($t0)
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sw $a1, (%lo(GRUB_MACHINE_PCI_CONFSPACE) + GRUB_CS5536_MSR_MAILBOX_DATA0) ($t0)
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jr $ra
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sw $a2, (%lo(GRUB_MACHINE_PCI_CONFSPACE) + GRUB_CS5536_MSR_MAILBOX_DATA1) ($t0)
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/* Wait for SMBus data or empty transmitter. */
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/* In: $a0 = exception handler. Out: none. Clobbered: $t0, $t1 */
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smbus_wait:
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1:
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lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_STATUS + GRUB_MACHINE_PCI_IO_BASE)
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lb $t0, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_STATUS + GRUB_MACHINE_PCI_IO_BASE) ($t0)
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andi $t1, $t0, GRUB_CS5536_SMB_REG_STATUS_SDAST
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bne $t1, $zero, return
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nop
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andi $t1, $t0, (GRUB_CS5536_SMB_REG_STATUS_BER | GRUB_CS5536_SMB_REG_STATUS_NACK)
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beq $t1, $zero, 1b
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nop
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jr $a0
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nop
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return:
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jr $ra
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nop
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/* Read SPD byte. In: $a0 byte, $a1 device. Out: $v0 read byte (0x100 on failure).
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Clobbered: $t0, $t1, $t2, $t3, $a0. */
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read_spd:
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move $t2, $a0
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move $t3, $ra
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lui $a0, %hi(read_spd_fail)
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addiu $a0, $a0, %hi(read_spd_fail)
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/* Send START. */
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lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE)
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lb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
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ori $t1, $t1, GRUB_CS5536_SMB_REG_CTRL1_START
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bal smbus_wait
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sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
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/* Send device address. */
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lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE)
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sll $t1, $a1, 1
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bal smbus_wait
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sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE) ($t0)
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/* Send ACK. */
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lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE)
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lb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
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ori $t1, $t1, GRUB_CS5536_SMB_REG_CTRL1_ACK
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sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
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/* Send byte address. */
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lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE)
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bal smbus_wait
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sb $t2, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE) ($t0)
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/* Send START. */
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lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE)
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lb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
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ori $t1, $t1, GRUB_CS5536_SMB_REG_CTRL1_START
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bal smbus_wait
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sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
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/* Send device address. */
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lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE)
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sll $t1, $a1, 1
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ori $t1, $t1, 1
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bal smbus_wait
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sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE) ($t0)
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/* Send STOP. */
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lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE)
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lb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
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ori $t1, $t1, GRUB_CS5536_SMB_REG_CTRL1_STOP
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bal smbus_wait
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sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
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lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE)
|
|
lb $v0, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE) ($t0)
|
|
jr $t3
|
|
andi $v0, $v0, 0xff
|
|
read_spd_fail:
|
|
jr $t3
|
|
ori $v0, $v0, 0x100
|
|
|
|
notification_string: .asciz "GRUB "
|
|
no_cs5536: .asciz "No CS5536 found.\n\r"
|
|
cs5536_found: .asciz "CS5536 at "
|
|
sm_failed: .asciz "SM transaction failed.\n\r"
|
|
unhandled_tlb_refill: .asciz "Unhandled TLB refill.\n\r"
|
|
unhandled_cache_error: .asciz "Unhandled cache error.\n\r"
|
|
unhandled_exception: .asciz "Unhandled exception.\n\r"
|
|
smbus_enabled: .asciz "SMBus controller enabled.\n\r"
|
|
unimplemented_memory_type: .asciz "non-DDR2 memory isn't supported.\n\r"
|
|
no_cas_latency: .asciz "Couldn't determine CAS latency.\n\r"
|
|
cause: .asciz "Cause: "
|
|
epc: .asciz "\n\rEPC: "
|
|
badvaddr: .asciz "\n\rBadVaddr: "
|
|
newline: .asciz "\n\r"
|
|
return_msg: .asciz "\n\rReturn address: "
|
|
caches_enabled: .asciz "Caches enabled\n\r"
|
|
|
|
.p2align 3
|
|
|
|
regdump:
|
|
.quad 0x0100010000000101 /* 0 */
|
|
.quad 0x0100010100000000 /* 2 */
|
|
.quad 0x0101000001000000 /* 3 */
|
|
.quad 0x0100020200010101 /* 4 */
|
|
.quad 0x0a04030603050203 /* 6 */
|
|
.quad 0x0f0e040000010a0b /* 7 */
|
|
.quad 0x0000010200000102 /* 8 */
|
|
.quad 0x0000060c00000000 /* 9 */
|
|
.quad 0x2323233f3f1f0200 /* a */
|
|
.quad 0x5f7f232323232323 /* b */
|
|
.quad 0x002a3c0615000000 /* c */
|
|
.quad 0x002a002a002a002a /* d */
|
|
.quad 0x002a002a002a002a /* e */
|
|
.quad 0x00b40020006d0004 /* f */
|
|
.quad 0x070007ff00000087 /* 10 */
|
|
.quad 0x000000000016101f /* 11 */
|
|
.quad 0x001c000000000000 /* 12 */
|
|
.quad 0x28e1000200c8006b /* 13 */
|
|
.quad 0x0000204200c8002f /* 14 */
|
|
.quad 0x0000000000030d40 /* 15 */
|
|
.quad 0 /* 16 */
|
|
.quad 0 /* 17 */
|
|
.quad 0 /* 18 */
|
|
.quad 0 /* 19 */
|
|
.quad 0 /* 1a */
|
|
.quad 0 /* 1b */
|
|
.quad 0 /* 1c */
|
|
|
|
.p2align
|
|
|
|
write_dumpreg:
|
|
ld $t2, 0($t6)
|
|
sd $t2, 0($t4)
|
|
addiu $t4, $t4, GRUB_CPU_LOONGSON_DDR2_REG_STEP
|
|
jr $ra
|
|
addiu $t6, $t6, GRUB_CPU_LOONGSON_DDR2_REG_SIZE
|
|
|
|
continue:
|
|
lui $t4, %hi(GRUB_CPU_LOONGSON_DDR2_BASE)
|
|
addiu $t4, $t4, %lo(GRUB_CPU_LOONGSON_DDR2_BASE)
|
|
lui $t6, %hi(regdump)
|
|
|
|
/* 0 */
|
|
bal write_dumpreg
|
|
addiu $t6, $t6, %lo(regdump)
|
|
|
|
/* 1 */
|
|
ori $a1, $a1, GRUB_SMB_RAM_START_ADDR
|
|
move $t8, $zero
|
|
lui $t5, 0x0001
|
|
bal read_spd
|
|
ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_NUM_BANKS_ADDR
|
|
ori $t7, $zero, 8
|
|
bne $v0, $t7, 1f
|
|
ori $t5, $t5, 0x0001
|
|
ori $t8, $t8, GRUB_CPU_LOONGSON_DDR2_REG1_HI_8BANKS
|
|
1:
|
|
dsll $t8, $t8, 32
|
|
or $t5, $t5, $t8
|
|
sd $t5, 0 ($t4)
|
|
addiu $t4, $t4, GRUB_CPU_LOONGSON_DDR2_REG_STEP
|
|
|
|
/* 2 */
|
|
bal write_dumpreg
|
|
nop
|
|
|
|
/* 3 */
|
|
bal write_dumpreg
|
|
nop
|
|
|
|
/* 4 */
|
|
bal write_dumpreg
|
|
nop
|
|
|
|
/* 5 */
|
|
/* FIXME: figure termination resistance. */
|
|
ori $t5, $zero, 0x2
|
|
bal read_spd
|
|
ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_NUM_ROWS_ADDR
|
|
/* $v0 = 15 - $v0. */
|
|
xori $v0, $v0, 0xf
|
|
andi $v0, $v0, 0x7
|
|
sll $v0, $v0, 8
|
|
or $t5, $t5, $v0
|
|
|
|
/* Find the fastest supported CAS latency. */
|
|
bal read_spd
|
|
ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_CAS_LATENCY_ADDR
|
|
ori $t0, $zero, GRUB_SMBUS_SPD_MEMORY_CAS_LATENCY_MIN_VALUE
|
|
ori $t1, $zero, (1 << GRUB_SMBUS_SPD_MEMORY_CAS_LATENCY_MIN_VALUE)
|
|
2:
|
|
and $t2, $t1, $v0
|
|
bne $t2, $zero, 1f
|
|
ori $t3, $zero, 8
|
|
lui $a0, %hi(no_cas_latency)
|
|
beq $t0, $t3, fatal
|
|
addiu $a0, $a0, %lo(no_cas_latency)
|
|
addiu $t0, $t0, 1
|
|
b 2b
|
|
sll $t1, $t1, 1
|
|
1:
|
|
sll $t0, $t0, 16
|
|
or $t5, $t5, $t0
|
|
|
|
bal read_spd
|
|
ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_NUM_COLUMNS_ADDR
|
|
/* $v0 = 15 - ($v0 + 1) = 14 - $v0. */
|
|
addiu $v0, $v0, 1
|
|
xori $v0, $v0, 0xf
|
|
andi $v0, $v0, 0x7
|
|
sll $v0, 24
|
|
or $t5, $t5, $v0
|
|
sd $t5, 0 ($t4)
|
|
|
|
addiu $t4, $t4, GRUB_CPU_LOONGSON_DDR2_REG_STEP
|
|
|
|
ori $t7, $zero, 0x16
|
|
|
|
1:
|
|
ld $t2, 0($t6)
|
|
sd $t2, 0($t4)
|
|
addiu $t4, $t4, GRUB_CPU_LOONGSON_DDR2_REG_STEP
|
|
addiu $t7, $t7, -1
|
|
bne $t7, $zero, 1b
|
|
addiu $t6, $t6, GRUB_CPU_LOONGSON_DDR2_REG_SIZE
|
|
|
|
lui $t4, %hi(GRUB_CPU_LOONGSON_DDR2_BASE)
|
|
ld $t5, (%lo(GRUB_CPU_LOONGSON_DDR2_BASE) + 0x30) ($t4)
|
|
ori $t0, $zero, 1
|
|
dsll $t0, $t0, 40
|
|
or $t5, $t5, $t0
|
|
sd $t5, (%lo(GRUB_CPU_LOONGSON_DDR2_BASE) + 0x30) ($t4)
|
|
|
|
/* Desactivate DDR2 registers. */
|
|
lui $t0, %hi (GRUB_CPU_LOONGSON_CORECFG)
|
|
ld $t1, %lo (GRUB_CPU_LOONGSON_CORECFG) ($t0)
|
|
ori $t1, $t1, GRUB_CPU_LOONGSON_CORECFG_DISABLE_DDR2_SPACE
|
|
sd $t1, %lo (GRUB_CPU_LOONGSON_CORECFG) ($t0)
|
|
|
|
/* Enable cache. */
|
|
mfc0 $t0, GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG
|
|
addiu $t1, $zero, ~GRUB_CPU_LOONGSON_CACHE_TYPE_MASK
|
|
and $t0, $t1, $t1
|
|
/* Set line size to 32 bytes and disabled cache. */
|
|
ori $t0, $t0, (GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG_ILINESIZE \
|
|
| GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG_DLINESIZE \
|
|
| GRUB_CPU_LOONGSON_CACHE_ACCELERATED)
|
|
mtc0 $t0, GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG
|
|
|
|
/* Invalidate all I-cache entries. */
|
|
srl $t1, $t0, GRUB_CPU_LOONGSON_COP0_CACHE_ISIZE_SHIFT
|
|
andi $t1, $t1, GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_MASK
|
|
ori $t2, $zero, (1 << (GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_OFFSET \
|
|
- GRUB_CPU_LOONGSON_CACHE_LINE_SIZE_LOG_BIG \
|
|
- GRUB_CPU_LOONGSON_I_CACHE_LOG_WAYS))
|
|
sll $t1, $t2, $t1
|
|
lui $t2, 0x8000
|
|
|
|
1:
|
|
cache GRUB_CPU_LOONGSON_COP0_I_INDEX_INVALIDATE, 0($t2)
|
|
addiu $t1, $t1, -1
|
|
bne $t1, $zero, 1b
|
|
addiu $t2, $t2, (1 << GRUB_CPU_LOONGSON_COP0_I_INDEX_BIT_OFFSET)
|
|
|
|
/* Invalidate all D-cache entries. */
|
|
srl $t1, $t0, GRUB_CPU_LOONGSON_COP0_CACHE_DSIZE_SHIFT
|
|
andi $t1, $t1, GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_MASK
|
|
ori $t2, $zero, (1 << (GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_OFFSET \
|
|
- GRUB_CPU_LOONGSON_CACHE_LINE_SIZE_LOG_BIG \
|
|
- GRUB_CPU_LOONGSON_D_CACHE_LOG_WAYS))
|
|
sll $t1, $t2, $t1
|
|
lui $t2, 0x8000
|
|
mtc0 $zero, GRUB_CPU_LOONGSON_COP0_CACHE_TAGLO
|
|
mtc0 $zero, GRUB_CPU_LOONGSON_COP0_CACHE_TAGHI
|
|
1:
|
|
/* All four ways. */
|
|
cache GRUB_CPU_LOONGSON_COP0_D_INDEX_TAG_STORE, 0($t2)
|
|
cache GRUB_CPU_LOONGSON_COP0_D_INDEX_TAG_STORE, 1($t2)
|
|
cache GRUB_CPU_LOONGSON_COP0_D_INDEX_TAG_STORE, 2($t2)
|
|
cache GRUB_CPU_LOONGSON_COP0_D_INDEX_TAG_STORE, 3($t2)
|
|
addiu $t1, $t1, -1
|
|
bne $t1, $zero, 1b
|
|
addiu $t2, $t2, (1 << GRUB_CPU_LOONGSON_COP0_D_INDEX_BIT_OFFSET)
|
|
|
|
/* Invalidate all S-cache entries. */
|
|
ori $t1, $zero, (1 << (GRUB_CPU_LOONGSON_SECONDARY_CACHE_LOG_SIZE \
|
|
- GRUB_CPU_LOONGSON_CACHE_LINE_SIZE_LOG_BIG \
|
|
- GRUB_CPU_LOONGSON_S_CACHE_LOG_WAYS))
|
|
lui $t2, 0x8000
|
|
mtc0 $zero, GRUB_CPU_LOONGSON_COP0_CACHE_TAGLO
|
|
mtc0 $zero, GRUB_CPU_LOONGSON_COP0_CACHE_TAGHI
|
|
1:
|
|
/* All four ways. */
|
|
cache GRUB_CPU_LOONGSON_COP0_S_INDEX_TAG_STORE, 0($t2)
|
|
cache GRUB_CPU_LOONGSON_COP0_S_INDEX_TAG_STORE, 1($t2)
|
|
cache GRUB_CPU_LOONGSON_COP0_S_INDEX_TAG_STORE, 2($t2)
|
|
cache GRUB_CPU_LOONGSON_COP0_S_INDEX_TAG_STORE, 3($t2)
|
|
addiu $t1, $t1, -1
|
|
bne $t1, $zero, 1b
|
|
addiu $t2, $t2, (1 << GRUB_CPU_LOONGSON_COP0_D_INDEX_BIT_OFFSET)
|
|
|
|
/* Finally enable cache. */
|
|
mfc0 $t0, GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG
|
|
addiu $t1, $zero, ~GRUB_CPU_LOONGSON_CACHE_TYPE_MASK
|
|
and $t0, $t1, $t1
|
|
ori $t0, $t0, GRUB_CPU_LOONGSON_CACHE_CACHED
|
|
mtc0 $t0, GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG
|
|
|
|
lui $a0, %hi(caches_enabled)
|
|
bal message
|
|
addiu $a0, $a0, %lo(caches_enabled)
|
|
|
|
/* Set ROM delay cycles to 1. */
|
|
lui $t0, %hi(GRUB_CPU_LOONGSON_LIOCFG)
|
|
lw $t1, %lo(GRUB_CPU_LOONGSON_LIOCFG) ($t0)
|
|
addiu $t2, $zero, ~(GRUB_CPU_LOONGSON_ROM_DELAY_MASK \
|
|
<< GRUB_CPU_LOONGSON_ROM_DELAY_OFFSET)
|
|
and $t1, $t1, $t2
|
|
ori $t1, $t1, (1 << GRUB_CPU_LOONGSON_ROM_DELAY_OFFSET)
|
|
sw $t1, %lo(GRUB_CPU_LOONGSON_LIOCFG) ($t0)
|
|
|
|
addiu $a0, $zero, -1
|
|
addiu $a1, $zero, -1
|
|
|
|
/* Take advantage of cache. */
|
|
lui $t0, %hi(cached_continue - 0x20000000)
|
|
addiu $t0, $t0, %lo(cached_continue - 0x20000000)
|
|
jr $t0
|
|
addiu $a2, $zero, -1
|
|
|
|
cached_continue: |