138 lines
No EOL
3 KiB
ArmAsm
138 lines
No EOL
3 KiB
ArmAsm
/*
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* GRUB -- GRand Unified Bootloader
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* Copyright (C) 2013 Free Software Foundation, Inc.
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*
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* GRUB is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* GRUB is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <grub/symbol.h>
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.file "cache_armv7.S"
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.text
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.syntax unified
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#if !defined (__thumb2__)
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.arch armv7a
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.arm
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#else
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.arch armv7
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.thumb
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#endif
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# define DMB dmb
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# define DSB dsb
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# define ISB isb
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#define ARMV7 1
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FUNCTION(grub_arm_clean_dcache_range_poc_armv7)
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DSB
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@ Clean data cache for range to point-of-coherence
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1: cmp r0, r1
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bge 2f
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mcr p15, 0, r0, c7, c14, 1 @ DCCMVAC
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add r0, r0, r2 @ Next line
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b 1b
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2: DSB
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bx lr
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@ r0 - CLIDR
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@ r1 - LoC
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@ r2 - current level
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@ r3 - num sets
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@ r4 - num ways
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@ r5 - current set
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@ r6 - current way
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@ r7 - line size
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@ r8 - scratch
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@ r9 - scratch
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@ r10 - scratch
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@ r11 - scratch
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clean_invalidate_dcache:
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push {r4-r12, lr}
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mrc p15, 1, r0, c0, c0, 1 @ Read CLIDR
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lsr r1, r0, #24 @ Extract LoC
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and r1, r1, #0x7
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mov r2, #0 @ First level, L1
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2: and r8, r0, #7 @ cache type at current level
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cmp r8, #2
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blt 5f @ instruction only, or none, skip level
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@ set current cache level/type (for CCSIDR read)
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lsl r8, r2, #1
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mcr p15, 2, r8, c0, c0, 0 @ Write CSSELR (level, type: data/uni)
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@ read current cache information
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mrc p15, 1, r8, c0, c0, 0 @ Read CCSIDR
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lsr r3, r8, #13 @ Number of sets -1
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@ Keep only 14 bits of r3
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lsl r3, r3, #18
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lsr r3, r3, #18
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lsr r4, r8, #3 @ Number of ways -1
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@ Keep only 9 bits of r4
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lsl r4, r4, #23
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lsr r4, r4, #23
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and r7, r8, #7 @ log2(line size in words) - 2
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add r7, r7, #2 @ adjust
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mov r8, #1
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lsl r7, r8, r7 @ -> line size in words
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lsl r7, r7, #2 @ -> bytes
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@ set loop
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mov r5, #0 @ current set = 0
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3: lsl r8, r2, #1 @ insert level
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clz r9, r7 @ calculate set field offset
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mov r10, #31
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sub r9, r10, r9
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lsl r10, r5, r9
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orr r8, r8, r10 @ insert set field
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@ way loop
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@ calculate way field offset
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mov r6, #0 @ current way = 0
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add r10, r4, #1
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clz r9, r10 @ r9 = way field offset
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add r9, r9, #1
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4: lsl r10, r6, r9
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orr r11, r8, r10 @ insert way field
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@ clean and invalidate line by set/way
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mcr p15, 0, r11, c7, c14, 2 @ DCCISW
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@ next way
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add r6, r6, #1
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cmp r6, r4
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ble 4b
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@ next set
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add r5, r5, #1
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cmp r5, r3
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ble 3b
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@ next level
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5: lsr r0, r0, #3 @ align next level CLIDR 'type' field
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add r2, r2, #1 @ increment cache level counter
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cmp r2, r1
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blt 2b @ outer loop
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@ return
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6: DSB
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ISB
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pop {r4-r12, lr}
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bx lr
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#include "cache.S" |