0d8f04cd83
when rest of GRUB is compiled for hisher stepping. Instead use .set mips3/.set mips1 around cache and sync opcodes.
54 lines
883 B
ArmAsm
54 lines
883 B
ArmAsm
#ifndef CACHE_OP_DEFINED
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#define CACHE_OP_DEFINED 1
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.macro cache_op op addr
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.set mips3
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cache \op, \addr
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.set mips1
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.endm
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.macro sync_op
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.set mips3
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sync
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.set mips1
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.endm
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#endif
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move $t2, $a0
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addu $t3, $a0, $a1
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srl $t2, $t2, 5
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sll $t2, $t2, 5
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addu $t3, $t3, 0x1f
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srl $t3, $t3, 5
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sll $t3, $t3, 5
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move $t0, $t2
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subu $t1, $t3, $t2
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1:
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cache_op 1, 0($t0)
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/* All four ways. */
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#ifdef GRUB_MACHINE_MIPS_LOONGSON
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cache_op 1, 1($t0)
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cache_op 1, 2($t0)
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cache_op 1, 3($t0)
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addiu $t1, $t1, -0x20
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bne $t1, $zero, 1b
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addiu $t0, $t0, 0x20
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#else
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addiu $t1, $t1, -0x4
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bne $t1, $zero, 1b
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addiu $t0, $t0, 0x4
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#endif
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sync_op
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move $t0, $t2
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subu $t1, $t3, $t2
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2:
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cache_op 0, 0($t0)
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#ifdef GRUB_MACHINE_MIPS_LOONGSON
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addiu $t1, $t1, -0x20
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bne $t1, $zero, 2b
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addiu $t0, $t0, 0x20
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#else
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addiu $t1, $t1, -0x4
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bne $t1, $zero, 2b
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addiu $t0, $t0, 0x4
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#endif
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sync_op
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