115 lines
3.9 KiB
Text
115 lines
3.9 KiB
Text
Copyright 2001 Free Software Foundation, Inc.
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This file is part of the GNU MP Library.
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The GNU MP Library is free software; you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation; either version 2.1 of the License, or (at your
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option) any later version.
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The GNU MP Library is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with the GNU MP Library; see the file COPYING.LIB. If not, write to
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the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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02110-1301, USA.
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INTEL PENTIUM-4 MPN SUBROUTINES
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This directory contains mpn functions optimized for Intel Pentium-4.
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The mmx subdirectory has routines using MMX instructions, the sse2
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subdirectory has routines using SSE2 instructions. All P4s have these, the
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separate directories are just so configure can omit that code if the
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assembler doesn't support it.
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STATUS
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cycles/limb
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mpn_add_n/sub_n 4 normal, 6 in-place
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mpn_mul_1 4 normal, 6 in-place
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mpn_addmul_1 6
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mpn_submul_1 7
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mpn_mul_basecase 6 cycles/crossproduct (approx)
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mpn_sqr_basecase 3.5 cycles/crossproduct (approx)
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or 7.0 cycles/triangleproduct (approx)
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mpn_l/rshift 1.75
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The shifts ought to be able to go at 1.5 c/l, but not much effort has been
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applied to them yet.
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In-place operations, and all addmul, submul, mul_basecase and sqr_basecase
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calls, suffer from pipeline anomalies associated with write combining and
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movd reads and writes to the same or nearby locations. The movq
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instructions do not trigger the same hardware problems. Unfortunately,
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using movq and splitting/combining seems to require too many extra
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instructions to help. Perhaps future chip steppings will be better.
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NOTES
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The Pentium-4 pipeline "Netburst", provides for quite a number of surprises.
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Many traditional x86 instructions run very slowly, requiring use of
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alterative instructions for acceptable performance.
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adcl and sbbl are quite slow at 8 cycles for reg->reg. paddq of 32-bits
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within a 64-bit mmx register seems better, though the combination
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paddq/psrlq when propagating a carry is still a 4 cycle latency.
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incl and decl should be avoided, instead use add $1 and sub $1. Apparently
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the carry flag is not separately renamed, so incl and decl depend on all
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previous flags-setting instructions.
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shll and shrl have a 4 cycle latency, or 8 times the latency of the fastest
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integer instructions (addl, subl, orl, andl, and some more). shldl and
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shrdl seem to have 13 and 15 cycles latency, respectively. Bizarre.
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movq mmx -> mmx does have 6 cycle latency, as noted in the documentation.
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pxor/por or similar combination at 2 cycles latency can be used instead.
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The movq however executes in the float unit, thereby saving MMX execution
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resources. With the right juggling, data moves shouldn't be on a dependent
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chain.
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L1 is write-through, but the write-combining sounds like it does enough to
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not require explicit destination prefetching.
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xmm registers so far haven't found a use, but not much effort has been
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expended. A configure test for whether the operating system knows
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fxsave/fxrestor will be needed if they're used.
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REFERENCES
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Intel Pentium-4 processor manuals,
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http://developer.intel.com/design/pentium4/manuals
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"Intel Pentium 4 Processor Optimization Reference Manual", Intel, 2001,
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order number 248966. Available on-line:
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http://developer.intel.com/design/pentium4/manuals/248966.htm
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----------------
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Local variables:
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mode: text
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fill-column: 76
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End:
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