IQ4_XS: a 4.25 bpw quantization (#5747)
* Try IQ4_NL with blocks of 64 - does not look good * iq4_xs: go to super-blocks of 256 and 6-bit scales for blocks of 32 * iq4_xs: CUDA works - 133.2 t/s * iq4_xs: AVX2 dot product * iq4_xs: ARM_NEON dot product * iq4_nl: Metal implementation As usual, Metal / Apple Silicon don't like my quants. * iq3_xs: minor fix * iq4_xs: shrink by using IQ3_S for attn_k and attn_q * iq4_xs: revert using IQ3_S for attn_k and attn_v PPL vs size is good, but CPU performance suffers: on M2 Max TG-128 drops to 21.7 t/s from 28.8, and on a Ryzen-7950X to 14.5 t/s from 15.8 t/s. On CUDA we have 135 t/s when using IQ3_S vs 133 t/s with pure IQ4_XS. * Fix CI * iq4_xs: Added forgotten check for 256 divisibility --------- Co-authored-by: Iwan Kawrakow <iwan.kawrakow@gmail.com>
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11 changed files with 668 additions and 38 deletions
224
ggml-metal.metal
224
ggml-metal.metal
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@ -2560,6 +2560,13 @@ typedef struct {
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uint8_t qs[QK4_NL/2];
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} block_iq4_nl;
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typedef struct {
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half d;
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uint16_t scales_h;
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uint8_t scales_l[QK_K/64];
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uint8_t qs[QK_K/2];
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} block_iq4_xs;
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//====================================== dot products =========================
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void kernel_mul_mv_q2_K_f32_impl(
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@ -5160,6 +5167,100 @@ void kernel_mul_mv_iq4_nl_f32_impl(
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}
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}
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void kernel_mul_mv_iq4_xs_f32_impl(
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device const void * src0,
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device const float * src1,
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device float * dst,
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constant int64_t & ne00,
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constant int64_t & ne01,
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constant int64_t & ne02,
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constant int64_t & ne10,
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constant int64_t & ne12,
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constant int64_t & ne0,
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constant int64_t & ne1,
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constant uint & r2,
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constant uint & r3,
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threadgroup float * shared_values [[threadgroup(0)]],
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uint3 tgpig[[threadgroup_position_in_grid]],
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uint tiisg[[thread_index_in_simdgroup]],
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uint sgitg[[simdgroup_index_in_threadgroup]]) {
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const int nb = ne00/QK_K;
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const int r0 = tgpig.x;
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const int r1 = tgpig.y;
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const int im = tgpig.z;
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const int first_row = (r0 * 2 + sgitg) * 2;
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const int ib_row = first_row * nb;
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const uint i12 = im%ne12;
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const uint i13 = im/ne12;
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const uint offset0 = (i12/r2)*(nb*ne01) + (i13/r3)*(nb*ne01*ne02);
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device const block_iq4_xs * x = (device const block_iq4_xs *) src0 + ib_row + offset0;
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device const float * y = (device const float *) src1 + r1*ne10 + im*ne00*ne1;
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const int ix = tiisg/16; // 0 or 1
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const int it = tiisg%16; // 0...15
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const int ib = it/2;
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const int il = it%2;
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shared_values[tiisg] = kvalues_iq4nl_f[tiisg%16];
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threadgroup_barrier(mem_flags::mem_threadgroup);
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float4 yl[4];
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float sumf[2]={0.f}, all_sum;
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device const float * yb = y + ix * QK_K + ib * 32 + il * 8;
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uint32_t aux32[2];
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thread const uint8_t * q8 = (thread const uint8_t *)aux32;
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float4 qf1, qf2;
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for (int ibl = ix; ibl < nb; ibl += 2) {
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device const float4 * y4 = (device const float4 *)yb;
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yl[0] = y4[0]; yl[1] = y4[4]; yl[2] = y4[1]; yl[3] = y4[5];
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for (int row = 0; row < 2; ++row) {
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device const block_iq4_xs & xb = x[row*nb + ibl];
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device const uint32_t * q4 = (device const uint32_t *)(xb.qs + 16*ib + 8*il);
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float4 acc1 = {0.f}, acc2 = {0.f};
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aux32[0] = q4[0] & 0x0f0f0f0f;
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aux32[1] = (q4[0] >> 4) & 0x0f0f0f0f;
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qf1 = {shared_values[q8[0]], shared_values[q8[1]], shared_values[q8[2]], shared_values[q8[3]]};
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qf2 = {shared_values[q8[4]], shared_values[q8[5]], shared_values[q8[6]], shared_values[q8[7]]};
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acc1 += yl[0] * qf1;
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acc2 += yl[1] * qf2;
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aux32[0] = q4[1] & 0x0f0f0f0f;
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aux32[1] = (q4[1] >> 4) & 0x0f0f0f0f;
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qf1 = {shared_values[q8[0]], shared_values[q8[1]], shared_values[q8[2]], shared_values[q8[3]]};
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qf2 = {shared_values[q8[4]], shared_values[q8[5]], shared_values[q8[6]], shared_values[q8[7]]};
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acc1 += yl[2] * qf1;
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acc2 += yl[3] * qf2;
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acc1 += acc2;
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const int ls = (((xb.scales_l[ib/2] >> 4*(ib%2)) & 0xf) | (((xb.scales_h >> 2*ib) & 3) << 4)) - 32;
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sumf[row] += (float)xb.d * ls * (acc1[0] + acc1[1] + acc1[2] + acc1[3]);
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}
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yb += 2 * QK_K;
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}
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for (int row = 0; row < 2; ++row) {
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all_sum = simd_sum(sumf[row]);
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if (tiisg == 0) {
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dst[r1*ne0 + im*ne0*ne1 + first_row + row] = all_sum;
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}
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}
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}
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[[host_name("kernel_mul_mv_iq1_s_f32")]]
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kernel void kernel_mul_mv_iq1_s_f32(
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device const void * src0,
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@ -5217,6 +5318,35 @@ kernel void kernel_mul_mv_iq4_nl_f32(
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kernel_mul_mv_iq4_nl_f32_impl(src0, src1, dst, ne00, ne01, ne02, ne10, ne12, ne0, ne1, r2, r3, shared_values, tgpig, tiisg, sgitg);
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}
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[[host_name("kernel_mul_mv_iq4_xs_f32")]]
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kernel void kernel_mul_mv_iq4_xs_f32(
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device const void * src0,
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device const float * src1,
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device float * dst,
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constant int64_t & ne00,
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constant int64_t & ne01,
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constant int64_t & ne02,
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constant uint64_t & nb00,
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constant uint64_t & nb01,
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constant uint64_t & nb02,
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constant int64_t & ne10,
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constant int64_t & ne11,
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constant int64_t & ne12,
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constant uint64_t & nb10,
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constant uint64_t & nb11,
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constant uint64_t & nb12,
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constant int64_t & ne0,
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constant int64_t & ne1,
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constant uint & r2,
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constant uint & r3,
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threadgroup float * shared_values [[threadgroup(0)]],
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uint3 tgpig[[threadgroup_position_in_grid]],
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uint tiisg[[thread_index_in_simdgroup]],
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uint sgitg[[simdgroup_index_in_threadgroup]]) {
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kernel_mul_mv_iq4_xs_f32_impl(src0, src1, dst, ne00, ne01, ne02, ne10, ne12, ne0, ne1, r2, r3, shared_values, tgpig, tiisg, sgitg);
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}
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//============================= templates and their specializations =============================
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// NOTE: this is not dequantizing - we are simply fitting the template
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@ -5638,6 +5768,26 @@ void dequantize_iq4_nl(device const block_iq4_nl * xb, short il, thread type4x4
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}
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}
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template <typename type4x4>
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void dequantize_iq4_xs(device const block_iq4_xs * xb, short il, thread type4x4 & reg) {
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// il is 0...15 for QK_K = 256 => index of block of 32 is il/2
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const int ib32 = il/2;
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il = il%2;
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// il = 0 or 1. il = 0 processes the first 16 quants in a block of 32, il = 1 the second 16
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device const uint32_t * q4 = (device const uint32_t *)xb->qs + 4*ib32;
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const int ls = ((xb->scales_l[ib32/2] >> 4*(ib32%2)) & 0xf) | (((xb->scales_h >> 2*ib32) & 3) << 4);
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const float d = (float)xb->d * (ls - 32);
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uint32_t aux32;
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thread const uint8_t * q8 = (thread const uint8_t *)&aux32;
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for (int i = 0; i < 4; ++i) {
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aux32 = (q4[i] >> 4*il) & 0x0f0f0f0f;
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reg[i][0] = d * kvalues_iq4nl_f[q8[0]];
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reg[i][1] = d * kvalues_iq4nl_f[q8[1]];
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reg[i][2] = d * kvalues_iq4nl_f[q8[2]];
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reg[i][3] = d * kvalues_iq4nl_f[q8[3]];
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}
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}
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template<typename block_q, short nl, void (*dequantize_func)(device const block_q *, short, thread float4x4 &)>
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kernel void kernel_get_rows(
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device const void * src0,
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@ -6183,7 +6333,8 @@ template [[host_name("kernel_get_rows_iq3_xxs")]] kernel get_rows_t kernel_get_r
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template [[host_name("kernel_get_rows_iq3_s")]] kernel get_rows_t kernel_get_rows<block_iq3_s, QK_NL, dequantize_iq3_s>;
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template [[host_name("kernel_get_rows_iq2_s")]] kernel get_rows_t kernel_get_rows<block_iq2_s, QK_NL, dequantize_iq2_s>;
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template [[host_name("kernel_get_rows_iq1_s")]] kernel get_rows_t kernel_get_rows<block_iq1_s, QK_NL, dequantize_iq1_s>;
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template [[host_name("kernel_get_rows_iq4_nl")]] kernel get_rows_t kernel_get_rows<block_iq4_nl, 2, dequantize_iq4_nl>;
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template [[host_name("kernel_get_rows_iq4_nl")]] kernel get_rows_t kernel_get_rows<block_iq4_nl, 2, dequantize_iq4_nl>;
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template [[host_name("kernel_get_rows_iq4_xs")]] kernel get_rows_t kernel_get_rows<block_iq4_xs, QK_NL, dequantize_iq4_xs>;
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//
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// matrix-matrix multiplication
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@ -6226,7 +6377,8 @@ template [[host_name("kernel_mul_mm_iq3_xxs_f32")]] kernel mat_mm_t kernel_mul_m
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template [[host_name("kernel_mul_mm_iq3_s_f32")]] kernel mat_mm_t kernel_mul_mm<block_iq3_s, QK_NL, dequantize_iq3_s>;
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template [[host_name("kernel_mul_mm_iq2_s_f32")]] kernel mat_mm_t kernel_mul_mm<block_iq2_s, QK_NL, dequantize_iq2_s>;
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template [[host_name("kernel_mul_mm_iq1_s_f32")]] kernel mat_mm_t kernel_mul_mm<block_iq1_s, QK_NL, dequantize_iq1_s>;
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template [[host_name("kernel_mul_mm_iq4_nl_f32")]] kernel mat_mm_t kernel_mul_mm<block_iq4_nl, 2, dequantize_iq4_nl>;
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template [[host_name("kernel_mul_mm_iq4_nl_f32")]] kernel mat_mm_t kernel_mul_mm<block_iq4_nl, 2, dequantize_iq4_nl>;
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template [[host_name("kernel_mul_mm_iq4_xs_f32")]] kernel mat_mm_t kernel_mul_mm<block_iq4_xs, QK_NL, dequantize_iq4_xs>;
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//
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// indirect matrix-matrix multiplication
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@ -6281,7 +6433,8 @@ template [[host_name("kernel_mul_mm_id_iq3_xxs_f32")]] kernel mat_mm_id_t kernel
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template [[host_name("kernel_mul_mm_id_iq3_s_f32")]] kernel mat_mm_id_t kernel_mul_mm_id<block_iq3_s, QK_NL, dequantize_iq3_s>;
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template [[host_name("kernel_mul_mm_id_iq2_s_f32")]] kernel mat_mm_id_t kernel_mul_mm_id<block_iq2_s, QK_NL, dequantize_iq2_s>;
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template [[host_name("kernel_mul_mm_id_iq1_s_f32")]] kernel mat_mm_id_t kernel_mul_mm_id<block_iq1_s, QK_NL, dequantize_iq1_s>;
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template [[host_name("kernel_mul_mm_id_iq4_nl_f32")]] kernel mat_mm_id_t kernel_mul_mm_id<block_iq4_nl, 2, dequantize_iq4_nl>;
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template [[host_name("kernel_mul_mm_id_iq4_nl_f32")]] kernel mat_mm_id_t kernel_mul_mm_id<block_iq4_nl, 2, dequantize_iq4_nl>;
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template [[host_name("kernel_mul_mm_id_iq4_xs_f32")]] kernel mat_mm_id_t kernel_mul_mm_id<block_iq4_xs, QK_NL, dequantize_iq4_xs>;
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//
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// matrix-vector multiplication
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@ -7507,3 +7660,68 @@ kernel void kernel_mul_mv_id_iq4_nl_f32(
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tiisg,
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sgitg);
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}
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[[host_name("kernel_mul_mv_id_iq4_xs_f32")]]
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kernel void kernel_mul_mv_id_iq4_xs_f32(
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device const char * ids,
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device const char * src1,
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device float * dst,
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constant uint64_t & nbi1,
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constant int64_t & ne00,
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constant int64_t & ne01,
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constant int64_t & ne02,
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constant uint64_t & nb00,
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constant uint64_t & nb01,
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constant uint64_t & nb02,
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constant int64_t & ne10,
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constant int64_t & ne11,
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constant int64_t & ne12,
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constant int64_t & ne13,
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constant uint64_t & nb10,
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constant uint64_t & nb11,
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constant uint64_t & nb12,
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constant int64_t & ne0,
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constant int64_t & ne1,
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constant uint64_t & nb1,
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constant uint & r2,
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constant uint & r3,
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constant int & idx,
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device const char * src00,
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device const char * src01,
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device const char * src02,
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device const char * src03,
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device const char * src04,
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device const char * src05,
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device const char * src06,
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device const char * src07,
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threadgroup float * shared_values [[threadgroup(0)]],
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uint3 tgpig[[threadgroup_position_in_grid]],
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uint tiitg[[thread_index_in_threadgroup]],
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uint tiisg[[thread_index_in_simdgroup]],
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uint sgitg[[simdgroup_index_in_threadgroup]]) {
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device const char * src0[8] = {src00, src01, src02, src03, src04, src05, src06, src07};
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const int64_t bid = tgpig.z/(ne12*ne13);
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tgpig.z = tgpig.z%(ne12*ne13);
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const int32_t id = ((device int32_t *) (ids + bid*nbi1))[idx];
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kernel_mul_mv_iq4_xs_f32_impl(
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src0[id],
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(device const float *) (src1 + bid*nb11),
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dst + bid*ne0,
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ne00,
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ne01,
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ne02,
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ne10,
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ne12,
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ne0,
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ne1,
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r2,
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r3,
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shared_values,
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tgpig,
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tiisg,
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sgitg);
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}
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