llava : add MobileVLM support (#5132)
* New Feature:
1. Sum_Rows:
fix cuda kernel overflow
fix block shape error when nrows too big
2. Im2Col:
Support Batch in cuda
Support f32 to f32 both in cpu && cuda
3. DepthWiseConv:
Support by Im2Col && MulMat
4. Pool_2d:
Supoort avg pooling in cuda
5. HardSigmoid:
Imp in cuda
6. HardSwish:
Imp in cuda
* fix tabs instead of spaces
* code clean
* CUDA POOL2D
* ADD POOL2D test case in test-backend-ops.cpp
* code clean
* fix pool2d_kernel
nits
* fix bug in pool2d kernel
* fix avg pooling, count_include_pad
nits
* test-backend-ops : add more pool_2d tests
* cuda : fix warnings and formatting
* ggml : check types in release builds too in pool_2d
* test-backend-ops : remove f16 pool_2d tests
* cuda : more style fixes
* Add assert in ggml_cuda_op_pool2d
* pool2d float padding fallback
* test-backend-ops : add dst_type to im2col
---------
Co-authored-by: slaren <slarengh@gmail.com>
This commit is contained in:
JidongZhang-THU
GitHub
parent
b2b9f025e7
commit
15606309a0
5 changed files with 421 additions and 41 deletions
209
ggml-cuda.cu
209
ggml-cuda.cu
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@ -524,6 +524,8 @@ static_assert(sizeof(block_iq3_xxs) == sizeof(ggml_fp16_t) + 3*(QK_K/8), "wrong
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#define CUDA_SILU_BLOCK_SIZE 256
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#define CUDA_TANH_BLOCK_SIZE 256
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#define CUDA_RELU_BLOCK_SIZE 256
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#define CUDA_HARDSIGMOID_BLOCK_SIZE 256
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#define CUDA_HARDSWISH_BLOCK_SIZE 256
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#define CUDA_SQR_BLOCK_SIZE 256
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#define CUDA_CPY_BLOCK_SIZE 32
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#define CUDA_SCALE_BLOCK_SIZE 256
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@ -540,6 +542,7 @@ static_assert(sizeof(block_iq3_xxs) == sizeof(ggml_fp16_t) + 3*(QK_K/8), "wrong
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#define CUDA_PAD_BLOCK_SIZE 256
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#define CUDA_ACC_BLOCK_SIZE 256
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#define CUDA_IM2COL_BLOCK_SIZE 256
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#define CUDA_POOL2D_BLOCK_SIZE 256
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#define CUDA_Q8_0_NE_ALIGN 2048
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@ -823,6 +826,24 @@ static __global__ void relu_f32(const float * x, float * dst, const int k) {
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dst[i] = fmaxf(x[i], 0);
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}
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static __global__ void hardsigmoid_f32(const float * x, float * dst, const int k) {
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const int i = blockDim.x*blockIdx.x + threadIdx.x;
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if (i >= k) {
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return;
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}
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dst[i] = fminf(1.0f, fmaxf(0.0f, (x[i] + 3.0f) / 6.0f));
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}
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static __global__ void hardswish_f32(const float * x, float * dst, const int k) {
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const int i = blockDim.x*blockIdx.x + threadIdx.x;
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if (i >= k) {
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return;
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}
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dst[i] = x[i] * fminf(1.0f, fmaxf(0.0f, (x[i] + 3.0f) / 6.0f));
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}
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static __global__ void leaky_relu_f32(const float * x, float * dst, const int k, const float negative_slope) {
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const int i = blockDim.x*blockIdx.x + threadIdx.x;
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if (i >= k) {
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@ -5823,7 +5844,7 @@ static __global__ void alibi_f32(const float * x, float * dst, const int ncols,
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}
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static __global__ void k_sum_rows_f32(const float * x, float * dst, const int ncols) {
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const int row = blockIdx.y;
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const int row = blockIdx.x;
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const int col = threadIdx.x;
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float sum = 0.0f;
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@ -6145,9 +6166,10 @@ static __global__ void clamp_f32(const float * x, float * dst, const float min,
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dst[i] = x[i] < min ? min : (x[i] > max ? max : x[i]);
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}
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static __global__ void im2col_f32_f16(
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const float * x, half * dst,
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int offset_delta, int IW, int IH, int OW, int KW, int KH, int pelements, int CHW,
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template <typename T>
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static __global__ void im2col_kernel(
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const float * x, T * dst, int batch_offset,
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int offset_delta, int IC, int IW, int IH, int OH, int OW, int KW, int KH, int pelements, int CHW,
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int s0, int s1, int p0, int p1, int d0, int d1) {
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const int i = threadIdx.x + blockIdx.x * blockDim.x;
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if (i >= pelements) {
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@ -6160,21 +6182,73 @@ static __global__ void im2col_f32_f16(
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const int ky = (i - kd) / OW;
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const int ix = i % OW;
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const int oh = blockIdx.y;
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const int batch = blockIdx.z / IC;
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const int ic = blockIdx.z % IC;
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const int64_t iiw = ix * s0 + kx * d0 - p0;
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const int64_t iih = blockIdx.y * s1 + ky * d1 - p1;
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const int64_t iih = oh * s1 + ky * d1 - p1;
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const int64_t offset_dst =
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(blockIdx.y * OW + ix) * CHW +
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(blockIdx.z * (KW * KH) + ky * KW + kx);
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((batch * OH + oh) * OW + ix) * CHW +
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(ic * (KW * KH) + ky * KW + kx);
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if (iih < 0 || iih >= IH || iiw < 0 || iiw >= IW) {
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dst[offset_dst] = __float2half(0.0f);
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dst[offset_dst] = 0.0f;
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} else {
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const int64_t offset_src = blockIdx.z * offset_delta;
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dst[offset_dst] = __float2half(x[offset_src + iih * IW + iiw]);
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const int64_t offset_src = ic * offset_delta + batch * batch_offset;
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dst[offset_dst] = x[offset_src + iih * IW + iiw];
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}
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}
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template <typename Ti, typename To>
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static __global__ void pool2d_nchw_kernel(
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const int ih, const int iw, const int oh, const int ow,
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const int kh, const int kw, const int sh, const int sw,
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const int ph, const int pw, const int parallel_elements,
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const Ti* src, To* dst, const enum ggml_op_pool op) {
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int idx = threadIdx.x + blockIdx.x * blockDim.x;
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if (idx >= parallel_elements) {
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return;
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}
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const int I_HW = ih * iw;
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const int O_HW = oh * ow;
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const int nc = idx / O_HW;
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const int cur_oh = idx % O_HW / ow;
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const int cur_ow = idx % O_HW % ow;
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const Ti* i_ptr = src + nc * I_HW;
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To* o_ptr = dst + nc * O_HW;
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const int start_h = cur_oh * sh - ph;
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const int bh = max(0, start_h);
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const int eh = min(ih, start_h + kh);
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const int start_w = cur_ow * sw - pw;
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const int bw = max(0, start_w);
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const int ew = min(iw, start_w + kw);
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const To scale = 1. / (kh * kw);
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To res = 0;
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switch (op) {
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case GGML_OP_POOL_AVG: res = 0; break;
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case GGML_OP_POOL_MAX: res = -FLT_MAX; break;
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}
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for (int i = bh; i < eh; i += 1) {
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for (int j = bw; j < ew; j += 1) {
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#if __CUDA_ARCH__ >= 350
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Ti cur = __ldg(i_ptr + i * iw + j);
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#else
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Ti cur = i_ptr[i * iw + j];
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#endif
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switch (op) {
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case GGML_OP_POOL_AVG: res += cur * scale; break;
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case GGML_OP_POOL_MAX: res = max(res, (To)cur); break;
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}
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}
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}
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o_ptr[cur_oh * ow + cur_ow] = res;
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}
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template<int qk, int qr, dequantize_kernel_t dq>
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static void get_rows_cuda(const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst,
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const void * src0_dd, const int32_t * src1_dd, float * dst_dd, cudaStream_t stream) {
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@ -6388,6 +6462,16 @@ static void relu_f32_cuda(const float * x, float * dst, const int k, cudaStream_
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relu_f32<<<num_blocks, CUDA_RELU_BLOCK_SIZE, 0, stream>>>(x, dst, k);
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}
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static void hardsigmoid_f32_cuda(const float * x, float * dst, const int k, cudaStream_t stream) {
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const int num_blocks = (k + CUDA_HARDSIGMOID_BLOCK_SIZE - 1) / CUDA_HARDSIGMOID_BLOCK_SIZE;
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hardsigmoid_f32<<<num_blocks, CUDA_HARDSIGMOID_BLOCK_SIZE, 0, stream>>>(x, dst, k);
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}
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static void hardswish_f32_cuda(const float * x, float * dst, const int k, cudaStream_t stream) {
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const int num_blocks = (k + CUDA_HARDSWISH_BLOCK_SIZE - 1) / CUDA_HARDSWISH_BLOCK_SIZE;
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hardswish_f32<<<num_blocks, CUDA_HARDSWISH_BLOCK_SIZE, 0, stream>>>(x, dst, k);
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}
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static void leaky_relu_f32_cuda(const float * x, float * dst, const int k, const float negative_slope, cudaStream_t stream) {
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const int num_blocks = (k + CUDA_RELU_BLOCK_SIZE - 1) / CUDA_RELU_BLOCK_SIZE;
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leaky_relu_f32<<<num_blocks, CUDA_RELU_BLOCK_SIZE, 0, stream>>>(x, dst, k, negative_slope);
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@ -7475,7 +7559,7 @@ static void alibi_f32_cuda(const float * x, float * dst, const int ncols, const
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static void sum_rows_f32_cuda(const float * x, float * dst, const int ncols, const int nrows, cudaStream_t stream) {
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const dim3 block_dims(WARP_SIZE, 1, 1);
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const dim3 block_nums(1, nrows, 1);
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const dim3 block_nums(nrows, 1, 1);
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k_sum_rows_f32<<<block_nums, block_dims, 0, stream>>>(x, dst, ncols);
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}
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@ -7587,14 +7671,15 @@ static void soft_max_f32_cuda(const float * x, const float * y, float * dst, con
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}
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}
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static void im2col_f32_f16_cuda(const float* x, half* dst,
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template <typename T>
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static void im2col_cuda(const float* x, T* dst,
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int IW, int IH, int OW, int OH, int KW, int KH, int IC,
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int offset_delta,
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int batch, int batch_offset, int offset_delta,
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int s0,int s1,int p0,int p1,int d0,int d1, cudaStream_t stream) {
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const int parallel_elements = OW * KW * KH;
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const int num_blocks = (parallel_elements + CUDA_IM2COL_BLOCK_SIZE - 1) / CUDA_IM2COL_BLOCK_SIZE;
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dim3 block_nums(num_blocks, OH, IC);
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im2col_f32_f16<<<block_nums, CUDA_IM2COL_BLOCK_SIZE, 0, stream>>>(x, dst, offset_delta, IW, IH, OW, KW, KH, parallel_elements, (IC * KH * KW), s0, s1, p0, p1, d0, d1);
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dim3 block_nums(num_blocks, OH, batch * IC);
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im2col_kernel<<<block_nums, CUDA_IM2COL_BLOCK_SIZE, 0, stream>>>(x, dst, batch_offset, offset_delta, IC, IW, IH, OH, OW, KW, KH, parallel_elements, (IC * KH * KW), s0, s1, p0, p1, d0, d1);
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}
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// buffer pool for cuda
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@ -8179,6 +8264,34 @@ static void ggml_cuda_op_relu(
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(void) src1_dd;
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}
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static void ggml_cuda_op_hardsigmoid(
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const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst,
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const float * src0_dd, const float * src1_dd, float * dst_dd, cudaStream_t main_stream) {
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GGML_ASSERT(src0->type == GGML_TYPE_F32);
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GGML_ASSERT( dst->type == GGML_TYPE_F32);
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hardsigmoid_f32_cuda(src0_dd, dst_dd, ggml_nelements(src0), main_stream);
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(void) src1;
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(void) dst;
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(void) src1_dd;
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}
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static void ggml_cuda_op_hardswish(
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const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst,
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const float * src0_dd, const float * src1_dd, float * dst_dd, cudaStream_t main_stream) {
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GGML_ASSERT(src0->type == GGML_TYPE_F32);
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GGML_ASSERT( dst->type == GGML_TYPE_F32);
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hardswish_f32_cuda(src0_dd, dst_dd, ggml_nelements(src0), main_stream);
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(void) src1;
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(void) dst;
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(void) src1_dd;
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}
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static void ggml_cuda_op_leaky_relu(
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const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst,
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const float * src0_dd, const float * src1_dd, float * dst_dd, cudaStream_t main_stream) {
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@ -8810,13 +8923,46 @@ static void ggml_cuda_op_alibi(
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(void) src1_dd;
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}
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static void ggml_cuda_op_pool2d(
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const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst,
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const float * src0_dd, const float * src1_dd, float * dst_dd, cudaStream_t main_stream) {
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GGML_ASSERT(src0->type == GGML_TYPE_F32);
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GGML_ASSERT( dst->type == GGML_TYPE_F32);
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const int32_t * opts = (const int32_t *)dst->op_params;
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enum ggml_op_pool op = static_cast<ggml_op_pool>(opts[0]);
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const int k0 = opts[1];
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const int k1 = opts[2];
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const int s0 = opts[3];
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const int s1 = opts[4];
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const int p0 = opts[5];
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const int p1 = opts[6];
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const int64_t IH = src0->ne[1];
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const int64_t IW = src0->ne[0];
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const int64_t N = dst->ne[3];
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const int64_t OC = dst->ne[2];
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const int64_t OH = dst->ne[1];
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const int64_t OW = dst->ne[0];
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const int parallel_elements = N * OC * OH * OW;
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const int num_blocks = (parallel_elements + CUDA_POOL2D_BLOCK_SIZE - 1) / CUDA_POOL2D_BLOCK_SIZE;
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dim3 block_nums(num_blocks);
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pool2d_nchw_kernel<<<block_nums, CUDA_IM2COL_BLOCK_SIZE, 0, main_stream>>>(IH, IW, OH, OW, k1, k0, s1, s0, p1, p0, parallel_elements, src0_dd, dst_dd, op);
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(void) src1;
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(void) src1_dd;
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}
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static void ggml_cuda_op_im2col(
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const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst,
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const float * src0_dd, const float * src1_dd, float * dst_dd, cudaStream_t main_stream) {
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GGML_ASSERT(src0->type == GGML_TYPE_F16);
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GGML_ASSERT(src1->type == GGML_TYPE_F32);
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GGML_ASSERT( dst->type == GGML_TYPE_F16);
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GGML_ASSERT( dst->type == GGML_TYPE_F16 || dst->type == GGML_TYPE_F32);
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const int32_t s0 = ((const int32_t*)(dst->op_params))[0];
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const int32_t s1 = ((const int32_t*)(dst->op_params))[1];
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@ -8838,8 +8984,14 @@ static void ggml_cuda_op_im2col(
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const int64_t OW = dst->ne[1];
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const size_t delta_offset = src1->nb[is_2D ? 2 : 1] / 4; // nb is byte offset, src is type float32
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const int64_t batch = src1->ne[3];
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const size_t batch_offset = src1->nb[3] / 4; // nb is byte offset, src is type float32
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im2col_f32_f16_cuda(src1_dd, (half*) dst_dd, IW, IH, OW, OH, KW, KH, IC, delta_offset, s0, s1, p0, p1, d0, d1, main_stream);
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if(dst->type == GGML_TYPE_F16) {
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im2col_cuda(src1_dd, (half*) dst_dd, IW, IH, OW, OH, KW, KH, IC, batch, batch_offset, delta_offset, s0, s1, p0, p1, d0, d1, main_stream);
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} else {
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im2col_cuda(src1_dd, (float*) dst_dd, IW, IH, OW, OH, KW, KH, IC, batch, batch_offset, delta_offset, s0, s1, p0, p1, d0, d1, main_stream);
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}
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(void) src0;
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(void) src0_dd;
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@ -9435,6 +9587,13 @@ static void ggml_cuda_relu(const ggml_tensor * src0, const ggml_tensor * src1, g
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ggml_cuda_op_flatten(src0, src1, dst, ggml_cuda_op_relu);
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}
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static void ggml_cuda_hardsigmoid(const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) {
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ggml_cuda_op_flatten(src0, src1, dst, ggml_cuda_op_hardsigmoid);
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}
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static void ggml_cuda_hardswish(const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) {
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ggml_cuda_op_flatten(src0, src1, dst, ggml_cuda_op_hardswish);
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}
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static void ggml_cuda_leaky_relu(const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) {
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ggml_cuda_op_flatten(src0, src1, dst, ggml_cuda_op_leaky_relu);
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}
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@ -10220,6 +10379,10 @@ static void ggml_cuda_alibi(const ggml_tensor * src0, const ggml_tensor * src1,
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ggml_cuda_op_flatten(src0, src1, dst, ggml_cuda_op_alibi);
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}
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static void ggml_cuda_pool2d(const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) {
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ggml_cuda_op_flatten(src0, src1, dst, ggml_cuda_op_pool2d);
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}
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static void ggml_cuda_im2col(const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) {
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ggml_cuda_op_flatten(src0, src1, dst, ggml_cuda_op_im2col);
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}
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@ -10321,6 +10484,12 @@ GGML_CALL bool ggml_cuda_compute_forward(struct ggml_compute_params * params, st
|
|||
case GGML_UNARY_OP_RELU:
|
||||
func = ggml_cuda_relu;
|
||||
break;
|
||||
case GGML_UNARY_OP_HARDSIGMOID:
|
||||
func = ggml_cuda_hardsigmoid;
|
||||
break;
|
||||
case GGML_UNARY_OP_HARDSWISH:
|
||||
func = ggml_cuda_hardswish;
|
||||
break;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
|
@ -10395,6 +10564,9 @@ GGML_CALL bool ggml_cuda_compute_forward(struct ggml_compute_params * params, st
|
|||
case GGML_OP_IM2COL:
|
||||
func = ggml_cuda_im2col;
|
||||
break;
|
||||
case GGML_OP_POOL_2D:
|
||||
func = ggml_cuda_pool2d;
|
||||
break;
|
||||
case GGML_OP_SUM_ROWS:
|
||||
func = ggml_cuda_sum_rows;
|
||||
break;
|
||||
|
|
@ -11123,6 +11295,8 @@ GGML_CALL static bool ggml_backend_cuda_supports_op(ggml_backend_t backend, cons
|
|||
case GGML_UNARY_OP_GELU:
|
||||
case GGML_UNARY_OP_SILU:
|
||||
case GGML_UNARY_OP_RELU:
|
||||
case GGML_UNARY_OP_HARDSIGMOID:
|
||||
case GGML_UNARY_OP_HARDSWISH:
|
||||
case GGML_UNARY_OP_GELU_QUICK:
|
||||
case GGML_UNARY_OP_TANH:
|
||||
return true;
|
||||
|
|
@ -11221,6 +11395,7 @@ GGML_CALL static bool ggml_backend_cuda_supports_op(ggml_backend_t backend, cons
|
|||
case GGML_OP_ROPE:
|
||||
case GGML_OP_ALIBI:
|
||||
case GGML_OP_IM2COL:
|
||||
case GGML_OP_POOL_2D:
|
||||
case GGML_OP_SUM_ROWS:
|
||||
case GGML_OP_ARGSORT:
|
||||
case GGML_OP_ACC:
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue