IQ3_S: a much better alternative to Q3_K (#5676)
* iq4_nl: squash commits for easier rebase * Basics (quantize, dequantize) * CUDA dequantize and dot product * Slightly faster CUDA dot product (120 t/s) * Switch to 6-bit scales * Scalar dot product * AVX2 dot product * ARM_NEON dot product * Works on metal, but still slow * Slightly better Metal dot product * Another small Metal improvement * Metal dot product is getting there * Faster CUDA dot product * Add 1/8 ffn_down layers as Q5_K when no imatrix has been provided * Report the actual bpw * Add _xs mix that is 4.05 bpw for non-MoE models * Remove IQ4_XS for now, slightly adjust kvalues_iq4nl * AVX2 dot product uses Q8_0 instead of Q8_K * Add to test-backend-ops * Minor fix * Also use use Q5_K for attn_output in MoE models * Fixes after merging latest master * Switching to blocks of 32 * AVX2 for blocks of 32 * Scaler dot product for blocks of 32 * ARM_NEON dot product for blocks of 32 * Metal kernels for blocks of 32 * Slightly faster Metal kernels * Resurrecting iq3_xs After all the experimentation, nothing was better than this. * Minor PPL improvement via a block scale fudge factor * Minor improvement via 3 neighbours * iq3_xs: working scalar and AVX2 dot products * iq3_xs: ARM_NEON dot product - works but extremely slow (10 t/s) * iq3_xs: working Metal implementation * Adding IQ3_M - IQ3_XS mix with mostly Q4_K * iiq3_xs: a 3.4375 bpw variant * iq3_xs: make CUDA work for new version * iq3_xs: make scalar and AVX2 work for new version * iq3_s: make ARM_NEON work with new version * iq3_xs: make new version work on metal Performance is very similar to Q3_K_S * iq3_xs: tiny Metal speed improvement * iq3_xs: tiny Metal speed improvement * Fix stupid warning * Q3_K_XS now uses a mix of IQ3_XS and IQ3_XXS * iq3_xs: rename to iq3_s * iq3_s: make tests pass * Move Q3_K_XS mix to 3.25 bpw * Attempt to fix failing tests * Another attempt to fix the Windows builds * Attempt to fix ROCm * ROCm again * iq3_s: partial fix for QK_K = 64 * iq3_s: make it work on metal for QK_K = 64 Pleasent surprise: the coding was super-block size independent, so all it took was to delete some QK_K == 256 guards. * Will this fix ROCm? --------- Co-authored-by: Iwan Kawrakow <iwan.kawrakow@gmail.com>
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Kawrakow
GitHub
parent
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commit
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12 changed files with 1211 additions and 84 deletions
33
ggml-metal.m
33
ggml-metal.m
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@ -61,6 +61,7 @@ enum ggml_metal_kernel_type {
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GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ2_XXS,
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GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ2_XS,
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GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ3_XXS,
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GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ3_S,
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GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ1_S,
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GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ4_NL,
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GGML_METAL_KERNEL_TYPE_GET_ROWS_I32,
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@ -85,6 +86,7 @@ enum ggml_metal_kernel_type {
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GGML_METAL_KERNEL_TYPE_MUL_MV_IQ2_XXS_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MV_IQ2_XS_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MV_IQ3_XXS_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MV_IQ3_S_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MV_IQ1_S_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MV_IQ4_NL_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MV_ID_F32_F32,
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@ -105,6 +107,7 @@ enum ggml_metal_kernel_type {
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GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ2_XXS_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ2_XS_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ3_XXS_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ3_S_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ1_S_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ4_NL_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MM_F32_F32,
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@ -122,6 +125,7 @@ enum ggml_metal_kernel_type {
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GGML_METAL_KERNEL_TYPE_MUL_MM_IQ2_XXS_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MM_IQ2_XS_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MM_IQ3_XXS_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MM_IQ3_S_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MM_IQ1_S_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MM_IQ4_NL_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MM_ID_F32_F32,
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@ -139,6 +143,7 @@ enum ggml_metal_kernel_type {
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GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ2_XXS_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ2_XS_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ3_XXS_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ3_S_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ1_S_F32,
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GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ4_NL_F32,
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GGML_METAL_KERNEL_TYPE_ROPE_F32,
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@ -452,6 +457,7 @@ static struct ggml_metal_context * ggml_metal_init(int n_cb) {
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ2_XXS, get_rows_iq2_xxs, true);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ2_XS, get_rows_iq2_xs, true);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ3_XXS, get_rows_iq3_xxs, true);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ3_S, get_rows_iq3_s, true);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ1_S, get_rows_iq1_s, true);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ4_NL, get_rows_iq4_nl, true);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_I32, get_rows_i32, true);
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@ -476,6 +482,7 @@ static struct ggml_metal_context * ggml_metal_init(int n_cb) {
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_IQ2_XXS_F32, mul_mv_iq2_xxs_f32, ctx->support_simdgroup_reduction);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_IQ2_XS_F32, mul_mv_iq2_xs_f32, ctx->support_simdgroup_reduction);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_IQ3_XXS_F32, mul_mv_iq3_xxs_f32, ctx->support_simdgroup_reduction);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_IQ3_S_F32, mul_mv_iq3_s_f32, ctx->support_simdgroup_reduction);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_IQ1_S_F32, mul_mv_iq1_s_f32, ctx->support_simdgroup_reduction);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_IQ4_NL_F32, mul_mv_iq4_nl_f32, ctx->support_simdgroup_reduction);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_F32_F32, mul_mv_id_f32_f32, ctx->support_simdgroup_reduction);
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@ -496,6 +503,7 @@ static struct ggml_metal_context * ggml_metal_init(int n_cb) {
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ2_XXS_F32, mul_mv_id_iq2_xxs_f32, ctx->support_simdgroup_reduction);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ2_XS_F32, mul_mv_id_iq2_xs_f32, ctx->support_simdgroup_reduction);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ3_XXS_F32, mul_mv_id_iq3_xxs_f32, ctx->support_simdgroup_reduction);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ3_S_F32, mul_mv_id_iq3_s_f32, ctx->support_simdgroup_reduction);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ1_S_F32, mul_mv_id_iq1_s_f32, ctx->support_simdgroup_reduction);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ4_NL_F32, mul_mv_id_iq4_nl_f32, ctx->support_simdgroup_reduction);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_F32_F32, mul_mm_f32_f32, ctx->support_simdgroup_mm);
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@ -513,6 +521,7 @@ static struct ggml_metal_context * ggml_metal_init(int n_cb) {
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_IQ2_XXS_F32, mul_mm_iq2_xxs_f32, ctx->support_simdgroup_mm);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_IQ2_XS_F32, mul_mm_iq2_xs_f32, ctx->support_simdgroup_mm);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_IQ3_XXS_F32, mul_mm_iq3_xxs_f32, ctx->support_simdgroup_mm);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_IQ3_S_F32, mul_mm_iq3_s_f32, ctx->support_simdgroup_mm);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_IQ1_S_F32, mul_mm_iq1_s_f32, ctx->support_simdgroup_mm);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_IQ4_NL_F32, mul_mm_iq4_nl_f32, ctx->support_simdgroup_mm);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_F32_F32, mul_mm_id_f32_f32, ctx->support_simdgroup_mm);
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@ -530,6 +539,7 @@ static struct ggml_metal_context * ggml_metal_init(int n_cb) {
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ2_XXS_F32, mul_mm_id_iq2_xxs_f32, ctx->support_simdgroup_mm);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ2_XS_F32, mul_mm_id_iq2_xs_f32, ctx->support_simdgroup_mm);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ3_XXS_F32, mul_mm_id_iq3_xxs_f32, ctx->support_simdgroup_mm);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ3_S_F32, mul_mm_id_iq3_s_f32, ctx->support_simdgroup_mm);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ1_S_F32, mul_mm_id_iq1_s_f32, ctx->support_simdgroup_mm);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ4_NL_F32, mul_mm_id_iq4_nl_f32, ctx->support_simdgroup_mm);
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GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_ROPE_F32, rope_f32, true);
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@ -1347,6 +1357,7 @@ static bool ggml_metal_graph_compute(
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case GGML_TYPE_IQ2_XXS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_IQ2_XXS_F32].pipeline; break;
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case GGML_TYPE_IQ2_XS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_IQ2_XS_F32 ].pipeline; break;
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case GGML_TYPE_IQ3_XXS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_IQ3_XXS_F32].pipeline; break;
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case GGML_TYPE_IQ3_S: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_IQ3_S_F32 ].pipeline; break;
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case GGML_TYPE_IQ1_S: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_IQ1_S_F32 ].pipeline; break;
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case GGML_TYPE_IQ4_NL: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_IQ4_NL_F32 ].pipeline; break;
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default: GGML_ASSERT(false && "MUL MAT-MAT not implemented");
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@ -1483,6 +1494,12 @@ static bool ggml_metal_graph_compute(
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nth1 = 16;
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pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_IQ3_XXS_F32].pipeline;
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} break;
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case GGML_TYPE_IQ3_S:
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{
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nth0 = 4;
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nth1 = 16;
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pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_IQ3_S_F32].pipeline;
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} break;
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case GGML_TYPE_IQ1_S:
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{
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nth0 = 4;
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@ -1537,8 +1554,8 @@ static bool ggml_metal_graph_compute(
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[encoder setThreadgroupMemoryLength:mem_size atIndex:0];
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[encoder dispatchThreadgroups:MTLSizeMake((ne01 + 7)/8, ne11, ne12*ne13) threadsPerThreadgroup:MTLSizeMake(nth0, nth1, 1)];
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}
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else if (src0t == GGML_TYPE_IQ3_XXS) {
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const int mem_size = 256*4+128;
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else if (src0t == GGML_TYPE_IQ3_XXS || src0t == GGML_TYPE_IQ3_S) {
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const int mem_size = src0t == GGML_TYPE_IQ3_XXS ? 256*4+128 : 512*4;
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[encoder setThreadgroupMemoryLength:mem_size atIndex:0];
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[encoder dispatchThreadgroups:MTLSizeMake((ne01 + 7)/8, ne11, ne12*ne13) threadsPerThreadgroup:MTLSizeMake(nth0, nth1, 1)];
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}
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@ -1640,6 +1657,7 @@ static bool ggml_metal_graph_compute(
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case GGML_TYPE_IQ2_XXS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ2_XXS_F32].pipeline; break;
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case GGML_TYPE_IQ2_XS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ2_XS_F32 ].pipeline; break;
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case GGML_TYPE_IQ3_XXS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ3_XXS_F32].pipeline; break;
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case GGML_TYPE_IQ3_S: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ3_S_F32 ].pipeline; break;
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case GGML_TYPE_IQ1_S: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ1_S_F32 ].pipeline; break;
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case GGML_TYPE_IQ4_NL: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ4_NL_F32 ].pipeline; break;
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default: GGML_ASSERT(false && "MUL_MAT_ID not implemented");
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@ -1779,6 +1797,12 @@ static bool ggml_metal_graph_compute(
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nth1 = 16;
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pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ3_XXS_F32].pipeline;
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} break;
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case GGML_TYPE_IQ3_S:
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{
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nth0 = 4;
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nth1 = 16;
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pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ3_S_F32].pipeline;
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} break;
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case GGML_TYPE_IQ1_S:
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{
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nth0 = 4;
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@ -1849,8 +1873,8 @@ static bool ggml_metal_graph_compute(
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[encoder setThreadgroupMemoryLength:mem_size atIndex:0];
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[encoder dispatchThreadgroups:MTLSizeMake((ne21 + 7)/8, _ne1, ne01*ne12*ne13) threadsPerThreadgroup:MTLSizeMake(nth0, nth1, 1)];
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}
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else if (src2t == GGML_TYPE_IQ3_XXS) {
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const int mem_size = 256*4+128;
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else if (src2t == GGML_TYPE_IQ3_XXS || src2t == GGML_TYPE_IQ3_S) {
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const int mem_size = src2t == GGML_TYPE_IQ3_XXS ? 256*4+128 : 512*4;
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[encoder setThreadgroupMemoryLength:mem_size atIndex:0];
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[encoder dispatchThreadgroups:MTLSizeMake((ne21 + 7)/8, _ne1, ne01*ne12*ne13) threadsPerThreadgroup:MTLSizeMake(nth0, nth1, 1)];
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}
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@ -1900,6 +1924,7 @@ static bool ggml_metal_graph_compute(
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case GGML_TYPE_IQ2_XXS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ2_XXS].pipeline; break;
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case GGML_TYPE_IQ2_XS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ2_XS ].pipeline; break;
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case GGML_TYPE_IQ3_XXS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ3_XXS].pipeline; break;
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case GGML_TYPE_IQ3_S: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ3_S ].pipeline; break;
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case GGML_TYPE_IQ1_S: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ1_S ].pipeline; break;
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case GGML_TYPE_IQ4_NL: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ4_NL ].pipeline; break;
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case GGML_TYPE_I32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_I32 ].pipeline; break;
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