add some new ops, fix some operators and add batch operations to certain operators. (ggml/747)
* cuda: fix group_norm * cuda: add batch inference support for ggml_pad/ggml_upscale * add ggml_arrange * add ggml_timestep_embedding * update ggml_arange/ggml_timestep_embedding tests * cuda: fix im2col * add ggml_arange/ggml_timestep_embbeding support for metal backend * fix some bugs * fix some bugs * Update ggml.h Co-authored-by: Georgi Gerganov <ggerganov@gmail.com> * Update ggml-cuda.cu Co-authored-by: Georgi Gerganov <ggerganov@gmail.com> * Update ggml-metal.m Co-authored-by: Georgi Gerganov <ggerganov@gmail.com> * Update ggml-metal.m Co-authored-by: Georgi Gerganov <ggerganov@gmail.com> * Update ggml-metal.metal Co-authored-by: Georgi Gerganov <ggerganov@gmail.com> * modify according to the review comments * ggml : fix compile warnings + code style * ggml : normalize compute_forward calls + fix seg fault in debug * minor --------- Co-authored-by: Georgi Gerganov <ggerganov@gmail.com> Co-authored-by: slaren <slarengh@gmail.com>
This commit is contained in:
leejet
Georgi Gerganov
parent
82f3e668ad
commit
7d43c585dc
6 changed files with 550 additions and 52 deletions
227
ggml-cuda.cu
227
ggml-cuda.cu
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@ -616,6 +616,8 @@ static_assert(sizeof(block_iq4_xs) == sizeof(ggml_fp16_t) + sizeof(uint16_t) + Q
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#define CUDA_UPSCALE_BLOCK_SIZE 256
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#define CUDA_CONCAT_BLOCK_SIZE 256
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#define CUDA_PAD_BLOCK_SIZE 256
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#define CUDA_ARANGE_BLOCK_SIZE 256
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#define CUDA_TIMESTEP_EMBEDDING_BLOCK_SIZE 256
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#define CUDA_ACC_BLOCK_SIZE 256
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#define CUDA_IM2COL_BLOCK_SIZE 256
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#define CUDA_POOL2D_BLOCK_SIZE 256
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@ -990,17 +992,21 @@ static __global__ void concat_f32(const float * x,const float * y, float * dst,
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nidx +
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blockIdx.y * ne0 +
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blockIdx.z * ne0 * gridDim.y;
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dst[offset_dst] = x[offset_src];
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dst[offset_dst] = x[offset_src];
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} else {
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int offset_src =
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nidx +
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blockIdx.y * ne0 +
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(blockIdx.z - ne02) * ne0 * gridDim.y;
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dst[offset_dst] = y[offset_src];
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dst[offset_dst] = y[offset_src];
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}
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}
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static __global__ void upscale_f32(const float * x, float * dst, const int ne00, const int nb02, const int scale_factor) {
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static __global__ void upscale_f32(const float * x, float * dst, const int ne00, const int ne00xne01, const int scale_factor) {
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// blockIdx.z: idx of ne02*ne03
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// blockIdx.y: idx of ne01*scale_factor， aka ne1
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// blockIDx.x: idx of ne00*scale_factor / BLOCK_SIZE
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// ne00xne01: ne00 * ne01
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int ne0 = ne00 * scale_factor;
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int nidx = threadIdx.x + blockIdx.x * blockDim.x;
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if (nidx >= ne0) {
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@ -1012,7 +1018,7 @@ static __global__ void upscale_f32(const float * x, float * dst, const int ne00,
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int offset_src =
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i00 +
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i01 * ne00 +
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blockIdx.z * nb02;
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blockIdx.z * ne00xne01;
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int offset_dst =
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nidx +
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blockIdx.y * ne0 +
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@ -1020,7 +1026,10 @@ static __global__ void upscale_f32(const float * x, float * dst, const int ne00,
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dst[offset_dst] = x[offset_src];
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}
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static __global__ void pad_f32(const float * x, float * dst, const int ne0, const int ne00, const int ne01, const int ne02) {
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static __global__ void pad_f32(const float * x, float * dst, const int ne0, const int ne00, const int ne01, const int ne02, const int ne03) {
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// blockIdx.z: idx of ne2*ne3, aka ne02*ne03
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// blockIdx.y: idx of ne1
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// blockIDx.x: idx of ne0 / BLOCK_SIZE
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int nidx = threadIdx.x + blockIdx.x * blockDim.x;
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if (nidx >= ne0) {
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return;
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@ -1031,19 +1040,53 @@ static __global__ void pad_f32(const float * x, float * dst, const int ne0, cons
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nidx +
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blockIdx.y * ne0 +
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blockIdx.z * ne0 * gridDim.y;
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if (nidx < ne00 && blockIdx.y < ne01 && blockIdx.z < ne02) {
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if (nidx < ne00 && blockIdx.y < ne01 && blockIdx.z < ne02*ne03) {
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int offset_src =
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nidx +
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blockIdx.y * ne00 +
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blockIdx.z * ne00 * ne01;
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dst[offset_dst] = x[offset_src];
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dst[offset_dst] = x[offset_src];
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} else {
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dst[offset_dst] = 0.0f;
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}
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}
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static __global__ void arange_f32(float * dst, const int ne0, const float start, const float step) {
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// blockIDx.x: idx of ne0 / BLOCK_SIZE
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int nidx = threadIdx.x + blockIdx.x * blockDim.x;
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if (nidx >= ne0) {
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return;
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}
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dst[nidx] = start + step * nidx;
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}
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static __global__ void timestep_embedding_f32(const float * timesteps, float * dst, const int nb1, const int dim, const int max_period) {
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// blockIDx.y: idx of timesteps->ne[0]
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// blockIDx.x: idx of ((dim + 1) / 2) / BLOCK_SIZE
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int i = blockIdx.y;
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int j = threadIdx.x + blockIdx.x * blockDim.x;
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float * embed_data = (float *)((char *)dst + i*nb1);
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if (dim % 2 != 0 && j == ((dim + 1) / 2)) {
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embed_data[dim] = 0.f;
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}
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int half = dim / 2;
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if (j >= half) {
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return;
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}
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float timestep = timesteps[i];
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float freq = (float)expf(-logf(max_period) * j / half);
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float arg = timestep * freq;
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embed_data[j] = cosf(arg);
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embed_data[j + half] = sinf(arg);
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}
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template <int block_size>
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static __global__ void group_norm_f32(const float * x, float * dst, const int group_size, const int ne_elements, const float eps) {
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// blockIdx.x: num_groups idx
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// threadIdx.x: block_size idx
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int start = blockIdx.x * group_size;
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int end = start + group_size;
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@ -6448,7 +6491,7 @@ static __global__ void cpy_f32_f16(const char * cx, char * cdst, const int ne,
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const int ne00, const int ne01, const int ne02, const int nb00, const int nb01, const int nb02,
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const int nb03, const int ne10, const int ne11, const int ne12, const int nb10, const int nb11,
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const int nb12, const int nb13) {
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const int i = blockDim.x*blockIdx.x + threadIdx.x;
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const int64_t i = blockDim.x*blockIdx.x + threadIdx.x;
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if (i >= ne) {
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return;
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@ -6456,17 +6499,17 @@ static __global__ void cpy_f32_f16(const char * cx, char * cdst, const int ne,
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// determine indices i03/i13, i02/i12, i01/i11, i00/i10 as a function of index i of flattened tensor
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// then combine those indices with the corresponding byte offsets to get the total offsets
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const int i03 = i/(ne00 * ne01 * ne02);
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const int i02 = (i - i03*ne00*ne01*ne02 )/ (ne00*ne01);
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const int i01 = (i - i03*ne00*ne01*ne02 - i02*ne01*ne00) / ne00;
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const int i00 = i - i03*ne00*ne01*ne02 - i02*ne01*ne00 - i01*ne00;
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const int x_offset = i00*nb00 + i01*nb01 + i02*nb02 + i03 * nb03;
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const int64_t i03 = i/(ne00 * ne01 * ne02);
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const int64_t i02 = (i - i03*ne00*ne01*ne02 )/ (ne00*ne01);
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const int64_t i01 = (i - i03*ne00*ne01*ne02 - i02*ne01*ne00) / ne00;
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const int64_t i00 = i - i03*ne00*ne01*ne02 - i02*ne01*ne00 - i01*ne00;
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const int64_t x_offset = i00*nb00 + i01*nb01 + i02*nb02 + i03 * nb03;
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const int i13 = i/(ne10 * ne11 * ne12);
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const int i12 = (i - i13*ne10*ne11*ne12) / (ne10*ne11);
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const int i11 = (i - i13*ne10*ne11*ne12 - i12*ne10*ne11) / ne10;
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const int i10 = i - i13*ne10*ne11*ne12 - i12*ne10*ne11 - i11*ne10;
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const int dst_offset = i10*nb10 + i11*nb11 + i12*nb12 + i13 * nb13;
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const int64_t i13 = i/(ne10 * ne11 * ne12);
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const int64_t i12 = (i - i13*ne10*ne11*ne12) / (ne10*ne11);
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const int64_t i11 = (i - i13*ne10*ne11*ne12 - i12*ne10*ne11) / ne10;
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const int64_t i10 = i - i13*ne10*ne11*ne12 - i12*ne10*ne11 - i11*ne10;
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const int64_t dst_offset = i10*nb10 + i11*nb11 + i12*nb12 + i13 * nb13;
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cpy_1(cx + x_offset, cdst + dst_offset);
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}
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@ -6956,23 +6999,23 @@ static __global__ void clamp_f32(const float * x, float * dst, const float min,
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template <typename T>
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static __global__ void im2col_kernel(
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const float * x, T * dst, int batch_offset,
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int offset_delta, int IC, int IW, int IH, int OH, int OW, int KW, int KH, int pelements, int CHW,
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const float * x, T * dst, int64_t batch_offset,
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int64_t offset_delta, int64_t IC, int64_t IW, int64_t IH, int64_t OH, int64_t OW, int64_t KW, int64_t KH, int64_t pelements, int64_t CHW,
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int s0, int s1, int p0, int p1, int d0, int d1) {
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const int i = threadIdx.x + blockIdx.x * blockDim.x;
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const int64_t i = threadIdx.x + blockIdx.x * blockDim.x;
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if (i >= pelements) {
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return;
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}
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const int ksize = OW * (KH > 1 ? KW : 1);
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const int kx = i / ksize;
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const int kd = kx * ksize;
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const int ky = (i - kd) / OW;
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const int ix = i % OW;
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const int64_t ksize = OW * (KH > 1 ? KW : 1);
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const int64_t kx = i / ksize;
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const int64_t kd = kx * ksize;
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const int64_t ky = (i - kd) / OW;
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const int64_t ix = i % OW;
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const int oh = blockIdx.y;
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const int batch = blockIdx.z / IC;
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const int ic = blockIdx.z % IC;
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const int64_t oh = blockIdx.y;
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const int64_t batch = blockIdx.z / IC;
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const int64_t ic = blockIdx.z % IC;
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const int64_t iiw = ix * s0 + kx * d0 - p0;
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const int64_t iih = oh * s1 + ky * d1 - p1;
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@ -7298,19 +7341,33 @@ static void concat_f32_cuda(const float * x, const float * y, float * dst, const
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concat_f32<<<gridDim, CUDA_CONCAT_BLOCK_SIZE, 0, stream>>>(x, y, dst, ne0, ne02);
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}
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static void upscale_f32_cuda(const float * x, float * dst, const int ne00, const int ne01, const int ne02, const int scale_factor, cudaStream_t stream) {
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static void upscale_f32_cuda(const float * x, float * dst, const int ne00, const int ne01, const int ne02, const int ne03,
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const int scale_factor, cudaStream_t stream) {
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int ne0 = (ne00 * scale_factor);
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int num_blocks = (ne0 + CUDA_UPSCALE_BLOCK_SIZE - 1) / CUDA_UPSCALE_BLOCK_SIZE;
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dim3 gridDim(num_blocks, (ne01 * scale_factor), ne02);
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dim3 gridDim(num_blocks, (ne01 * scale_factor), ne02*ne03);
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upscale_f32<<<gridDim, CUDA_UPSCALE_BLOCK_SIZE, 0, stream>>>(x, dst, ne00, ne00 * ne01, scale_factor);
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}
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static void pad_f32_cuda(const float * x, float * dst,
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const int ne00, const int ne01, const int ne02,
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const int ne0, const int ne1, const int ne2, cudaStream_t stream) {
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const int ne00, const int ne01, const int ne02, const int ne03,
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const int ne0, const int ne1, const int ne2, const int ne3, cudaStream_t stream) {
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int num_blocks = (ne0 + CUDA_PAD_BLOCK_SIZE - 1) / CUDA_PAD_BLOCK_SIZE;
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dim3 gridDim(num_blocks, ne1, ne2);
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pad_f32<<<gridDim, CUDA_PAD_BLOCK_SIZE, 0, stream>>>(x, dst, ne0, ne00, ne01, ne02);
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dim3 gridDim(num_blocks, ne1, ne2*ne3);
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pad_f32<<<gridDim, CUDA_PAD_BLOCK_SIZE, 0, stream>>>(x, dst, ne0, ne00, ne01, ne02, ne03);
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}
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static void arange_f32_cuda(float * dst, const int ne0, const float start, const float step, cudaStream_t stream) {
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int num_blocks = (ne0 + CUDA_ARANGE_BLOCK_SIZE - 1) / CUDA_ARANGE_BLOCK_SIZE;
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arange_f32<<<num_blocks, CUDA_ARANGE_BLOCK_SIZE, 0, stream>>>(dst, ne0, start, step);
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}
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static void timestep_embedding_f32_cuda(const float * x, float * dst, const int ne00, const int nb1,
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const int dim, const int max_period, cudaStream_t stream) {
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int half_ceil = (dim + 1) / 2;
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int num_blocks = (half_ceil + CUDA_TIMESTEP_EMBEDDING_BLOCK_SIZE - 1) / CUDA_TIMESTEP_EMBEDDING_BLOCK_SIZE;
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dim3 gridDim(num_blocks, ne00, 1);
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timestep_embedding_f32<<<gridDim, CUDA_TIMESTEP_EMBEDDING_BLOCK_SIZE, 0, stream>>>(x, dst, nb1, dim, max_period);
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}
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static void rms_norm_f32_cuda(const float * x, float * dst, const int ncols, const int nrows, const float eps, cudaStream_t stream) {
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@ -8443,8 +8500,8 @@ static void soft_max_f32_cuda(const float * x, const float * mask, const float *
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template <typename T>
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static void im2col_cuda(const float* x, T* dst,
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int IW, int IH, int OW, int OH, int KW, int KH, int IC,
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int batch, int batch_offset, int offset_delta,
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int64_t IW, int64_t IH, int64_t OW, int64_t OH, int64_t KW, int64_t KH, int64_t IC,
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int64_t batch, int64_t batch_offset, int64_t offset_delta,
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int s0,int s1,int p0,int p1,int d0,int d1, cudaStream_t stream) {
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const int parallel_elements = OW * KW * KH;
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const int num_blocks = (parallel_elements + CUDA_IM2COL_BLOCK_SIZE - 1) / CUDA_IM2COL_BLOCK_SIZE;
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@ -9123,7 +9180,7 @@ static void ggml_cuda_op_group_norm(
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int num_groups = dst->op_params[0];
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int group_size = src0->ne[0] * src0->ne[1] * ((src0->ne[2] + num_groups - 1) / num_groups);
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group_norm_f32_cuda(src0_dd, dst_dd, num_groups, group_size, src0->ne[0] * src0->ne[1] * src0->ne[2], main_stream);
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group_norm_f32_cuda(src0_dd, dst_dd, num_groups * src0->ne[3], group_size, ggml_nelements(src0), main_stream);
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(void) src1;
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(void) dst;
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@ -9156,7 +9213,7 @@ static void ggml_cuda_op_upscale(
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const int scale_factor = dst->op_params[0];
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upscale_f32_cuda(src0_dd, dst_dd, src0->ne[0], src0->ne[1], src0->ne[2], scale_factor, main_stream);
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upscale_f32_cuda(src0_dd, dst_dd, src0->ne[0], src0->ne[1], src0->ne[2], src0->ne[3], scale_factor, main_stream);
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(void) src1;
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(void) dst;
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@ -9172,8 +9229,49 @@ static void ggml_cuda_op_pad(
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GGML_ASSERT(src0->ne[3] == 1 && dst->ne[3] == 1); // just 3D tensors
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pad_f32_cuda(src0_dd, dst_dd,
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src0->ne[0], src0->ne[1], src0->ne[2],
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dst->ne[0], dst->ne[1], dst->ne[2], main_stream);
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src0->ne[0], src0->ne[1], src0->ne[2], src0->ne[3],
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dst->ne[0], dst->ne[1], dst->ne[2], dst->ne[3], main_stream);
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(void) src1;
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(void) dst;
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(void) src1_dd;
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}
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static void ggml_cuda_op_arange(
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const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst,
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const float * src0_dd, const float * src1_dd, float * dst_dd, cudaStream_t main_stream) {
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GGML_ASSERT(dst->type == GGML_TYPE_F32);
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float start;
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float stop;
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float step;
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memcpy(&start, (float *)dst->op_params + 0, sizeof(float));
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memcpy(&stop, (float *)dst->op_params + 1, sizeof(float));
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memcpy(&step, (float *)dst->op_params + 2, sizeof(float));
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int64_t steps = (int64_t)ceil((stop - start) / step);
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GGML_ASSERT(ggml_nelements(dst) == steps);
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arange_f32_cuda(dst_dd, dst->ne[0], start, step, main_stream);
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(void) src0;
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(void) src1;
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(void) src0_dd;
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(void) src1_dd;
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}
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static void ggml_cuda_op_timestep_embedding(
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const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst,
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const float * src0_dd, const float * src1_dd, float * dst_dd, cudaStream_t main_stream) {
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GGML_ASSERT(src0->type == GGML_TYPE_F32);
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GGML_ASSERT(dst->type == GGML_TYPE_F32);
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const int dim = dst->op_params[0];
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const int max_period = dst->op_params[1];
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timestep_embedding_f32_cuda(src0_dd, dst_dd, src0->ne[0], dst->nb[1], dim, max_period, main_stream);
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(void) src1;
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(void) dst;
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@ -10458,6 +10556,45 @@ static void ggml_cuda_pad(const ggml_tensor * src0, const ggml_tensor * src1, gg
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ggml_cuda_op_flatten(src0, src1, dst, ggml_cuda_op_pad);
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}
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static void ggml_cuda_arange(const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) {
|
||||
ggml_tensor_extra_gpu * dst_extra = (ggml_tensor_extra_gpu *) dst->extra;
|
||||
|
||||
const bool dst_on_device = dst->backend == GGML_BACKEND_TYPE_GPU;
|
||||
|
||||
// dd = data device
|
||||
float * src0_ddf = nullptr;
|
||||
float * src1_ddf = nullptr;
|
||||
float * dst_ddf = nullptr;
|
||||
|
||||
cuda_pool_alloc<float> dst_f;
|
||||
|
||||
ggml_cuda_set_device(g_main_device);
|
||||
cudaStream_t main_stream = g_cudaStreams[g_main_device][0];
|
||||
|
||||
if (dst_on_device) {
|
||||
dst_ddf = (float *) dst_extra->data_device[g_main_device];
|
||||
} else {
|
||||
dst_ddf = dst_f.alloc(ggml_nelements(dst));
|
||||
}
|
||||
|
||||
// do the computation
|
||||
ggml_cuda_op_arange(src0, src1, dst, src0_ddf, src1_ddf, dst_ddf, main_stream);
|
||||
CUDA_CHECK(cudaGetLastError());
|
||||
|
||||
// copy dst to host if necessary
|
||||
if (!dst_on_device) {
|
||||
CUDA_CHECK(cudaMemcpyAsync(dst->data, dst_ddf, ggml_nbytes(dst), cudaMemcpyDeviceToHost, main_stream));
|
||||
}
|
||||
|
||||
if (dst->backend == GGML_BACKEND_TYPE_CPU) {
|
||||
CUDA_CHECK(cudaDeviceSynchronize());
|
||||
}
|
||||
}
|
||||
|
||||
static void ggml_cuda_timestep_embedding(const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) {
|
||||
ggml_cuda_op_flatten(src0, src1, dst, ggml_cuda_op_timestep_embedding);
|
||||
}
|
||||
|
||||
static void ggml_cuda_rms_norm(const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) {
|
||||
ggml_cuda_op_flatten(src0, src1, dst, ggml_cuda_op_rms_norm);
|
||||
}
|
||||
|
|
@ -11358,6 +11495,12 @@ GGML_CALL bool ggml_cuda_compute_forward(struct ggml_compute_params * params, st
|
|||
case GGML_OP_PAD:
|
||||
func = ggml_cuda_pad;
|
||||
break;
|
||||
case GGML_OP_ARANGE:
|
||||
func = ggml_cuda_arange;
|
||||
break;
|
||||
case GGML_OP_TIMESTEP_EMBEDDING:
|
||||
func = ggml_cuda_timestep_embedding;
|
||||
break;
|
||||
case GGML_OP_LEAKY_RELU:
|
||||
func = ggml_cuda_leaky_relu;
|
||||
break;
|
||||
|
|
@ -12253,6 +12396,8 @@ GGML_CALL static bool ggml_backend_cuda_supports_op(ggml_backend_t backend, cons
|
|||
case GGML_OP_GROUP_NORM:
|
||||
case GGML_OP_UPSCALE:
|
||||
case GGML_OP_PAD:
|
||||
case GGML_OP_ARANGE:
|
||||
case GGML_OP_TIMESTEP_EMBEDDING:
|
||||
case GGML_OP_LEAKY_RELU:
|
||||
return true;
|
||||
default:
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue