introduce r10 and r11, for vloadunpackhd.
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1 changed files with 11 additions and 7 deletions
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@ -204,8 +204,10 @@ void GGML_5bit_Unpack_Unaligned (const uint8x16_t * q4, const uint8_t * q1, uint
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"vprefetch0\t(%[SRC1])\n\t" // Issue our memory requests first thing.
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"vprefetch0\t(%[SRC4])\n\t"
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"vprefetchenta\t(%[DST])\n\t"
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"mov\t%[SRC4],\t%%r9\n\t" // Load the address of the head of our 4-bit list.
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"mov\t%[DST],\t%%r8\n\t" // Load the address of the head of our destination list.
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"mov\t%[SRC4],\t%%r9\n\t" // Load the address of the head of our 4-bit list into r9, for vloadunpackld.
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"mov\t%[SRC4],\t%%r10\n\t" // Load the address of the head of our 4-bit list into r10-r11, for vloadunpackhd.
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"mov\t%[SRC4],\t%%r11\n\t"
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"mov\t$0,%%ecx\n\t" // Initialize our counter.
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"vpbroadcastd\t%[MASK]%{uint8%},\t%%zmm0\n\t" // Load our mask.
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"vpbroadcastd\t%[BIT5]%{uint8},\t%%zmm1\n\t" // Load the bit we want to add (conditionally).
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@ -220,13 +222,13 @@ void GGML_5bit_Unpack_Unaligned (const uint8x16_t * q4, const uint8_t * q1, uint
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"vptestmd\t%%zmm4,\t%%zmm2,\t%%k2\n\t" // Test to see if our selected bit is set.
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"vloadunpackld\t\t(%%r9)%{uint8%},\t%%zmm5\n\t" // Load our odd 4 bit sequences. note that it loads two 4 bit sequences into each zmm value.
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"vloadunpackhd\t\t16(%%r9)%{uint8%},\t%%zmm5\n\t" // Load our odd 4 bit sequences. note that it loads two 4 bit sequences into each zmm value.
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"vloadunpackhd\t\t16(%%r10)%{uint8%},\t%%zmm5\n\t" // Load our odd 4 bit sequences. note that it loads two 4 bit sequences into each zmm value.
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"vpandd\t%%zmm0,\t%%zmm5,\t%%zmm6\n\t" // Apply a mask, storing the first set of four bits into a vector.
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"vpord\t%%zmm1,%%zmm6,%%zmm6%{%%k1%}\n\t" // Turn on bit 5 for all values that passed the prior test.
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"vmovdqa32\t\t%%zmm6%{uint8%},\t(%%r8)\n\t" // Save our result.
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"vloadunpackld\t\t16(%%r9)%{uint8%},\t%%zmm7\n\t" // Load our odd 4 bit sequences. note that it loads two 4 bit sequences into each zmm value.
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"vloadunpackhd\t\t32(%%r9)%{uint8%},\t%%zmm7\n\t" // Load our odd 4 bit sequences. note that it loads two 4 bit sequences into each zmm value.
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"vloadunpackhd\t\t32(%%r11)%{uint8%},\t%%zmm7\n\t" // Load our odd 4 bit sequences. note that it loads two 4 bit sequences into each zmm value.
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"vprefetch1\t32(%%r9)\n\t" // Pull the next set of 4 bit sequences into the L2 cache.
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"vpandd\t%%zmm0,\t%%zmm7,\t%%zmm8\n\t" // Apply a mask, storing the next set of four bits into a vector.
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"vpord\t%%zmm1,%%zmm8,%%zmm8%{%%k2%}\n\t" // Turn on bit 5 for all values that passed the prior test.
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@ -237,8 +239,8 @@ void GGML_5bit_Unpack_Unaligned (const uint8x16_t * q4, const uint8_t * q1, uint
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"vpslld\t$1,\t%%zmm2,\t%%zmm2\n\t" // Select the next bit to test for.
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"vptestmd\t%%zmm3,\t%%zmm2,\t%%k1\n\t" // Perform our test.
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"vptestmd\t%%zmm4,\t%%zmm2,\t%%k2\n\t" // Perform our test.
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"vptestmd\t%%zmm3,\t%%zmm2,\t%%k1\n\t" // Test to see if our selected bit is set.
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"vptestmd\t%%zmm4,\t%%zmm2,\t%%k2\n\t" // Test to see if our selected bit is set.
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"vpsrld\t$4,\t%%zmm5,\t%%zmm6\n\t" // Load our even 4 bit sequence.
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"vpsrld\t$4,\t%%zmm7,\t%%zmm8\n\t" // Load our next even 4 bit sequence.
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"vpord\t%%zmm1,%%zmm6,%%zmm6%{%%k1%}\n\t" // Turn on bit 5 for all values that passed the prior test.
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@ -252,8 +254,10 @@ void GGML_5bit_Unpack_Unaligned (const uint8x16_t * q4, const uint8_t * q1, uint
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"vprefetch0\t32(%%r9)\n\t"
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"vprefetch1\t96(%%r9)\n\t"
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"vpslld\t$1,\t%%zmm2,\t%%zmm2\n\t" // Select the next bit to test for.
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"add\t$32,\t%%r9\n\t"
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"add\t$32,\t%%r8\n\t"
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"add\t$32,\t%%r9\n\t"
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"add\t$32,\t%%r10\n\t"
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"add\t$32,\t%%r11\n\t"
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"jmp\t1b\n\t"
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"2:"
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: [DST] "+r" (dst)
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@ -262,7 +266,7 @@ void GGML_5bit_Unpack_Unaligned (const uint8x16_t * q4, const uint8_t * q1, uint
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[MASK] "m" (lowmask),
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[M] "m" (m),
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[BIT5] "m" (bit5)
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: "zmm0", "zmm1", "zmm2", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "cc", "ecx", "k1", "k2", "r8", "r9", "memory");
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: "zmm0", "zmm1", "zmm2", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "cc", "ecx", "k1", "k2", "r8", "r9", "r10", "r11", "memory");
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}
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// A function for getting the dot product of two vectors, one of 5 bit resolution, and one of 8.
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