64 lines
2 KiB
Text
64 lines
2 KiB
Text
#include "common.cuh"
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#include "count-equal.cuh"
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#include <cstdint>
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template <typename T>
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static __global__ void count_equal(const T * __restrict__ x, const T * __restrict__ y, int64_t * __restrict__ dst, const int64_t dk, const int64_t k) {
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const int64_t i0 = (int64_t) blockIdx.x*dk;
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const int64_t i1 = min(i0 + dk, k);
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int nequal = 0;
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for (int64_t i = i0 + threadIdx.x; i < i1; i += WARP_SIZE) {
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const T xi = x[i];
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const T yi = y[i];
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nequal += xi == yi;
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}
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nequal = warp_reduce_sum(nequal);
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if (threadIdx.x != 0) {
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return;
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}
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atomicAdd((int *) dst, nequal);
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}
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void ggml_cuda_count_equal(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
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const ggml_tensor * src0 = dst->src[0];
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const ggml_tensor * src1 = dst->src[1];
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GGML_ASSERT(src0->type == src1->type);
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GGML_ASSERT( dst->type == GGML_TYPE_I64);
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GGML_ASSERT(ggml_are_same_shape(src0, src1));
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GGML_ASSERT(ggml_is_contiguous(src0));
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GGML_ASSERT(ggml_is_contiguous(src1));
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GGML_ASSERT(ggml_is_contiguous(dst));
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int64_t * dst_d = (int64_t *) dst->data;
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cudaStream_t stream = ctx.stream();
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const int nsm = ggml_cuda_info().devices[ggml_cuda_get_device()].nsm;
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const int64_t ne = ggml_nelements(src0);
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GGML_ASSERT(ne < (1 << 30) && "atomicAdd implementation only supports int");
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const int64_t dne = GGML_PAD((ne + 4*nsm - 1) / (4*nsm), CUDA_COUNT_EQUAL_CHUNK_SIZE);
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CUDA_CHECK(cudaMemsetAsync(dst_d, 0, ggml_nbytes(dst), stream));
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const dim3 blocks_dim(WARP_SIZE, 1, 1);
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const dim3 blocks_num(std::min((int64_t)4*nsm, (ne + CUDA_COUNT_EQUAL_CHUNK_SIZE - 1)/CUDA_COUNT_EQUAL_CHUNK_SIZE), 1, 1);
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switch (src0->type) {
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case GGML_TYPE_I32: {
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const int * src0_d = (const int *) src0->data;
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const int * src1_d = (const int *) src1->data;
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count_equal<<<blocks_num, blocks_dim, 0, stream>>>(src0_d, src1_d, dst_d, dne, ne);
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} break;
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default:
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GGML_ASSERT(false);
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break;
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}
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}
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