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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright © 2006 - 2014 Intel Corporation .
2007-10-21 23:41:49 +00:00
*
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* Authors : David Woodhouse < dwmw2 @ infradead . org > ,
* Ashok Raj < ashok . raj @ intel . com > ,
* Shaohua Li < shaohua . li @ intel . com > ,
* Anil S Keshavamurthy < anil . s . keshavamurthy @ intel . com > ,
* Fenghua Yu < fenghua . yu @ intel . com >
2015-06-12 07:57:06 +00:00
* Joerg Roedel < jroedel @ suse . de >
2007-10-21 23:41:49 +00:00
*/
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# define pr_fmt(fmt) "DMAR: " fmt
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# define dev_fmt(fmt) pr_fmt(fmt)
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# include <linux/crash_dump.h>
# include <linux/dma-direct.h>
# include <linux/dmi.h>
# include <linux/memory.h>
# include <linux/pci.h>
# include <linux/pci-ats.h>
# include <linux/spinlock.h>
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# include <linux/syscore_ops.h>
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# include <linux/tboot.h>
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# include <uapi/linux/iommufd.h>
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# include "iommu.h"
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# include "../dma-iommu.h"
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# include "../irq_remapping.h"
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# include "../iommu-sva.h"
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# include "pasid.h"
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# include "cap_audit.h"
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# include "perfmon.h"
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# define ROOT_SIZE VTD_PAGE_SIZE
# define CONTEXT_SIZE VTD_PAGE_SIZE
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# define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
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# define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB)
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# define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
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# define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
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# define IOAPIC_RANGE_START (0xfee00000)
# define IOAPIC_RANGE_END (0xfeefffff)
# define IOVA_START_ADDR (0x1000)
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# define DEFAULT_DOMAIN_ADDRESS_WIDTH 57
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# define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << ((gaw) - VTD_PAGE_SHIFT)) - 1)
# define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << (gaw)) - 1)
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/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
to match . That way , we can use ' unsigned long ' for PFNs with impunity . */
# define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \
__DOMAIN_MAX_PFN ( gaw ) , ( unsigned long ) - 1 ) )
# define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
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/* IO virtual address start page frame number */
# define IOVA_START_PFN (1)
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# define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
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static void __init check_tylersburg_isoch ( void ) ;
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static int rwbf_quirk ;
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/*
* set to 1 to panic kernel if can ' t successfully enable VT - d
* ( used when kernel is launched w / TXT )
*/
static int force_on = 0 ;
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static int intel_iommu_tboot_noforce ;
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static int no_platform_optin ;
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# define ROOT_ENTRY_NR (VTD_PAGE_SIZE / sizeof(struct root_entry))
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/*
* Take a root_entry and return the Lower Context Table Pointer ( LCTP )
* if marked present .
*/
static phys_addr_t root_entry_lctp ( struct root_entry * re )
{
if ( ! ( re - > lo & 1 ) )
return 0 ;
return re - > lo & VTD_PAGE_MASK ;
}
/*
* Take a root_entry and return the Upper Context Table Pointer ( UCTP )
* if marked present .
*/
static phys_addr_t root_entry_uctp ( struct root_entry * re )
{
if ( ! ( re - > hi & 1 ) )
return 0 ;
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return re - > hi & VTD_PAGE_MASK ;
}
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static int device_rid_cmp_key ( const void * key , const struct rb_node * node )
{
struct device_domain_info * info =
rb_entry ( node , struct device_domain_info , node ) ;
const u16 * rid_lhs = key ;
if ( * rid_lhs < PCI_DEVID ( info - > bus , info - > devfn ) )
return - 1 ;
if ( * rid_lhs > PCI_DEVID ( info - > bus , info - > devfn ) )
return 1 ;
return 0 ;
}
static int device_rid_cmp ( struct rb_node * lhs , const struct rb_node * rhs )
{
struct device_domain_info * info =
rb_entry ( lhs , struct device_domain_info , node ) ;
u16 key = PCI_DEVID ( info - > bus , info - > devfn ) ;
return device_rid_cmp_key ( & key , rhs ) ;
}
/*
* Looks up an IOMMU - probed device using its source ID .
*
* Returns the pointer to the device if there is a match . Otherwise ,
* returns NULL .
*
* Note that this helper doesn ' t guarantee that the device won ' t be
* released by the iommu subsystem after being returned . The caller
* should use its own synchronization mechanism to avoid the device
* being released during its use if its possibly the case .
*/
struct device * device_rbtree_find ( struct intel_iommu * iommu , u16 rid )
{
struct device_domain_info * info = NULL ;
struct rb_node * node ;
unsigned long flags ;
spin_lock_irqsave ( & iommu - > device_rbtree_lock , flags ) ;
node = rb_find ( & rid , & iommu - > device_rbtree , device_rid_cmp_key ) ;
if ( node )
info = rb_entry ( node , struct device_domain_info , node ) ;
spin_unlock_irqrestore ( & iommu - > device_rbtree_lock , flags ) ;
return info ? info - > dev : NULL ;
}
static int device_rbtree_insert ( struct intel_iommu * iommu ,
struct device_domain_info * info )
{
struct rb_node * curr ;
unsigned long flags ;
spin_lock_irqsave ( & iommu - > device_rbtree_lock , flags ) ;
curr = rb_find_add ( & info - > node , & iommu - > device_rbtree , device_rid_cmp ) ;
spin_unlock_irqrestore ( & iommu - > device_rbtree_lock , flags ) ;
if ( WARN_ON ( curr ) )
return - EEXIST ;
return 0 ;
}
static void device_rbtree_remove ( struct device_domain_info * info )
{
struct intel_iommu * iommu = info - > iommu ;
unsigned long flags ;
spin_lock_irqsave ( & iommu - > device_rbtree_lock , flags ) ;
rb_erase ( & info - > node , & iommu - > device_rbtree ) ;
spin_unlock_irqrestore ( & iommu - > device_rbtree_lock , flags ) ;
}
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/*
* This domain is a statically identity mapping domain .
* 1. This domain creats a static 1 : 1 mapping to all usable memory .
* 2. It maps to each iommu if successful .
* 3. Each iommu mapps to this domain if successful .
*/
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static struct dmar_domain * si_domain ;
static int hw_pass_through = 1 ;
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struct dmar_rmrr_unit {
struct list_head list ; /* list of rmrr units */
struct acpi_dmar_header * hdr ; /* ACPI header */
u64 base_address ; /* reserved base address*/
u64 end_address ; /* reserved end address */
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struct dmar_dev_scope * devices ; /* target devices */
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int devices_cnt ; /* target device count */
} ;
struct dmar_atsr_unit {
struct list_head list ; /* list of ATSR units */
struct acpi_dmar_header * hdr ; /* ACPI header */
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struct dmar_dev_scope * devices ; /* target devices */
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int devices_cnt ; /* target device count */
u8 include_all : 1 ; /* include all ports */
} ;
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struct dmar_satc_unit {
struct list_head list ; /* list of SATC units */
struct acpi_dmar_header * hdr ; /* ACPI header */
struct dmar_dev_scope * devices ; /* target devices */
struct intel_iommu * iommu ; /* the corresponding iommu */
int devices_cnt ; /* target device count */
u8 atc_required : 1 ; /* ATS is required */
} ;
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static LIST_HEAD ( dmar_atsr_units ) ;
static LIST_HEAD ( dmar_rmrr_units ) ;
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static LIST_HEAD ( dmar_satc_units ) ;
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# define for_each_rmrr_units(rmrr) \
list_for_each_entry ( rmrr , & dmar_rmrr_units , list )
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static void intel_iommu_domain_free ( struct iommu_domain * domain ) ;
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int dmar_disabled = ! IS_ENABLED ( CONFIG_INTEL_IOMMU_DEFAULT_ON ) ;
int intel_iommu_sm = IS_ENABLED ( CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON ) ;
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int intel_iommu_enabled = 0 ;
EXPORT_SYMBOL_GPL ( intel_iommu_enabled ) ;
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static int dmar_map_gfx = 1 ;
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
static int intel_iommu_superpage = 1 ;
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static int iommu_identity_mapping ;
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static int iommu_skip_te_disable ;
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2015-09-09 10:58:59 +00:00
# define IDENTMAP_GFX 2
# define IDENTMAP_AZALIA 4
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const struct iommu_ops intel_iommu_ops ;
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static const struct iommu_dirty_ops intel_dirty_ops ;
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static bool translation_pre_enabled ( struct intel_iommu * iommu )
{
return ( iommu - > flags & VTD_FLAG_TRANS_PRE_ENABLED ) ;
}
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static void clear_translation_pre_enabled ( struct intel_iommu * iommu )
{
iommu - > flags & = ~ VTD_FLAG_TRANS_PRE_ENABLED ;
}
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static void init_translation_status ( struct intel_iommu * iommu )
{
u32 gsts ;
gsts = readl ( iommu - > reg + DMAR_GSTS_REG ) ;
if ( gsts & DMA_GSTS_TES )
iommu - > flags | = VTD_FLAG_TRANS_PRE_ENABLED ;
}
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static int __init intel_iommu_setup ( char * str )
{
if ( ! str )
return - EINVAL ;
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while ( * str ) {
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if ( ! strncmp ( str , " on " , 2 ) ) {
dmar_disabled = 0 ;
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pr_info ( " IOMMU enabled \n " ) ;
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} else if ( ! strncmp ( str , " off " , 3 ) ) {
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dmar_disabled = 1 ;
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no_platform_optin = 1 ;
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pr_info ( " IOMMU disabled \n " ) ;
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} else if ( ! strncmp ( str , " igfx_off " , 8 ) ) {
dmar_map_gfx = 0 ;
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pr_info ( " Disable GFX device mapping \n " ) ;
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} else if ( ! strncmp ( str , " forcedac " , 8 ) ) {
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pr_warn ( " intel_iommu=forcedac deprecated; use iommu.forcedac instead \n " ) ;
iommu_dma_forcedac = true ;
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} else if ( ! strncmp ( str , " strict " , 6 ) ) {
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pr_warn ( " intel_iommu=strict deprecated; use iommu.strict=1 instead \n " ) ;
2021-07-12 11:12:20 +00:00
iommu_set_dma_strict ( ) ;
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
} else if ( ! strncmp ( str , " sp_off " , 6 ) ) {
2015-06-12 07:57:06 +00:00
pr_info ( " Disable supported super page \n " ) ;
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
intel_iommu_superpage = 0 ;
2019-01-24 02:31:32 +00:00
} else if ( ! strncmp ( str , " sm_on " , 5 ) ) {
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pr_info ( " Enable scalable mode if hardware supports \n " ) ;
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intel_iommu_sm = 1 ;
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} else if ( ! strncmp ( str , " sm_off " , 6 ) ) {
pr_info ( " Scalable mode is disallowed \n " ) ;
intel_iommu_sm = 0 ;
2017-04-26 16:18:35 +00:00
} else if ( ! strncmp ( str , " tboot_noforce " , 13 ) ) {
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pr_info ( " Intel-IOMMU: not forcing on after tboot. This could expose security risk for tboot \n " ) ;
2017-04-26 16:18:35 +00:00
intel_iommu_tboot_noforce = 1 ;
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} else {
pr_notice ( " Unknown option - '%s' \n " , str ) ;
2007-10-21 23:41:49 +00:00
}
str + = strcspn ( str , " , " ) ;
while ( * str = = ' , ' )
str + + ;
}
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return 1 ;
2007-10-21 23:41:49 +00:00
}
__setup ( " intel_iommu= " , intel_iommu_setup ) ;
2023-01-23 20:35:59 +00:00
void * alloc_pgtable_page ( int node , gfp_t gfp )
Intel IOMMU: Avoid memory allocation failures in dma map api calls
Intel IOMMU driver needs memory during DMA map calls to setup its internal
page tables and for other data structures. As we all know that these DMA map
calls are mostly called in the interrupt context or with the spinlock held by
the upper level drivers(network/storage drivers), so in order to avoid any
memory allocation failure due to low memory issues, this patch makes memory
allocation by temporarily setting PF_MEMALLOC flags for the current task
before making memory allocation calls.
We evaluated mempools as a backup when kmem_cache_alloc() fails
and found that mempools are really not useful here because
1) We don't know for sure how much to reserve in advance
2) And mempools are not useful for GFP_ATOMIC case (as we call
memory alloc functions with GFP_ATOMIC)
(akpm: point 2 is wrong...)
With PF_MEMALLOC flag set in the current->flags, the VM subsystem avoids any
watermark checks before allocating memory thus guarantee'ing the memory till
the last free page. Further, looking at the code in mm/page_alloc.c in
__alloc_pages() function, looks like this flag is useful only in the
non-interrupt context.
If we are in the interrupt context and memory allocation in IOMMU driver fails
for some reason, then the DMA map api's will return failure and it is up to
the higher level drivers to retry. Suppose, if upper level driver programs
the controller with the buggy DMA virtual address, the IOMMU will block that
DMA transaction when that happens thus preventing any corruption to main
memory.
So far in our test scenario, we were unable to create any memory allocation
failure inside dma map api calls.
Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Cc: Andi Kleen <ak@suse.de>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Muli Ben-Yehuda <muli@il.ibm.com>
Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com>
Cc: Arjan van de Ven <arjan@infradead.org>
Cc: Ashok Raj <ashok.raj@intel.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Christoph Lameter <clameter@sgi.com>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-21 23:41:52 +00:00
{
2009-10-02 18:01:24 +00:00
struct page * page ;
void * vaddr = NULL ;
Intel IOMMU: Avoid memory allocation failures in dma map api calls
Intel IOMMU driver needs memory during DMA map calls to setup its internal
page tables and for other data structures. As we all know that these DMA map
calls are mostly called in the interrupt context or with the spinlock held by
the upper level drivers(network/storage drivers), so in order to avoid any
memory allocation failure due to low memory issues, this patch makes memory
allocation by temporarily setting PF_MEMALLOC flags for the current task
before making memory allocation calls.
We evaluated mempools as a backup when kmem_cache_alloc() fails
and found that mempools are really not useful here because
1) We don't know for sure how much to reserve in advance
2) And mempools are not useful for GFP_ATOMIC case (as we call
memory alloc functions with GFP_ATOMIC)
(akpm: point 2 is wrong...)
With PF_MEMALLOC flag set in the current->flags, the VM subsystem avoids any
watermark checks before allocating memory thus guarantee'ing the memory till
the last free page. Further, looking at the code in mm/page_alloc.c in
__alloc_pages() function, looks like this flag is useful only in the
non-interrupt context.
If we are in the interrupt context and memory allocation in IOMMU driver fails
for some reason, then the DMA map api's will return failure and it is up to
the higher level drivers to retry. Suppose, if upper level driver programs
the controller with the buggy DMA virtual address, the IOMMU will block that
DMA transaction when that happens thus preventing any corruption to main
memory.
So far in our test scenario, we were unable to create any memory allocation
failure inside dma map api calls.
Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Cc: Andi Kleen <ak@suse.de>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Muli Ben-Yehuda <muli@il.ibm.com>
Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com>
Cc: Arjan van de Ven <arjan@infradead.org>
Cc: Ashok Raj <ashok.raj@intel.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Christoph Lameter <clameter@sgi.com>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-21 23:41:52 +00:00
2023-01-23 20:35:59 +00:00
page = alloc_pages_node ( node , gfp | __GFP_ZERO , 0 ) ;
2009-10-02 18:01:24 +00:00
if ( page )
vaddr = page_address ( page ) ;
Intel IOMMU: Avoid memory allocation failures in dma map api calls
Intel IOMMU driver needs memory during DMA map calls to setup its internal
page tables and for other data structures. As we all know that these DMA map
calls are mostly called in the interrupt context or with the spinlock held by
the upper level drivers(network/storage drivers), so in order to avoid any
memory allocation failure due to low memory issues, this patch makes memory
allocation by temporarily setting PF_MEMALLOC flags for the current task
before making memory allocation calls.
We evaluated mempools as a backup when kmem_cache_alloc() fails
and found that mempools are really not useful here because
1) We don't know for sure how much to reserve in advance
2) And mempools are not useful for GFP_ATOMIC case (as we call
memory alloc functions with GFP_ATOMIC)
(akpm: point 2 is wrong...)
With PF_MEMALLOC flag set in the current->flags, the VM subsystem avoids any
watermark checks before allocating memory thus guarantee'ing the memory till
the last free page. Further, looking at the code in mm/page_alloc.c in
__alloc_pages() function, looks like this flag is useful only in the
non-interrupt context.
If we are in the interrupt context and memory allocation in IOMMU driver fails
for some reason, then the DMA map api's will return failure and it is up to
the higher level drivers to retry. Suppose, if upper level driver programs
the controller with the buggy DMA virtual address, the IOMMU will block that
DMA transaction when that happens thus preventing any corruption to main
memory.
So far in our test scenario, we were unable to create any memory allocation
failure inside dma map api calls.
Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Cc: Andi Kleen <ak@suse.de>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Muli Ben-Yehuda <muli@il.ibm.com>
Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com>
Cc: Arjan van de Ven <arjan@infradead.org>
Cc: Ashok Raj <ashok.raj@intel.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Christoph Lameter <clameter@sgi.com>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-21 23:41:52 +00:00
return vaddr ;
2007-10-21 23:41:49 +00:00
}
2018-07-14 07:46:57 +00:00
void free_pgtable_page ( void * vaddr )
2007-10-21 23:41:49 +00:00
{
free_page ( ( unsigned long ) vaddr ) ;
}
2023-12-18 07:34:45 +00:00
static int domain_type_is_si ( struct dmar_domain * domain )
2015-07-21 12:45:31 +00:00
{
2021-10-14 05:38:33 +00:00
return domain - > domain . type = = IOMMU_DOMAIN_IDENTITY ;
2015-07-21 12:45:31 +00:00
}
2023-12-18 07:34:45 +00:00
static int domain_pfn_supported ( struct dmar_domain * domain , unsigned long pfn )
2014-07-11 06:19:35 +00:00
{
int addr_width = agaw_to_width ( domain - > agaw ) - VTD_PAGE_SHIFT ;
return ! ( addr_width < BITS_PER_LONG & & pfn > > addr_width ) ;
}
2022-08-23 06:15:55 +00:00
/*
* Calculate the Supported Adjusted Guest Address Widths of an IOMMU .
* Refer to 11.4 .2 of the VT - d spec for the encoding of each bit of
* the returned SAGAW .
*/
static unsigned long __iommu_calculate_sagaw ( struct intel_iommu * iommu )
{
unsigned long fl_sagaw , sl_sagaw ;
2022-09-26 13:15:27 +00:00
fl_sagaw = BIT ( 2 ) | ( cap_fl5lp_support ( iommu - > cap ) ? BIT ( 3 ) : 0 ) ;
2022-08-23 06:15:55 +00:00
sl_sagaw = cap_sagaw ( iommu - > cap ) ;
/* Second level only. */
if ( ! sm_supported ( iommu ) | | ! ecap_flts ( iommu - > ecap ) )
return sl_sagaw ;
/* First level only. */
if ( ! ecap_slts ( iommu - > ecap ) )
return fl_sagaw ;
return fl_sagaw & sl_sagaw ;
}
2009-04-25 00:30:20 +00:00
static int __iommu_calculate_agaw ( struct intel_iommu * iommu , int max_gaw )
2008-12-08 07:34:06 +00:00
{
unsigned long sagaw ;
2021-06-10 02:00:53 +00:00
int agaw ;
2008-12-08 07:34:06 +00:00
2022-08-23 06:15:55 +00:00
sagaw = __iommu_calculate_sagaw ( iommu ) ;
for ( agaw = width_to_agaw ( max_gaw ) ; agaw > = 0 ; agaw - - ) {
2008-12-08 07:34:06 +00:00
if ( test_bit ( agaw , & sagaw ) )
break ;
}
return agaw ;
}
2009-04-25 00:30:20 +00:00
/*
* Calculate max SAGAW for each iommu .
*/
int iommu_calculate_max_sagaw ( struct intel_iommu * iommu )
{
return __iommu_calculate_agaw ( iommu , MAX_AGAW_WIDTH ) ;
}
/*
* calculate agaw for each iommu .
* " SAGAW " may be different across iommus , use a default agaw , and
* get a supported less agaw for iommus that don ' t support the default agaw .
*/
int iommu_calculate_agaw ( struct intel_iommu * iommu )
{
return __iommu_calculate_agaw ( iommu , DEFAULT_DOMAIN_ADDRESS_WIDTH ) ;
}
2023-12-18 07:34:45 +00:00
static bool iommu_paging_structure_coherency ( struct intel_iommu * iommu )
2020-06-22 23:13:44 +00:00
{
return sm_supported ( iommu ) ?
ecap_smpwc ( iommu - > ecap ) : ecap_coherent ( iommu - > ecap ) ;
}
2008-12-08 07:49:06 +00:00
static void domain_update_iommu_coherency ( struct dmar_domain * domain )
{
2022-07-12 00:09:05 +00:00
struct iommu_domain_info * info ;
2014-03-12 00:10:29 +00:00
struct dmar_drhd_unit * drhd ;
struct intel_iommu * iommu ;
2015-02-06 09:59:53 +00:00
bool found = false ;
2022-07-12 00:09:05 +00:00
unsigned long i ;
2011-11-12 00:26:44 +00:00
iommu/vt-d: Use bitfields for DMAR capabilities
IOTLB device presence, iommu coherency and snooping are boolean
capabilities. Use them as bits and keep them adjacent.
Structure layout before the reorg.
$ pahole -C dmar_domain drivers/iommu/intel/dmar.o
struct dmar_domain {
int nid; /* 0 4 */
unsigned int iommu_refcnt[128]; /* 4 512 */
/* --- cacheline 8 boundary (512 bytes) was 4 bytes ago --- */
u16 iommu_did[128]; /* 516 256 */
/* --- cacheline 12 boundary (768 bytes) was 4 bytes ago --- */
bool has_iotlb_device; /* 772 1 */
/* XXX 3 bytes hole, try to pack */
struct list_head devices; /* 776 16 */
struct list_head subdevices; /* 792 16 */
struct iova_domain iovad __attribute__((__aligned__(8)));
/* 808 2320 */
/* --- cacheline 48 boundary (3072 bytes) was 56 bytes ago --- */
struct dma_pte * pgd; /* 3128 8 */
/* --- cacheline 49 boundary (3136 bytes) --- */
int gaw; /* 3136 4 */
int agaw; /* 3140 4 */
int flags; /* 3144 4 */
int iommu_coherency; /* 3148 4 */
int iommu_snooping; /* 3152 4 */
int iommu_count; /* 3156 4 */
int iommu_superpage; /* 3160 4 */
/* XXX 4 bytes hole, try to pack */
u64 max_addr; /* 3168 8 */
u32 default_pasid; /* 3176 4 */
/* XXX 4 bytes hole, try to pack */
struct iommu_domain domain; /* 3184 72 */
/* size: 3256, cachelines: 51, members: 18 */
/* sum members: 3245, holes: 3, sum holes: 11 */
/* forced alignments: 1 */
/* last cacheline: 56 bytes */
} __attribute__((__aligned__(8)));
After arranging it for natural padding and to make flags as u8 bits, it
saves 8 bytes for the struct.
struct dmar_domain {
int nid; /* 0 4 */
unsigned int iommu_refcnt[128]; /* 4 512 */
/* --- cacheline 8 boundary (512 bytes) was 4 bytes ago --- */
u16 iommu_did[128]; /* 516 256 */
/* --- cacheline 12 boundary (768 bytes) was 4 bytes ago --- */
u8 has_iotlb_device:1; /* 772: 0 1 */
u8 iommu_coherency:1; /* 772: 1 1 */
u8 iommu_snooping:1; /* 772: 2 1 */
/* XXX 5 bits hole, try to pack */
/* XXX 3 bytes hole, try to pack */
struct list_head devices; /* 776 16 */
struct list_head subdevices; /* 792 16 */
struct iova_domain iovad __attribute__((__aligned__(8)));
/* 808 2320 */
/* --- cacheline 48 boundary (3072 bytes) was 56 bytes ago --- */
struct dma_pte * pgd; /* 3128 8 */
/* --- cacheline 49 boundary (3136 bytes) --- */
int gaw; /* 3136 4 */
int agaw; /* 3140 4 */
int flags; /* 3144 4 */
int iommu_count; /* 3148 4 */
int iommu_superpage; /* 3152 4 */
/* XXX 4 bytes hole, try to pack */
u64 max_addr; /* 3160 8 */
u32 default_pasid; /* 3168 4 */
/* XXX 4 bytes hole, try to pack */
struct iommu_domain domain; /* 3176 72 */
/* size: 3248, cachelines: 51, members: 18 */
/* sum members: 3236, holes: 3, sum holes: 11 */
/* sum bitfield members: 3 bits, bit holes: 1, sum bit holes: 5 bits */
/* forced alignments: 1 */
/* last cacheline: 48 bytes */
} __attribute__((__aligned__(8)));
Signed-off-by: Parav Pandit <parav@nvidia.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210530075053.264218-1-parav@nvidia.com
Link: https://lore.kernel.org/r/20210610020115.1637656-20-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-06-10 02:01:11 +00:00
domain - > iommu_coherency = true ;
2022-07-12 00:09:05 +00:00
xa_for_each ( & domain - > iommu_array , i , info ) {
2015-02-06 09:59:53 +00:00
found = true ;
2022-07-12 00:09:05 +00:00
if ( ! iommu_paging_structure_coherency ( info - > iommu ) ) {
iommu/vt-d: Use bitfields for DMAR capabilities
IOTLB device presence, iommu coherency and snooping are boolean
capabilities. Use them as bits and keep them adjacent.
Structure layout before the reorg.
$ pahole -C dmar_domain drivers/iommu/intel/dmar.o
struct dmar_domain {
int nid; /* 0 4 */
unsigned int iommu_refcnt[128]; /* 4 512 */
/* --- cacheline 8 boundary (512 bytes) was 4 bytes ago --- */
u16 iommu_did[128]; /* 516 256 */
/* --- cacheline 12 boundary (768 bytes) was 4 bytes ago --- */
bool has_iotlb_device; /* 772 1 */
/* XXX 3 bytes hole, try to pack */
struct list_head devices; /* 776 16 */
struct list_head subdevices; /* 792 16 */
struct iova_domain iovad __attribute__((__aligned__(8)));
/* 808 2320 */
/* --- cacheline 48 boundary (3072 bytes) was 56 bytes ago --- */
struct dma_pte * pgd; /* 3128 8 */
/* --- cacheline 49 boundary (3136 bytes) --- */
int gaw; /* 3136 4 */
int agaw; /* 3140 4 */
int flags; /* 3144 4 */
int iommu_coherency; /* 3148 4 */
int iommu_snooping; /* 3152 4 */
int iommu_count; /* 3156 4 */
int iommu_superpage; /* 3160 4 */
/* XXX 4 bytes hole, try to pack */
u64 max_addr; /* 3168 8 */
u32 default_pasid; /* 3176 4 */
/* XXX 4 bytes hole, try to pack */
struct iommu_domain domain; /* 3184 72 */
/* size: 3256, cachelines: 51, members: 18 */
/* sum members: 3245, holes: 3, sum holes: 11 */
/* forced alignments: 1 */
/* last cacheline: 56 bytes */
} __attribute__((__aligned__(8)));
After arranging it for natural padding and to make flags as u8 bits, it
saves 8 bytes for the struct.
struct dmar_domain {
int nid; /* 0 4 */
unsigned int iommu_refcnt[128]; /* 4 512 */
/* --- cacheline 8 boundary (512 bytes) was 4 bytes ago --- */
u16 iommu_did[128]; /* 516 256 */
/* --- cacheline 12 boundary (768 bytes) was 4 bytes ago --- */
u8 has_iotlb_device:1; /* 772: 0 1 */
u8 iommu_coherency:1; /* 772: 1 1 */
u8 iommu_snooping:1; /* 772: 2 1 */
/* XXX 5 bits hole, try to pack */
/* XXX 3 bytes hole, try to pack */
struct list_head devices; /* 776 16 */
struct list_head subdevices; /* 792 16 */
struct iova_domain iovad __attribute__((__aligned__(8)));
/* 808 2320 */
/* --- cacheline 48 boundary (3072 bytes) was 56 bytes ago --- */
struct dma_pte * pgd; /* 3128 8 */
/* --- cacheline 49 boundary (3136 bytes) --- */
int gaw; /* 3136 4 */
int agaw; /* 3140 4 */
int flags; /* 3144 4 */
int iommu_count; /* 3148 4 */
int iommu_superpage; /* 3152 4 */
/* XXX 4 bytes hole, try to pack */
u64 max_addr; /* 3160 8 */
u32 default_pasid; /* 3168 4 */
/* XXX 4 bytes hole, try to pack */
struct iommu_domain domain; /* 3176 72 */
/* size: 3248, cachelines: 51, members: 18 */
/* sum members: 3236, holes: 3, sum holes: 11 */
/* sum bitfield members: 3 bits, bit holes: 1, sum bit holes: 5 bits */
/* forced alignments: 1 */
/* last cacheline: 48 bytes */
} __attribute__((__aligned__(8)));
Signed-off-by: Parav Pandit <parav@nvidia.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210530075053.264218-1-parav@nvidia.com
Link: https://lore.kernel.org/r/20210610020115.1637656-20-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-06-10 02:01:11 +00:00
domain - > iommu_coherency = false ;
2008-12-08 07:49:06 +00:00
break ;
}
}
2014-03-12 00:10:29 +00:00
if ( found )
return ;
/* No hardware attached; use lowest common denominator */
rcu_read_lock ( ) ;
for_each_active_iommu ( iommu , drhd ) {
2020-06-22 23:13:44 +00:00
if ( ! iommu_paging_structure_coherency ( iommu ) ) {
iommu/vt-d: Use bitfields for DMAR capabilities
IOTLB device presence, iommu coherency and snooping are boolean
capabilities. Use them as bits and keep them adjacent.
Structure layout before the reorg.
$ pahole -C dmar_domain drivers/iommu/intel/dmar.o
struct dmar_domain {
int nid; /* 0 4 */
unsigned int iommu_refcnt[128]; /* 4 512 */
/* --- cacheline 8 boundary (512 bytes) was 4 bytes ago --- */
u16 iommu_did[128]; /* 516 256 */
/* --- cacheline 12 boundary (768 bytes) was 4 bytes ago --- */
bool has_iotlb_device; /* 772 1 */
/* XXX 3 bytes hole, try to pack */
struct list_head devices; /* 776 16 */
struct list_head subdevices; /* 792 16 */
struct iova_domain iovad __attribute__((__aligned__(8)));
/* 808 2320 */
/* --- cacheline 48 boundary (3072 bytes) was 56 bytes ago --- */
struct dma_pte * pgd; /* 3128 8 */
/* --- cacheline 49 boundary (3136 bytes) --- */
int gaw; /* 3136 4 */
int agaw; /* 3140 4 */
int flags; /* 3144 4 */
int iommu_coherency; /* 3148 4 */
int iommu_snooping; /* 3152 4 */
int iommu_count; /* 3156 4 */
int iommu_superpage; /* 3160 4 */
/* XXX 4 bytes hole, try to pack */
u64 max_addr; /* 3168 8 */
u32 default_pasid; /* 3176 4 */
/* XXX 4 bytes hole, try to pack */
struct iommu_domain domain; /* 3184 72 */
/* size: 3256, cachelines: 51, members: 18 */
/* sum members: 3245, holes: 3, sum holes: 11 */
/* forced alignments: 1 */
/* last cacheline: 56 bytes */
} __attribute__((__aligned__(8)));
After arranging it for natural padding and to make flags as u8 bits, it
saves 8 bytes for the struct.
struct dmar_domain {
int nid; /* 0 4 */
unsigned int iommu_refcnt[128]; /* 4 512 */
/* --- cacheline 8 boundary (512 bytes) was 4 bytes ago --- */
u16 iommu_did[128]; /* 516 256 */
/* --- cacheline 12 boundary (768 bytes) was 4 bytes ago --- */
u8 has_iotlb_device:1; /* 772: 0 1 */
u8 iommu_coherency:1; /* 772: 1 1 */
u8 iommu_snooping:1; /* 772: 2 1 */
/* XXX 5 bits hole, try to pack */
/* XXX 3 bytes hole, try to pack */
struct list_head devices; /* 776 16 */
struct list_head subdevices; /* 792 16 */
struct iova_domain iovad __attribute__((__aligned__(8)));
/* 808 2320 */
/* --- cacheline 48 boundary (3072 bytes) was 56 bytes ago --- */
struct dma_pte * pgd; /* 3128 8 */
/* --- cacheline 49 boundary (3136 bytes) --- */
int gaw; /* 3136 4 */
int agaw; /* 3140 4 */
int flags; /* 3144 4 */
int iommu_count; /* 3148 4 */
int iommu_superpage; /* 3152 4 */
/* XXX 4 bytes hole, try to pack */
u64 max_addr; /* 3160 8 */
u32 default_pasid; /* 3168 4 */
/* XXX 4 bytes hole, try to pack */
struct iommu_domain domain; /* 3176 72 */
/* size: 3248, cachelines: 51, members: 18 */
/* sum members: 3236, holes: 3, sum holes: 11 */
/* sum bitfield members: 3 bits, bit holes: 1, sum bit holes: 5 bits */
/* forced alignments: 1 */
/* last cacheline: 48 bytes */
} __attribute__((__aligned__(8)));
Signed-off-by: Parav Pandit <parav@nvidia.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210530075053.264218-1-parav@nvidia.com
Link: https://lore.kernel.org/r/20210610020115.1637656-20-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-06-10 02:01:11 +00:00
domain - > iommu_coherency = false ;
2014-03-12 00:10:29 +00:00
break ;
}
}
rcu_read_unlock ( ) ;
2008-12-08 07:49:06 +00:00
}
2020-01-02 00:18:20 +00:00
static int domain_update_iommu_superpage ( struct dmar_domain * domain ,
struct intel_iommu * skip )
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
{
2011-10-14 19:32:17 +00:00
struct dmar_drhd_unit * drhd ;
2014-07-11 06:19:37 +00:00
struct intel_iommu * iommu ;
2020-01-02 00:18:20 +00:00
int mask = 0x3 ;
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
2021-06-10 02:01:13 +00:00
if ( ! intel_iommu_superpage )
2014-07-11 06:19:37 +00:00
return 0 ;
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
2011-10-14 19:32:17 +00:00
/* set iommu_superpage to the smallest common denominator */
2014-02-19 06:07:34 +00:00
rcu_read_lock ( ) ;
2011-10-14 19:32:17 +00:00
for_each_active_iommu ( iommu , drhd ) {
2014-07-11 06:19:37 +00:00
if ( iommu ! = skip ) {
2022-11-22 00:29:49 +00:00
if ( domain & & domain - > use_first_level ) {
2020-01-02 00:18:20 +00:00
if ( ! cap_fl1gp_support ( iommu - > cap ) )
mask = 0x1 ;
} else {
mask & = cap_super_page_val ( iommu - > cap ) ;
}
2014-07-11 06:19:37 +00:00
if ( ! mask )
break ;
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
}
}
2014-02-19 06:07:34 +00:00
rcu_read_unlock ( ) ;
2014-07-11 06:19:37 +00:00
return fls ( mask ) ;
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
}
2020-09-22 06:08:43 +00:00
static int domain_update_device_node ( struct dmar_domain * domain )
{
struct device_domain_info * info ;
int nid = NUMA_NO_NODE ;
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unsigned long flags ;
2020-09-22 06:08:43 +00:00
2022-08-23 06:15:56 +00:00
spin_lock_irqsave ( & domain - > lock , flags ) ;
2020-09-22 06:08:43 +00:00
list_for_each_entry ( info , & domain - > devices , link ) {
/*
* There could possibly be multiple device numa nodes as devices
* within the same domain may sit behind different IOMMUs . There
* isn ' t perfect answer in such situation , so we select first
* come first served policy .
*/
nid = dev_to_node ( info - > dev ) ;
if ( nid ! = NUMA_NO_NODE )
break ;
}
2022-08-23 06:15:56 +00:00
spin_unlock_irqrestore ( & domain - > lock , flags ) ;
2020-09-22 06:08:43 +00:00
return nid ;
}
2021-07-20 02:06:13 +00:00
/* Return the super pagesize bitmap if supported. */
static unsigned long domain_super_pgsize_bitmap ( struct dmar_domain * domain )
{
unsigned long bitmap = 0 ;
/*
* 1 - level super page supports page size of 2 MiB , 2 - level super page
* supports page size of both 2 MiB and 1 GiB .
*/
if ( domain - > iommu_superpage = = 1 )
bitmap | = SZ_2M ;
else if ( domain - > iommu_superpage = = 2 )
bitmap | = SZ_2M | SZ_1G ;
return bitmap ;
}
2009-03-18 07:33:05 +00:00
/* Some capabilities may be different across iommus */
2023-10-26 04:42:13 +00:00
void domain_update_iommu_cap ( struct dmar_domain * domain )
2009-03-18 07:33:05 +00:00
{
domain_update_iommu_coherency ( domain ) ;
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domain - > iommu_superpage = domain_update_iommu_superpage ( domain , NULL ) ;
2020-09-22 06:08:43 +00:00
/*
* If RHSA is missing , we should default to the device numa domain
* as fall back .
*/
if ( domain - > nid = = NUMA_NO_NODE )
domain - > nid = domain_update_device_node ( domain ) ;
2020-11-24 08:20:55 +00:00
/*
* First - level translation restricts the input - address to a
* canonical address ( i . e . , address bits 63 : N have the same
* value as address bit [ N - 1 ] , where N is 48 - bits with 4 - level
* paging and 57 - bits with 5 - level paging ) . Hence , skip bit
* [ N - 1 ] .
*/
2022-11-22 00:29:49 +00:00
if ( domain - > use_first_level )
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domain - > domain . geometry . aperture_end = __DOMAIN_MAX_ADDR ( domain - > gaw - 1 ) ;
else
domain - > domain . geometry . aperture_end = __DOMAIN_MAX_ADDR ( domain - > gaw ) ;
2021-01-06 16:03:57 +00:00
2021-07-20 02:06:13 +00:00
domain - > domain . pgsize_bitmap | = domain_super_pgsize_bitmap ( domain ) ;
2021-01-06 16:03:57 +00:00
domain_update_iotlb ( domain ) ;
2009-03-18 07:33:05 +00:00
}
2018-09-12 00:11:36 +00:00
struct context_entry * iommu_context_addr ( struct intel_iommu * iommu , u8 bus ,
u8 devfn , int alloc )
2015-02-13 14:35:21 +00:00
{
struct root_entry * root = & iommu - > root_entry [ bus ] ;
struct context_entry * context ;
u64 * entry ;
2022-08-23 06:15:54 +00:00
/*
* Except that the caller requested to allocate a new entry ,
* returning a copied context entry makes no sense .
*/
if ( ! alloc & & context_copied ( iommu , bus , devfn ) )
return NULL ;
2015-08-25 08:54:28 +00:00
entry = & root - > lo ;
2018-12-10 01:58:55 +00:00
if ( sm_supported ( iommu ) ) {
2015-02-13 14:35:21 +00:00
if ( devfn > = 0x80 ) {
devfn - = 0x80 ;
entry = & root - > hi ;
}
devfn * = 2 ;
}
if ( * entry & 1 )
context = phys_to_virt ( * entry & VTD_PAGE_MASK ) ;
else {
unsigned long phy_addr ;
if ( ! alloc )
return NULL ;
2023-01-23 20:35:59 +00:00
context = alloc_pgtable_page ( iommu - > node , GFP_ATOMIC ) ;
2015-02-13 14:35:21 +00:00
if ( ! context )
return NULL ;
__iommu_flush_cache ( iommu , ( void * ) context , CONTEXT_SIZE ) ;
phy_addr = virt_to_phys ( ( void * ) context ) ;
* entry = phy_addr | 1 ;
__iommu_flush_cache ( iommu , entry , sizeof ( * entry ) ) ;
}
return & context [ devfn ] ;
}
2019-06-03 06:53:32 +00:00
/**
* is_downstream_to_pci_bridge - test if a device belongs to the PCI
* sub - hierarchy of a candidate PCI - PCI bridge
* @ dev : candidate PCI device belonging to @ bridge PCI sub - hierarchy
* @ bridge : the candidate PCI - PCI bridge
*
* Return : true if @ dev belongs to @ bridge PCI sub - hierarchy , else false .
*/
static bool
is_downstream_to_pci_bridge ( struct device * dev , struct device * bridge )
{
struct pci_dev * pdev , * pbridge ;
if ( ! dev_is_pci ( dev ) | | ! dev_is_pci ( bridge ) )
return false ;
pdev = to_pci_dev ( dev ) ;
pbridge = to_pci_dev ( bridge ) ;
if ( pbridge - > subordinate & &
pbridge - > subordinate - > number < = pdev - > bus - > number & &
pbridge - > subordinate - > busn_res . end > = pdev - > bus - > number )
return true ;
return false ;
}
2020-09-03 06:51:32 +00:00
static bool quirk_ioat_snb_local_iommu ( struct pci_dev * pdev )
{
struct dmar_drhd_unit * drhd ;
u32 vtbar ;
int rc ;
/* We know that this device on this chipset has its own IOMMU.
* If we find it under a different IOMMU , then the BIOS is lying
* to us . Hope that the IOMMU for this device is actually
* disabled , and it needs no translation . . .
*/
rc = pci_bus_read_config_dword ( pdev - > bus , PCI_DEVFN ( 0 , 0 ) , 0xb0 , & vtbar ) ;
if ( rc ) {
/* "can't" happen */
dev_info ( & pdev - > dev , " failed to run vt-d quirk \n " ) ;
return false ;
}
vtbar & = 0xffff0000 ;
/* we know that the this iommu should be at offset 0xa000 from vtbar */
drhd = dmar_find_matched_drhd_unit ( pdev ) ;
if ( ! drhd | | drhd - > reg_base_addr - vtbar ! = 0xa000 ) {
pr_warn_once ( FW_BUG " BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device \n " ) ;
add_taint ( TAINT_FIRMWARE_WORKAROUND , LOCKDEP_STILL_OK ) ;
return true ;
}
return false ;
}
static bool iommu_is_dummy ( struct intel_iommu * iommu , struct device * dev )
{
if ( ! iommu | | iommu - > drhd - > ignored )
return true ;
if ( dev_is_pci ( dev ) ) {
struct pci_dev * pdev = to_pci_dev ( dev ) ;
if ( pdev - > vendor = = PCI_VENDOR_ID_INTEL & &
pdev - > device = = PCI_DEVICE_ID_INTEL_IOAT_SNB & &
quirk_ioat_snb_local_iommu ( pdev ) )
return true ;
}
return false ;
}
2023-12-18 07:34:42 +00:00
static struct intel_iommu * device_lookup_iommu ( struct device * dev , u8 * bus , u8 * devfn )
2008-12-08 14:51:37 +00:00
{
struct dmar_drhd_unit * drhd = NULL ;
2020-07-24 01:49:21 +00:00
struct pci_dev * pdev = NULL ;
2014-02-19 06:07:32 +00:00
struct intel_iommu * iommu ;
2014-03-09 21:00:57 +00:00
struct device * tmp ;
2014-05-26 12:14:06 +00:00
u16 segment = 0 ;
2008-12-08 14:51:37 +00:00
int i ;
2020-09-03 06:51:32 +00:00
if ( ! dev )
2015-05-11 13:59:20 +00:00
return NULL ;
2014-03-09 21:00:57 +00:00
if ( dev_is_pci ( dev ) ) {
2016-10-21 22:32:05 +00:00
struct pci_dev * pf_pdev ;
2020-01-21 13:37:49 +00:00
pdev = pci_real_dma_dev ( to_pci_dev ( dev ) ) ;
2017-08-30 21:05:59 +00:00
2016-10-21 22:32:05 +00:00
/* VFs aren't listed in scope tables; we need to look up
* the PF instead to find the IOMMU . */
pf_pdev = pci_physfn ( pdev ) ;
dev = & pf_pdev - > dev ;
2014-03-09 21:00:57 +00:00
segment = pci_domain_nr ( pdev - > bus ) ;
2015-03-16 22:49:08 +00:00
} else if ( has_acpi_companion ( dev ) )
2014-03-09 21:00:57 +00:00
dev = & ACPI_COMPANION ( dev ) - > dev ;
2014-02-19 06:07:34 +00:00
rcu_read_lock ( ) ;
2020-09-03 06:51:32 +00:00
for_each_iommu ( iommu , drhd ) {
2014-03-09 21:00:57 +00:00
if ( pdev & & segment ! = drhd - > segment )
2009-04-04 00:45:37 +00:00
continue ;
2008-12-08 14:51:37 +00:00
2014-02-19 06:07:32 +00:00
for_each_active_dev_scope ( drhd - > devices ,
2014-03-09 21:00:57 +00:00
drhd - > devices_cnt , i , tmp ) {
if ( tmp = = dev ) {
2016-10-21 22:32:05 +00:00
/* For a VF use its original BDF# not that of the PF
* which we used for the IOMMU lookup . Strictly speaking
* we could do this for all PCI devices ; we only need to
* get the BDF # from the scope table for ACPI matches . */
2017-03-01 20:02:50 +00:00
if ( pdev & & pdev - > is_virtfn )
2016-10-21 22:32:05 +00:00
goto got_pdev ;
2020-07-24 01:49:21 +00:00
if ( bus & & devfn ) {
* bus = drhd - > devices [ i ] . bus ;
* devfn = drhd - > devices [ i ] . devfn ;
}
2014-02-19 06:07:32 +00:00
goto out ;
2014-03-09 21:00:57 +00:00
}
2019-06-03 06:53:32 +00:00
if ( is_downstream_to_pci_bridge ( dev , tmp ) )
2014-03-09 21:00:57 +00:00
goto got_pdev ;
2009-04-03 23:39:25 +00:00
}
2008-12-08 14:51:37 +00:00
2014-03-09 21:00:57 +00:00
if ( pdev & & drhd - > include_all ) {
2022-03-01 02:01:55 +00:00
got_pdev :
2020-07-24 01:49:21 +00:00
if ( bus & & devfn ) {
* bus = pdev - > bus - > number ;
* devfn = pdev - > devfn ;
}
2014-02-19 06:07:32 +00:00
goto out ;
2014-03-09 21:00:57 +00:00
}
2008-12-08 14:51:37 +00:00
}
2014-02-19 06:07:32 +00:00
iommu = NULL ;
2022-03-01 02:01:55 +00:00
out :
2020-09-03 06:51:32 +00:00
if ( iommu_is_dummy ( iommu , dev ) )
iommu = NULL ;
2014-02-19 06:07:34 +00:00
rcu_read_unlock ( ) ;
2008-12-08 14:51:37 +00:00
2014-02-19 06:07:32 +00:00
return iommu ;
2008-12-08 14:51:37 +00:00
}
2008-12-08 15:00:00 +00:00
static void domain_flush_cache ( struct dmar_domain * domain ,
void * addr , int size )
{
if ( ! domain - > iommu_coherency )
clflush_cache_range ( addr , size ) ;
}
2007-10-21 23:41:49 +00:00
static void free_context_table ( struct intel_iommu * iommu )
{
struct context_entry * context ;
2022-07-12 00:08:55 +00:00
int i ;
if ( ! iommu - > root_entry )
return ;
2007-10-21 23:41:49 +00:00
for ( i = 0 ; i < ROOT_ENTRY_NR ; i + + ) {
2015-02-13 14:35:21 +00:00
context = iommu_context_addr ( iommu , i , 0 , 0 ) ;
2007-10-21 23:41:49 +00:00
if ( context )
free_pgtable_page ( context ) ;
2015-02-13 14:35:21 +00:00
2018-12-10 01:58:55 +00:00
if ( ! sm_supported ( iommu ) )
2015-02-13 14:35:21 +00:00
continue ;
context = iommu_context_addr ( iommu , i , 0x80 , 0 ) ;
if ( context )
free_pgtable_page ( context ) ;
2007-10-21 23:41:49 +00:00
}
2022-07-12 00:08:55 +00:00
2007-10-21 23:41:49 +00:00
free_pgtable_page ( iommu - > root_entry ) ;
iommu - > root_entry = NULL ;
}
2021-10-14 05:38:32 +00:00
# ifdef CONFIG_DMAR_DEBUG
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static void pgtable_walk ( struct intel_iommu * iommu , unsigned long pfn ,
u8 bus , u8 devfn , struct dma_pte * parent , int level )
2021-10-14 05:38:32 +00:00
{
2022-08-23 06:15:57 +00:00
struct dma_pte * pte ;
int offset ;
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while ( 1 ) {
offset = pfn_level_offset ( pfn , level ) ;
pte = & parent [ offset ] ;
if ( ! pte | | ( dma_pte_superpage ( pte ) | | ! dma_pte_present ( pte ) ) ) {
pr_info ( " PTE not present at level %d \n " , level ) ;
break ;
}
pr_info ( " pte level: %d, pte value: 0x%016llx \n " , level , pte - > val ) ;
if ( level = = 1 )
break ;
parent = phys_to_virt ( dma_pte_addr ( pte ) ) ;
level - - ;
}
}
void dmar_fault_dump_ptes ( struct intel_iommu * iommu , u16 source_id ,
unsigned long long addr , u32 pasid )
{
struct pasid_dir_entry * dir , * pde ;
struct pasid_entry * entries , * pte ;
struct context_entry * ctx_entry ;
struct root_entry * rt_entry ;
2022-08-23 06:15:57 +00:00
int i , dir_index , index , level ;
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u8 devfn = source_id & 0xff ;
u8 bus = source_id > > 8 ;
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struct dma_pte * pgtable ;
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pr_info ( " Dump %s table entries for IOVA 0x%llx \n " , iommu - > name , addr ) ;
/* root entry dump */
rt_entry = & iommu - > root_entry [ bus ] ;
if ( ! rt_entry ) {
pr_info ( " root table entry is not present \n " ) ;
return ;
}
if ( sm_supported ( iommu ) )
pr_info ( " scalable mode root entry: hi 0x%016llx, low 0x%016llx \n " ,
rt_entry - > hi , rt_entry - > lo ) ;
else
pr_info ( " root entry: 0x%016llx " , rt_entry - > lo ) ;
/* context entry dump */
ctx_entry = iommu_context_addr ( iommu , bus , devfn , 0 ) ;
if ( ! ctx_entry ) {
pr_info ( " context table entry is not present \n " ) ;
return ;
}
pr_info ( " context entry: hi 0x%016llx, low 0x%016llx \n " ,
ctx_entry - > hi , ctx_entry - > lo ) ;
/* legacy mode does not require PASID entries */
2022-08-23 06:15:57 +00:00
if ( ! sm_supported ( iommu ) ) {
level = agaw_to_level ( ctx_entry - > hi & 7 ) ;
pgtable = phys_to_virt ( ctx_entry - > lo & VTD_PAGE_MASK ) ;
2021-10-14 05:38:32 +00:00
goto pgtable_walk ;
2022-08-23 06:15:57 +00:00
}
2021-10-14 05:38:32 +00:00
/* get the pointer to pasid directory entry */
dir = phys_to_virt ( ctx_entry - > lo & VTD_PAGE_MASK ) ;
if ( ! dir ) {
pr_info ( " pasid directory entry is not present \n " ) ;
return ;
}
/* For request-without-pasid, get the pasid from context entry */
2023-03-22 20:08:02 +00:00
if ( intel_iommu_sm & & pasid = = IOMMU_PASID_INVALID )
2023-08-09 12:47:54 +00:00
pasid = IOMMU_NO_PASID ;
2021-10-14 05:38:32 +00:00
dir_index = pasid > > PASID_PDE_SHIFT ;
pde = & dir [ dir_index ] ;
pr_info ( " pasid dir entry: 0x%016llx \n " , pde - > val ) ;
/* get the pointer to the pasid table entry */
entries = get_pasid_table_from_pde ( pde ) ;
if ( ! entries ) {
pr_info ( " pasid table entry is not present \n " ) ;
return ;
}
index = pasid & PASID_PTE_MASK ;
pte = & entries [ index ] ;
for ( i = 0 ; i < ARRAY_SIZE ( pte - > val ) ; i + + )
pr_info ( " pasid table entry[%d]: 0x%016llx \n " , i , pte - > val [ i ] ) ;
2022-08-23 06:15:57 +00:00
if ( pasid_pte_get_pgtt ( pte ) = = PASID_ENTRY_PGTT_FL_ONLY ) {
level = pte - > val [ 2 ] & BIT_ULL ( 2 ) ? 5 : 4 ;
pgtable = phys_to_virt ( pte - > val [ 2 ] & VTD_PAGE_MASK ) ;
} else {
level = agaw_to_level ( ( pte - > val [ 0 ] > > 2 ) & 0x7 ) ;
pgtable = phys_to_virt ( pte - > val [ 0 ] & VTD_PAGE_MASK ) ;
}
2021-10-14 05:38:32 +00:00
pgtable_walk :
2022-08-23 06:15:57 +00:00
pgtable_walk ( iommu , addr > > VTD_PAGE_SHIFT , bus , devfn , pgtable , level ) ;
2021-10-14 05:38:32 +00:00
}
# endif
2009-06-28 09:37:25 +00:00
static struct dma_pte * pfn_to_dma_pte ( struct dmar_domain * domain ,
2023-01-23 20:36:00 +00:00
unsigned long pfn , int * target_level ,
gfp_t gfp )
2007-10-21 23:41:49 +00:00
{
2019-02-08 22:06:08 +00:00
struct dma_pte * parent , * pte ;
2007-10-21 23:41:49 +00:00
int level = agaw_to_level ( domain - > agaw ) ;
2011-10-14 19:32:46 +00:00
int offset ;
2007-10-21 23:41:49 +00:00
2014-07-11 06:19:35 +00:00
if ( ! domain_pfn_supported ( domain , pfn ) )
2013-10-09 08:03:52 +00:00
/* Address beyond IOMMU's addressing capabilities. */
return NULL ;
2007-10-21 23:41:49 +00:00
parent = domain - > pgd ;
2014-03-19 16:07:49 +00:00
while ( 1 ) {
2007-10-21 23:41:49 +00:00
void * tmp_page ;
2009-06-28 09:37:25 +00:00
offset = pfn_level_offset ( pfn , level ) ;
2007-10-21 23:41:49 +00:00
pte = & parent [ offset ] ;
2014-03-19 16:07:49 +00:00
if ( ! * target_level & & ( dma_pte_superpage ( pte ) | | ! dma_pte_present ( pte ) ) )
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
break ;
2014-03-19 16:07:49 +00:00
if ( level = = * target_level )
2007-10-21 23:41:49 +00:00
break ;
2008-11-21 16:56:53 +00:00
if ( ! dma_pte_present ( pte ) ) {
2009-07-01 18:21:24 +00:00
uint64_t pteval ;
2023-01-23 20:36:00 +00:00
tmp_page = alloc_pgtable_page ( domain - > nid , gfp ) ;
2007-10-21 23:41:49 +00:00
2009-07-01 18:30:28 +00:00
if ( ! tmp_page )
2007-10-21 23:41:49 +00:00
return NULL ;
2009-07-01 18:30:28 +00:00
2009-07-01 18:21:24 +00:00
domain_flush_cache ( domain , tmp_page , VTD_PAGE_SIZE ) ;
2009-09-17 01:05:55 +00:00
pteval = ( ( uint64_t ) virt_to_dma_pfn ( tmp_page ) < < VTD_PAGE_SHIFT ) | DMA_PTE_READ | DMA_PTE_WRITE ;
2022-11-22 00:29:49 +00:00
if ( domain - > use_first_level )
2022-11-16 05:15:43 +00:00
pteval | = DMA_FL_PTE_XD | DMA_FL_PTE_US | DMA_FL_PTE_ACCESS ;
2014-05-26 12:13:47 +00:00
if ( cmpxchg64 ( & pte - > val , 0ULL , pteval ) )
2009-07-01 18:21:24 +00:00
/* Someone else set it while we were thinking; use theirs. */
free_pgtable_page ( tmp_page ) ;
2014-05-26 12:13:47 +00:00
else
2009-07-01 18:21:24 +00:00
domain_flush_cache ( domain , pte , sizeof ( * pte ) ) ;
2007-10-21 23:41:49 +00:00
}
2014-03-19 16:07:49 +00:00
if ( level = = 1 )
break ;
2008-11-21 16:56:53 +00:00
parent = phys_to_virt ( dma_pte_addr ( pte ) ) ;
2007-10-21 23:41:49 +00:00
level - - ;
}
2014-03-19 16:07:49 +00:00
if ( ! * target_level )
* target_level = level ;
2007-10-21 23:41:49 +00:00
return pte ;
}
/* return address's pte at specific level */
2009-06-27 16:14:59 +00:00
static struct dma_pte * dma_pfn_level_pte ( struct dmar_domain * domain ,
unsigned long pfn ,
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
int level , int * large_page )
2007-10-21 23:41:49 +00:00
{
2019-02-08 22:06:08 +00:00
struct dma_pte * parent , * pte ;
2007-10-21 23:41:49 +00:00
int total = agaw_to_level ( domain - > agaw ) ;
int offset ;
parent = domain - > pgd ;
while ( level < = total ) {
2009-06-27 16:14:59 +00:00
offset = pfn_level_offset ( pfn , total ) ;
2007-10-21 23:41:49 +00:00
pte = & parent [ offset ] ;
if ( level = = total )
return pte ;
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
if ( ! dma_pte_present ( pte ) ) {
* large_page = total ;
2007-10-21 23:41:49 +00:00
break ;
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
}
2014-05-20 12:37:51 +00:00
if ( dma_pte_superpage ( pte ) ) {
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
* large_page = total ;
return pte ;
}
2008-11-21 16:56:53 +00:00
parent = phys_to_virt ( dma_pte_addr ( pte ) ) ;
2007-10-21 23:41:49 +00:00
total - - ;
}
return NULL ;
}
/* clear last level pte, a tlb flush should be followed */
2014-03-19 16:07:49 +00:00
static void dma_pte_clear_range ( struct dmar_domain * domain ,
2009-06-27 21:09:11 +00:00
unsigned long start_pfn ,
unsigned long last_pfn )
2007-10-21 23:41:49 +00:00
{
2019-02-08 22:06:08 +00:00
unsigned int large_page ;
2009-06-28 17:52:20 +00:00
struct dma_pte * first_pte , * pte ;
2009-06-27 18:00:32 +00:00
2023-04-13 04:06:40 +00:00
if ( WARN_ON ( ! domain_pfn_supported ( domain , last_pfn ) ) | |
WARN_ON ( start_pfn > last_pfn ) )
return ;
2007-10-21 23:41:49 +00:00
2009-06-27 18:15:01 +00:00
/* we don't need lock here; nobody else touches the iova range */
2009-09-19 14:36:28 +00:00
do {
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
large_page = 1 ;
first_pte = pte = dma_pfn_level_pte ( domain , start_pfn , 1 , & large_page ) ;
2009-06-28 17:52:20 +00:00
if ( ! pte ) {
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
start_pfn = align_to_level ( start_pfn + 1 , large_page + 1 ) ;
2009-06-28 17:52:20 +00:00
continue ;
}
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
do {
2009-06-28 17:52:20 +00:00
dma_clear_pte ( pte ) ;
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
start_pfn + = lvl_to_nr_pages ( large_page ) ;
2009-06-28 17:52:20 +00:00
pte + + ;
2009-07-02 10:21:16 +00:00
} while ( start_pfn < = last_pfn & & ! first_pte_in_page ( pte ) ) ;
2009-06-28 17:52:20 +00:00
domain_flush_cache ( domain , first_pte ,
( void * ) pte - ( void * ) first_pte ) ;
2009-09-19 14:36:28 +00:00
} while ( start_pfn & & start_pfn < = last_pfn ) ;
2007-10-21 23:41:49 +00:00
}
2013-06-15 16:27:19 +00:00
static void dma_pte_free_level ( struct dmar_domain * domain , int level ,
2017-06-29 02:42:23 +00:00
int retain_level , struct dma_pte * pte ,
unsigned long pfn , unsigned long start_pfn ,
unsigned long last_pfn )
2013-06-15 16:27:19 +00:00
{
pfn = max ( start_pfn , pfn ) ;
pte = & pte [ pfn_level_offset ( pfn , level ) ] ;
do {
unsigned long level_pfn ;
struct dma_pte * level_pte ;
if ( ! dma_pte_present ( pte ) | | dma_pte_superpage ( pte ) )
goto next ;
2017-01-31 03:11:11 +00:00
level_pfn = pfn & level_mask ( level ) ;
2013-06-15 16:27:19 +00:00
level_pte = phys_to_virt ( dma_pte_addr ( pte ) ) ;
2017-06-29 02:42:23 +00:00
if ( level > 2 ) {
dma_pte_free_level ( domain , level - 1 , retain_level ,
level_pte , level_pfn , start_pfn ,
last_pfn ) ;
}
2013-06-15 16:27:19 +00:00
2017-06-29 02:42:23 +00:00
/*
* Free the page table if we ' re below the level we want to
* retain and the range covers the entire table .
*/
if ( level < retain_level & & ! ( start_pfn > level_pfn | |
2014-01-21 23:48:18 +00:00
last_pfn < level_pfn + level_size ( level ) - 1 ) ) {
2013-06-15 16:27:19 +00:00
dma_clear_pte ( pte ) ;
domain_flush_cache ( domain , pte , sizeof ( * pte ) ) ;
free_pgtable_page ( level_pte ) ;
}
next :
pfn + = level_size ( level ) ;
} while ( ! first_pte_in_page ( + + pte ) & & pfn < = last_pfn ) ;
}
2017-06-29 02:42:23 +00:00
/*
* clear last level ( leaf ) ptes and free page table pages below the
* level we wish to keep intact .
*/
2007-10-21 23:41:49 +00:00
static void dma_pte_free_pagetable ( struct dmar_domain * domain ,
2009-06-27 23:27:49 +00:00
unsigned long start_pfn ,
2017-06-29 02:42:23 +00:00
unsigned long last_pfn ,
int retain_level )
2007-10-21 23:41:49 +00:00
{
2014-07-11 06:19:34 +00:00
dma_pte_clear_range ( domain , start_pfn , last_pfn ) ;
2009-06-30 02:40:07 +00:00
/* We don't need lock here; nobody else touches the iova range */
2017-06-29 02:42:23 +00:00
dma_pte_free_level ( domain , agaw_to_level ( domain - > agaw ) , retain_level ,
2013-06-15 16:27:19 +00:00
domain - > pgd , 0 , start_pfn , last_pfn ) ;
2009-06-27 21:41:00 +00:00
2007-10-21 23:41:49 +00:00
/* free pgd */
2009-06-27 23:27:49 +00:00
if ( start_pfn = = 0 & & last_pfn = = DOMAIN_MAX_PFN ( domain - > gaw ) ) {
2007-10-21 23:41:49 +00:00
free_pgtable_page ( domain - > pgd ) ;
domain - > pgd = NULL ;
}
}
2014-03-05 17:09:32 +00:00
/* When a page at a given level is being unlinked from its parent, we don't
need to * modify * it at all . All we need to do is make a list of all the
pages which can be freed just as soon as we ' ve flushed the IOTLB and we
know the hardware page - walk will no longer touch them .
The ' pte ' argument is the * parent * PTE , pointing to the page that is to
be freed . */
2021-12-17 15:31:00 +00:00
static void dma_pte_list_pagetables ( struct dmar_domain * domain ,
int level , struct dma_pte * pte ,
struct list_head * freelist )
2014-03-05 17:09:32 +00:00
{
struct page * pg ;
pg = pfn_to_page ( dma_pte_addr ( pte ) > > PAGE_SHIFT ) ;
2021-12-17 15:31:00 +00:00
list_add_tail ( & pg - > lru , freelist ) ;
2014-03-05 17:09:32 +00:00
if ( level = = 1 )
2021-12-17 15:31:00 +00:00
return ;
2014-03-05 17:09:32 +00:00
2014-04-09 02:20:39 +00:00
pte = page_address ( pg ) ;
do {
2014-03-05 17:09:32 +00:00
if ( dma_pte_present ( pte ) & & ! dma_pte_superpage ( pte ) )
2021-12-17 15:31:00 +00:00
dma_pte_list_pagetables ( domain , level - 1 , pte , freelist ) ;
2014-04-09 02:20:39 +00:00
pte + + ;
} while ( ! first_pte_in_page ( pte ) ) ;
2014-03-05 17:09:32 +00:00
}
2021-12-17 15:31:00 +00:00
static void dma_pte_clear_level ( struct dmar_domain * domain , int level ,
struct dma_pte * pte , unsigned long pfn ,
unsigned long start_pfn , unsigned long last_pfn ,
struct list_head * freelist )
2014-03-05 17:09:32 +00:00
{
struct dma_pte * first_pte = NULL , * last_pte = NULL ;
pfn = max ( start_pfn , pfn ) ;
pte = & pte [ pfn_level_offset ( pfn , level ) ] ;
do {
iommu/vt-d: Fix unmap_pages support
When supporting only the .map and .unmap callbacks of iommu_ops,
the IOMMU driver can make assumptions about the size and alignment
used for mappings based on the driver provided pgsize_bitmap. VT-d
previously used essentially PAGE_MASK for this bitmap as any power
of two mapping was acceptably filled by native page sizes.
However, with the .map_pages and .unmap_pages interface we're now
getting page-size and count arguments. If we simply combine these
as (page-size * count) and make use of the previous map/unmap
functions internally, any size and alignment assumptions are very
different.
As an example, a given vfio device assignment VM will often create
a 4MB mapping at IOVA pfn [0x3fe00 - 0x401ff]. On a system that
does not support IOMMU super pages, the unmap_pages interface will
ask to unmap 1024 4KB pages at the base IOVA. dma_pte_clear_level()
will recurse down to level 2 of the page table where the first half
of the pfn range exactly matches the entire pte level. We clear the
pte, increment the pfn by the level size, but (oops) the next pte is
on a new page, so we exit the loop an pop back up a level. When we
then update the pfn based on that higher level, we seem to assume
that the previous pfn value was at the start of the level. In this
case the level size is 256K pfns, which we add to the base pfn and
get a results of 0x7fe00, which is clearly greater than 0x401ff,
so we're done. Meanwhile we never cleared the ptes for the remainder
of the range. When the VM remaps this range, we're overwriting valid
ptes and the VT-d driver complains loudly, as reported by the user
report linked below.
The fix for this seems relatively simple, if each iteration of the
loop in dma_pte_clear_level() is assumed to clear to the end of the
level pte page, then our next pfn should be calculated from level_pfn
rather than our working pfn.
Fixes: 3f34f1259776 ("iommu/vt-d: Implement map/unmap_pages() iommu_ops callback")
Reported-by: Ajay Garg <ajaygargnsit@gmail.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Tested-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Link: https://lore.kernel.org/all/20211002124012.18186-1-ajaygargnsit@gmail.com/
Link: https://lore.kernel.org/r/163659074748.1617923.12716161410774184024.stgit@omen
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20211126135556.397932-3-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-11-26 13:55:56 +00:00
unsigned long level_pfn = pfn & level_mask ( level ) ;
2014-03-05 17:09:32 +00:00
if ( ! dma_pte_present ( pte ) )
goto next ;
/* If range covers entire pagetable, free it */
if ( start_pfn < = level_pfn & &
last_pfn > = level_pfn + level_size ( level ) - 1 ) {
/* These suborbinate page tables are going away entirely. Don't
bother to clear them ; we ' re just going to * free * them . */
if ( level > 1 & & ! dma_pte_superpage ( pte ) )
2021-12-17 15:31:00 +00:00
dma_pte_list_pagetables ( domain , level - 1 , pte , freelist ) ;
2014-03-05 17:09:32 +00:00
dma_clear_pte ( pte ) ;
if ( ! first_pte )
first_pte = pte ;
last_pte = pte ;
} else if ( level > 1 ) {
/* Recurse down into a level that isn't *entirely* obsolete */
2021-12-17 15:31:00 +00:00
dma_pte_clear_level ( domain , level - 1 ,
phys_to_virt ( dma_pte_addr ( pte ) ) ,
level_pfn , start_pfn , last_pfn ,
freelist ) ;
2014-03-05 17:09:32 +00:00
}
next :
iommu/vt-d: Fix unmap_pages support
When supporting only the .map and .unmap callbacks of iommu_ops,
the IOMMU driver can make assumptions about the size and alignment
used for mappings based on the driver provided pgsize_bitmap. VT-d
previously used essentially PAGE_MASK for this bitmap as any power
of two mapping was acceptably filled by native page sizes.
However, with the .map_pages and .unmap_pages interface we're now
getting page-size and count arguments. If we simply combine these
as (page-size * count) and make use of the previous map/unmap
functions internally, any size and alignment assumptions are very
different.
As an example, a given vfio device assignment VM will often create
a 4MB mapping at IOVA pfn [0x3fe00 - 0x401ff]. On a system that
does not support IOMMU super pages, the unmap_pages interface will
ask to unmap 1024 4KB pages at the base IOVA. dma_pte_clear_level()
will recurse down to level 2 of the page table where the first half
of the pfn range exactly matches the entire pte level. We clear the
pte, increment the pfn by the level size, but (oops) the next pte is
on a new page, so we exit the loop an pop back up a level. When we
then update the pfn based on that higher level, we seem to assume
that the previous pfn value was at the start of the level. In this
case the level size is 256K pfns, which we add to the base pfn and
get a results of 0x7fe00, which is clearly greater than 0x401ff,
so we're done. Meanwhile we never cleared the ptes for the remainder
of the range. When the VM remaps this range, we're overwriting valid
ptes and the VT-d driver complains loudly, as reported by the user
report linked below.
The fix for this seems relatively simple, if each iteration of the
loop in dma_pte_clear_level() is assumed to clear to the end of the
level pte page, then our next pfn should be calculated from level_pfn
rather than our working pfn.
Fixes: 3f34f1259776 ("iommu/vt-d: Implement map/unmap_pages() iommu_ops callback")
Reported-by: Ajay Garg <ajaygargnsit@gmail.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Tested-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Link: https://lore.kernel.org/all/20211002124012.18186-1-ajaygargnsit@gmail.com/
Link: https://lore.kernel.org/r/163659074748.1617923.12716161410774184024.stgit@omen
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20211126135556.397932-3-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-11-26 13:55:56 +00:00
pfn = level_pfn + level_size ( level ) ;
2014-03-05 17:09:32 +00:00
} while ( ! first_pte_in_page ( + + pte ) & & pfn < = last_pfn ) ;
if ( first_pte )
domain_flush_cache ( domain , first_pte ,
( void * ) + + last_pte - ( void * ) first_pte ) ;
}
/* We can't just free the pages because the IOMMU may still be walking
the page tables , and may have cached the intermediate levels . The
pages can only be freed after the IOTLB flush has been done . */
2021-12-17 15:31:00 +00:00
static void domain_unmap ( struct dmar_domain * domain , unsigned long start_pfn ,
unsigned long last_pfn , struct list_head * freelist )
2014-03-05 17:09:32 +00:00
{
2023-04-13 04:06:40 +00:00
if ( WARN_ON ( ! domain_pfn_supported ( domain , last_pfn ) ) | |
WARN_ON ( start_pfn > last_pfn ) )
return ;
2014-03-05 17:09:32 +00:00
/* we don't need lock here; nobody else touches the iova range */
2021-12-17 15:31:00 +00:00
dma_pte_clear_level ( domain , agaw_to_level ( domain - > agaw ) ,
domain - > pgd , 0 , start_pfn , last_pfn , freelist ) ;
2014-03-05 17:09:32 +00:00
/* free pgd */
if ( start_pfn = = 0 & & last_pfn = = DOMAIN_MAX_PFN ( domain - > gaw ) ) {
struct page * pgd_page = virt_to_page ( domain - > pgd ) ;
2021-12-17 15:31:00 +00:00
list_add_tail ( & pgd_page - > lru , freelist ) ;
2014-03-05 17:09:32 +00:00
domain - > pgd = NULL ;
}
}
2007-10-21 23:41:49 +00:00
/* iommu handling */
static int iommu_alloc_root_entry ( struct intel_iommu * iommu )
{
struct root_entry * root ;
2023-06-14 02:47:02 +00:00
root = alloc_pgtable_page ( iommu - > node , GFP_ATOMIC ) ;
2014-11-09 14:48:02 +00:00
if ( ! root ) {
2015-06-12 07:57:06 +00:00
pr_err ( " Allocating root entry for %s failed \n " ,
2014-11-09 14:48:02 +00:00
iommu - > name ) ;
2007-10-21 23:41:49 +00:00
return - ENOMEM ;
2014-11-09 14:48:02 +00:00
}
2007-10-21 23:41:49 +00:00
2008-10-17 01:02:32 +00:00
__iommu_flush_cache ( iommu , root , ROOT_SIZE ) ;
2007-10-21 23:41:49 +00:00
iommu - > root_entry = root ;
return 0 ;
}
static void iommu_set_root_entry ( struct intel_iommu * iommu )
{
2015-02-13 14:35:21 +00:00
u64 addr ;
2009-05-10 19:30:58 +00:00
u32 sts ;
2007-10-21 23:41:49 +00:00
unsigned long flag ;
2015-02-13 14:35:21 +00:00
addr = virt_to_phys ( iommu - > root_entry ) ;
2018-12-10 01:59:03 +00:00
if ( sm_supported ( iommu ) )
addr | = DMA_RTADDR_SMT ;
2007-10-21 23:41:49 +00:00
2011-07-19 14:19:51 +00:00
raw_spin_lock_irqsave ( & iommu - > register_lock , flag ) ;
2015-02-13 14:35:21 +00:00
dmar_writeq ( iommu - > reg + DMAR_RTADDR_REG , addr ) ;
2007-10-21 23:41:49 +00:00
2009-05-10 19:30:58 +00:00
writel ( iommu - > gcmd | DMA_GCMD_SRTP , iommu - > reg + DMAR_GCMD_REG ) ;
2007-10-21 23:41:49 +00:00
/* Make sure hardware complete it */
IOMMU_WAIT_OP ( iommu , DMAR_GSTS_REG ,
2009-05-10 19:30:58 +00:00
readl , ( sts & DMA_GSTS_RTPS ) , sts ) ;
2007-10-21 23:41:49 +00:00
2011-07-19 14:19:51 +00:00
raw_spin_unlock_irqrestore ( & iommu - > register_lock , flag ) ;
2021-03-20 02:54:13 +00:00
2022-09-26 13:15:29 +00:00
/*
* Hardware invalidates all DMA remapping hardware translation
* caches as part of SRTP flow .
*/
if ( cap_esrtps ( iommu - > cap ) )
return ;
2021-03-20 02:54:13 +00:00
iommu - > flush . flush_context ( iommu , 0 , 0 , 0 , DMA_CCMD_GLOBAL_INVL ) ;
if ( sm_supported ( iommu ) )
qi_flush_pasid_cache ( iommu , 0 , QI_PC_GLOBAL , 0 ) ;
iommu - > flush . flush_iotlb ( iommu , 0 , 0 , 0 , DMA_TLB_GLOBAL_FLUSH ) ;
2007-10-21 23:41:49 +00:00
}
2018-12-10 01:59:00 +00:00
void iommu_flush_write_buffer ( struct intel_iommu * iommu )
2007-10-21 23:41:49 +00:00
{
u32 val ;
unsigned long flag ;
2009-02-13 23:18:03 +00:00
if ( ! rwbf_quirk & & ! cap_rwbf ( iommu - > cap ) )
2007-10-21 23:41:49 +00:00
return ;
2011-07-19 14:19:51 +00:00
raw_spin_lock_irqsave ( & iommu - > register_lock , flag ) ;
2009-05-10 19:18:18 +00:00
writel ( iommu - > gcmd | DMA_GCMD_WBF , iommu - > reg + DMAR_GCMD_REG ) ;
2007-10-21 23:41:49 +00:00
/* Make sure hardware complete it */
IOMMU_WAIT_OP ( iommu , DMAR_GSTS_REG ,
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readl , ( ! ( val & DMA_GSTS_WBFS ) ) , val ) ;
2007-10-21 23:41:49 +00:00
2011-07-19 14:19:51 +00:00
raw_spin_unlock_irqrestore ( & iommu - > register_lock , flag ) ;
2007-10-21 23:41:49 +00:00
}
/* return value determine if we need a write buffer flush */
2009-05-10 16:16:06 +00:00
static void __iommu_flush_context ( struct intel_iommu * iommu ,
u16 did , u16 source_id , u8 function_mask ,
u64 type )
2007-10-21 23:41:49 +00:00
{
u64 val = 0 ;
unsigned long flag ;
switch ( type ) {
case DMA_CCMD_GLOBAL_INVL :
val = DMA_CCMD_GLOBAL_INVL ;
break ;
case DMA_CCMD_DOMAIN_INVL :
val = DMA_CCMD_DOMAIN_INVL | DMA_CCMD_DID ( did ) ;
break ;
case DMA_CCMD_DEVICE_INVL :
val = DMA_CCMD_DEVICE_INVL | DMA_CCMD_DID ( did )
| DMA_CCMD_SID ( source_id ) | DMA_CCMD_FM ( function_mask ) ;
break ;
default :
2023-04-13 04:06:41 +00:00
pr_warn ( " %s: Unexpected context-cache invalidation type 0x%llx \n " ,
iommu - > name , type ) ;
return ;
2007-10-21 23:41:49 +00:00
}
val | = DMA_CCMD_ICC ;
2011-07-19 14:19:51 +00:00
raw_spin_lock_irqsave ( & iommu - > register_lock , flag ) ;
2007-10-21 23:41:49 +00:00
dmar_writeq ( iommu - > reg + DMAR_CCMD_REG , val ) ;
/* Make sure hardware complete it */
IOMMU_WAIT_OP ( iommu , DMAR_CCMD_REG ,
dmar_readq , ( ! ( val & DMA_CCMD_ICC ) ) , val ) ;
2011-07-19 14:19:51 +00:00
raw_spin_unlock_irqrestore ( & iommu - > register_lock , flag ) ;
2007-10-21 23:41:49 +00:00
}
/* return value determine if we need a write buffer flush */
2009-05-10 18:58:49 +00:00
static void __iommu_flush_iotlb ( struct intel_iommu * iommu , u16 did ,
u64 addr , unsigned int size_order , u64 type )
2007-10-21 23:41:49 +00:00
{
int tlb_offset = ecap_iotlb_offset ( iommu - > ecap ) ;
u64 val = 0 , val_iva = 0 ;
unsigned long flag ;
switch ( type ) {
case DMA_TLB_GLOBAL_FLUSH :
/* global flush doesn't need set IVA_REG */
val = DMA_TLB_GLOBAL_FLUSH | DMA_TLB_IVT ;
break ;
case DMA_TLB_DSI_FLUSH :
val = DMA_TLB_DSI_FLUSH | DMA_TLB_IVT | DMA_TLB_DID ( did ) ;
break ;
case DMA_TLB_PSI_FLUSH :
val = DMA_TLB_PSI_FLUSH | DMA_TLB_IVT | DMA_TLB_DID ( did ) ;
2014-03-05 17:09:32 +00:00
/* IH bit is passed in as part of address */
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val_iva = size_order | addr ;
break ;
default :
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pr_warn ( " %s: Unexpected iotlb invalidation type 0x%llx \n " ,
iommu - > name , type ) ;
return ;
2007-10-21 23:41:49 +00:00
}
2023-06-14 02:47:05 +00:00
2007-10-21 23:41:49 +00:00
if ( cap_write_drain ( iommu - > cap ) )
val | = DMA_TLB_WRITE_DRAIN ;
2011-07-19 14:19:51 +00:00
raw_spin_lock_irqsave ( & iommu - > register_lock , flag ) ;
2007-10-21 23:41:49 +00:00
/* Note: Only uses first TLB reg currently */
if ( val_iva )
dmar_writeq ( iommu - > reg + tlb_offset , val_iva ) ;
dmar_writeq ( iommu - > reg + tlb_offset + 8 , val ) ;
/* Make sure hardware complete it */
IOMMU_WAIT_OP ( iommu , tlb_offset + 8 ,
dmar_readq , ( ! ( val & DMA_TLB_IVT ) ) , val ) ;
2011-07-19 14:19:51 +00:00
raw_spin_unlock_irqrestore ( & iommu - > register_lock , flag ) ;
2007-10-21 23:41:49 +00:00
/* check IOTLB invalidation granularity */
if ( DMA_TLB_IAIG ( val ) = = 0 )
2015-06-12 07:57:06 +00:00
pr_err ( " Flush IOTLB failed \n " ) ;
2007-10-21 23:41:49 +00:00
if ( DMA_TLB_IAIG ( val ) ! = DMA_TLB_IIRG ( type ) )
2015-06-12 07:57:06 +00:00
pr_debug ( " TLB flush request %Lx, actual %Lx \n " ,
2008-10-17 01:02:32 +00:00
( unsigned long long ) DMA_TLB_IIRG ( type ) ,
( unsigned long long ) DMA_TLB_IAIG ( val ) ) ;
2007-10-21 23:41:49 +00:00
}
2014-03-09 19:52:30 +00:00
static struct device_domain_info *
2022-09-26 13:15:25 +00:00
domain_lookup_dev_info ( struct dmar_domain * domain ,
struct intel_iommu * iommu , u8 bus , u8 devfn )
2009-05-18 05:51:37 +00:00
{
struct device_domain_info * info ;
2022-08-23 06:15:56 +00:00
unsigned long flags ;
2009-05-18 05:51:37 +00:00
2022-08-23 06:15:56 +00:00
spin_lock_irqsave ( & domain - > lock , flags ) ;
2022-07-12 00:09:01 +00:00
list_for_each_entry ( info , & domain - > devices , link ) {
2014-07-11 06:19:25 +00:00
if ( info - > iommu = = iommu & & info - > bus = = bus & &
info - > devfn = = devfn ) {
2022-08-23 06:15:56 +00:00
spin_unlock_irqrestore ( & domain - > lock , flags ) ;
2022-09-26 13:15:25 +00:00
return info ;
2009-05-18 05:51:37 +00:00
}
2022-07-12 00:09:01 +00:00
}
2022-08-23 06:15:56 +00:00
spin_unlock_irqrestore ( & domain - > lock , flags ) ;
2009-05-18 05:51:37 +00:00
2015-10-12 13:17:37 +00:00
return NULL ;
2009-05-18 05:51:37 +00:00
}
2024-02-19 11:15:55 +00:00
void domain_update_iotlb ( struct dmar_domain * domain )
2016-04-20 16:03:35 +00:00
{
2023-08-09 12:48:00 +00:00
struct dev_pasid_info * dev_pasid ;
2016-04-20 16:03:35 +00:00
struct device_domain_info * info ;
bool has_iotlb_device = false ;
2022-08-23 06:15:56 +00:00
unsigned long flags ;
2016-04-20 16:03:35 +00:00
2022-08-23 06:15:56 +00:00
spin_lock_irqsave ( & domain - > lock , flags ) ;
2022-07-12 00:09:01 +00:00
list_for_each_entry ( info , & domain - > devices , link ) {
2021-01-06 16:03:57 +00:00
if ( info - > ats_enabled ) {
2016-04-20 16:03:35 +00:00
has_iotlb_device = true ;
break ;
}
2022-07-12 00:09:01 +00:00
}
2023-08-09 12:48:00 +00:00
list_for_each_entry ( dev_pasid , & domain - > dev_pasids , link_domain ) {
info = dev_iommu_priv_get ( dev_pasid - > dev ) ;
if ( info - > ats_enabled ) {
has_iotlb_device = true ;
break ;
}
}
2016-04-20 16:03:35 +00:00
domain - > has_iotlb_device = has_iotlb_device ;
2022-08-23 06:15:56 +00:00
spin_unlock_irqrestore ( & domain - > lock , flags ) ;
2016-04-20 16:03:35 +00:00
}
2022-12-01 04:01:24 +00:00
/*
* The extra devTLB flush quirk impacts those QAT devices with PCI device
* IDs ranging from 0x4940 to 0x4943 . It is exempted from risky_device ( )
* check because it applies only to the built - in QAT devices and it doesn ' t
* grant additional privileges .
*/
2022-12-05 13:14:12 +00:00
# define BUGGY_QAT_DEVID_MASK 0x4940
2022-12-01 04:01:24 +00:00
static bool dev_needs_extra_dtlb_flush ( struct pci_dev * pdev )
{
if ( pdev - > vendor ! = PCI_VENDOR_ID_INTEL )
return false ;
if ( ( pdev - > device & 0xfffc ) ! = BUGGY_QAT_DEVID_MASK )
return false ;
return true ;
}
2022-09-26 13:15:25 +00:00
static void iommu_enable_pci_caps ( struct device_domain_info * info )
2007-10-21 23:41:49 +00:00
{
2015-07-20 14:10:36 +00:00
struct pci_dev * pdev ;
2022-11-22 00:29:44 +00:00
if ( ! dev_is_pci ( info - > dev ) )
2009-05-18 05:51:37 +00:00
return ;
2015-07-20 14:10:36 +00:00
pdev = to_pci_dev ( info - > dev ) ;
2015-10-12 13:17:37 +00:00
/* The PCIe spec, in its wisdom, declares that the behaviour of
the device if you enable PASID support after ATS support is
undefined . So always enable PASID support on devices which
have it , even if we can ' t yet know if we ' re ever going to
use it . */
if ( info - > pasid_supported & & ! pci_enable_pasid ( pdev , info - > pasid_supported & ~ 1 ) )
info - > pasid_enabled = 1 ;
2020-05-20 15:22:03 +00:00
if ( info - > ats_supported & & pci_ats_page_aligned ( pdev ) & &
2018-10-29 10:47:08 +00:00
! pci_enable_ats ( pdev , VTD_PAGE_SHIFT ) ) {
2015-10-12 13:17:37 +00:00
info - > ats_enabled = 1 ;
2016-04-20 16:03:35 +00:00
domain_update_iotlb ( info - > domain ) ;
2015-10-12 13:17:37 +00:00
}
2009-05-18 05:51:37 +00:00
}
2022-11-22 00:29:46 +00:00
static void iommu_disable_pci_caps ( struct device_domain_info * info )
2009-05-18 05:51:37 +00:00
{
2015-10-12 13:17:37 +00:00
struct pci_dev * pdev ;
2016-01-15 05:33:06 +00:00
if ( ! dev_is_pci ( info - > dev ) )
2009-05-18 05:51:37 +00:00
return ;
2015-10-12 13:17:37 +00:00
pdev = to_pci_dev ( info - > dev ) ;
if ( info - > ats_enabled ) {
pci_disable_ats ( pdev ) ;
info - > ats_enabled = 0 ;
2016-04-20 16:03:35 +00:00
domain_update_iotlb ( info - > domain ) ;
2015-10-12 13:17:37 +00:00
}
2022-09-26 13:15:25 +00:00
2015-10-12 13:17:37 +00:00
if ( info - > pasid_enabled ) {
pci_disable_pasid ( pdev ) ;
info - > pasid_enabled = 0 ;
}
2009-05-18 05:51:37 +00:00
}
2021-01-06 16:03:57 +00:00
static void __iommu_flush_dev_iotlb ( struct device_domain_info * info ,
u64 addr , unsigned int mask )
{
u16 sid , qdep ;
if ( ! info | | ! info - > ats_enabled )
return ;
sid = info - > bus < < 8 | info - > devfn ;
qdep = info - > ats_qdep ;
qi_flush_dev_iotlb ( info - > iommu , sid , info - > pfsid ,
qdep , addr , mask ) ;
2023-08-09 12:47:54 +00:00
quirk_extra_dev_tlb_flush ( info , addr , mask , IOMMU_NO_PASID , qdep ) ;
2021-01-06 16:03:57 +00:00
}
2009-05-18 05:51:37 +00:00
static void iommu_flush_dev_iotlb ( struct dmar_domain * domain ,
u64 addr , unsigned mask )
{
2023-08-09 12:48:00 +00:00
struct dev_pasid_info * dev_pasid ;
2009-05-18 05:51:37 +00:00
struct device_domain_info * info ;
2022-08-23 06:15:56 +00:00
unsigned long flags ;
2009-05-18 05:51:37 +00:00
2016-04-20 16:03:35 +00:00
if ( ! domain - > has_iotlb_device )
return ;
2022-08-23 06:15:56 +00:00
spin_lock_irqsave ( & domain - > lock , flags ) ;
2021-01-06 16:03:57 +00:00
list_for_each_entry ( info , & domain - > devices , link )
__iommu_flush_dev_iotlb ( info , addr , mask ) ;
2023-08-09 12:48:00 +00:00
list_for_each_entry ( dev_pasid , & domain - > dev_pasids , link_domain ) {
info = dev_iommu_priv_get ( dev_pasid - > dev ) ;
if ( ! info - > ats_enabled )
continue ;
qi_flush_dev_iotlb_pasid ( info - > iommu ,
PCI_DEVID ( info - > bus , info - > devfn ) ,
info - > pfsid , dev_pasid - > pasid ,
info - > ats_qdep , addr ,
mask ) ;
}
2022-08-23 06:15:56 +00:00
spin_unlock_irqrestore ( & domain - > lock , flags ) ;
2009-05-18 05:51:37 +00:00
}
2023-08-09 12:47:56 +00:00
static void domain_flush_pasid_iotlb ( struct intel_iommu * iommu ,
struct dmar_domain * domain , u64 addr ,
unsigned long npages , bool ih )
{
u16 did = domain_id_iommu ( domain , iommu ) ;
2023-08-09 12:48:00 +00:00
struct dev_pasid_info * dev_pasid ;
2023-08-09 12:47:56 +00:00
unsigned long flags ;
spin_lock_irqsave ( & domain - > lock , flags ) ;
2023-08-09 12:48:00 +00:00
list_for_each_entry ( dev_pasid , & domain - > dev_pasids , link_domain )
qi_flush_piotlb ( iommu , did , dev_pasid - > pasid , addr , npages , ih ) ;
2023-08-09 12:47:59 +00:00
if ( ! list_empty ( & domain - > devices ) )
qi_flush_piotlb ( iommu , did , IOMMU_NO_PASID , addr , npages , ih ) ;
2022-08-23 06:15:56 +00:00
spin_unlock_irqrestore ( & domain - > lock , flags ) ;
2009-05-18 05:51:37 +00:00
}
2024-02-19 11:15:53 +00:00
static void __iommu_flush_iotlb_psi ( struct intel_iommu * iommu , u16 did ,
unsigned long pfn , unsigned int pages ,
int ih )
{
unsigned int aligned_pages = __roundup_pow_of_two ( pages ) ;
unsigned long bitmask = aligned_pages - 1 ;
unsigned int mask = ilog2 ( aligned_pages ) ;
u64 addr = ( u64 ) pfn < < VTD_PAGE_SHIFT ;
/*
* PSI masks the low order bits of the base address . If the
* address isn ' t aligned to the mask , then compute a mask value
* needed to ensure the target range is flushed .
*/
if ( unlikely ( bitmask & pfn ) ) {
unsigned long end_pfn = pfn + pages - 1 , shared_bits ;
/*
* Since end_pfn < = pfn + bitmask , the only way bits
* higher than bitmask can differ in pfn and end_pfn is
* by carrying . This means after masking out bitmask ,
* high bits starting with the first set bit in
* shared_bits are all equal in both pfn and end_pfn .
*/
shared_bits = ~ ( pfn ^ end_pfn ) & ~ bitmask ;
mask = shared_bits ? __ffs ( shared_bits ) : BITS_PER_LONG ;
}
/*
* Fallback to domain selective flush if no PSI support or
* the size is too big .
*/
if ( ! cap_pgsel_inv ( iommu - > cap ) | | mask > cap_max_amask_val ( iommu - > cap ) )
iommu - > flush . flush_iotlb ( iommu , did , 0 , 0 ,
DMA_TLB_DSI_FLUSH ) ;
else
iommu - > flush . flush_iotlb ( iommu , did , addr | ih , mask ,
DMA_TLB_PSI_FLUSH ) ;
}
2015-07-21 13:20:32 +00:00
static void iommu_flush_iotlb_psi ( struct intel_iommu * iommu ,
struct dmar_domain * domain ,
unsigned long pfn , unsigned int pages ,
int ih , int map )
2007-10-21 23:41:49 +00:00
{
iommu/vt-d: Calculate mask for non-aligned flushes
Calculate the appropriate mask for non-size-aligned page selective
invalidation. Since psi uses the mask value to mask out the lower order
bits of the target address, properly flushing the iotlb requires using a
mask value such that [pfn, pfn+pages) all lie within the flushed
size-aligned region. This is not normally an issue because iova.c
always allocates iovas that are aligned to their size. However, iovas
which come from other sources (e.g. userspace via VFIO) may not be
aligned.
To properly flush the IOTLB, both the start and end pfns need to be
equal after applying the mask. That means that the most efficient mask
to use is the index of the lowest bit that is equal where all higher
bits are also equal. For example, if pfn=0x17f and pages=3, then
end_pfn=0x181, so the smallest mask we can use is 8. Any differences
above the highest bit of pages are due to carrying, so by xnor'ing pfn
and end_pfn and then masking out the lower order bits based on pages, we
get 0xffffff00, where the first set bit is the mask we want to use.
Fixes: 6fe1010d6d9c ("vfio/type1: DMA unmap chunking")
Cc: stable@vger.kernel.org
Signed-off-by: David Stevens <stevensd@chromium.org>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Link: https://lore.kernel.org/r/20220401022430.1262215-1-stevensd@google.com
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20220410013533.3959168-2-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2022-04-10 01:35:33 +00:00
unsigned int aligned_pages = __roundup_pow_of_two ( pages ) ;
unsigned int mask = ilog2 ( aligned_pages ) ;
2009-06-28 14:33:46 +00:00
uint64_t addr = ( uint64_t ) pfn < < VTD_PAGE_SHIFT ;
2022-07-12 00:09:05 +00:00
u16 did = domain_id_iommu ( domain , iommu ) ;
2007-10-21 23:41:49 +00:00
2023-04-13 04:06:41 +00:00
if ( WARN_ON ( ! pages ) )
return ;
2007-10-21 23:41:49 +00:00
2014-03-05 17:09:32 +00:00
if ( ih )
ih = 1 < < 6 ;
2020-01-02 00:18:18 +00:00
2024-02-19 11:15:53 +00:00
if ( domain - > use_first_level )
2023-08-09 12:47:56 +00:00
domain_flush_pasid_iotlb ( iommu , domain , addr , pages , ih ) ;
2024-02-19 11:15:53 +00:00
else
__iommu_flush_iotlb_psi ( iommu , did , pfn , pages , ih ) ;
2009-06-29 03:31:45 +00:00
/*
2010-04-01 10:24:40 +00:00
* In caching mode , changes of pages from non - present to present require
* flush . However , device IOTLB doesn ' t need to be flushed in this case .
2009-06-29 03:31:45 +00:00
*/
2010-04-01 10:24:40 +00:00
if ( ! cap_caching_mode ( iommu - > cap ) | | ! map )
iommu/vt-d: Use domain instead of cache fetching
after commit a1ddcbe93010 ("iommu/vt-d: Pass dmar_domain directly into
iommu_flush_iotlb_psi", 2015-08-12), we have domain pointer as parameter
to iommu_flush_iotlb_psi(), so no need to fetch it from cache again.
More importantly, a NULL reference pointer bug is reported on RHEL7 (and
it can be reproduced on some old upstream kernels too, e.g., v4.13) by
unplugging an 40g nic from a VM (hard to test unplug on real host, but
it should be the same):
https://bugzilla.redhat.com/show_bug.cgi?id=1531367
[ 24.391863] pciehp 0000:00:03.0:pcie004: Slot(0): Attention button pressed
[ 24.393442] pciehp 0000:00:03.0:pcie004: Slot(0): Powering off due to button press
[ 29.721068] i40evf 0000:01:00.0: Unable to send opcode 2 to PF, err I40E_ERR_QUEUE_EMPTY, aq_err OK
[ 29.783557] iommu: Removing device 0000:01:00.0 from group 3
[ 29.784662] BUG: unable to handle kernel NULL pointer dereference at 0000000000000304
[ 29.785817] IP: iommu_flush_iotlb_psi+0xcf/0x120
[ 29.786486] PGD 0
[ 29.786487] P4D 0
[ 29.786812]
[ 29.787390] Oops: 0000 [#1] SMP
[ 29.787876] Modules linked in: ip6t_rpfilter ip6t_REJECT nf_reject_ipv6 xt_conntrack ip_set nfnetlink ebtable_nat ebtable_broute bridge stp llc ip6table_ng
[ 29.795371] CPU: 0 PID: 156 Comm: kworker/0:2 Not tainted 4.13.0 #14
[ 29.796366] Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 1.11.0-1.el7 04/01/2014
[ 29.797593] Workqueue: pciehp-0 pciehp_power_thread
[ 29.798328] task: ffff94f5745b4a00 task.stack: ffffb326805ac000
[ 29.799178] RIP: 0010:iommu_flush_iotlb_psi+0xcf/0x120
[ 29.799919] RSP: 0018:ffffb326805afbd0 EFLAGS: 00010086
[ 29.800666] RAX: ffff94f5bc56e800 RBX: 0000000000000000 RCX: 0000000200000025
[ 29.801667] RDX: ffff94f5bc56e000 RSI: 0000000000000082 RDI: 0000000000000000
[ 29.802755] RBP: ffffb326805afbf8 R08: 0000000000000000 R09: ffff94f5bc86bbf0
[ 29.803772] R10: ffffb326805afba8 R11: 00000000000ffdc4 R12: ffff94f5bc86a400
[ 29.804789] R13: 0000000000000000 R14: 00000000ffdc4000 R15: 0000000000000000
[ 29.805792] FS: 0000000000000000(0000) GS:ffff94f5bfc00000(0000) knlGS:0000000000000000
[ 29.806923] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 29.807736] CR2: 0000000000000304 CR3: 000000003499d000 CR4: 00000000000006f0
[ 29.808747] Call Trace:
[ 29.809156] flush_unmaps_timeout+0x126/0x1c0
[ 29.809800] domain_exit+0xd6/0x100
[ 29.810322] device_notifier+0x6b/0x70
[ 29.810902] notifier_call_chain+0x4a/0x70
[ 29.812822] __blocking_notifier_call_chain+0x47/0x60
[ 29.814499] blocking_notifier_call_chain+0x16/0x20
[ 29.816137] device_del+0x233/0x320
[ 29.817588] pci_remove_bus_device+0x6f/0x110
[ 29.819133] pci_stop_and_remove_bus_device+0x1a/0x20
[ 29.820817] pciehp_unconfigure_device+0x7a/0x1d0
[ 29.822434] pciehp_disable_slot+0x52/0xe0
[ 29.823931] pciehp_power_thread+0x8a/0xa0
[ 29.825411] process_one_work+0x18c/0x3a0
[ 29.826875] worker_thread+0x4e/0x3b0
[ 29.828263] kthread+0x109/0x140
[ 29.829564] ? process_one_work+0x3a0/0x3a0
[ 29.831081] ? kthread_park+0x60/0x60
[ 29.832464] ret_from_fork+0x25/0x30
[ 29.833794] Code: 85 ed 74 0b 5b 41 5c 41 5d 41 5e 41 5f 5d c3 49 8b 54 24 60 44 89 f8 0f b6 c4 48 8b 04 c2 48 85 c0 74 49 45 0f b6 ff 4a 8b 3c f8 <80> bf
[ 29.838514] RIP: iommu_flush_iotlb_psi+0xcf/0x120 RSP: ffffb326805afbd0
[ 29.840362] CR2: 0000000000000304
[ 29.841716] ---[ end trace b10ec0d6900868d3 ]---
This patch fixes that problem if applied to v4.13 kernel.
The bug does not exist on latest upstream kernel since it's fixed as a
side effect of commit 13cf01744608 ("iommu/vt-d: Make use of iova
deferred flushing", 2017-08-15). But IMHO it's still good to have this
patch upstream.
CC: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Peter Xu <peterx@redhat.com>
Fixes: a1ddcbe93010 ("iommu/vt-d: Pass dmar_domain directly into iommu_flush_iotlb_psi")
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2018-01-10 05:51:37 +00:00
iommu_flush_dev_iotlb ( domain , addr , mask ) ;
2007-10-21 23:41:49 +00:00
}
2018-05-04 02:34:52 +00:00
/* Notification for newly created mappings */
2023-12-18 07:34:45 +00:00
static void __mapping_notify_one ( struct intel_iommu * iommu , struct dmar_domain * domain ,
unsigned long pfn , unsigned int pages )
2018-05-04 02:34:52 +00:00
{
2020-01-02 00:18:18 +00:00
/*
* It ' s a non - present to present mapping . Only flush if caching mode
* and second level .
*/
2022-11-22 00:29:49 +00:00
if ( cap_caching_mode ( iommu - > cap ) & & ! domain - > use_first_level )
2018-05-04 02:34:52 +00:00
iommu_flush_iotlb_psi ( iommu , domain , pfn , pages , 0 , 1 ) ;
else
iommu_flush_write_buffer ( iommu ) ;
}
2024-02-19 11:15:54 +00:00
/*
* Flush the relevant caches in nested translation if the domain
* also serves as a parent
*/
static void parent_domain_flush ( struct dmar_domain * domain ,
unsigned long pfn ,
unsigned long pages , int ih )
{
struct dmar_domain * s1_domain ;
spin_lock ( & domain - > s1_lock ) ;
list_for_each_entry ( s1_domain , & domain - > s1_domains , s2_link ) {
2024-02-19 11:15:56 +00:00
struct device_domain_info * device_info ;
2024-02-19 11:15:54 +00:00
struct iommu_domain_info * info ;
2024-02-19 11:15:56 +00:00
unsigned long flags ;
2024-02-19 11:15:54 +00:00
unsigned long i ;
xa_for_each ( & s1_domain - > iommu_array , i , info )
__iommu_flush_iotlb_psi ( info - > iommu , info - > did ,
pfn , pages , ih ) ;
2024-02-19 11:15:56 +00:00
if ( ! s1_domain - > has_iotlb_device )
continue ;
spin_lock_irqsave ( & s1_domain - > lock , flags ) ;
list_for_each_entry ( device_info , & s1_domain - > devices , link )
/*
* Address translation cache in device side caches the
* result of nested translation . There is no easy way
* to identify the exact set of nested translations
* affected by a change in S2 . So just flush the entire
* device cache .
*/
__iommu_flush_dev_iotlb ( device_info , 0 ,
MAX_AGAW_PFN_WIDTH ) ;
spin_unlock_irqrestore ( & s1_domain - > lock , flags ) ;
2024-02-19 11:15:54 +00:00
}
spin_unlock ( & domain - > s1_lock ) ;
}
2020-11-24 08:20:56 +00:00
static void intel_flush_iotlb_all ( struct iommu_domain * domain )
2017-08-11 09:40:10 +00:00
{
2020-11-24 08:20:56 +00:00
struct dmar_domain * dmar_domain = to_dmar_domain ( domain ) ;
2022-07-12 00:09:05 +00:00
struct iommu_domain_info * info ;
unsigned long idx ;
2017-08-11 09:40:10 +00:00
2022-07-12 00:09:05 +00:00
xa_for_each ( & dmar_domain - > iommu_array , idx , info ) {
struct intel_iommu * iommu = info - > iommu ;
u16 did = domain_id_iommu ( dmar_domain , iommu ) ;
2017-08-11 09:40:10 +00:00
2022-11-22 00:29:49 +00:00
if ( dmar_domain - > use_first_level )
2023-08-09 12:47:56 +00:00
domain_flush_pasid_iotlb ( iommu , dmar_domain , 0 , - 1 , 0 ) ;
2020-01-02 00:18:18 +00:00
else
iommu - > flush . flush_iotlb ( iommu , did , 0 , 0 ,
DMA_TLB_DSI_FLUSH ) ;
2017-08-11 09:40:10 +00:00
if ( ! cap_caching_mode ( iommu - > cap ) )
2022-03-01 02:01:48 +00:00
iommu_flush_dev_iotlb ( dmar_domain , 0 , MAX_AGAW_PFN_WIDTH ) ;
2017-08-11 09:40:10 +00:00
}
2024-02-19 11:15:54 +00:00
if ( dmar_domain - > nested_parent )
parent_domain_flush ( dmar_domain , 0 , - 1 , 0 ) ;
2017-08-11 09:40:10 +00:00
}
2008-02-08 12:18:38 +00:00
static void iommu_disable_protect_mem_regions ( struct intel_iommu * iommu )
{
u32 pmen ;
unsigned long flags ;
2019-03-20 01:58:33 +00:00
if ( ! cap_plmr ( iommu - > cap ) & & ! cap_phmr ( iommu - > cap ) )
return ;
2011-07-19 14:19:51 +00:00
raw_spin_lock_irqsave ( & iommu - > register_lock , flags ) ;
2008-02-08 12:18:38 +00:00
pmen = readl ( iommu - > reg + DMAR_PMEN_REG ) ;
pmen & = ~ DMA_PMEN_EPM ;
writel ( pmen , iommu - > reg + DMAR_PMEN_REG ) ;
/* wait for the protected region status bit to clear */
IOMMU_WAIT_OP ( iommu , DMAR_PMEN_REG ,
readl , ! ( pmen & DMA_PMEN_PRS ) , pmen ) ;
2011-07-19 14:19:51 +00:00
raw_spin_unlock_irqrestore ( & iommu - > register_lock , flags ) ;
2008-02-08 12:18:38 +00:00
}
2014-07-11 06:19:33 +00:00
static void iommu_enable_translation ( struct intel_iommu * iommu )
2007-10-21 23:41:49 +00:00
{
u32 sts ;
unsigned long flags ;
2011-07-19 14:19:51 +00:00
raw_spin_lock_irqsave ( & iommu - > register_lock , flags ) ;
2009-05-10 19:30:58 +00:00
iommu - > gcmd | = DMA_GCMD_TE ;
writel ( iommu - > gcmd , iommu - > reg + DMAR_GCMD_REG ) ;
2007-10-21 23:41:49 +00:00
/* Make sure hardware complete it */
IOMMU_WAIT_OP ( iommu , DMAR_GSTS_REG ,
2009-05-10 19:30:58 +00:00
readl , ( sts & DMA_GSTS_TES ) , sts ) ;
2007-10-21 23:41:49 +00:00
2011-07-19 14:19:51 +00:00
raw_spin_unlock_irqrestore ( & iommu - > register_lock , flags ) ;
2007-10-21 23:41:49 +00:00
}
2014-07-11 06:19:33 +00:00
static void iommu_disable_translation ( struct intel_iommu * iommu )
2007-10-21 23:41:49 +00:00
{
u32 sts ;
unsigned long flag ;
2020-07-23 01:34:37 +00:00
if ( iommu_skip_te_disable & & iommu - > drhd - > gfx_dedicated & &
( cap_read_drain ( iommu - > cap ) | | cap_write_drain ( iommu - > cap ) ) )
return ;
2011-07-19 14:19:51 +00:00
raw_spin_lock_irqsave ( & iommu - > register_lock , flag ) ;
2007-10-21 23:41:49 +00:00
iommu - > gcmd & = ~ DMA_GCMD_TE ;
writel ( iommu - > gcmd , iommu - > reg + DMAR_GCMD_REG ) ;
/* Make sure hardware complete it */
IOMMU_WAIT_OP ( iommu , DMAR_GSTS_REG ,
2009-05-10 19:30:58 +00:00
readl , ( ! ( sts & DMA_GSTS_TES ) ) , sts ) ;
2007-10-21 23:41:49 +00:00
2011-07-19 14:19:51 +00:00
raw_spin_unlock_irqrestore ( & iommu - > register_lock , flag ) ;
2007-10-21 23:41:49 +00:00
}
static int iommu_init_domains ( struct intel_iommu * iommu )
{
2021-12-17 08:38:14 +00:00
u32 ndomains ;
2007-10-21 23:41:49 +00:00
ndomains = cap_ndoms ( iommu - > cap ) ;
2015-07-21 08:41:21 +00:00
pr_debug ( " %s: Number of Domains supported <%d> \n " ,
2015-06-12 07:57:06 +00:00
iommu - > name , ndomains ) ;
2007-10-21 23:41:49 +00:00
2009-08-20 20:51:34 +00:00
spin_lock_init ( & iommu - > lock ) ;
2021-12-17 08:38:14 +00:00
iommu - > domain_ids = bitmap_zalloc ( ndomains , GFP_KERNEL ) ;
2021-08-18 13:48:45 +00:00
if ( ! iommu - > domain_ids )
2007-10-21 23:41:49 +00:00
return - ENOMEM ;
2015-07-21 08:41:21 +00:00
2007-10-21 23:41:49 +00:00
/*
2015-07-21 07:39:46 +00:00
* If Caching mode is set , then invalid translations are tagged
* with domain - id 0 , hence we need to pre - allocate it . We also
* use domain - id 0 as a marker for non - allocated domain - id , so
* make sure it is not used for a real domain .
2007-10-21 23:41:49 +00:00
*/
2015-07-21 07:39:46 +00:00
set_bit ( 0 , iommu - > domain_ids ) ;
2018-12-10 01:58:59 +00:00
/*
* Vt - d spec rev3 .0 ( section 6.2 .3 .1 ) requires that each pasid
* entry for first - level or pass - through translation modes should
* be programmed with a domain id different from those used for
* second - level or nested translation . We reserve a domain id for
* this purpose .
*/
if ( sm_supported ( iommu ) )
set_bit ( FLPT_DEFAULT_DID , iommu - > domain_ids ) ;
2007-10-21 23:41:49 +00:00
return 0 ;
}
2014-11-09 14:48:02 +00:00
static void disable_dmar_iommu ( struct intel_iommu * iommu )
2007-10-21 23:41:49 +00:00
{
2022-03-01 02:01:48 +00:00
if ( ! iommu - > domain_ids )
2015-07-21 15:17:12 +00:00
return ;
2014-02-19 06:07:30 +00:00
2022-07-12 00:08:53 +00:00
/*
* All iommu domains must have been detached from the devices ,
* hence there should be no domain IDs in use .
*/
if ( WARN_ON ( bitmap_weight ( iommu - > domain_ids , cap_ndoms ( iommu - > cap ) )
> NUM_RESERVED_DID ) )
return ;
2007-10-21 23:41:49 +00:00
if ( iommu - > gcmd & DMA_GCMD_TE )
iommu_disable_translation ( iommu ) ;
2014-11-09 14:48:02 +00:00
}
2007-10-21 23:41:49 +00:00
2014-11-09 14:48:02 +00:00
static void free_dmar_iommu ( struct intel_iommu * iommu )
{
2022-03-01 02:01:48 +00:00
if ( iommu - > domain_ids ) {
2021-12-17 08:38:14 +00:00
bitmap_free ( iommu - > domain_ids ) ;
2014-11-09 14:48:02 +00:00
iommu - > domain_ids = NULL ;
}
2007-10-21 23:41:49 +00:00
2022-08-23 06:15:54 +00:00
if ( iommu - > copied_tables ) {
bitmap_free ( iommu - > copied_tables ) ;
iommu - > copied_tables = NULL ;
}
2007-10-21 23:41:49 +00:00
/* free context mapping */
free_context_table ( iommu ) ;
2015-03-24 14:54:56 +00:00
# ifdef CONFIG_INTEL_IOMMU_SVM
2018-12-10 01:58:55 +00:00
if ( pasid_supported ( iommu ) ) {
2015-10-07 22:35:18 +00:00
if ( ecap_prs ( iommu - > ecap ) )
intel_svm_finish_prq ( iommu ) ;
}
2015-03-24 14:54:56 +00:00
# endif
2007-10-21 23:41:49 +00:00
}
2020-01-02 00:18:14 +00:00
/*
* Check and return whether first level is used by default for
2020-01-02 00:18:21 +00:00
* DMA translation .
2020-01-02 00:18:14 +00:00
*/
2021-10-14 05:38:35 +00:00
static bool first_level_by_default ( unsigned int type )
2020-01-02 00:18:14 +00:00
{
2021-10-14 05:38:35 +00:00
/* Only SL is available in legacy mode */
if ( ! scalable_mode_support ( ) )
return false ;
/* Only level (either FL or SL) is available, just use it */
if ( intel_cap_flts_sanity ( ) ^ intel_cap_slts_sanity ( ) )
return intel_cap_flts_sanity ( ) ;
/* Both levels are available, decide it based on domain type */
return type ! = IOMMU_DOMAIN_UNMANAGED ;
2020-01-02 00:18:14 +00:00
}
2021-10-14 05:38:33 +00:00
static struct dmar_domain * alloc_domain ( unsigned int type )
2007-10-21 23:41:49 +00:00
{
struct dmar_domain * domain ;
2022-03-01 02:01:51 +00:00
domain = kzalloc ( sizeof ( * domain ) , GFP_KERNEL ) ;
2007-10-21 23:41:49 +00:00
if ( ! domain )
return NULL ;
2019-03-05 23:42:58 +00:00
domain - > nid = NUMA_NO_NODE ;
2021-10-14 05:38:35 +00:00
if ( first_level_by_default ( type ) )
2022-11-22 00:29:49 +00:00
domain - > use_first_level = true ;
2016-04-20 16:03:35 +00:00
domain - > has_iotlb_device = false ;
2014-02-19 06:07:28 +00:00
INIT_LIST_HEAD ( & domain - > devices ) ;
2023-08-09 12:48:00 +00:00
INIT_LIST_HEAD ( & domain - > dev_pasids ) ;
2022-07-12 00:09:02 +00:00
spin_lock_init ( & domain - > lock ) ;
2022-07-12 00:09:05 +00:00
xa_init ( & domain - > iommu_array ) ;
2009-06-19 20:47:29 +00:00
return domain ;
}
2023-10-26 04:42:13 +00:00
int domain_attach_iommu ( struct dmar_domain * domain , struct intel_iommu * iommu )
2014-07-11 06:19:28 +00:00
{
2022-07-12 00:09:05 +00:00
struct iommu_domain_info * info , * curr ;
2014-07-11 06:19:29 +00:00
unsigned long ndomains ;
2022-07-12 00:09:05 +00:00
int num , ret = - ENOSPC ;
2014-07-11 06:19:29 +00:00
2022-07-12 00:09:05 +00:00
info = kzalloc ( sizeof ( * info ) , GFP_KERNEL ) ;
if ( ! info )
return - ENOMEM ;
2007-10-21 23:41:49 +00:00
2022-07-12 00:08:57 +00:00
spin_lock ( & iommu - > lock ) ;
2022-07-12 00:09:05 +00:00
curr = xa_load ( & domain - > iommu_array , iommu - > seq_id ) ;
if ( curr ) {
curr - > refcnt + + ;
spin_unlock ( & iommu - > lock ) ;
kfree ( info ) ;
return 0 ;
}
2015-07-22 09:52:53 +00:00
2022-07-12 00:09:05 +00:00
ndomains = cap_ndoms ( iommu - > cap ) ;
num = find_first_zero_bit ( iommu - > domain_ids , ndomains ) ;
if ( num > = ndomains ) {
pr_err ( " %s: No free domain ids \n " , iommu - > name ) ;
goto err_unlock ;
2014-07-11 06:19:28 +00:00
}
2007-10-21 23:41:49 +00:00
2022-07-12 00:09:05 +00:00
set_bit ( num , iommu - > domain_ids ) ;
info - > refcnt = 1 ;
info - > did = num ;
info - > iommu = iommu ;
curr = xa_cmpxchg ( & domain - > iommu_array , iommu - > seq_id ,
NULL , info , GFP_ATOMIC ) ;
if ( curr ) {
ret = xa_err ( curr ) ? : - EBUSY ;
goto err_clear ;
2014-07-11 06:19:28 +00:00
}
2022-07-12 00:09:05 +00:00
domain_update_iommu_cap ( domain ) ;
2015-07-22 09:52:53 +00:00
2022-07-12 00:08:57 +00:00
spin_unlock ( & iommu - > lock ) ;
2015-07-22 14:50:40 +00:00
return 0 ;
2022-07-12 00:09:05 +00:00
err_clear :
clear_bit ( info - > did , iommu - > domain_ids ) ;
err_unlock :
spin_unlock ( & iommu - > lock ) ;
kfree ( info ) ;
2022-07-12 00:08:57 +00:00
return ret ;
2014-07-11 06:19:28 +00:00
}
2023-10-26 04:42:13 +00:00
void domain_detach_iommu ( struct dmar_domain * domain , struct intel_iommu * iommu )
2014-07-11 06:19:28 +00:00
{
2022-07-12 00:09:05 +00:00
struct iommu_domain_info * info ;
2014-07-11 06:19:28 +00:00
2022-07-12 00:08:57 +00:00
spin_lock ( & iommu - > lock ) ;
2022-07-12 00:09:05 +00:00
info = xa_load ( & domain - > iommu_array , iommu - > seq_id ) ;
if ( - - info - > refcnt = = 0 ) {
clear_bit ( info - > did , iommu - > domain_ids ) ;
xa_erase ( & domain - > iommu_array , iommu - > seq_id ) ;
domain - > nid = NUMA_NO_NODE ;
2014-07-11 06:19:28 +00:00
domain_update_iommu_cap ( domain ) ;
2022-07-12 00:09:05 +00:00
kfree ( info ) ;
2014-07-11 06:19:28 +00:00
}
2022-07-12 00:08:57 +00:00
spin_unlock ( & iommu - > lock ) ;
2014-07-11 06:19:28 +00:00
}
2023-12-18 07:34:45 +00:00
static int guestwidth_to_adjustwidth ( int gaw )
2007-10-21 23:41:49 +00:00
{
int agaw ;
int r = ( gaw - 12 ) % 9 ;
if ( r = = 0 )
agaw = gaw ;
else
agaw = gaw + 9 - r ;
if ( agaw > 64 )
agaw = 64 ;
return agaw ;
}
static void domain_exit ( struct dmar_domain * domain )
{
2019-07-16 21:38:06 +00:00
if ( domain - > pgd ) {
2021-12-17 15:31:00 +00:00
LIST_HEAD ( freelist ) ;
2007-10-21 23:41:49 +00:00
2021-12-17 15:31:00 +00:00
domain_unmap ( domain , 0 , DOMAIN_MAX_PFN ( domain - > gaw ) , & freelist ) ;
put_pages_list ( & freelist ) ;
2019-07-16 21:38:06 +00:00
}
2014-03-05 17:09:32 +00:00
2022-07-12 00:08:59 +00:00
if ( WARN_ON ( ! list_empty ( & domain - > devices ) ) )
return ;
2022-03-01 02:01:51 +00:00
kfree ( domain ) ;
2007-10-21 23:41:49 +00:00
}
2018-12-10 01:59:03 +00:00
/*
* Get the PASID directory size for scalable mode context entry .
* Value of X in the PDTS field of a scalable mode context entry
* indicates PASID directory with 2 ^ ( X + 7 ) entries .
*/
2023-12-18 07:34:45 +00:00
static unsigned long context_get_sm_pds ( struct pasid_table * table )
2018-12-10 01:59:03 +00:00
{
2021-12-15 23:24:32 +00:00
unsigned long pds , max_pde ;
2018-12-10 01:59:03 +00:00
max_pde = table - > max_pasid > > PASID_PDE_SHIFT ;
2021-12-15 23:24:32 +00:00
pds = find_first_bit ( & max_pde , MAX_NR_PASID_BITS ) ;
2018-12-10 01:59:03 +00:00
if ( pds < 7 )
return 0 ;
return pds - 7 ;
}
2014-03-09 19:52:30 +00:00
static int domain_context_mapping_one ( struct dmar_domain * domain ,
struct intel_iommu * iommu ,
2018-12-10 01:59:02 +00:00
struct pasid_table * table ,
2015-07-21 12:45:31 +00:00
u8 bus , u8 devfn )
2007-10-21 23:41:49 +00:00
{
2022-07-12 00:09:01 +00:00
struct device_domain_info * info =
2022-09-26 13:15:25 +00:00
domain_lookup_dev_info ( domain , iommu , bus , devfn ) ;
2022-07-12 00:09:05 +00:00
u16 did = domain_id_iommu ( domain , iommu ) ;
2015-07-21 12:45:31 +00:00
int translation = CONTEXT_TT_MULTI_LEVEL ;
2007-10-21 23:41:49 +00:00
struct context_entry * context ;
2018-12-10 01:59:03 +00:00
int ret ;
2015-07-21 12:45:31 +00:00
if ( hw_pass_through & & domain_type_is_si ( domain ) )
translation = CONTEXT_TT_PASS_THROUGH ;
2007-10-21 23:41:49 +00:00
pr_debug ( " Set context mapping for %02x:%02x.%d \n " ,
bus , PCI_SLOT ( devfn ) , PCI_FUNC ( devfn ) ) ;
2009-04-25 00:30:20 +00:00
2015-07-22 14:50:40 +00:00
spin_lock ( & iommu - > lock ) ;
ret = - ENOMEM ;
2015-02-13 14:35:21 +00:00
context = iommu_context_addr ( iommu , bus , devfn , 1 ) ;
2007-10-21 23:41:49 +00:00
if ( ! context )
2015-07-22 14:50:40 +00:00
goto out_unlock ;
2007-10-21 23:41:49 +00:00
2015-07-22 14:50:40 +00:00
ret = 0 ;
2022-08-23 06:15:54 +00:00
if ( context_present ( context ) & & ! context_copied ( iommu , bus , devfn ) )
2015-07-22 14:50:40 +00:00
goto out_unlock ;
2015-06-12 10:21:46 +00:00
2016-12-05 12:09:07 +00:00
/*
* For kdump cases , old valid entries may be cached due to the
* in - flight DMA and copied pgtable , but there is no unmapping
* behaviour for them , thus we need an explicit cache flush for
* the newly - mapped device . For kdump , at this point , the device
* is supposed to finish reset at its driver probe stage , so no
* in - flight DMA will exist , and we don ' t need to worry anymore
* hereafter .
*/
2022-08-23 06:15:54 +00:00
if ( context_copied ( iommu , bus , devfn ) ) {
2016-12-05 12:09:07 +00:00
u16 did_old = context_domain_id ( context ) ;
2017-10-08 22:33:31 +00:00
if ( did_old < cap_ndoms ( iommu - > cap ) ) {
2016-12-05 12:09:07 +00:00
iommu - > flush . flush_context ( iommu , did_old ,
( ( ( u16 ) bus ) < < 8 ) | devfn ,
DMA_CCMD_MASK_NOBIT ,
DMA_CCMD_DEVICE_INVL ) ;
2017-05-05 18:39:59 +00:00
iommu - > flush . flush_iotlb ( iommu , did_old , 0 , 0 ,
DMA_TLB_DSI_FLUSH ) ;
}
2022-08-23 06:15:54 +00:00
clear_context_copied ( iommu , bus , devfn ) ;
2016-12-05 12:09:07 +00:00
}
2015-07-21 12:53:04 +00:00
context_clear_entry ( context ) ;
2008-12-08 15:08:15 +00:00
2018-12-10 01:59:03 +00:00
if ( sm_supported ( iommu ) ) {
unsigned long pds ;
2009-04-25 00:30:20 +00:00
2018-12-10 01:59:03 +00:00
/* Setup the PASID DIR pointer: */
pds = context_get_sm_pds ( table ) ;
context - > lo = ( u64 ) virt_to_phys ( table - > table ) |
context_pdts ( pds ) ;
/* Setup the RID_PASID field: */
2023-08-09 12:47:54 +00:00
context_set_sm_rid2pasid ( context , IOMMU_NO_PASID ) ;
2015-07-21 12:53:04 +00:00
/*
2018-12-10 01:59:03 +00:00
* Setup the Device - TLB enable bit and Page request
* Enable bit :
2015-07-21 12:53:04 +00:00
*/
2018-12-10 01:59:03 +00:00
if ( info & & info - > ats_supported )
context_set_sm_dte ( context ) ;
if ( info & & info - > pri_supported )
context_set_sm_pre ( context ) ;
2022-09-26 13:15:25 +00:00
if ( info & & info - > pasid_supported )
context_set_pasid ( context ) ;
2018-12-10 01:59:03 +00:00
} else {
struct dma_pte * pgd = domain - > pgd ;
int agaw ;
context_set_domain_id ( context , did ) ;
if ( translation ! = CONTEXT_TT_PASS_THROUGH ) {
/*
* Skip top levels of page tables for iommu which has
* less agaw than default . Unnecessary for PT mode .
*/
for ( agaw = domain - > agaw ; agaw > iommu - > agaw ; agaw - - ) {
ret = - ENOMEM ;
pgd = phys_to_virt ( dma_pte_addr ( pgd ) ) ;
if ( ! dma_pte_present ( pgd ) )
goto out_unlock ;
}
if ( info & & info - > ats_supported )
translation = CONTEXT_TT_DEV_IOTLB ;
else
translation = CONTEXT_TT_MULTI_LEVEL ;
context_set_address_root ( context , virt_to_phys ( pgd ) ) ;
context_set_address_width ( context , agaw ) ;
} else {
/*
* In pass through mode , AW must be programmed to
* indicate the largest AGAW value supported by
* hardware . And ASR is ignored by hardware .
*/
context_set_address_width ( context , iommu - > msagaw ) ;
}
2019-03-01 03:23:11 +00:00
context_set_translation_type ( context , translation ) ;
2009-05-18 05:51:37 +00:00
}
2009-04-25 00:30:20 +00:00
2008-11-21 16:54:46 +00:00
context_set_fault_enable ( context ) ;
context_set_present ( context ) ;
2020-06-22 23:13:44 +00:00
if ( ! ecap_coherent ( iommu - > ecap ) )
clflush_cache_range ( context , sizeof ( * context ) ) ;
2007-10-21 23:41:49 +00:00
2009-05-10 16:16:06 +00:00
/*
* It ' s a non - present to present mapping . If hardware doesn ' t cache
* non - present entry we only need to flush the write - buffer . If the
* _does_ cache non - present entries , then it does so in the special
* domain # 0 , which we have to flush :
*/
if ( cap_caching_mode ( iommu - > cap ) ) {
iommu - > flush . flush_context ( iommu , 0 ,
( ( ( u16 ) bus ) < < 8 ) | devfn ,
DMA_CCMD_MASK_NOBIT ,
DMA_CCMD_DEVICE_INVL ) ;
2015-07-22 11:11:53 +00:00
iommu - > flush . flush_iotlb ( iommu , did , 0 , 0 , DMA_TLB_DSI_FLUSH ) ;
2009-05-10 16:16:06 +00:00
} else {
2007-10-21 23:41:49 +00:00
iommu_flush_write_buffer ( iommu ) ;
2009-05-10 16:16:06 +00:00
}
2008-12-08 14:51:37 +00:00
2015-07-22 14:50:40 +00:00
ret = 0 ;
out_unlock :
spin_unlock ( & iommu - > lock ) ;
2014-07-11 06:19:28 +00:00
2016-07-13 13:53:21 +00:00
return ret ;
2007-10-21 23:41:49 +00:00
}
2019-08-26 08:50:56 +00:00
struct domain_context_mapping_data {
struct dmar_domain * domain ;
struct intel_iommu * iommu ;
struct pasid_table * table ;
} ;
static int domain_context_mapping_cb ( struct pci_dev * pdev ,
u16 alias , void * opaque )
{
struct domain_context_mapping_data * data = opaque ;
return domain_context_mapping_one ( data - > domain , data - > iommu ,
data - > table , PCI_BUS_NUM ( alias ) ,
alias & 0xff ) ;
}
2007-10-21 23:41:49 +00:00
static int
2015-07-21 12:45:31 +00:00
domain_context_mapping ( struct dmar_domain * domain , struct device * dev )
2007-10-21 23:41:49 +00:00
{
2023-12-18 07:34:42 +00:00
struct device_domain_info * info = dev_iommu_priv_get ( dev ) ;
2019-08-26 08:50:56 +00:00
struct domain_context_mapping_data data ;
2023-12-18 07:34:42 +00:00
struct intel_iommu * iommu = info - > iommu ;
u8 bus = info - > bus , devfn = info - > devfn ;
2018-12-10 01:59:02 +00:00
struct pasid_table * table ;
2007-10-21 23:41:49 +00:00
2018-12-10 01:59:02 +00:00
table = intel_pasid_get_table ( dev ) ;
2019-08-26 08:50:56 +00:00
if ( ! dev_is_pci ( dev ) )
return domain_context_mapping_one ( domain , iommu , table ,
bus , devfn ) ;
data . domain = domain ;
data . iommu = iommu ;
data . table = table ;
return pci_for_each_dma_alias ( to_pci_dev ( dev ) ,
& domain_context_mapping_cb , & data ) ;
2014-07-03 15:51:43 +00:00
}
2009-08-04 22:09:37 +00:00
/* Returns a number of VTD pages, but aligned to MM page size */
2023-12-18 07:34:45 +00:00
static unsigned long aligned_nrpages ( unsigned long host_addr , size_t size )
2009-08-04 22:09:37 +00:00
{
host_addr & = ~ PAGE_MASK ;
return PAGE_ALIGN ( host_addr + size ) > > VTD_PAGE_SHIFT ;
}
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
/* Return largest possible superpage level for a given mapping */
2023-12-18 07:34:45 +00:00
static int hardware_largepage_caps ( struct dmar_domain * domain , unsigned long iov_pfn ,
unsigned long phy_pfn , unsigned long pages )
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
{
int support , level = 1 ;
unsigned long pfnmerge ;
support = domain - > iommu_superpage ;
/* To use a large page, the virtual *and* physical addresses
must be aligned to 2 MiB / 1 GiB / etc . Lower bits set in either
of them will mean we have to use smaller pages . So just
merge them and check both at once . */
pfnmerge = iov_pfn | phy_pfn ;
while ( support & & ! ( pfnmerge & ~ VTD_STRIDE_MASK ) ) {
pages > > = VTD_STRIDE_SHIFT ;
if ( ! pages )
break ;
pfnmerge > > = VTD_STRIDE_SHIFT ;
level + + ;
support - - ;
}
return level ;
}
iommu/vt-d: Force to flush iotlb before creating superpage
The translation caches may preserve obsolete data when the
mapping size is changed, suppose the following sequence which
can reveal the problem with high probability.
1.mmap(4GB,MAP_HUGETLB)
2.
while (1) {
(a) DMA MAP 0,0xa0000
(b) DMA UNMAP 0,0xa0000
(c) DMA MAP 0,0xc0000000
* DMA read IOVA 0 may failure here (Not present)
* if the problem occurs.
(d) DMA UNMAP 0,0xc0000000
}
The page table(only focus on IOVA 0) after (a) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x1a30a72003 entry:0xffff89b39cacb000
PTE: 0x21d200803 entry:0xffff89b3b0a72000
The page table after (b) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x1a30a72003 entry:0xffff89b39cacb000
PTE: 0x0 entry:0xffff89b3b0a72000
The page table after (c) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x21d200883 entry:0xffff89b39cacb000 (*)
Because the PDE entry after (b) is present, it won't be
flushed even if the iommu driver flush cache when unmap,
so the obsolete data may be preserved in cache, which
would cause the wrong translation at end.
However, we can see the PDE entry is finally switch to
2M-superpage mapping, but it does not transform
to 0x21d200883 directly:
1. PDE: 0x1a30a72003
2. __domain_mapping
dma_pte_free_pagetable
Set the PDE entry to ZERO
Set the PDE entry to 0x21d200883
So we must flush the cache after the entry switch to ZERO
to avoid the obsolete info be preserved.
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Lu Baolu <baolu.lu@linux.intel.com>
Cc: Nadav Amit <nadav.amit@gmail.com>
Cc: Alex Williamson <alex.williamson@redhat.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Kevin Tian <kevin.tian@intel.com>
Cc: Gonglei (Arei) <arei.gonglei@huawei.com>
Fixes: 6491d4d02893 ("intel-iommu: Free old page tables before creating superpage")
Cc: <stable@vger.kernel.org> # v3.0+
Link: https://lore.kernel.org/linux-iommu/670baaf8-4ff8-4e84-4be3-030b95ab5a5e@huawei.com/
Suggested-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210415004628.1779-1-longpeng2@huawei.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-15 00:46:28 +00:00
/*
* Ensure that old small page tables are removed to make room for superpage ( s ) .
* We ' re going to add new large pages , so make sure we don ' t remove their parent
* tables . The IOTLB / devTLBs should be flushed if any PDE / PTEs are cleared .
*/
static void switch_to_super_page ( struct dmar_domain * domain ,
unsigned long start_pfn ,
unsigned long end_pfn , int level )
{
unsigned long lvl_pages = lvl_to_nr_pages ( level ) ;
2022-07-12 00:09:05 +00:00
struct iommu_domain_info * info ;
iommu/vt-d: Force to flush iotlb before creating superpage
The translation caches may preserve obsolete data when the
mapping size is changed, suppose the following sequence which
can reveal the problem with high probability.
1.mmap(4GB,MAP_HUGETLB)
2.
while (1) {
(a) DMA MAP 0,0xa0000
(b) DMA UNMAP 0,0xa0000
(c) DMA MAP 0,0xc0000000
* DMA read IOVA 0 may failure here (Not present)
* if the problem occurs.
(d) DMA UNMAP 0,0xc0000000
}
The page table(only focus on IOVA 0) after (a) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x1a30a72003 entry:0xffff89b39cacb000
PTE: 0x21d200803 entry:0xffff89b3b0a72000
The page table after (b) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x1a30a72003 entry:0xffff89b39cacb000
PTE: 0x0 entry:0xffff89b3b0a72000
The page table after (c) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x21d200883 entry:0xffff89b39cacb000 (*)
Because the PDE entry after (b) is present, it won't be
flushed even if the iommu driver flush cache when unmap,
so the obsolete data may be preserved in cache, which
would cause the wrong translation at end.
However, we can see the PDE entry is finally switch to
2M-superpage mapping, but it does not transform
to 0x21d200883 directly:
1. PDE: 0x1a30a72003
2. __domain_mapping
dma_pte_free_pagetable
Set the PDE entry to ZERO
Set the PDE entry to 0x21d200883
So we must flush the cache after the entry switch to ZERO
to avoid the obsolete info be preserved.
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Lu Baolu <baolu.lu@linux.intel.com>
Cc: Nadav Amit <nadav.amit@gmail.com>
Cc: Alex Williamson <alex.williamson@redhat.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Kevin Tian <kevin.tian@intel.com>
Cc: Gonglei (Arei) <arei.gonglei@huawei.com>
Fixes: 6491d4d02893 ("intel-iommu: Free old page tables before creating superpage")
Cc: <stable@vger.kernel.org> # v3.0+
Link: https://lore.kernel.org/linux-iommu/670baaf8-4ff8-4e84-4be3-030b95ab5a5e@huawei.com/
Suggested-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210415004628.1779-1-longpeng2@huawei.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-15 00:46:28 +00:00
struct dma_pte * pte = NULL ;
2022-07-12 00:09:05 +00:00
unsigned long i ;
iommu/vt-d: Force to flush iotlb before creating superpage
The translation caches may preserve obsolete data when the
mapping size is changed, suppose the following sequence which
can reveal the problem with high probability.
1.mmap(4GB,MAP_HUGETLB)
2.
while (1) {
(a) DMA MAP 0,0xa0000
(b) DMA UNMAP 0,0xa0000
(c) DMA MAP 0,0xc0000000
* DMA read IOVA 0 may failure here (Not present)
* if the problem occurs.
(d) DMA UNMAP 0,0xc0000000
}
The page table(only focus on IOVA 0) after (a) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x1a30a72003 entry:0xffff89b39cacb000
PTE: 0x21d200803 entry:0xffff89b3b0a72000
The page table after (b) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x1a30a72003 entry:0xffff89b39cacb000
PTE: 0x0 entry:0xffff89b3b0a72000
The page table after (c) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x21d200883 entry:0xffff89b39cacb000 (*)
Because the PDE entry after (b) is present, it won't be
flushed even if the iommu driver flush cache when unmap,
so the obsolete data may be preserved in cache, which
would cause the wrong translation at end.
However, we can see the PDE entry is finally switch to
2M-superpage mapping, but it does not transform
to 0x21d200883 directly:
1. PDE: 0x1a30a72003
2. __domain_mapping
dma_pte_free_pagetable
Set the PDE entry to ZERO
Set the PDE entry to 0x21d200883
So we must flush the cache after the entry switch to ZERO
to avoid the obsolete info be preserved.
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Lu Baolu <baolu.lu@linux.intel.com>
Cc: Nadav Amit <nadav.amit@gmail.com>
Cc: Alex Williamson <alex.williamson@redhat.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Kevin Tian <kevin.tian@intel.com>
Cc: Gonglei (Arei) <arei.gonglei@huawei.com>
Fixes: 6491d4d02893 ("intel-iommu: Free old page tables before creating superpage")
Cc: <stable@vger.kernel.org> # v3.0+
Link: https://lore.kernel.org/linux-iommu/670baaf8-4ff8-4e84-4be3-030b95ab5a5e@huawei.com/
Suggested-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210415004628.1779-1-longpeng2@huawei.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-15 00:46:28 +00:00
while ( start_pfn < = end_pfn ) {
if ( ! pte )
2023-01-23 20:36:00 +00:00
pte = pfn_to_dma_pte ( domain , start_pfn , & level ,
GFP_ATOMIC ) ;
iommu/vt-d: Force to flush iotlb before creating superpage
The translation caches may preserve obsolete data when the
mapping size is changed, suppose the following sequence which
can reveal the problem with high probability.
1.mmap(4GB,MAP_HUGETLB)
2.
while (1) {
(a) DMA MAP 0,0xa0000
(b) DMA UNMAP 0,0xa0000
(c) DMA MAP 0,0xc0000000
* DMA read IOVA 0 may failure here (Not present)
* if the problem occurs.
(d) DMA UNMAP 0,0xc0000000
}
The page table(only focus on IOVA 0) after (a) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x1a30a72003 entry:0xffff89b39cacb000
PTE: 0x21d200803 entry:0xffff89b3b0a72000
The page table after (b) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x1a30a72003 entry:0xffff89b39cacb000
PTE: 0x0 entry:0xffff89b3b0a72000
The page table after (c) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x21d200883 entry:0xffff89b39cacb000 (*)
Because the PDE entry after (b) is present, it won't be
flushed even if the iommu driver flush cache when unmap,
so the obsolete data may be preserved in cache, which
would cause the wrong translation at end.
However, we can see the PDE entry is finally switch to
2M-superpage mapping, but it does not transform
to 0x21d200883 directly:
1. PDE: 0x1a30a72003
2. __domain_mapping
dma_pte_free_pagetable
Set the PDE entry to ZERO
Set the PDE entry to 0x21d200883
So we must flush the cache after the entry switch to ZERO
to avoid the obsolete info be preserved.
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Lu Baolu <baolu.lu@linux.intel.com>
Cc: Nadav Amit <nadav.amit@gmail.com>
Cc: Alex Williamson <alex.williamson@redhat.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Kevin Tian <kevin.tian@intel.com>
Cc: Gonglei (Arei) <arei.gonglei@huawei.com>
Fixes: 6491d4d02893 ("intel-iommu: Free old page tables before creating superpage")
Cc: <stable@vger.kernel.org> # v3.0+
Link: https://lore.kernel.org/linux-iommu/670baaf8-4ff8-4e84-4be3-030b95ab5a5e@huawei.com/
Suggested-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210415004628.1779-1-longpeng2@huawei.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-15 00:46:28 +00:00
if ( dma_pte_present ( pte ) ) {
dma_pte_free_pagetable ( domain , start_pfn ,
start_pfn + lvl_pages - 1 ,
level + 1 ) ;
2022-07-12 00:09:05 +00:00
xa_for_each ( & domain - > iommu_array , i , info )
iommu_flush_iotlb_psi ( info - > iommu , domain ,
iommu/vt-d: Force to flush iotlb before creating superpage
The translation caches may preserve obsolete data when the
mapping size is changed, suppose the following sequence which
can reveal the problem with high probability.
1.mmap(4GB,MAP_HUGETLB)
2.
while (1) {
(a) DMA MAP 0,0xa0000
(b) DMA UNMAP 0,0xa0000
(c) DMA MAP 0,0xc0000000
* DMA read IOVA 0 may failure here (Not present)
* if the problem occurs.
(d) DMA UNMAP 0,0xc0000000
}
The page table(only focus on IOVA 0) after (a) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x1a30a72003 entry:0xffff89b39cacb000
PTE: 0x21d200803 entry:0xffff89b3b0a72000
The page table after (b) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x1a30a72003 entry:0xffff89b39cacb000
PTE: 0x0 entry:0xffff89b3b0a72000
The page table after (c) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x21d200883 entry:0xffff89b39cacb000 (*)
Because the PDE entry after (b) is present, it won't be
flushed even if the iommu driver flush cache when unmap,
so the obsolete data may be preserved in cache, which
would cause the wrong translation at end.
However, we can see the PDE entry is finally switch to
2M-superpage mapping, but it does not transform
to 0x21d200883 directly:
1. PDE: 0x1a30a72003
2. __domain_mapping
dma_pte_free_pagetable
Set the PDE entry to ZERO
Set the PDE entry to 0x21d200883
So we must flush the cache after the entry switch to ZERO
to avoid the obsolete info be preserved.
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Lu Baolu <baolu.lu@linux.intel.com>
Cc: Nadav Amit <nadav.amit@gmail.com>
Cc: Alex Williamson <alex.williamson@redhat.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Kevin Tian <kevin.tian@intel.com>
Cc: Gonglei (Arei) <arei.gonglei@huawei.com>
Fixes: 6491d4d02893 ("intel-iommu: Free old page tables before creating superpage")
Cc: <stable@vger.kernel.org> # v3.0+
Link: https://lore.kernel.org/linux-iommu/670baaf8-4ff8-4e84-4be3-030b95ab5a5e@huawei.com/
Suggested-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210415004628.1779-1-longpeng2@huawei.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-15 00:46:28 +00:00
start_pfn , lvl_pages ,
0 , 0 ) ;
2024-02-19 11:15:54 +00:00
if ( domain - > nested_parent )
parent_domain_flush ( domain , start_pfn ,
lvl_pages , 0 ) ;
iommu/vt-d: Force to flush iotlb before creating superpage
The translation caches may preserve obsolete data when the
mapping size is changed, suppose the following sequence which
can reveal the problem with high probability.
1.mmap(4GB,MAP_HUGETLB)
2.
while (1) {
(a) DMA MAP 0,0xa0000
(b) DMA UNMAP 0,0xa0000
(c) DMA MAP 0,0xc0000000
* DMA read IOVA 0 may failure here (Not present)
* if the problem occurs.
(d) DMA UNMAP 0,0xc0000000
}
The page table(only focus on IOVA 0) after (a) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x1a30a72003 entry:0xffff89b39cacb000
PTE: 0x21d200803 entry:0xffff89b3b0a72000
The page table after (b) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x1a30a72003 entry:0xffff89b39cacb000
PTE: 0x0 entry:0xffff89b3b0a72000
The page table after (c) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x21d200883 entry:0xffff89b39cacb000 (*)
Because the PDE entry after (b) is present, it won't be
flushed even if the iommu driver flush cache when unmap,
so the obsolete data may be preserved in cache, which
would cause the wrong translation at end.
However, we can see the PDE entry is finally switch to
2M-superpage mapping, but it does not transform
to 0x21d200883 directly:
1. PDE: 0x1a30a72003
2. __domain_mapping
dma_pte_free_pagetable
Set the PDE entry to ZERO
Set the PDE entry to 0x21d200883
So we must flush the cache after the entry switch to ZERO
to avoid the obsolete info be preserved.
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Lu Baolu <baolu.lu@linux.intel.com>
Cc: Nadav Amit <nadav.amit@gmail.com>
Cc: Alex Williamson <alex.williamson@redhat.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Kevin Tian <kevin.tian@intel.com>
Cc: Gonglei (Arei) <arei.gonglei@huawei.com>
Fixes: 6491d4d02893 ("intel-iommu: Free old page tables before creating superpage")
Cc: <stable@vger.kernel.org> # v3.0+
Link: https://lore.kernel.org/linux-iommu/670baaf8-4ff8-4e84-4be3-030b95ab5a5e@huawei.com/
Suggested-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210415004628.1779-1-longpeng2@huawei.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-15 00:46:28 +00:00
}
pte + + ;
start_pfn + = lvl_pages ;
if ( first_pte_in_page ( pte ) )
pte = NULL ;
}
}
2020-11-24 08:20:57 +00:00
static int
__domain_mapping ( struct dmar_domain * domain , unsigned long iov_pfn ,
2023-01-23 20:36:00 +00:00
unsigned long phys_pfn , unsigned long nr_pages , int prot ,
gfp_t gfp )
2009-06-29 10:17:38 +00:00
{
2021-07-20 02:06:15 +00:00
struct dma_pte * first_pte = NULL , * pte = NULL ;
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
unsigned int largepage_lvl = 0 ;
unsigned long lvl_pages = 0 ;
2020-11-24 08:20:57 +00:00
phys_addr_t pteval ;
2020-01-02 00:18:17 +00:00
u64 attr ;
2009-06-29 10:17:38 +00:00
2023-04-13 04:06:43 +00:00
if ( unlikely ( ! domain_pfn_supported ( domain , iov_pfn + nr_pages - 1 ) ) )
return - EINVAL ;
2009-06-29 10:17:38 +00:00
if ( ( prot & ( DMA_PTE_READ | DMA_PTE_WRITE ) ) = = 0 )
return - EINVAL ;
2023-10-26 04:42:16 +00:00
if ( ! ( prot & DMA_PTE_WRITE ) & & domain - > nested_parent ) {
pr_err_ratelimited ( " Read-only mapping is disallowed on the domain which serves as the parent in a nested configuration, due to HW errata (ERRATA_772415_SPR17) \n " ) ;
return - EINVAL ;
}
2020-01-02 00:18:17 +00:00
attr = prot & ( DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP ) ;
2021-03-20 02:54:12 +00:00
attr | = DMA_FL_PTE_PRESENT ;
2022-11-22 00:29:49 +00:00
if ( domain - > use_first_level ) {
2021-08-18 13:48:48 +00:00
attr | = DMA_FL_PTE_XD | DMA_FL_PTE_US | DMA_FL_PTE_ACCESS ;
if ( prot & DMA_PTE_WRITE )
attr | = DMA_FL_PTE_DIRTY ;
2021-01-15 00:42:02 +00:00
}
2023-11-22 03:26:02 +00:00
domain - > has_mappings = true ;
2020-11-24 08:20:57 +00:00
pteval = ( ( phys_addr_t ) phys_pfn < < VTD_PAGE_SHIFT ) | attr ;
2009-06-29 11:30:54 +00:00
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
while ( nr_pages > 0 ) {
2009-07-01 18:21:24 +00:00
uint64_t tmp ;
2009-06-29 10:17:38 +00:00
if ( ! pte ) {
2020-11-24 08:20:57 +00:00
largepage_lvl = hardware_largepage_caps ( domain , iov_pfn ,
phys_pfn , nr_pages ) ;
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
2023-01-23 20:36:00 +00:00
pte = pfn_to_dma_pte ( domain , iov_pfn , & largepage_lvl ,
gfp ) ;
2009-06-29 10:17:38 +00:00
if ( ! pte )
return - ENOMEM ;
2021-07-20 02:06:15 +00:00
first_pte = pte ;
iommu/vt-d: Avoid duplicate removing in __domain_mapping()
The __domain_mapping() always removes the pages in the range from
'iov_pfn' to 'end_pfn', but the 'end_pfn' is always the last pfn
of the range that the caller wants to map.
This would introduce too many duplicated removing and leads the
map operation take too long, for example:
Map iova=0x100000,nr_pages=0x7d61800
iov_pfn: 0x100000, end_pfn: 0x7e617ff
iov_pfn: 0x140000, end_pfn: 0x7e617ff
iov_pfn: 0x180000, end_pfn: 0x7e617ff
iov_pfn: 0x1c0000, end_pfn: 0x7e617ff
iov_pfn: 0x200000, end_pfn: 0x7e617ff
...
it takes about 50ms in total.
We can reduce the cost by recalculate the 'end_pfn' and limit it
to the boundary of the end of this pte page.
Map iova=0x100000,nr_pages=0x7d61800
iov_pfn: 0x100000, end_pfn: 0x13ffff
iov_pfn: 0x140000, end_pfn: 0x17ffff
iov_pfn: 0x180000, end_pfn: 0x1bffff
iov_pfn: 0x1c0000, end_pfn: 0x1fffff
iov_pfn: 0x200000, end_pfn: 0x23ffff
...
it only need 9ms now.
This also removes a meaningless BUG_ON() in __domain_mapping().
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Tested-by: Liujunjie <liujunjie23@huawei.com>
Link: https://lore.kernel.org/r/20211008000433.1115-1-longpeng2@huawei.com
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20211014053839.727419-10-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-10-14 05:38:39 +00:00
lvl_pages = lvl_to_nr_pages ( largepage_lvl ) ;
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
/* It is large page*/
2012-12-19 13:25:35 +00:00
if ( largepage_lvl > 1 ) {
iommu/vt-d: Force to flush iotlb before creating superpage
The translation caches may preserve obsolete data when the
mapping size is changed, suppose the following sequence which
can reveal the problem with high probability.
1.mmap(4GB,MAP_HUGETLB)
2.
while (1) {
(a) DMA MAP 0,0xa0000
(b) DMA UNMAP 0,0xa0000
(c) DMA MAP 0,0xc0000000
* DMA read IOVA 0 may failure here (Not present)
* if the problem occurs.
(d) DMA UNMAP 0,0xc0000000
}
The page table(only focus on IOVA 0) after (a) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x1a30a72003 entry:0xffff89b39cacb000
PTE: 0x21d200803 entry:0xffff89b3b0a72000
The page table after (b) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x1a30a72003 entry:0xffff89b39cacb000
PTE: 0x0 entry:0xffff89b3b0a72000
The page table after (c) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x21d200883 entry:0xffff89b39cacb000 (*)
Because the PDE entry after (b) is present, it won't be
flushed even if the iommu driver flush cache when unmap,
so the obsolete data may be preserved in cache, which
would cause the wrong translation at end.
However, we can see the PDE entry is finally switch to
2M-superpage mapping, but it does not transform
to 0x21d200883 directly:
1. PDE: 0x1a30a72003
2. __domain_mapping
dma_pte_free_pagetable
Set the PDE entry to ZERO
Set the PDE entry to 0x21d200883
So we must flush the cache after the entry switch to ZERO
to avoid the obsolete info be preserved.
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Lu Baolu <baolu.lu@linux.intel.com>
Cc: Nadav Amit <nadav.amit@gmail.com>
Cc: Alex Williamson <alex.williamson@redhat.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Kevin Tian <kevin.tian@intel.com>
Cc: Gonglei (Arei) <arei.gonglei@huawei.com>
Fixes: 6491d4d02893 ("intel-iommu: Free old page tables before creating superpage")
Cc: <stable@vger.kernel.org> # v3.0+
Link: https://lore.kernel.org/linux-iommu/670baaf8-4ff8-4e84-4be3-030b95ab5a5e@huawei.com/
Suggested-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210415004628.1779-1-longpeng2@huawei.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-15 00:46:28 +00:00
unsigned long end_pfn ;
iommu/vt-d: Avoid duplicate removing in __domain_mapping()
The __domain_mapping() always removes the pages in the range from
'iov_pfn' to 'end_pfn', but the 'end_pfn' is always the last pfn
of the range that the caller wants to map.
This would introduce too many duplicated removing and leads the
map operation take too long, for example:
Map iova=0x100000,nr_pages=0x7d61800
iov_pfn: 0x100000, end_pfn: 0x7e617ff
iov_pfn: 0x140000, end_pfn: 0x7e617ff
iov_pfn: 0x180000, end_pfn: 0x7e617ff
iov_pfn: 0x1c0000, end_pfn: 0x7e617ff
iov_pfn: 0x200000, end_pfn: 0x7e617ff
...
it takes about 50ms in total.
We can reduce the cost by recalculate the 'end_pfn' and limit it
to the boundary of the end of this pte page.
Map iova=0x100000,nr_pages=0x7d61800
iov_pfn: 0x100000, end_pfn: 0x13ffff
iov_pfn: 0x140000, end_pfn: 0x17ffff
iov_pfn: 0x180000, end_pfn: 0x1bffff
iov_pfn: 0x1c0000, end_pfn: 0x1fffff
iov_pfn: 0x200000, end_pfn: 0x23ffff
...
it only need 9ms now.
This also removes a meaningless BUG_ON() in __domain_mapping().
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Tested-by: Liujunjie <liujunjie23@huawei.com>
Link: https://lore.kernel.org/r/20211008000433.1115-1-longpeng2@huawei.com
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20211014053839.727419-10-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-10-14 05:38:39 +00:00
unsigned long pages_to_remove ;
2015-06-10 16:41:45 +00:00
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
pteval | = DMA_PTE_LARGE_PAGE ;
iommu/vt-d: Avoid duplicate removing in __domain_mapping()
The __domain_mapping() always removes the pages in the range from
'iov_pfn' to 'end_pfn', but the 'end_pfn' is always the last pfn
of the range that the caller wants to map.
This would introduce too many duplicated removing and leads the
map operation take too long, for example:
Map iova=0x100000,nr_pages=0x7d61800
iov_pfn: 0x100000, end_pfn: 0x7e617ff
iov_pfn: 0x140000, end_pfn: 0x7e617ff
iov_pfn: 0x180000, end_pfn: 0x7e617ff
iov_pfn: 0x1c0000, end_pfn: 0x7e617ff
iov_pfn: 0x200000, end_pfn: 0x7e617ff
...
it takes about 50ms in total.
We can reduce the cost by recalculate the 'end_pfn' and limit it
to the boundary of the end of this pte page.
Map iova=0x100000,nr_pages=0x7d61800
iov_pfn: 0x100000, end_pfn: 0x13ffff
iov_pfn: 0x140000, end_pfn: 0x17ffff
iov_pfn: 0x180000, end_pfn: 0x1bffff
iov_pfn: 0x1c0000, end_pfn: 0x1fffff
iov_pfn: 0x200000, end_pfn: 0x23ffff
...
it only need 9ms now.
This also removes a meaningless BUG_ON() in __domain_mapping().
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Tested-by: Liujunjie <liujunjie23@huawei.com>
Link: https://lore.kernel.org/r/20211008000433.1115-1-longpeng2@huawei.com
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20211014053839.727419-10-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-10-14 05:38:39 +00:00
pages_to_remove = min_t ( unsigned long , nr_pages ,
nr_pte_to_next_page ( pte ) * lvl_pages ) ;
end_pfn = iov_pfn + pages_to_remove - 1 ;
iommu/vt-d: Force to flush iotlb before creating superpage
The translation caches may preserve obsolete data when the
mapping size is changed, suppose the following sequence which
can reveal the problem with high probability.
1.mmap(4GB,MAP_HUGETLB)
2.
while (1) {
(a) DMA MAP 0,0xa0000
(b) DMA UNMAP 0,0xa0000
(c) DMA MAP 0,0xc0000000
* DMA read IOVA 0 may failure here (Not present)
* if the problem occurs.
(d) DMA UNMAP 0,0xc0000000
}
The page table(only focus on IOVA 0) after (a) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x1a30a72003 entry:0xffff89b39cacb000
PTE: 0x21d200803 entry:0xffff89b3b0a72000
The page table after (b) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x1a30a72003 entry:0xffff89b39cacb000
PTE: 0x0 entry:0xffff89b3b0a72000
The page table after (c) is:
PML4: 0x19db5c1003 entry:0xffff899bdcd2f000
PDPE: 0x1a1cacb003 entry:0xffff89b35b5c1000
PDE: 0x21d200883 entry:0xffff89b39cacb000 (*)
Because the PDE entry after (b) is present, it won't be
flushed even if the iommu driver flush cache when unmap,
so the obsolete data may be preserved in cache, which
would cause the wrong translation at end.
However, we can see the PDE entry is finally switch to
2M-superpage mapping, but it does not transform
to 0x21d200883 directly:
1. PDE: 0x1a30a72003
2. __domain_mapping
dma_pte_free_pagetable
Set the PDE entry to ZERO
Set the PDE entry to 0x21d200883
So we must flush the cache after the entry switch to ZERO
to avoid the obsolete info be preserved.
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Lu Baolu <baolu.lu@linux.intel.com>
Cc: Nadav Amit <nadav.amit@gmail.com>
Cc: Alex Williamson <alex.williamson@redhat.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Kevin Tian <kevin.tian@intel.com>
Cc: Gonglei (Arei) <arei.gonglei@huawei.com>
Fixes: 6491d4d02893 ("intel-iommu: Free old page tables before creating superpage")
Cc: <stable@vger.kernel.org> # v3.0+
Link: https://lore.kernel.org/linux-iommu/670baaf8-4ff8-4e84-4be3-030b95ab5a5e@huawei.com/
Suggested-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com>
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210415004628.1779-1-longpeng2@huawei.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-15 00:46:28 +00:00
switch_to_super_page ( domain , iov_pfn , end_pfn , largepage_lvl ) ;
2012-12-19 13:25:35 +00:00
} else {
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
pteval & = ~ ( uint64_t ) DMA_PTE_LARGE_PAGE ;
2012-12-19 13:25:35 +00:00
}
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
2009-06-29 10:17:38 +00:00
}
/* We don't need lock here, nobody else
* touches the iova range
*/
2009-07-01 19:27:03 +00:00
tmp = cmpxchg64_local ( & pte - > val , 0ULL , pteval ) ;
2009-07-01 18:21:24 +00:00
if ( tmp ) {
2009-06-29 21:06:43 +00:00
static int dumps = 5 ;
2015-06-12 07:57:06 +00:00
pr_crit ( " ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx) \n " ,
iov_pfn , tmp , ( unsigned long long ) pteval ) ;
2009-06-29 21:06:43 +00:00
if ( dumps ) {
dumps - - ;
debug_dma_dump_mappings ( NULL ) ;
}
WARN_ON ( 1 ) ;
}
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
nr_pages - = lvl_pages ;
iov_pfn + = lvl_pages ;
phys_pfn + = lvl_pages ;
pteval + = lvl_pages * VTD_PAGE_SIZE ;
/* If the next PTE would be the first in a new page, then we
2020-11-24 08:20:57 +00:00
* need to flush the cache on the entries we ' ve just written .
* And then we ' ll need to recalculate ' pte ' , so clear it and
* let it get set again in the if ( ! pte ) block above .
*
* If we ' re done ( ! nr_pages ) we need to flush the cache too .
*
* Also if we ' ve been setting superpages , we may need to
* recalculate ' pte ' and switch back to smaller pages for the
* end of the mapping , if the trailing size is not enough to
* use another superpage ( i . e . nr_pages < lvl_pages ) .
*/
2009-06-29 10:17:38 +00:00
pte + + ;
intel-iommu: Enable super page (2MiB, 1GiB, etc.) support
There are no externally-visible changes with this. In the loop in the
internal __domain_mapping() function, we simply detect if we are mapping:
- size >= 2MiB, and
- virtual address aligned to 2MiB, and
- physical address aligned to 2MiB, and
- on hardware that supports superpages.
(and likewise for larger superpages).
We automatically use a superpage for such mappings. We never have to
worry about *breaking* superpages, since we trust that we will always
*unmap* the same range that was mapped. So all we need to do is ensure
that dma_pte_clear_range() will also cope with superpages.
Adjust pfn_to_dma_pte() to take a superpage 'level' as an argument, so
it can return a PTE at the appropriate level rather than always
extending the page tables all the way down to level 1. Again, this is
simplified by the fact that we should never encounter existing small
pages when we're creating a mapping; any old mapping that used the same
virtual range will have been entirely removed and its obsolete page
tables freed.
Provide an 'intel_iommu=sp_off' argument on the command line as a
chicken bit. Not that it should ever be required.
==
The original commit seen in the iommu-2.6.git was Youquan's
implementation (and completion) of my own half-baked code which I'd
typed into an email. Followed by half a dozen subsequent 'fixes'.
I've taken the unusual step of rewriting history and collapsing the
original commits in order to keep the main history simpler, and make
life easier for the people who are going to have to backport this to
older kernels. And also so I can give it a more coherent commit comment
which (hopefully) gives a better explanation of what's going on.
The original sequence of commits leading to identical code was:
Youquan Song (3):
intel-iommu: super page support
intel-iommu: Fix superpage alignment calculation error
intel-iommu: Fix superpage level calculation error in dma_pfn_level_pte()
David Woodhouse (4):
intel-iommu: Precalculate superpage support for dmar_domain
intel-iommu: Fix hardware_largepage_caps()
intel-iommu: Fix inappropriate use of superpages in __domain_mapping()
intel-iommu: Fix phys_pfn in __domain_mapping for sglist pages
Signed-off-by: Youquan Song <youquan.song@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2011-05-25 18:13:49 +00:00
if ( ! nr_pages | | first_pte_in_page ( pte ) | |
2021-07-20 02:06:15 +00:00
( largepage_lvl > 1 & & nr_pages < lvl_pages ) ) {
domain_flush_cache ( domain , first_pte ,
( void * ) pte - ( void * ) first_pte ) ;
2009-06-29 10:17:38 +00:00
pte = NULL ;
2021-07-20 02:06:15 +00:00
}
2019-04-29 01:16:02 +00:00
}
return 0 ;
2018-05-04 02:34:53 +00:00
}
2021-07-12 07:13:15 +00:00
static void domain_context_clear_one ( struct device_domain_info * info , u8 bus , u8 devfn )
2007-10-21 23:41:49 +00:00
{
2021-07-12 07:13:15 +00:00
struct intel_iommu * iommu = info - > iommu ;
2017-08-31 08:58:11 +00:00
struct context_entry * context ;
u16 did_old ;
2008-12-08 14:51:37 +00:00
if ( ! iommu )
return ;
2008-12-08 07:29:22 +00:00
2022-07-12 00:08:56 +00:00
spin_lock ( & iommu - > lock ) ;
2017-08-31 08:58:11 +00:00
context = iommu_context_addr ( iommu , bus , devfn , 0 ) ;
if ( ! context ) {
2022-07-12 00:08:56 +00:00
spin_unlock ( & iommu - > lock ) ;
2017-08-31 08:58:11 +00:00
return ;
}
2021-07-12 07:13:15 +00:00
if ( sm_supported ( iommu ) ) {
if ( hw_pass_through & & domain_type_is_si ( info - > domain ) )
did_old = FLPT_DEFAULT_DID ;
else
2022-07-12 00:09:05 +00:00
did_old = domain_id_iommu ( info - > domain , iommu ) ;
2021-07-12 07:13:15 +00:00
} else {
did_old = context_domain_id ( context ) ;
}
2017-08-31 08:58:11 +00:00
context_clear_entry ( context ) ;
__iommu_flush_cache ( iommu , context , sizeof ( * context ) ) ;
2022-07-12 00:08:56 +00:00
spin_unlock ( & iommu - > lock ) ;
2017-08-31 08:58:11 +00:00
iommu - > flush . flush_context ( iommu ,
did_old ,
( ( ( u16 ) bus ) < < 8 ) | devfn ,
DMA_CCMD_MASK_NOBIT ,
DMA_CCMD_DEVICE_INVL ) ;
2021-03-20 02:54:13 +00:00
if ( sm_supported ( iommu ) )
qi_flush_pasid_cache ( iommu , did_old , QI_PC_ALL_PASIDS , 0 ) ;
2017-08-31 08:58:11 +00:00
iommu - > flush . flush_iotlb ( iommu ,
did_old ,
0 ,
0 ,
DMA_TLB_DSI_FLUSH ) ;
2021-07-12 07:13:15 +00:00
__iommu_flush_dev_iotlb ( info , 0 , MAX_AGAW_PFN_WIDTH ) ;
2007-10-21 23:41:49 +00:00
}
2020-01-02 00:18:17 +00:00
static int domain_setup_first_level ( struct intel_iommu * iommu ,
struct dmar_domain * domain ,
struct device * dev ,
2020-09-15 16:30:05 +00:00
u32 pasid )
2020-01-02 00:18:17 +00:00
{
struct dma_pte * pgd = domain - > pgd ;
int agaw , level ;
2021-05-19 01:50:27 +00:00
int flags = 0 ;
2020-01-02 00:18:17 +00:00
/*
* Skip top levels of page tables for iommu which has
* less agaw than default . Unnecessary for PT mode .
*/
for ( agaw = domain - > agaw ; agaw > iommu - > agaw ; agaw - - ) {
pgd = phys_to_virt ( dma_pte_addr ( pgd ) ) ;
if ( ! dma_pte_present ( pgd ) )
return - ENOMEM ;
}
level = agaw_to_level ( agaw ) ;
if ( level ! = 4 & & level ! = 5 )
return - EINVAL ;
2021-05-19 01:50:27 +00:00
if ( level = = 5 )
flags | = PASID_FLAG_FL5LP ;
2020-01-02 00:18:17 +00:00
2022-05-10 02:34:05 +00:00
if ( domain - > force_snooping )
2021-03-30 02:11:45 +00:00
flags | = PASID_FLAG_PAGE_SNOOP ;
2020-01-02 00:18:17 +00:00
return intel_pasid_setup_first_level ( iommu , dev , ( pgd_t * ) pgd , pasid ,
2022-07-12 00:09:05 +00:00
domain_id_iommu ( domain , iommu ) ,
2020-01-02 00:18:17 +00:00
flags ) ;
}
2020-05-27 16:56:15 +00:00
static bool dev_is_real_dma_subdevice ( struct device * dev )
{
return dev & & dev_is_pci ( dev ) & &
pci_real_dma_dev ( to_pci_dev ( dev ) ) ! = to_pci_dev ( dev ) ;
}
2009-06-26 17:50:28 +00:00
static int iommu_domain_identity_map ( struct dmar_domain * domain ,
2020-05-16 06:21:01 +00:00
unsigned long first_vpfn ,
unsigned long last_vpfn )
2007-10-21 23:41:49 +00:00
{
/*
* RMRR range might have overlap with physical memory range ,
* clear it first
*/
2009-06-28 15:35:56 +00:00
dma_pte_clear_range ( domain , first_vpfn , last_vpfn ) ;
2007-10-21 23:41:49 +00:00
2020-11-24 08:20:57 +00:00
return __domain_mapping ( domain , first_vpfn ,
2018-05-04 02:34:53 +00:00
first_vpfn , last_vpfn - first_vpfn + 1 ,
2023-01-23 20:36:01 +00:00
DMA_PTE_READ | DMA_PTE_WRITE , GFP_KERNEL ) ;
2009-06-26 17:50:28 +00:00
}
2019-07-22 14:21:05 +00:00
static int md_domain_init ( struct dmar_domain * domain , int guest_width ) ;
2009-08-24 05:30:22 +00:00
static int __init si_domain_init ( int hw )
2009-06-19 20:47:29 +00:00
{
2019-05-25 05:41:27 +00:00
struct dmar_rmrr_unit * rmrr ;
struct device * dev ;
int i , nid , ret ;
2009-06-19 20:47:29 +00:00
2021-10-14 05:38:33 +00:00
si_domain = alloc_domain ( IOMMU_DOMAIN_IDENTITY ) ;
2009-06-19 20:47:29 +00:00
if ( ! si_domain )
return - EFAULT ;
2019-07-22 14:21:05 +00:00
if ( md_domain_init ( si_domain , DEFAULT_DOMAIN_ADDRESS_WIDTH ) ) {
2009-06-19 20:47:29 +00:00
domain_exit ( si_domain ) ;
2022-10-19 00:44:47 +00:00
si_domain = NULL ;
2009-06-19 20:47:29 +00:00
return - EFAULT ;
}
2009-08-04 15:19:20 +00:00
if ( hw )
return 0 ;
2009-06-26 18:10:36 +00:00
for_each_online_node ( nid ) {
2011-07-14 07:46:10 +00:00
unsigned long start_pfn , end_pfn ;
int i ;
for_each_mem_pfn_range ( i , nid , & start_pfn , & end_pfn , NULL ) {
ret = iommu_domain_identity_map ( si_domain ,
2023-08-09 12:48:05 +00:00
mm_to_dma_pfn_start ( start_pfn ) ,
mm_to_dma_pfn_end ( end_pfn ) ) ;
2011-07-14 07:46:10 +00:00
if ( ret )
return ret ;
}
2009-06-26 18:10:36 +00:00
}
2019-05-25 05:41:27 +00:00
/*
2020-01-15 03:03:58 +00:00
* Identity map the RMRRs so that devices with RMRRs could also use
* the si_domain .
2019-05-25 05:41:27 +00:00
*/
for_each_rmrr_units ( rmrr ) {
for_each_active_dev_scope ( rmrr - > devices , rmrr - > devices_cnt ,
i , dev ) {
unsigned long long start = rmrr - > base_address ;
unsigned long long end = rmrr - > end_address ;
if ( WARN_ON ( end < start | |
end > > agaw_to_width ( si_domain - > agaw ) ) )
continue ;
2020-06-22 23:13:45 +00:00
ret = iommu_domain_identity_map ( si_domain ,
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mm_to_dma_pfn_start ( start > > PAGE_SHIFT ) ,
mm_to_dma_pfn_end ( end > > PAGE_SHIFT ) ) ;
2019-05-25 05:41:27 +00:00
if ( ret )
return ret ;
}
}
2009-06-19 20:47:29 +00:00
return 0 ;
}
2022-11-22 00:29:47 +00:00
static int dmar_domain_attach_device ( struct dmar_domain * domain ,
struct device * dev )
2009-06-19 20:47:29 +00:00
{
2022-05-10 02:34:02 +00:00
struct device_domain_info * info = dev_iommu_priv_get ( dev ) ;
2023-12-18 07:34:42 +00:00
struct intel_iommu * iommu = info - > iommu ;
2022-08-23 06:15:56 +00:00
unsigned long flags ;
2022-05-10 02:34:02 +00:00
int ret ;
2009-06-19 20:47:29 +00:00
2022-05-10 02:34:02 +00:00
ret = domain_attach_iommu ( domain , iommu ) ;
2022-07-12 00:09:01 +00:00
if ( ret )
2022-05-10 02:34:02 +00:00
return ret ;
2022-07-12 00:09:01 +00:00
info - > domain = domain ;
2022-08-23 06:15:56 +00:00
spin_lock_irqsave ( & domain - > lock , flags ) ;
2022-05-10 02:34:02 +00:00
list_add ( & info - > link , & domain - > devices ) ;
2022-08-23 06:15:56 +00:00
spin_unlock_irqrestore ( & domain - > lock , flags ) ;
2022-05-10 02:34:02 +00:00
/* PASID table is mandatory for a PCI device in scalable mode. */
if ( sm_supported ( iommu ) & & ! dev_is_real_dma_subdevice ( dev ) ) {
/* Setup the PASID entry for requests without PASID: */
if ( hw_pass_through & & domain_type_is_si ( domain ) )
2023-12-18 07:34:43 +00:00
ret = intel_pasid_setup_pass_through ( iommu ,
2023-08-09 12:47:54 +00:00
dev , IOMMU_NO_PASID ) ;
2022-11-22 00:29:49 +00:00
else if ( domain - > use_first_level )
2022-05-10 02:34:02 +00:00
ret = domain_setup_first_level ( iommu , domain , dev ,
2023-08-09 12:47:54 +00:00
IOMMU_NO_PASID ) ;
2022-05-10 02:34:02 +00:00
else
ret = intel_pasid_setup_second_level ( iommu , domain ,
2023-08-09 12:47:54 +00:00
dev , IOMMU_NO_PASID ) ;
2022-05-10 02:34:02 +00:00
if ( ret ) {
dev_err ( dev , " Setup RID2PASID failed \n " ) ;
2022-11-22 00:29:44 +00:00
device_block_translation ( dev ) ;
2022-05-10 02:34:02 +00:00
return ret ;
}
}
ret = domain_context_mapping ( domain , dev ) ;
if ( ret ) {
dev_err ( dev , " Domain context map failed \n " ) ;
2022-11-22 00:29:44 +00:00
device_block_translation ( dev ) ;
2022-05-10 02:34:02 +00:00
return ret ;
}
2009-06-19 20:47:29 +00:00
2023-11-22 03:26:04 +00:00
if ( sm_supported ( info - > iommu ) | | ! domain_type_is_si ( info - > domain ) )
iommu_enable_pci_caps ( info ) ;
2022-11-22 00:29:44 +00:00
2009-06-19 20:47:29 +00:00
return 0 ;
}
2019-06-03 06:53:36 +00:00
/**
* device_rmrr_is_relaxable - Test whether the RMRR of this device
* is relaxable ( ie . is allowed to be not enforced under some conditions )
* @ dev : device handle
*
* We assume that PCI USB devices with RMRRs have them largely
* for historical reasons and that the RMRR space is not actively used post
* boot . This exclusion may change if vendors begin to abuse it .
*
* The same exception is made for graphics devices , with the requirement that
* any use of the RMRR regions will be torn down before assigning the device
* to a guest .
*
* Return : true if the RMRR is relaxable , false otherwise
*/
static bool device_rmrr_is_relaxable ( struct device * dev )
{
struct pci_dev * pdev ;
if ( ! dev_is_pci ( dev ) )
return false ;
pdev = to_pci_dev ( dev ) ;
if ( IS_USB_DEVICE ( pdev ) | | IS_GFX_DEVICE ( pdev ) )
return true ;
else
return false ;
}
2019-05-25 05:41:26 +00:00
/*
* Return the required default domain type for a specific device .
*
* @ dev : the device in query
* @ startup : true if this is during early boot
*
* Returns :
* - IOMMU_DOMAIN_DMA : device requires a dynamic mapping domain
* - IOMMU_DOMAIN_IDENTITY : device requires an identical mapping domain
* - 0 : both identity and dynamic domains work for this device
*/
2019-05-25 05:41:34 +00:00
static int device_def_domain_type ( struct device * dev )
2009-07-04 17:24:27 +00:00
{
2014-03-09 23:03:08 +00:00
if ( dev_is_pci ( dev ) ) {
struct pci_dev * pdev = to_pci_dev ( dev ) ;
2012-11-20 19:43:17 +00:00
2014-03-09 23:03:08 +00:00
if ( ( iommu_identity_mapping & IDENTMAP_AZALIA ) & & IS_AZALIA ( pdev ) )
2019-05-25 05:41:26 +00:00
return IOMMU_DOMAIN_IDENTITY ;
2009-09-30 16:12:17 +00:00
2014-03-09 23:03:08 +00:00
if ( ( iommu_identity_mapping & IDENTMAP_GFX ) & & IS_GFX_DEVICE ( pdev ) )
2019-05-25 05:41:26 +00:00
return IOMMU_DOMAIN_IDENTITY ;
2014-03-09 23:03:08 +00:00
}
intel-iommu: Don't use identity mapping for PCI devices behind bridges
Our current strategy for pass-through mode is to put all devices into
the 1:1 domain at startup (which is before we know what their dma_mask
will be), and only _later_ take them out of that domain, if it turns out
that they really can't address all of memory.
However, when there are a bunch of PCI devices behind a bridge, they all
end up with the same source-id on their DMA transactions, and hence in
the same IOMMU domain. This means that we _can't_ easily move them from
the 1:1 domain into their own domain at runtime, because there might be DMA
in-flight from their siblings.
So we have to adjust our pass-through strategy: For PCI devices not on
the root bus, and for the bridges which will take responsibility for
their transactions, we have to start up _out_ of the 1:1 domain, just in
case.
This fixes the BUG() we see when we have 32-bit-capable devices behind a
PCI-PCI bridge, and use the software identity mapping.
It does mean that we might end up using 'normal' mapping mode for some
devices which could actually live with the faster 1:1 mapping -- but
this is only for PCI devices behind bridges, which presumably aren't the
devices for which people are most concerned about performance.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-07-04 18:11:08 +00:00
2020-01-15 03:03:59 +00:00
return 0 ;
2019-05-25 05:41:26 +00:00
}
2014-11-09 14:48:02 +00:00
static void intel_iommu_init_qi ( struct intel_iommu * iommu )
{
/*
* Start from the sane iommu hardware state .
* If the queued invalidation is already initialized by us
* ( for example , while enabling interrupt - remapping ) then
* we got the things already rolling from a sane state .
*/
if ( ! iommu - > qi ) {
/*
* Clear any previous faults .
*/
dmar_fault ( - 1 , iommu ) ;
/*
* Disable queued invalidation if supported and already enabled
* before OS handover .
*/
dmar_disable_qi ( iommu ) ;
}
if ( dmar_enable_qi ( iommu ) ) {
/*
* Queued Invalidate not enabled , use Register Based Invalidate
*/
iommu - > flush . flush_context = __iommu_flush_context ;
iommu - > flush . flush_iotlb = __iommu_flush_iotlb ;
2015-06-12 07:57:06 +00:00
pr_info ( " %s: Using Register based invalidation \n " ,
2014-11-09 14:48:02 +00:00
iommu - > name ) ;
} else {
iommu - > flush . flush_context = qi_flush_context ;
iommu - > flush . flush_iotlb = qi_flush_iotlb ;
2015-06-12 07:57:06 +00:00
pr_info ( " %s: Using Queued invalidation \n " , iommu - > name ) ;
2014-11-09 14:48:02 +00:00
}
}
2015-06-12 09:56:10 +00:00
static int copy_context_table ( struct intel_iommu * iommu ,
2015-10-09 22:16:46 +00:00
struct root_entry * old_re ,
2015-06-12 09:56:10 +00:00
struct context_entry * * tbl ,
int bus , bool ext )
{
2015-06-12 10:02:09 +00:00
int tbl_idx , pos = 0 , idx , devfn , ret = 0 , did ;
2015-08-13 09:56:59 +00:00
struct context_entry * new_ce = NULL , ce ;
2015-10-09 22:16:46 +00:00
struct context_entry * old_ce = NULL ;
2015-08-13 09:56:59 +00:00
struct root_entry re ;
2015-06-12 09:56:10 +00:00
phys_addr_t old_ce_phys ;
tbl_idx = ext ? bus * 2 : bus ;
2015-10-09 22:16:46 +00:00
memcpy ( & re , old_re , sizeof ( re ) ) ;
2015-06-12 09:56:10 +00:00
for ( devfn = 0 ; devfn < 256 ; devfn + + ) {
/* First calculate the correct index */
idx = ( ext ? devfn * 2 : devfn ) % 256 ;
if ( idx = = 0 ) {
/* First save what we may have and clean up */
if ( new_ce ) {
tbl [ tbl_idx ] = new_ce ;
__iommu_flush_cache ( iommu , new_ce ,
VTD_PAGE_SIZE ) ;
pos = 1 ;
}
if ( old_ce )
2018-11-21 09:53:47 +00:00
memunmap ( old_ce ) ;
2015-06-12 09:56:10 +00:00
ret = 0 ;
if ( devfn < 0x80 )
2015-08-13 09:56:59 +00:00
old_ce_phys = root_entry_lctp ( & re ) ;
2015-06-12 09:56:10 +00:00
else
2015-08-13 09:56:59 +00:00
old_ce_phys = root_entry_uctp ( & re ) ;
2015-06-12 09:56:10 +00:00
if ( ! old_ce_phys ) {
if ( ext & & devfn = = 0 ) {
/* No LCTP, try UCTP */
devfn = 0x7f ;
continue ;
} else {
goto out ;
}
}
ret = - ENOMEM ;
2015-10-09 22:16:46 +00:00
old_ce = memremap ( old_ce_phys , PAGE_SIZE ,
MEMREMAP_WB ) ;
2015-06-12 09:56:10 +00:00
if ( ! old_ce )
goto out ;
2023-01-23 20:36:01 +00:00
new_ce = alloc_pgtable_page ( iommu - > node , GFP_KERNEL ) ;
2015-06-12 09:56:10 +00:00
if ( ! new_ce )
goto out_unmap ;
ret = 0 ;
}
/* Now copy the context entry */
2015-10-09 22:16:46 +00:00
memcpy ( & ce , old_ce + idx , sizeof ( ce ) ) ;
2015-06-12 09:56:10 +00:00
2022-08-23 06:15:54 +00:00
if ( ! context_present ( & ce ) )
2015-06-12 09:56:10 +00:00
continue ;
2015-06-12 10:02:09 +00:00
did = context_domain_id ( & ce ) ;
if ( did > = 0 & & did < cap_ndoms ( iommu - > cap ) )
set_bit ( did , iommu - > domain_ids ) ;
2022-08-23 06:15:54 +00:00
set_context_copied ( iommu , bus , devfn ) ;
2015-06-12 09:56:10 +00:00
new_ce [ idx ] = ce ;
}
tbl [ tbl_idx + pos ] = new_ce ;
__iommu_flush_cache ( iommu , new_ce , VTD_PAGE_SIZE ) ;
out_unmap :
2015-10-09 22:16:46 +00:00
memunmap ( old_ce ) ;
2015-06-12 09:56:10 +00:00
out :
return ret ;
}
static int copy_translation_tables ( struct intel_iommu * iommu )
{
struct context_entry * * ctxt_tbls ;
2015-10-09 22:16:46 +00:00
struct root_entry * old_rt ;
2015-06-12 09:56:10 +00:00
phys_addr_t old_rt_phys ;
int ctxt_table_entries ;
u64 rtaddr_reg ;
int bus , ret ;
2015-06-12 10:39:25 +00:00
bool new_ext , ext ;
2015-06-12 09:56:10 +00:00
rtaddr_reg = dmar_readq ( iommu - > reg + DMAR_RTADDR_REG ) ;
2022-08-23 06:15:54 +00:00
ext = ! ! ( rtaddr_reg & DMA_RTADDR_SMT ) ;
new_ext = ! ! sm_supported ( iommu ) ;
2015-06-12 10:39:25 +00:00
/*
* The RTT bit can only be changed when translation is disabled ,
* but disabling translation means to open a window for data
* corruption . So bail out and don ' t copy anything if we would
* have to change the bit .
*/
if ( new_ext ! = ext )
return - EINVAL ;
2015-06-12 09:56:10 +00:00
2022-08-23 06:15:54 +00:00
iommu - > copied_tables = bitmap_zalloc ( BIT_ULL ( 16 ) , GFP_KERNEL ) ;
if ( ! iommu - > copied_tables )
return - ENOMEM ;
2015-06-12 09:56:10 +00:00
old_rt_phys = rtaddr_reg & VTD_PAGE_MASK ;
if ( ! old_rt_phys )
return - EINVAL ;
2015-10-09 22:16:46 +00:00
old_rt = memremap ( old_rt_phys , PAGE_SIZE , MEMREMAP_WB ) ;
2015-06-12 09:56:10 +00:00
if ( ! old_rt )
return - ENOMEM ;
/* This is too big for the stack - allocate it from slab */
ctxt_table_entries = ext ? 512 : 256 ;
ret = - ENOMEM ;
treewide: kzalloc() -> kcalloc()
The kzalloc() function has a 2-factor argument form, kcalloc(). This
patch replaces cases of:
kzalloc(a * b, gfp)
with:
kcalloc(a * b, gfp)
as well as handling cases of:
kzalloc(a * b * c, gfp)
with:
kzalloc(array3_size(a, b, c), gfp)
as it's slightly less ugly than:
kzalloc_array(array_size(a, b), c, gfp)
This does, however, attempt to ignore constant size factors like:
kzalloc(4 * 1024, gfp)
though any constants defined via macros get caught up in the conversion.
Any factors with a sizeof() of "unsigned char", "char", and "u8" were
dropped, since they're redundant.
The Coccinelle script used for this was:
// Fix redundant parens around sizeof().
@@
type TYPE;
expression THING, E;
@@
(
kzalloc(
- (sizeof(TYPE)) * E
+ sizeof(TYPE) * E
, ...)
|
kzalloc(
- (sizeof(THING)) * E
+ sizeof(THING) * E
, ...)
)
// Drop single-byte sizes and redundant parens.
@@
expression COUNT;
typedef u8;
typedef __u8;
@@
(
kzalloc(
- sizeof(u8) * (COUNT)
+ COUNT
, ...)
|
kzalloc(
- sizeof(__u8) * (COUNT)
+ COUNT
, ...)
|
kzalloc(
- sizeof(char) * (COUNT)
+ COUNT
, ...)
|
kzalloc(
- sizeof(unsigned char) * (COUNT)
+ COUNT
, ...)
|
kzalloc(
- sizeof(u8) * COUNT
+ COUNT
, ...)
|
kzalloc(
- sizeof(__u8) * COUNT
+ COUNT
, ...)
|
kzalloc(
- sizeof(char) * COUNT
+ COUNT
, ...)
|
kzalloc(
- sizeof(unsigned char) * COUNT
+ COUNT
, ...)
)
// 2-factor product with sizeof(type/expression) and identifier or constant.
@@
type TYPE;
expression THING;
identifier COUNT_ID;
constant COUNT_CONST;
@@
(
- kzalloc
+ kcalloc
(
- sizeof(TYPE) * (COUNT_ID)
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(TYPE) * COUNT_ID
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(TYPE) * (COUNT_CONST)
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(TYPE) * COUNT_CONST
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(THING) * (COUNT_ID)
+ COUNT_ID, sizeof(THING)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(THING) * COUNT_ID
+ COUNT_ID, sizeof(THING)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(THING) * (COUNT_CONST)
+ COUNT_CONST, sizeof(THING)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(THING) * COUNT_CONST
+ COUNT_CONST, sizeof(THING)
, ...)
)
// 2-factor product, only identifiers.
@@
identifier SIZE, COUNT;
@@
- kzalloc
+ kcalloc
(
- SIZE * COUNT
+ COUNT, SIZE
, ...)
// 3-factor product with 1 sizeof(type) or sizeof(expression), with
// redundant parens removed.
@@
expression THING;
identifier STRIDE, COUNT;
type TYPE;
@@
(
kzalloc(
- sizeof(TYPE) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
kzalloc(
- sizeof(TYPE) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
kzalloc(
- sizeof(TYPE) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
kzalloc(
- sizeof(TYPE) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
kzalloc(
- sizeof(THING) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
kzalloc(
- sizeof(THING) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
kzalloc(
- sizeof(THING) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
kzalloc(
- sizeof(THING) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
)
// 3-factor product with 2 sizeof(variable), with redundant parens removed.
@@
expression THING1, THING2;
identifier COUNT;
type TYPE1, TYPE2;
@@
(
kzalloc(
- sizeof(TYPE1) * sizeof(TYPE2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
kzalloc(
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
kzalloc(
- sizeof(THING1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
kzalloc(
- sizeof(THING1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
kzalloc(
- sizeof(TYPE1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
|
kzalloc(
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
)
// 3-factor product, only identifiers, with redundant parens removed.
@@
identifier STRIDE, SIZE, COUNT;
@@
(
kzalloc(
- (COUNT) * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kzalloc(
- COUNT * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kzalloc(
- COUNT * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kzalloc(
- (COUNT) * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kzalloc(
- COUNT * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kzalloc(
- (COUNT) * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kzalloc(
- (COUNT) * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kzalloc(
- COUNT * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
)
// Any remaining multi-factor products, first at least 3-factor products,
// when they're not all constants...
@@
expression E1, E2, E3;
constant C1, C2, C3;
@@
(
kzalloc(C1 * C2 * C3, ...)
|
kzalloc(
- (E1) * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
|
kzalloc(
- (E1) * (E2) * E3
+ array3_size(E1, E2, E3)
, ...)
|
kzalloc(
- (E1) * (E2) * (E3)
+ array3_size(E1, E2, E3)
, ...)
|
kzalloc(
- E1 * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
)
// And then all remaining 2 factors products when they're not all constants,
// keeping sizeof() as the second factor argument.
@@
expression THING, E1, E2;
type TYPE;
constant C1, C2, C3;
@@
(
kzalloc(sizeof(THING) * C2, ...)
|
kzalloc(sizeof(TYPE) * C2, ...)
|
kzalloc(C1 * C2 * C3, ...)
|
kzalloc(C1 * C2, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(TYPE) * (E2)
+ E2, sizeof(TYPE)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(TYPE) * E2
+ E2, sizeof(TYPE)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(THING) * (E2)
+ E2, sizeof(THING)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(THING) * E2
+ E2, sizeof(THING)
, ...)
|
- kzalloc
+ kcalloc
(
- (E1) * E2
+ E1, E2
, ...)
|
- kzalloc
+ kcalloc
(
- (E1) * (E2)
+ E1, E2
, ...)
|
- kzalloc
+ kcalloc
(
- E1 * E2
+ E1, E2
, ...)
)
Signed-off-by: Kees Cook <keescook@chromium.org>
2018-06-12 21:03:40 +00:00
ctxt_tbls = kcalloc ( ctxt_table_entries , sizeof ( void * ) , GFP_KERNEL ) ;
2015-06-12 09:56:10 +00:00
if ( ! ctxt_tbls )
goto out_unmap ;
for ( bus = 0 ; bus < 256 ; bus + + ) {
ret = copy_context_table ( iommu , & old_rt [ bus ] ,
ctxt_tbls , bus , ext ) ;
if ( ret ) {
pr_err ( " %s: Failed to copy context table for bus %d \n " ,
iommu - > name , bus ) ;
continue ;
}
}
2022-07-12 00:08:56 +00:00
spin_lock ( & iommu - > lock ) ;
2015-06-12 09:56:10 +00:00
/* Context tables are copied, now write them to the root_entry table */
for ( bus = 0 ; bus < 256 ; bus + + ) {
int idx = ext ? bus * 2 : bus ;
u64 val ;
if ( ctxt_tbls [ idx ] ) {
val = virt_to_phys ( ctxt_tbls [ idx ] ) | 1 ;
iommu - > root_entry [ bus ] . lo = val ;
}
if ( ! ext | | ! ctxt_tbls [ idx + 1 ] )
continue ;
val = virt_to_phys ( ctxt_tbls [ idx + 1 ] ) | 1 ;
iommu - > root_entry [ bus ] . hi = val ;
}
2022-07-12 00:08:56 +00:00
spin_unlock ( & iommu - > lock ) ;
2015-06-12 09:56:10 +00:00
kfree ( ctxt_tbls ) ;
__iommu_flush_cache ( iommu , iommu - > root_entry , PAGE_SIZE ) ;
ret = 0 ;
out_unmap :
2015-10-09 22:16:46 +00:00
memunmap ( old_rt ) ;
2015-06-12 09:56:10 +00:00
return ret ;
}
2011-05-03 07:08:37 +00:00
static int __init init_dmars ( void )
2007-10-21 23:41:49 +00:00
{
struct dmar_drhd_unit * drhd ;
struct intel_iommu * iommu ;
2019-05-25 05:41:36 +00:00
int ret ;
2009-06-19 20:47:29 +00:00
2021-02-04 01:43:56 +00:00
ret = intel_cap_audit ( CAP_AUDIT_STATIC_DMAR , NULL ) ;
if ( ret )
goto free_iommu ;
2019-06-12 00:28:47 +00:00
for_each_iommu ( iommu , drhd ) {
if ( drhd - > ignored ) {
iommu_disable_translation ( iommu ) ;
continue ;
}
2018-07-14 07:46:54 +00:00
/*
* Find the max pasid size of all IOMMU ' s in the system .
* We need to ensure the system pasid table is no bigger
* than the smallest supported .
*/
2018-12-10 01:58:55 +00:00
if ( pasid_supported ( iommu ) ) {
2018-07-14 07:46:54 +00:00
u32 temp = 2 < < ecap_pss ( iommu - > ecap ) ;
intel_pasid_max_id = min_t ( u32 , temp ,
intel_pasid_max_id ) ;
}
2015-06-12 07:14:34 +00:00
intel_iommu_init_qi ( iommu ) ;
2008-07-10 18:16:35 +00:00
ret = iommu_init_domains ( iommu ) ;
if ( ret )
2014-02-19 06:07:21 +00:00
goto free_iommu ;
2008-07-10 18:16:35 +00:00
2015-06-12 08:14:02 +00:00
init_translation_status ( iommu ) ;
2015-06-12 09:56:10 +00:00
if ( translation_pre_enabled ( iommu ) & & ! is_kdump_kernel ( ) ) {
iommu_disable_translation ( iommu ) ;
clear_translation_pre_enabled ( iommu ) ;
pr_warn ( " Translation was enabled for %s but we are not in kdump mode \n " ,
iommu - > name ) ;
}
2015-06-12 08:14:02 +00:00
2007-10-21 23:41:49 +00:00
/*
* TBD :
* we could share the same root & context tables
2011-03-31 01:57:33 +00:00
* among all IOMMU ' s . Need to Split it later .
2007-10-21 23:41:49 +00:00
*/
ret = iommu_alloc_root_entry ( iommu ) ;
2014-11-09 14:48:02 +00:00
if ( ret )
2014-02-19 06:07:21 +00:00
goto free_iommu ;
2015-06-12 07:18:53 +00:00
2015-06-12 09:56:10 +00:00
if ( translation_pre_enabled ( iommu ) ) {
pr_info ( " Translation already enabled - trying to copy translation structures \n " ) ;
ret = copy_translation_tables ( iommu ) ;
if ( ret ) {
/*
* We found the IOMMU with translation
* enabled - but failed to copy over the
* old root - entry table . Try to proceed
* by disabling translation now and
* allocating a clean root - entry table .
* This might cause DMAR faults , but
* probably the dump will still succeed .
*/
pr_err ( " Failed to copy translation tables from previous kernel for %s \n " ,
iommu - > name ) ;
iommu_disable_translation ( iommu ) ;
clear_translation_pre_enabled ( iommu ) ;
} else {
pr_info ( " Copied translation tables from previous kernel for %s \n " ,
iommu - > name ) ;
}
}
2009-04-25 00:30:20 +00:00
if ( ! ecap_pass_through ( iommu - > ecap ) )
2009-08-04 15:19:20 +00:00
hw_pass_through = 0 ;
2020-01-02 00:18:03 +00:00
intel_svm_check ( iommu ) ;
2007-10-21 23:41:49 +00:00
}
2016-06-17 09:29:48 +00:00
/*
* Now that qi is enabled on all iommus , set the root entry and flush
* caches . This is required on some Intel X58 chipsets , otherwise the
* flush_context function will loop forever and the boot hangs .
*/
for_each_active_iommu ( iommu , drhd ) {
iommu_flush_write_buffer ( iommu ) ;
iommu_set_root_entry ( iommu ) ;
}
2011-08-24 00:05:25 +00:00
# ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
2019-05-02 01:34:26 +00:00
dmar_map_gfx = 0 ;
2009-08-04 15:19:20 +00:00
# endif
2009-09-30 16:12:17 +00:00
2019-05-02 01:34:26 +00:00
if ( ! dmar_map_gfx )
iommu_identity_mapping | = IDENTMAP_GFX ;
2017-01-30 17:39:53 +00:00
check_tylersburg_isoch ( ) ;
2019-05-25 05:41:27 +00:00
ret = si_domain_init ( hw_pass_through ) ;
if ( ret )
goto free_iommu ;
2015-06-12 10:27:16 +00:00
2007-10-21 23:41:49 +00:00
/*
* for each drhd
* enable fault log
* global invalidate context cache
* global invalidate iotlb
* enable translation
*/
2014-01-06 06:18:18 +00:00
for_each_iommu ( iommu , drhd ) {
2011-03-21 18:04:24 +00:00
if ( drhd - > ignored ) {
/*
* we always have to disable PMRs or DMA may fail on
* this device
*/
if ( force_on )
2014-01-06 06:18:18 +00:00
iommu_disable_protect_mem_regions ( iommu ) ;
2007-10-21 23:41:49 +00:00
continue ;
2011-03-21 18:04:24 +00:00
}
2007-10-21 23:41:49 +00:00
iommu_flush_write_buffer ( iommu ) ;
2015-10-07 22:35:18 +00:00
# ifdef CONFIG_INTEL_IOMMU_SVM
2018-12-10 01:58:55 +00:00
if ( pasid_supported ( iommu ) & & ecap_prs ( iommu - > ecap ) ) {
2019-04-19 06:43:29 +00:00
/*
* Call dmar_alloc_hwirq ( ) with dmar_global_lock held ,
* could cause possible lock race condition .
*/
up_write ( & dmar_global_lock ) ;
2015-10-07 22:35:18 +00:00
ret = intel_svm_enable_prq ( iommu ) ;
2019-04-19 06:43:29 +00:00
down_write ( & dmar_global_lock ) ;
2015-10-07 22:35:18 +00:00
if ( ret )
goto free_iommu ;
}
# endif
2007-10-21 23:41:54 +00:00
ret = dmar_set_interrupt ( iommu ) ;
if ( ret )
2014-02-19 06:07:21 +00:00
goto free_iommu ;
2007-10-21 23:41:49 +00:00
}
return 0 ;
2014-02-19 06:07:21 +00:00
free_iommu :
2014-11-09 14:48:02 +00:00
for_each_active_iommu ( iommu , drhd ) {
disable_dmar_iommu ( iommu ) ;
2014-01-06 06:18:20 +00:00
free_dmar_iommu ( iommu ) ;
2014-11-09 14:48:02 +00:00
}
2022-10-19 00:44:47 +00:00
if ( si_domain ) {
domain_exit ( si_domain ) ;
si_domain = NULL ;
}
2017-08-11 09:40:10 +00:00
2007-10-21 23:41:49 +00:00
return ret ;
}
static void __init init_no_remapping_devices ( void )
{
struct dmar_drhd_unit * drhd ;
2014-03-07 15:08:36 +00:00
struct device * dev ;
2014-02-19 06:07:32 +00:00
int i ;
2007-10-21 23:41:49 +00:00
for_each_drhd_unit ( drhd ) {
if ( ! drhd - > include_all ) {
2014-02-19 06:07:32 +00:00
for_each_active_dev_scope ( drhd - > devices ,
drhd - > devices_cnt , i , dev )
break ;
2014-03-07 15:08:36 +00:00
/* ignore DMAR unit if no devices exist */
2007-10-21 23:41:49 +00:00
if ( i = = drhd - > devices_cnt )
drhd - > ignored = 1 ;
}
}
2014-01-06 06:18:18 +00:00
for_each_active_drhd_unit ( drhd ) {
if ( drhd - > include_all )
2007-10-21 23:41:49 +00:00
continue ;
2014-02-19 06:07:32 +00:00
for_each_active_dev_scope ( drhd - > devices ,
drhd - > devices_cnt , i , dev )
2014-03-07 15:08:36 +00:00
if ( ! dev_is_pci ( dev ) | | ! IS_GFX_DEVICE ( to_pci_dev ( dev ) ) )
2007-10-21 23:41:49 +00:00
break ;
if ( i < drhd - > devices_cnt )
continue ;
2011-10-14 19:59:46 +00:00
/* This IOMMU has *only* gfx devices. Either bypass it or
set the gfx_mapped flag , as appropriate */
2020-07-23 01:34:37 +00:00
drhd - > gfx_dedicated = 1 ;
2020-09-03 06:51:32 +00:00
if ( ! dmar_map_gfx )
2011-10-14 19:59:46 +00:00
drhd - > ignored = 1 ;
2007-10-21 23:41:49 +00:00
}
}
2009-03-27 21:22:42 +00:00
# ifdef CONFIG_SUSPEND
static int init_iommu_hw ( void )
{
struct dmar_drhd_unit * drhd ;
struct intel_iommu * iommu = NULL ;
2023-06-14 02:47:03 +00:00
int ret ;
2009-03-27 21:22:42 +00:00
2023-06-14 02:47:03 +00:00
for_each_active_iommu ( iommu , drhd ) {
if ( iommu - > qi ) {
ret = dmar_reenable_qi ( iommu ) ;
if ( ret )
return ret ;
}
}
2009-03-27 21:22:42 +00:00
2011-05-03 07:08:37 +00:00
for_each_iommu ( iommu , drhd ) {
if ( drhd - > ignored ) {
/*
* we always have to disable PMRs or DMA may fail on
* this device
*/
if ( force_on )
iommu_disable_protect_mem_regions ( iommu ) ;
continue ;
}
2019-04-29 01:16:02 +00:00
2009-03-27 21:22:42 +00:00
iommu_flush_write_buffer ( iommu ) ;
iommu_set_root_entry ( iommu ) ;
2014-07-11 06:19:33 +00:00
iommu_enable_translation ( iommu ) ;
2009-09-19 22:28:12 +00:00
iommu_disable_protect_mem_regions ( iommu ) ;
2009-03-27 21:22:42 +00:00
}
return 0 ;
}
static void iommu_flush_all ( void )
{
struct dmar_drhd_unit * drhd ;
struct intel_iommu * iommu ;
for_each_active_iommu ( iommu , drhd ) {
iommu - > flush . flush_context ( iommu , 0 , 0 , 0 ,
2009-05-10 18:58:49 +00:00
DMA_CCMD_GLOBAL_INVL ) ;
2009-03-27 21:22:42 +00:00
iommu - > flush . flush_iotlb ( iommu , 0 , 0 , 0 ,
2009-05-10 18:58:49 +00:00
DMA_TLB_GLOBAL_FLUSH ) ;
2009-03-27 21:22:42 +00:00
}
}
2011-03-23 21:16:14 +00:00
static int iommu_suspend ( void )
2009-03-27 21:22:42 +00:00
{
struct dmar_drhd_unit * drhd ;
struct intel_iommu * iommu = NULL ;
unsigned long flag ;
iommu_flush_all ( ) ;
for_each_active_iommu ( iommu , drhd ) {
iommu_disable_translation ( iommu ) ;
2011-07-19 14:19:51 +00:00
raw_spin_lock_irqsave ( & iommu - > register_lock , flag ) ;
2009-03-27 21:22:42 +00:00
iommu - > iommu_state [ SR_DMAR_FECTL_REG ] =
readl ( iommu - > reg + DMAR_FECTL_REG ) ;
iommu - > iommu_state [ SR_DMAR_FEDATA_REG ] =
readl ( iommu - > reg + DMAR_FEDATA_REG ) ;
iommu - > iommu_state [ SR_DMAR_FEADDR_REG ] =
readl ( iommu - > reg + DMAR_FEADDR_REG ) ;
iommu - > iommu_state [ SR_DMAR_FEUADDR_REG ] =
readl ( iommu - > reg + DMAR_FEUADDR_REG ) ;
2011-07-19 14:19:51 +00:00
raw_spin_unlock_irqrestore ( & iommu - > register_lock , flag ) ;
2009-03-27 21:22:42 +00:00
}
return 0 ;
}
2011-03-23 21:16:14 +00:00
static void iommu_resume ( void )
2009-03-27 21:22:42 +00:00
{
struct dmar_drhd_unit * drhd ;
struct intel_iommu * iommu = NULL ;
unsigned long flag ;
if ( init_iommu_hw ( ) ) {
2011-05-03 07:08:37 +00:00
if ( force_on )
panic ( " tboot: IOMMU setup failed, DMAR can not resume! \n " ) ;
else
WARN ( 1 , " IOMMU setup failed, DMAR can not resume! \n " ) ;
2011-03-23 21:16:14 +00:00
return ;
2009-03-27 21:22:42 +00:00
}
for_each_active_iommu ( iommu , drhd ) {
2011-07-19 14:19:51 +00:00
raw_spin_lock_irqsave ( & iommu - > register_lock , flag ) ;
2009-03-27 21:22:42 +00:00
writel ( iommu - > iommu_state [ SR_DMAR_FECTL_REG ] ,
iommu - > reg + DMAR_FECTL_REG ) ;
writel ( iommu - > iommu_state [ SR_DMAR_FEDATA_REG ] ,
iommu - > reg + DMAR_FEDATA_REG ) ;
writel ( iommu - > iommu_state [ SR_DMAR_FEADDR_REG ] ,
iommu - > reg + DMAR_FEADDR_REG ) ;
writel ( iommu - > iommu_state [ SR_DMAR_FEUADDR_REG ] ,
iommu - > reg + DMAR_FEUADDR_REG ) ;
2011-07-19 14:19:51 +00:00
raw_spin_unlock_irqrestore ( & iommu - > register_lock , flag ) ;
2009-03-27 21:22:42 +00:00
}
}
2011-03-23 21:16:14 +00:00
static struct syscore_ops iommu_syscore_ops = {
2009-03-27 21:22:42 +00:00
. resume = iommu_resume ,
. suspend = iommu_suspend ,
} ;
2011-03-23 21:16:14 +00:00
static void __init init_iommu_pm_ops ( void )
2009-03-27 21:22:42 +00:00
{
2011-03-23 21:16:14 +00:00
register_syscore_ops ( & iommu_syscore_ops ) ;
2009-03-27 21:22:42 +00:00
}
# else
2011-06-07 19:32:31 +00:00
static inline void init_iommu_pm_ops ( void ) { }
2009-03-27 21:22:42 +00:00
# endif /* CONFIG_PM */
2022-03-01 02:01:57 +00:00
static int __init rmrr_sanity_check ( struct acpi_dmar_reserved_memory * rmrr )
2020-01-15 03:03:57 +00:00
{
if ( ! IS_ALIGNED ( rmrr - > base_address , PAGE_SIZE ) | |
! IS_ALIGNED ( rmrr - > end_address + 1 , PAGE_SIZE ) | |
rmrr - > end_address < = rmrr - > base_address | |
arch_rmrr_sanity_check ( rmrr ) )
return - EINVAL ;
return 0 ;
}
2014-11-09 14:47:56 +00:00
int __init dmar_parse_one_rmrr ( struct acpi_dmar_header * header , void * arg )
2011-08-24 00:05:20 +00:00
{
struct acpi_dmar_reserved_memory * rmrr ;
struct dmar_rmrr_unit * rmrru ;
2019-10-17 11:39:19 +00:00
rmrr = ( struct acpi_dmar_reserved_memory * ) header ;
iommu/vt-d: dmar_parse_one_rmrr: replace WARN_TAINT with pr_warn + add_taint
Quoting from the comment describing the WARN functions in
include/asm-generic/bug.h:
* WARN(), WARN_ON(), WARN_ON_ONCE, and so on can be used to report
* significant kernel issues that need prompt attention if they should ever
* appear at runtime.
*
* Do not use these macros when checking for invalid external inputs
The (buggy) firmware tables which the dmar code was calling WARN_TAINT
for really are invalid external inputs. They are not under the kernel's
control and the issues in them cannot be fixed by a kernel update.
So logging a backtrace, which invites bug reports to be filed about this,
is not helpful.
Some distros, e.g. Fedora, have tools watching for the kernel backtraces
logged by the WARN macros and offer the user an option to file a bug for
this when these are encountered. The WARN_TAINT in dmar_parse_one_rmrr
+ another iommu WARN_TAINT, addressed in another patch, have lead to over
a 100 bugs being filed this way.
This commit replaces the WARN_TAINT("...") call, with a
pr_warn(FW_BUG "...") + add_taint(TAINT_FIRMWARE_WORKAROUND, ...) call
avoiding the backtrace and thus also avoiding bug-reports being filed
about this against the kernel.
Fixes: f5a68bb0752e ("iommu/vt-d: Mark firmware tainted if RMRR fails sanity check")
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Cc: stable@vger.kernel.org
Cc: Barret Rhoden <brho@google.com>
Link: https://lore.kernel.org/r/20200309140138.3753-3-hdegoede@redhat.com
BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1808874
2020-03-09 14:01:38 +00:00
if ( rmrr_sanity_check ( rmrr ) ) {
pr_warn ( FW_BUG
2020-01-15 03:03:56 +00:00
" Your BIOS is broken; bad RMRR [%#018Lx-%#018Lx] \n "
" BIOS vendor: %s; Ver: %s; Product Version: %s \n " ,
rmrr - > base_address , rmrr - > end_address ,
dmi_get_system_info ( DMI_BIOS_VENDOR ) ,
dmi_get_system_info ( DMI_BIOS_VERSION ) ,
dmi_get_system_info ( DMI_PRODUCT_VERSION ) ) ;
iommu/vt-d: dmar_parse_one_rmrr: replace WARN_TAINT with pr_warn + add_taint
Quoting from the comment describing the WARN functions in
include/asm-generic/bug.h:
* WARN(), WARN_ON(), WARN_ON_ONCE, and so on can be used to report
* significant kernel issues that need prompt attention if they should ever
* appear at runtime.
*
* Do not use these macros when checking for invalid external inputs
The (buggy) firmware tables which the dmar code was calling WARN_TAINT
for really are invalid external inputs. They are not under the kernel's
control and the issues in them cannot be fixed by a kernel update.
So logging a backtrace, which invites bug reports to be filed about this,
is not helpful.
Some distros, e.g. Fedora, have tools watching for the kernel backtraces
logged by the WARN macros and offer the user an option to file a bug for
this when these are encountered. The WARN_TAINT in dmar_parse_one_rmrr
+ another iommu WARN_TAINT, addressed in another patch, have lead to over
a 100 bugs being filed this way.
This commit replaces the WARN_TAINT("...") call, with a
pr_warn(FW_BUG "...") + add_taint(TAINT_FIRMWARE_WORKAROUND, ...) call
avoiding the backtrace and thus also avoiding bug-reports being filed
about this against the kernel.
Fixes: f5a68bb0752e ("iommu/vt-d: Mark firmware tainted if RMRR fails sanity check")
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Cc: stable@vger.kernel.org
Cc: Barret Rhoden <brho@google.com>
Link: https://lore.kernel.org/r/20200309140138.3753-3-hdegoede@redhat.com
BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1808874
2020-03-09 14:01:38 +00:00
add_taint ( TAINT_FIRMWARE_WORKAROUND , LOCKDEP_STILL_OK ) ;
}
2011-08-24 00:05:20 +00:00
rmrru = kzalloc ( sizeof ( * rmrru ) , GFP_KERNEL ) ;
if ( ! rmrru )
2017-01-19 20:57:53 +00:00
goto out ;
2011-08-24 00:05:20 +00:00
rmrru - > hdr = header ;
2019-10-17 11:39:19 +00:00
2011-08-24 00:05:20 +00:00
rmrru - > base_address = rmrr - > base_address ;
rmrru - > end_address = rmrr - > end_address ;
2017-01-19 20:57:53 +00:00
2014-02-19 06:07:36 +00:00
rmrru - > devices = dmar_alloc_dev_scope ( ( void * ) ( rmrr + 1 ) ,
( ( void * ) rmrr ) + rmrr - > header . length ,
& rmrru - > devices_cnt ) ;
2017-01-19 20:57:53 +00:00
if ( rmrru - > devices_cnt & & rmrru - > devices = = NULL )
2019-06-03 06:53:31 +00:00
goto free_rmrru ;
2011-08-24 00:05:20 +00:00
2014-02-19 06:07:36 +00:00
list_add ( & rmrru - > list , & dmar_rmrr_units ) ;
2011-08-24 00:05:20 +00:00
2014-02-19 06:07:36 +00:00
return 0 ;
2017-01-19 20:57:53 +00:00
free_rmrru :
kfree ( rmrru ) ;
out :
return - ENOMEM ;
2011-08-24 00:05:20 +00:00
}
2014-11-09 14:47:58 +00:00
static struct dmar_atsr_unit * dmar_find_atsr ( struct acpi_dmar_atsr * atsr )
{
struct dmar_atsr_unit * atsru ;
struct acpi_dmar_atsr * tmp ;
2020-03-17 15:03:26 +00:00
list_for_each_entry_rcu ( atsru , & dmar_atsr_units , list ,
dmar_rcu_check ( ) ) {
2014-11-09 14:47:58 +00:00
tmp = ( struct acpi_dmar_atsr * ) atsru - > hdr ;
if ( atsr - > segment ! = tmp - > segment )
continue ;
if ( atsr - > header . length ! = tmp - > header . length )
continue ;
if ( memcmp ( atsr , tmp , atsr - > header . length ) = = 0 )
return atsru ;
}
return NULL ;
}
int dmar_parse_one_atsr ( struct acpi_dmar_header * hdr , void * arg )
2011-08-24 00:05:20 +00:00
{
struct acpi_dmar_atsr * atsr ;
struct dmar_atsr_unit * atsru ;
2017-05-16 18:42:41 +00:00
if ( system_state > = SYSTEM_RUNNING & & ! intel_iommu_enabled )
2014-11-09 14:47:58 +00:00
return 0 ;
2011-08-24 00:05:20 +00:00
atsr = container_of ( hdr , struct acpi_dmar_atsr , header ) ;
2014-11-09 14:47:58 +00:00
atsru = dmar_find_atsr ( atsr ) ;
if ( atsru )
return 0 ;
atsru = kzalloc ( sizeof ( * atsru ) + hdr - > length , GFP_KERNEL ) ;
2011-08-24 00:05:20 +00:00
if ( ! atsru )
return - ENOMEM ;
2014-11-09 14:47:58 +00:00
/*
* If memory is allocated from slab by ACPI _DSM method , we need to
* copy the memory content because the memory buffer will be freed
* on return .
*/
atsru - > hdr = ( void * ) ( atsru + 1 ) ;
memcpy ( atsru - > hdr , hdr , hdr - > length ) ;
2011-08-24 00:05:20 +00:00
atsru - > include_all = atsr - > flags & 0x1 ;
2014-02-19 06:07:36 +00:00
if ( ! atsru - > include_all ) {
atsru - > devices = dmar_alloc_dev_scope ( ( void * ) ( atsr + 1 ) ,
( void * ) atsr + atsr - > header . length ,
& atsru - > devices_cnt ) ;
if ( atsru - > devices_cnt & & atsru - > devices = = NULL ) {
kfree ( atsru ) ;
return - ENOMEM ;
}
}
2011-08-24 00:05:20 +00:00
2014-02-19 06:07:34 +00:00
list_add_rcu ( & atsru - > list , & dmar_atsr_units ) ;
2011-08-24 00:05:20 +00:00
return 0 ;
}
2014-01-06 06:18:27 +00:00
static void intel_iommu_free_atsr ( struct dmar_atsr_unit * atsru )
{
dmar_free_dev_scope ( & atsru - > devices , & atsru - > devices_cnt ) ;
kfree ( atsru ) ;
}
2014-11-09 14:47:58 +00:00
int dmar_release_one_atsr ( struct acpi_dmar_header * hdr , void * arg )
{
struct acpi_dmar_atsr * atsr ;
struct dmar_atsr_unit * atsru ;
atsr = container_of ( hdr , struct acpi_dmar_atsr , header ) ;
atsru = dmar_find_atsr ( atsr ) ;
if ( atsru ) {
list_del_rcu ( & atsru - > list ) ;
synchronize_rcu ( ) ;
intel_iommu_free_atsr ( atsru ) ;
}
return 0 ;
}
int dmar_check_one_atsr ( struct acpi_dmar_header * hdr , void * arg )
{
int i ;
struct device * dev ;
struct acpi_dmar_atsr * atsr ;
struct dmar_atsr_unit * atsru ;
atsr = container_of ( hdr , struct acpi_dmar_atsr , header ) ;
atsru = dmar_find_atsr ( atsr ) ;
if ( ! atsru )
return 0 ;
2016-07-28 03:03:31 +00:00
if ( ! atsru - > include_all & & atsru - > devices & & atsru - > devices_cnt ) {
2014-11-09 14:47:58 +00:00
for_each_active_dev_scope ( atsru - > devices , atsru - > devices_cnt ,
i , dev )
return - EBUSY ;
2016-07-28 03:03:31 +00:00
}
2014-11-09 14:47:58 +00:00
return 0 ;
}
2021-02-04 01:44:00 +00:00
static struct dmar_satc_unit * dmar_find_satc ( struct acpi_dmar_satc * satc )
{
struct dmar_satc_unit * satcu ;
struct acpi_dmar_satc * tmp ;
list_for_each_entry_rcu ( satcu , & dmar_satc_units , list ,
dmar_rcu_check ( ) ) {
tmp = ( struct acpi_dmar_satc * ) satcu - > hdr ;
if ( satc - > segment ! = tmp - > segment )
continue ;
if ( satc - > header . length ! = tmp - > header . length )
continue ;
if ( memcmp ( satc , tmp , satc - > header . length ) = = 0 )
return satcu ;
}
return NULL ;
}
int dmar_parse_one_satc ( struct acpi_dmar_header * hdr , void * arg )
{
struct acpi_dmar_satc * satc ;
struct dmar_satc_unit * satcu ;
if ( system_state > = SYSTEM_RUNNING & & ! intel_iommu_enabled )
return 0 ;
satc = container_of ( hdr , struct acpi_dmar_satc , header ) ;
satcu = dmar_find_satc ( satc ) ;
if ( satcu )
return 0 ;
satcu = kzalloc ( sizeof ( * satcu ) + hdr - > length , GFP_KERNEL ) ;
if ( ! satcu )
return - ENOMEM ;
satcu - > hdr = ( void * ) ( satcu + 1 ) ;
memcpy ( satcu - > hdr , hdr , hdr - > length ) ;
satcu - > atc_required = satc - > flags & 0x1 ;
satcu - > devices = dmar_alloc_dev_scope ( ( void * ) ( satc + 1 ) ,
( void * ) satc + satc - > header . length ,
& satcu - > devices_cnt ) ;
if ( satcu - > devices_cnt & & ! satcu - > devices ) {
kfree ( satcu ) ;
return - ENOMEM ;
}
list_add_rcu ( & satcu - > list , & dmar_satc_units ) ;
return 0 ;
}
2014-11-09 14:48:02 +00:00
static int intel_iommu_add ( struct dmar_drhd_unit * dmaru )
{
2019-02-08 22:06:08 +00:00
int sp , ret ;
2014-11-09 14:48:02 +00:00
struct intel_iommu * iommu = dmaru - > iommu ;
2021-02-04 01:43:56 +00:00
ret = intel_cap_audit ( CAP_AUDIT_HOTPLUG_DMAR , iommu ) ;
if ( ret )
goto out ;
2014-11-09 14:48:02 +00:00
if ( hw_pass_through & & ! ecap_pass_through ( iommu - > ecap ) ) {
2015-06-12 07:57:06 +00:00
pr_warn ( " %s: Doesn't support hardware pass through. \n " ,
2014-11-09 14:48:02 +00:00
iommu - > name ) ;
return - ENXIO ;
}
2022-05-10 02:34:06 +00:00
2020-01-02 00:18:20 +00:00
sp = domain_update_iommu_superpage ( NULL , iommu ) - 1 ;
2014-11-09 14:48:02 +00:00
if ( sp > = 0 & & ! ( cap_super_page_val ( iommu - > cap ) & ( 1 < < sp ) ) ) {
2015-06-12 07:57:06 +00:00
pr_warn ( " %s: Doesn't support large page. \n " ,
2014-11-09 14:48:02 +00:00
iommu - > name ) ;
return - ENXIO ;
}
/*
* Disable translation if already enabled prior to OS handover .
*/
if ( iommu - > gcmd & DMA_GCMD_TE )
iommu_disable_translation ( iommu ) ;
ret = iommu_init_domains ( iommu ) ;
if ( ret = = 0 )
ret = iommu_alloc_root_entry ( iommu ) ;
if ( ret )
goto out ;
2020-01-02 00:18:03 +00:00
intel_svm_check ( iommu ) ;
2015-03-24 14:54:56 +00:00
2014-11-09 14:48:02 +00:00
if ( dmaru - > ignored ) {
/*
* we always have to disable PMRs or DMA may fail on this device
*/
if ( force_on )
iommu_disable_protect_mem_regions ( iommu ) ;
return 0 ;
}
intel_iommu_init_qi ( iommu ) ;
iommu_flush_write_buffer ( iommu ) ;
2015-10-07 22:35:18 +00:00
# ifdef CONFIG_INTEL_IOMMU_SVM
2018-12-10 01:58:55 +00:00
if ( pasid_supported ( iommu ) & & ecap_prs ( iommu - > ecap ) ) {
2015-10-07 22:35:18 +00:00
ret = intel_svm_enable_prq ( iommu ) ;
if ( ret )
goto disable_iommu ;
}
# endif
2014-11-09 14:48:02 +00:00
ret = dmar_set_interrupt ( iommu ) ;
if ( ret )
goto disable_iommu ;
iommu_set_root_entry ( iommu ) ;
iommu_enable_translation ( iommu ) ;
iommu_disable_protect_mem_regions ( iommu ) ;
return 0 ;
disable_iommu :
disable_dmar_iommu ( iommu ) ;
out :
free_dmar_iommu ( iommu ) ;
return ret ;
}
2014-11-09 14:47:58 +00:00
int dmar_iommu_hotplug ( struct dmar_drhd_unit * dmaru , bool insert )
{
2014-11-09 14:48:02 +00:00
int ret = 0 ;
struct intel_iommu * iommu = dmaru - > iommu ;
if ( ! intel_iommu_enabled )
return 0 ;
if ( iommu = = NULL )
return - EINVAL ;
if ( insert ) {
ret = intel_iommu_add ( dmaru ) ;
} else {
disable_dmar_iommu ( iommu ) ;
free_dmar_iommu ( iommu ) ;
}
return ret ;
2014-11-09 14:47:58 +00:00
}
2014-01-06 06:18:27 +00:00
static void intel_iommu_free_dmars ( void )
{
struct dmar_rmrr_unit * rmrru , * rmrr_n ;
struct dmar_atsr_unit * atsru , * atsr_n ;
2021-02-04 01:44:00 +00:00
struct dmar_satc_unit * satcu , * satc_n ;
2014-01-06 06:18:27 +00:00
list_for_each_entry_safe ( rmrru , rmrr_n , & dmar_rmrr_units , list ) {
list_del ( & rmrru - > list ) ;
dmar_free_dev_scope ( & rmrru - > devices , & rmrru - > devices_cnt ) ;
kfree ( rmrru ) ;
2011-08-24 00:05:20 +00:00
}
2014-01-06 06:18:27 +00:00
list_for_each_entry_safe ( atsru , atsr_n , & dmar_atsr_units , list ) {
list_del ( & atsru - > list ) ;
intel_iommu_free_atsr ( atsru ) ;
}
2021-02-04 01:44:00 +00:00
list_for_each_entry_safe ( satcu , satc_n , & dmar_satc_units , list ) {
list_del ( & satcu - > list ) ;
dmar_free_dev_scope ( & satcu - > devices , & satcu - > devices_cnt ) ;
kfree ( satcu ) ;
}
2011-08-24 00:05:20 +00:00
}
2022-03-01 02:01:59 +00:00
static struct dmar_satc_unit * dmar_find_matched_satc_unit ( struct pci_dev * dev )
{
struct dmar_satc_unit * satcu ;
struct acpi_dmar_satc * satc ;
struct device * tmp ;
int i ;
dev = pci_physfn ( dev ) ;
rcu_read_lock ( ) ;
list_for_each_entry_rcu ( satcu , & dmar_satc_units , list ) {
satc = container_of ( satcu - > hdr , struct acpi_dmar_satc , header ) ;
if ( satc - > segment ! = pci_domain_nr ( dev - > bus ) )
continue ;
for_each_dev_scope ( satcu - > devices , satcu - > devices_cnt , i , tmp )
if ( to_pci_dev ( tmp ) = = dev )
goto out ;
}
satcu = NULL ;
out :
rcu_read_unlock ( ) ;
return satcu ;
}
static int dmar_ats_supported ( struct pci_dev * dev , struct intel_iommu * iommu )
2011-08-24 00:05:20 +00:00
{
2014-02-19 06:07:32 +00:00
int i , ret = 1 ;
2011-08-24 00:05:20 +00:00
struct pci_bus * bus ;
2014-03-07 15:08:36 +00:00
struct pci_dev * bridge = NULL ;
struct device * tmp ;
2011-08-24 00:05:20 +00:00
struct acpi_dmar_atsr * atsr ;
struct dmar_atsr_unit * atsru ;
2022-03-01 02:01:59 +00:00
struct dmar_satc_unit * satcu ;
2011-08-24 00:05:20 +00:00
dev = pci_physfn ( dev ) ;
2022-03-01 02:01:59 +00:00
satcu = dmar_find_matched_satc_unit ( dev ) ;
if ( satcu )
/*
* This device supports ATS as it is in SATC table .
* When IOMMU is in legacy mode , enabling ATS is done
* automatically by HW for the device that requires
* ATS , hence OS should not enable this device ATS
* to avoid duplicated TLB invalidation .
*/
return ! ( satcu - > atc_required & & ! sm_supported ( iommu ) ) ;
2011-08-24 00:05:20 +00:00
for ( bus = dev - > bus ; bus ; bus = bus - > parent ) {
iommu/vt-d: Fix error in detect ATS capability
Current Intel IOMMU driver only matches a PCIe root port with the first
DRHD unit with the samge segment number. It will report false result
if there are multiple DRHD units with the same segment number, thus fail
to detect ATS capability for some PCIe devices.
This patch refines function dmar_find_matched_atsr_unit() to search all
DRHD units with the same segment number.
An example DMAR table entries as below:
[1D0h 0464 2] Subtable Type : 0002 <Root Port ATS Capability>
[1D2h 0466 2] Length : 0028
[1D4h 0468 1] Flags : 00
[1D5h 0469 1] Reserved : 00
[1D6h 0470 2] PCI Segment Number : 0000
[1D8h 0472 1] Device Scope Entry Type : 02
[1D9h 0473 1] Entry Length : 08
[1DAh 0474 2] Reserved : 0000
[1DCh 0476 1] Enumeration ID : 00
[1DDh 0477 1] PCI Bus Number : 00
[1DEh 0478 2] PCI Path : [02, 00]
[1E0h 0480 1] Device Scope Entry Type : 02
[1E1h 0481 1] Entry Length : 08
[1E2h 0482 2] Reserved : 0000
[1E4h 0484 1] Enumeration ID : 00
[1E5h 0485 1] PCI Bus Number : 00
[1E6h 0486 2] PCI Path : [03, 00]
[1E8h 0488 1] Device Scope Entry Type : 02
[1E9h 0489 1] Entry Length : 08
[1EAh 0490 2] Reserved : 0000
[1ECh 0492 1] Enumeration ID : 00
[1EDh 0493 1] PCI Bus Number : 00
[1EEh 0494 2] PCI Path : [03, 02]
[1F0h 0496 1] Device Scope Entry Type : 02
[1F1h 0497 1] Entry Length : 08
[1F2h 0498 2] Reserved : 0000
[1F4h 0500 1] Enumeration ID : 00
[1F5h 0501 1] PCI Bus Number : 00
[1F6h 0502 2] PCI Path : [03, 03]
[1F8h 0504 2] Subtable Type : 0002 <Root Port ATS Capability>
[1FAh 0506 2] Length : 0020
[1FCh 0508 1] Flags : 00
[1FDh 0509 1] Reserved : 00
[1FEh 0510 2] PCI Segment Number : 0000
[200h 0512 1] Device Scope Entry Type : 02
[201h 0513 1] Entry Length : 08
[202h 0514 2] Reserved : 0000
[204h 0516 1] Enumeration ID : 00
[205h 0517 1] PCI Bus Number : 40
[206h 0518 2] PCI Path : [02, 00]
[208h 0520 1] Device Scope Entry Type : 02
[209h 0521 1] Entry Length : 08
[20Ah 0522 2] Reserved : 0000
[20Ch 0524 1] Enumeration ID : 00
[20Dh 0525 1] PCI Bus Number : 40
[20Eh 0526 2] PCI Path : [02, 02]
[210h 0528 1] Device Scope Entry Type : 02
[211h 0529 1] Entry Length : 08
[212h 0530 2] Reserved : 0000
[214h 0532 1] Enumeration ID : 00
[215h 0533 1] PCI Bus Number : 40
[216h 0534 2] PCI Path : [03, 00]
[218h 0536 2] Subtable Type : 0002 <Root Port ATS Capability>
[21Ah 0538 2] Length : 0020
[21Ch 0540 1] Flags : 00
[21Dh 0541 1] Reserved : 00
[21Eh 0542 2] PCI Segment Number : 0000
[220h 0544 1] Device Scope Entry Type : 02
[221h 0545 1] Entry Length : 08
[222h 0546 2] Reserved : 0000
[224h 0548 1] Enumeration ID : 00
[225h 0549 1] PCI Bus Number : 80
[226h 0550 2] PCI Path : [02, 00]
[228h 0552 1] Device Scope Entry Type : 02
[229h 0553 1] Entry Length : 08
[22Ah 0554 2] Reserved : 0000
[22Ch 0556 1] Enumeration ID : 00
[22Dh 0557 1] PCI Bus Number : 80
[22Eh 0558 2] PCI Path : [02, 02]
[230h 0560 1] Device Scope Entry Type : 02
[231h 0561 1] Entry Length : 08
[232h 0562 2] Reserved : 0000
[234h 0564 1] Enumeration ID : 00
[235h 0565 1] PCI Bus Number : 80
[236h 0566 2] PCI Path : [03, 00]
[238h 0568 2] Subtable Type : 0002 <Root Port ATS Capability>
[23Ah 0570 2] Length : 0020
[23Ch 0572 1] Flags : 00
[23Dh 0573 1] Reserved : 00
[23Eh 0574 2] PCI Segment Number : 0000
[240h 0576 1] Device Scope Entry Type : 02
[241h 0577 1] Entry Length : 08
[242h 0578 2] Reserved : 0000
[244h 0580 1] Enumeration ID : 00
[245h 0581 1] PCI Bus Number : C0
[246h 0582 2] PCI Path : [02, 00]
[248h 0584 1] Device Scope Entry Type : 02
[249h 0585 1] Entry Length : 08
[24Ah 0586 2] Reserved : 0000
[24Ch 0588 1] Enumeration ID : 00
[24Dh 0589 1] PCI Bus Number : C0
[24Eh 0590 2] PCI Path : [02, 02]
[250h 0592 1] Device Scope Entry Type : 02
[251h 0593 1] Entry Length : 08
[252h 0594 2] Reserved : 0000
[254h 0596 1] Enumeration ID : 00
[255h 0597 1] PCI Bus Number : C0
[256h 0598 2] PCI Path : [03, 00]
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:31 +00:00
bridge = bus - > self ;
2015-10-15 08:28:06 +00:00
/* If it's an integrated device, allow ATS */
if ( ! bridge )
return 1 ;
/* Connected via non-PCIe: no ATS */
if ( ! pci_is_pcie ( bridge ) | |
2012-07-24 09:20:03 +00:00
pci_pcie_type ( bridge ) = = PCI_EXP_TYPE_PCI_BRIDGE )
2011-08-24 00:05:20 +00:00
return 0 ;
2015-10-15 08:28:06 +00:00
/* If we found the root port, look it up in the ATSR */
iommu/vt-d: Fix error in detect ATS capability
Current Intel IOMMU driver only matches a PCIe root port with the first
DRHD unit with the samge segment number. It will report false result
if there are multiple DRHD units with the same segment number, thus fail
to detect ATS capability for some PCIe devices.
This patch refines function dmar_find_matched_atsr_unit() to search all
DRHD units with the same segment number.
An example DMAR table entries as below:
[1D0h 0464 2] Subtable Type : 0002 <Root Port ATS Capability>
[1D2h 0466 2] Length : 0028
[1D4h 0468 1] Flags : 00
[1D5h 0469 1] Reserved : 00
[1D6h 0470 2] PCI Segment Number : 0000
[1D8h 0472 1] Device Scope Entry Type : 02
[1D9h 0473 1] Entry Length : 08
[1DAh 0474 2] Reserved : 0000
[1DCh 0476 1] Enumeration ID : 00
[1DDh 0477 1] PCI Bus Number : 00
[1DEh 0478 2] PCI Path : [02, 00]
[1E0h 0480 1] Device Scope Entry Type : 02
[1E1h 0481 1] Entry Length : 08
[1E2h 0482 2] Reserved : 0000
[1E4h 0484 1] Enumeration ID : 00
[1E5h 0485 1] PCI Bus Number : 00
[1E6h 0486 2] PCI Path : [03, 00]
[1E8h 0488 1] Device Scope Entry Type : 02
[1E9h 0489 1] Entry Length : 08
[1EAh 0490 2] Reserved : 0000
[1ECh 0492 1] Enumeration ID : 00
[1EDh 0493 1] PCI Bus Number : 00
[1EEh 0494 2] PCI Path : [03, 02]
[1F0h 0496 1] Device Scope Entry Type : 02
[1F1h 0497 1] Entry Length : 08
[1F2h 0498 2] Reserved : 0000
[1F4h 0500 1] Enumeration ID : 00
[1F5h 0501 1] PCI Bus Number : 00
[1F6h 0502 2] PCI Path : [03, 03]
[1F8h 0504 2] Subtable Type : 0002 <Root Port ATS Capability>
[1FAh 0506 2] Length : 0020
[1FCh 0508 1] Flags : 00
[1FDh 0509 1] Reserved : 00
[1FEh 0510 2] PCI Segment Number : 0000
[200h 0512 1] Device Scope Entry Type : 02
[201h 0513 1] Entry Length : 08
[202h 0514 2] Reserved : 0000
[204h 0516 1] Enumeration ID : 00
[205h 0517 1] PCI Bus Number : 40
[206h 0518 2] PCI Path : [02, 00]
[208h 0520 1] Device Scope Entry Type : 02
[209h 0521 1] Entry Length : 08
[20Ah 0522 2] Reserved : 0000
[20Ch 0524 1] Enumeration ID : 00
[20Dh 0525 1] PCI Bus Number : 40
[20Eh 0526 2] PCI Path : [02, 02]
[210h 0528 1] Device Scope Entry Type : 02
[211h 0529 1] Entry Length : 08
[212h 0530 2] Reserved : 0000
[214h 0532 1] Enumeration ID : 00
[215h 0533 1] PCI Bus Number : 40
[216h 0534 2] PCI Path : [03, 00]
[218h 0536 2] Subtable Type : 0002 <Root Port ATS Capability>
[21Ah 0538 2] Length : 0020
[21Ch 0540 1] Flags : 00
[21Dh 0541 1] Reserved : 00
[21Eh 0542 2] PCI Segment Number : 0000
[220h 0544 1] Device Scope Entry Type : 02
[221h 0545 1] Entry Length : 08
[222h 0546 2] Reserved : 0000
[224h 0548 1] Enumeration ID : 00
[225h 0549 1] PCI Bus Number : 80
[226h 0550 2] PCI Path : [02, 00]
[228h 0552 1] Device Scope Entry Type : 02
[229h 0553 1] Entry Length : 08
[22Ah 0554 2] Reserved : 0000
[22Ch 0556 1] Enumeration ID : 00
[22Dh 0557 1] PCI Bus Number : 80
[22Eh 0558 2] PCI Path : [02, 02]
[230h 0560 1] Device Scope Entry Type : 02
[231h 0561 1] Entry Length : 08
[232h 0562 2] Reserved : 0000
[234h 0564 1] Enumeration ID : 00
[235h 0565 1] PCI Bus Number : 80
[236h 0566 2] PCI Path : [03, 00]
[238h 0568 2] Subtable Type : 0002 <Root Port ATS Capability>
[23Ah 0570 2] Length : 0020
[23Ch 0572 1] Flags : 00
[23Dh 0573 1] Reserved : 00
[23Eh 0574 2] PCI Segment Number : 0000
[240h 0576 1] Device Scope Entry Type : 02
[241h 0577 1] Entry Length : 08
[242h 0578 2] Reserved : 0000
[244h 0580 1] Enumeration ID : 00
[245h 0581 1] PCI Bus Number : C0
[246h 0582 2] PCI Path : [02, 00]
[248h 0584 1] Device Scope Entry Type : 02
[249h 0585 1] Entry Length : 08
[24Ah 0586 2] Reserved : 0000
[24Ch 0588 1] Enumeration ID : 00
[24Dh 0589 1] PCI Bus Number : C0
[24Eh 0590 2] PCI Path : [02, 02]
[250h 0592 1] Device Scope Entry Type : 02
[251h 0593 1] Entry Length : 08
[252h 0594 2] Reserved : 0000
[254h 0596 1] Enumeration ID : 00
[255h 0597 1] PCI Bus Number : C0
[256h 0598 2] PCI Path : [03, 00]
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:31 +00:00
if ( pci_pcie_type ( bridge ) = = PCI_EXP_TYPE_ROOT_PORT )
2011-08-24 00:05:20 +00:00
break ;
}
2014-02-19 06:07:34 +00:00
rcu_read_lock ( ) ;
iommu/vt-d: Fix error in detect ATS capability
Current Intel IOMMU driver only matches a PCIe root port with the first
DRHD unit with the samge segment number. It will report false result
if there are multiple DRHD units with the same segment number, thus fail
to detect ATS capability for some PCIe devices.
This patch refines function dmar_find_matched_atsr_unit() to search all
DRHD units with the same segment number.
An example DMAR table entries as below:
[1D0h 0464 2] Subtable Type : 0002 <Root Port ATS Capability>
[1D2h 0466 2] Length : 0028
[1D4h 0468 1] Flags : 00
[1D5h 0469 1] Reserved : 00
[1D6h 0470 2] PCI Segment Number : 0000
[1D8h 0472 1] Device Scope Entry Type : 02
[1D9h 0473 1] Entry Length : 08
[1DAh 0474 2] Reserved : 0000
[1DCh 0476 1] Enumeration ID : 00
[1DDh 0477 1] PCI Bus Number : 00
[1DEh 0478 2] PCI Path : [02, 00]
[1E0h 0480 1] Device Scope Entry Type : 02
[1E1h 0481 1] Entry Length : 08
[1E2h 0482 2] Reserved : 0000
[1E4h 0484 1] Enumeration ID : 00
[1E5h 0485 1] PCI Bus Number : 00
[1E6h 0486 2] PCI Path : [03, 00]
[1E8h 0488 1] Device Scope Entry Type : 02
[1E9h 0489 1] Entry Length : 08
[1EAh 0490 2] Reserved : 0000
[1ECh 0492 1] Enumeration ID : 00
[1EDh 0493 1] PCI Bus Number : 00
[1EEh 0494 2] PCI Path : [03, 02]
[1F0h 0496 1] Device Scope Entry Type : 02
[1F1h 0497 1] Entry Length : 08
[1F2h 0498 2] Reserved : 0000
[1F4h 0500 1] Enumeration ID : 00
[1F5h 0501 1] PCI Bus Number : 00
[1F6h 0502 2] PCI Path : [03, 03]
[1F8h 0504 2] Subtable Type : 0002 <Root Port ATS Capability>
[1FAh 0506 2] Length : 0020
[1FCh 0508 1] Flags : 00
[1FDh 0509 1] Reserved : 00
[1FEh 0510 2] PCI Segment Number : 0000
[200h 0512 1] Device Scope Entry Type : 02
[201h 0513 1] Entry Length : 08
[202h 0514 2] Reserved : 0000
[204h 0516 1] Enumeration ID : 00
[205h 0517 1] PCI Bus Number : 40
[206h 0518 2] PCI Path : [02, 00]
[208h 0520 1] Device Scope Entry Type : 02
[209h 0521 1] Entry Length : 08
[20Ah 0522 2] Reserved : 0000
[20Ch 0524 1] Enumeration ID : 00
[20Dh 0525 1] PCI Bus Number : 40
[20Eh 0526 2] PCI Path : [02, 02]
[210h 0528 1] Device Scope Entry Type : 02
[211h 0529 1] Entry Length : 08
[212h 0530 2] Reserved : 0000
[214h 0532 1] Enumeration ID : 00
[215h 0533 1] PCI Bus Number : 40
[216h 0534 2] PCI Path : [03, 00]
[218h 0536 2] Subtable Type : 0002 <Root Port ATS Capability>
[21Ah 0538 2] Length : 0020
[21Ch 0540 1] Flags : 00
[21Dh 0541 1] Reserved : 00
[21Eh 0542 2] PCI Segment Number : 0000
[220h 0544 1] Device Scope Entry Type : 02
[221h 0545 1] Entry Length : 08
[222h 0546 2] Reserved : 0000
[224h 0548 1] Enumeration ID : 00
[225h 0549 1] PCI Bus Number : 80
[226h 0550 2] PCI Path : [02, 00]
[228h 0552 1] Device Scope Entry Type : 02
[229h 0553 1] Entry Length : 08
[22Ah 0554 2] Reserved : 0000
[22Ch 0556 1] Enumeration ID : 00
[22Dh 0557 1] PCI Bus Number : 80
[22Eh 0558 2] PCI Path : [02, 02]
[230h 0560 1] Device Scope Entry Type : 02
[231h 0561 1] Entry Length : 08
[232h 0562 2] Reserved : 0000
[234h 0564 1] Enumeration ID : 00
[235h 0565 1] PCI Bus Number : 80
[236h 0566 2] PCI Path : [03, 00]
[238h 0568 2] Subtable Type : 0002 <Root Port ATS Capability>
[23Ah 0570 2] Length : 0020
[23Ch 0572 1] Flags : 00
[23Dh 0573 1] Reserved : 00
[23Eh 0574 2] PCI Segment Number : 0000
[240h 0576 1] Device Scope Entry Type : 02
[241h 0577 1] Entry Length : 08
[242h 0578 2] Reserved : 0000
[244h 0580 1] Enumeration ID : 00
[245h 0581 1] PCI Bus Number : C0
[246h 0582 2] PCI Path : [02, 00]
[248h 0584 1] Device Scope Entry Type : 02
[249h 0585 1] Entry Length : 08
[24Ah 0586 2] Reserved : 0000
[24Ch 0588 1] Enumeration ID : 00
[24Dh 0589 1] PCI Bus Number : C0
[24Eh 0590 2] PCI Path : [02, 02]
[250h 0592 1] Device Scope Entry Type : 02
[251h 0593 1] Entry Length : 08
[252h 0594 2] Reserved : 0000
[254h 0596 1] Enumeration ID : 00
[255h 0597 1] PCI Bus Number : C0
[256h 0598 2] PCI Path : [03, 00]
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:31 +00:00
list_for_each_entry_rcu ( atsru , & dmar_atsr_units , list ) {
atsr = container_of ( atsru - > hdr , struct acpi_dmar_atsr , header ) ;
if ( atsr - > segment ! = pci_domain_nr ( dev - > bus ) )
continue ;
2014-02-19 06:07:32 +00:00
for_each_dev_scope ( atsru - > devices , atsru - > devices_cnt , i , tmp )
2014-03-07 15:08:36 +00:00
if ( tmp = = & bridge - > dev )
2014-02-19 06:07:32 +00:00
goto out ;
iommu/vt-d: Fix error in detect ATS capability
Current Intel IOMMU driver only matches a PCIe root port with the first
DRHD unit with the samge segment number. It will report false result
if there are multiple DRHD units with the same segment number, thus fail
to detect ATS capability for some PCIe devices.
This patch refines function dmar_find_matched_atsr_unit() to search all
DRHD units with the same segment number.
An example DMAR table entries as below:
[1D0h 0464 2] Subtable Type : 0002 <Root Port ATS Capability>
[1D2h 0466 2] Length : 0028
[1D4h 0468 1] Flags : 00
[1D5h 0469 1] Reserved : 00
[1D6h 0470 2] PCI Segment Number : 0000
[1D8h 0472 1] Device Scope Entry Type : 02
[1D9h 0473 1] Entry Length : 08
[1DAh 0474 2] Reserved : 0000
[1DCh 0476 1] Enumeration ID : 00
[1DDh 0477 1] PCI Bus Number : 00
[1DEh 0478 2] PCI Path : [02, 00]
[1E0h 0480 1] Device Scope Entry Type : 02
[1E1h 0481 1] Entry Length : 08
[1E2h 0482 2] Reserved : 0000
[1E4h 0484 1] Enumeration ID : 00
[1E5h 0485 1] PCI Bus Number : 00
[1E6h 0486 2] PCI Path : [03, 00]
[1E8h 0488 1] Device Scope Entry Type : 02
[1E9h 0489 1] Entry Length : 08
[1EAh 0490 2] Reserved : 0000
[1ECh 0492 1] Enumeration ID : 00
[1EDh 0493 1] PCI Bus Number : 00
[1EEh 0494 2] PCI Path : [03, 02]
[1F0h 0496 1] Device Scope Entry Type : 02
[1F1h 0497 1] Entry Length : 08
[1F2h 0498 2] Reserved : 0000
[1F4h 0500 1] Enumeration ID : 00
[1F5h 0501 1] PCI Bus Number : 00
[1F6h 0502 2] PCI Path : [03, 03]
[1F8h 0504 2] Subtable Type : 0002 <Root Port ATS Capability>
[1FAh 0506 2] Length : 0020
[1FCh 0508 1] Flags : 00
[1FDh 0509 1] Reserved : 00
[1FEh 0510 2] PCI Segment Number : 0000
[200h 0512 1] Device Scope Entry Type : 02
[201h 0513 1] Entry Length : 08
[202h 0514 2] Reserved : 0000
[204h 0516 1] Enumeration ID : 00
[205h 0517 1] PCI Bus Number : 40
[206h 0518 2] PCI Path : [02, 00]
[208h 0520 1] Device Scope Entry Type : 02
[209h 0521 1] Entry Length : 08
[20Ah 0522 2] Reserved : 0000
[20Ch 0524 1] Enumeration ID : 00
[20Dh 0525 1] PCI Bus Number : 40
[20Eh 0526 2] PCI Path : [02, 02]
[210h 0528 1] Device Scope Entry Type : 02
[211h 0529 1] Entry Length : 08
[212h 0530 2] Reserved : 0000
[214h 0532 1] Enumeration ID : 00
[215h 0533 1] PCI Bus Number : 40
[216h 0534 2] PCI Path : [03, 00]
[218h 0536 2] Subtable Type : 0002 <Root Port ATS Capability>
[21Ah 0538 2] Length : 0020
[21Ch 0540 1] Flags : 00
[21Dh 0541 1] Reserved : 00
[21Eh 0542 2] PCI Segment Number : 0000
[220h 0544 1] Device Scope Entry Type : 02
[221h 0545 1] Entry Length : 08
[222h 0546 2] Reserved : 0000
[224h 0548 1] Enumeration ID : 00
[225h 0549 1] PCI Bus Number : 80
[226h 0550 2] PCI Path : [02, 00]
[228h 0552 1] Device Scope Entry Type : 02
[229h 0553 1] Entry Length : 08
[22Ah 0554 2] Reserved : 0000
[22Ch 0556 1] Enumeration ID : 00
[22Dh 0557 1] PCI Bus Number : 80
[22Eh 0558 2] PCI Path : [02, 02]
[230h 0560 1] Device Scope Entry Type : 02
[231h 0561 1] Entry Length : 08
[232h 0562 2] Reserved : 0000
[234h 0564 1] Enumeration ID : 00
[235h 0565 1] PCI Bus Number : 80
[236h 0566 2] PCI Path : [03, 00]
[238h 0568 2] Subtable Type : 0002 <Root Port ATS Capability>
[23Ah 0570 2] Length : 0020
[23Ch 0572 1] Flags : 00
[23Dh 0573 1] Reserved : 00
[23Eh 0574 2] PCI Segment Number : 0000
[240h 0576 1] Device Scope Entry Type : 02
[241h 0577 1] Entry Length : 08
[242h 0578 2] Reserved : 0000
[244h 0580 1] Enumeration ID : 00
[245h 0581 1] PCI Bus Number : C0
[246h 0582 2] PCI Path : [02, 00]
[248h 0584 1] Device Scope Entry Type : 02
[249h 0585 1] Entry Length : 08
[24Ah 0586 2] Reserved : 0000
[24Ch 0588 1] Enumeration ID : 00
[24Dh 0589 1] PCI Bus Number : C0
[24Eh 0590 2] PCI Path : [02, 02]
[250h 0592 1] Device Scope Entry Type : 02
[251h 0593 1] Entry Length : 08
[252h 0594 2] Reserved : 0000
[254h 0596 1] Enumeration ID : 00
[255h 0597 1] PCI Bus Number : C0
[256h 0598 2] PCI Path : [03, 00]
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:31 +00:00
if ( atsru - > include_all )
2014-02-19 06:07:32 +00:00
goto out ;
iommu/vt-d: Fix error in detect ATS capability
Current Intel IOMMU driver only matches a PCIe root port with the first
DRHD unit with the samge segment number. It will report false result
if there are multiple DRHD units with the same segment number, thus fail
to detect ATS capability for some PCIe devices.
This patch refines function dmar_find_matched_atsr_unit() to search all
DRHD units with the same segment number.
An example DMAR table entries as below:
[1D0h 0464 2] Subtable Type : 0002 <Root Port ATS Capability>
[1D2h 0466 2] Length : 0028
[1D4h 0468 1] Flags : 00
[1D5h 0469 1] Reserved : 00
[1D6h 0470 2] PCI Segment Number : 0000
[1D8h 0472 1] Device Scope Entry Type : 02
[1D9h 0473 1] Entry Length : 08
[1DAh 0474 2] Reserved : 0000
[1DCh 0476 1] Enumeration ID : 00
[1DDh 0477 1] PCI Bus Number : 00
[1DEh 0478 2] PCI Path : [02, 00]
[1E0h 0480 1] Device Scope Entry Type : 02
[1E1h 0481 1] Entry Length : 08
[1E2h 0482 2] Reserved : 0000
[1E4h 0484 1] Enumeration ID : 00
[1E5h 0485 1] PCI Bus Number : 00
[1E6h 0486 2] PCI Path : [03, 00]
[1E8h 0488 1] Device Scope Entry Type : 02
[1E9h 0489 1] Entry Length : 08
[1EAh 0490 2] Reserved : 0000
[1ECh 0492 1] Enumeration ID : 00
[1EDh 0493 1] PCI Bus Number : 00
[1EEh 0494 2] PCI Path : [03, 02]
[1F0h 0496 1] Device Scope Entry Type : 02
[1F1h 0497 1] Entry Length : 08
[1F2h 0498 2] Reserved : 0000
[1F4h 0500 1] Enumeration ID : 00
[1F5h 0501 1] PCI Bus Number : 00
[1F6h 0502 2] PCI Path : [03, 03]
[1F8h 0504 2] Subtable Type : 0002 <Root Port ATS Capability>
[1FAh 0506 2] Length : 0020
[1FCh 0508 1] Flags : 00
[1FDh 0509 1] Reserved : 00
[1FEh 0510 2] PCI Segment Number : 0000
[200h 0512 1] Device Scope Entry Type : 02
[201h 0513 1] Entry Length : 08
[202h 0514 2] Reserved : 0000
[204h 0516 1] Enumeration ID : 00
[205h 0517 1] PCI Bus Number : 40
[206h 0518 2] PCI Path : [02, 00]
[208h 0520 1] Device Scope Entry Type : 02
[209h 0521 1] Entry Length : 08
[20Ah 0522 2] Reserved : 0000
[20Ch 0524 1] Enumeration ID : 00
[20Dh 0525 1] PCI Bus Number : 40
[20Eh 0526 2] PCI Path : [02, 02]
[210h 0528 1] Device Scope Entry Type : 02
[211h 0529 1] Entry Length : 08
[212h 0530 2] Reserved : 0000
[214h 0532 1] Enumeration ID : 00
[215h 0533 1] PCI Bus Number : 40
[216h 0534 2] PCI Path : [03, 00]
[218h 0536 2] Subtable Type : 0002 <Root Port ATS Capability>
[21Ah 0538 2] Length : 0020
[21Ch 0540 1] Flags : 00
[21Dh 0541 1] Reserved : 00
[21Eh 0542 2] PCI Segment Number : 0000
[220h 0544 1] Device Scope Entry Type : 02
[221h 0545 1] Entry Length : 08
[222h 0546 2] Reserved : 0000
[224h 0548 1] Enumeration ID : 00
[225h 0549 1] PCI Bus Number : 80
[226h 0550 2] PCI Path : [02, 00]
[228h 0552 1] Device Scope Entry Type : 02
[229h 0553 1] Entry Length : 08
[22Ah 0554 2] Reserved : 0000
[22Ch 0556 1] Enumeration ID : 00
[22Dh 0557 1] PCI Bus Number : 80
[22Eh 0558 2] PCI Path : [02, 02]
[230h 0560 1] Device Scope Entry Type : 02
[231h 0561 1] Entry Length : 08
[232h 0562 2] Reserved : 0000
[234h 0564 1] Enumeration ID : 00
[235h 0565 1] PCI Bus Number : 80
[236h 0566 2] PCI Path : [03, 00]
[238h 0568 2] Subtable Type : 0002 <Root Port ATS Capability>
[23Ah 0570 2] Length : 0020
[23Ch 0572 1] Flags : 00
[23Dh 0573 1] Reserved : 00
[23Eh 0574 2] PCI Segment Number : 0000
[240h 0576 1] Device Scope Entry Type : 02
[241h 0577 1] Entry Length : 08
[242h 0578 2] Reserved : 0000
[244h 0580 1] Enumeration ID : 00
[245h 0581 1] PCI Bus Number : C0
[246h 0582 2] PCI Path : [02, 00]
[248h 0584 1] Device Scope Entry Type : 02
[249h 0585 1] Entry Length : 08
[24Ah 0586 2] Reserved : 0000
[24Ch 0588 1] Enumeration ID : 00
[24Dh 0589 1] PCI Bus Number : C0
[24Eh 0590 2] PCI Path : [02, 02]
[250h 0592 1] Device Scope Entry Type : 02
[251h 0593 1] Entry Length : 08
[252h 0594 2] Reserved : 0000
[254h 0596 1] Enumeration ID : 00
[255h 0597 1] PCI Bus Number : C0
[256h 0598 2] PCI Path : [03, 00]
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:31 +00:00
}
2014-02-19 06:07:32 +00:00
ret = 0 ;
out :
2014-02-19 06:07:34 +00:00
rcu_read_unlock ( ) ;
2011-08-24 00:05:20 +00:00
2014-02-19 06:07:32 +00:00
return ret ;
2011-08-24 00:05:20 +00:00
}
2014-02-19 06:07:35 +00:00
int dmar_iommu_notify_scope_dev ( struct dmar_pci_notify_info * info )
{
2019-02-08 22:06:08 +00:00
int ret ;
2014-02-19 06:07:35 +00:00
struct dmar_rmrr_unit * rmrru ;
struct dmar_atsr_unit * atsru ;
2021-02-04 01:44:00 +00:00
struct dmar_satc_unit * satcu ;
2014-02-19 06:07:35 +00:00
struct acpi_dmar_atsr * atsr ;
struct acpi_dmar_reserved_memory * rmrr ;
2021-02-04 01:44:00 +00:00
struct acpi_dmar_satc * satc ;
2014-02-19 06:07:35 +00:00
2017-05-16 18:42:41 +00:00
if ( ! intel_iommu_enabled & & system_state > = SYSTEM_RUNNING )
2014-02-19 06:07:35 +00:00
return 0 ;
list_for_each_entry ( rmrru , & dmar_rmrr_units , list ) {
rmrr = container_of ( rmrru - > hdr ,
struct acpi_dmar_reserved_memory , header ) ;
if ( info - > event = = BUS_NOTIFY_ADD_DEVICE ) {
ret = dmar_insert_dev_scope ( info , ( void * ) ( rmrr + 1 ) ,
( ( void * ) rmrr ) + rmrr - > header . length ,
rmrr - > segment , rmrru - > devices ,
rmrru - > devices_cnt ) ;
2019-02-08 22:06:08 +00:00
if ( ret < 0 )
2014-02-19 06:07:35 +00:00
return ret ;
2016-02-29 22:49:47 +00:00
} else if ( info - > event = = BUS_NOTIFY_REMOVED_DEVICE ) {
2014-06-20 07:08:06 +00:00
dmar_remove_dev_scope ( info , rmrr - > segment ,
rmrru - > devices , rmrru - > devices_cnt ) ;
2014-02-19 06:07:35 +00:00
}
}
list_for_each_entry ( atsru , & dmar_atsr_units , list ) {
if ( atsru - > include_all )
continue ;
atsr = container_of ( atsru - > hdr , struct acpi_dmar_atsr , header ) ;
if ( info - > event = = BUS_NOTIFY_ADD_DEVICE ) {
ret = dmar_insert_dev_scope ( info , ( void * ) ( atsr + 1 ) ,
( void * ) atsr + atsr - > header . length ,
atsr - > segment , atsru - > devices ,
atsru - > devices_cnt ) ;
if ( ret > 0 )
break ;
2019-02-08 22:06:08 +00:00
else if ( ret < 0 )
2014-02-19 06:07:35 +00:00
return ret ;
2016-02-29 22:49:47 +00:00
} else if ( info - > event = = BUS_NOTIFY_REMOVED_DEVICE ) {
2014-02-19 06:07:35 +00:00
if ( dmar_remove_dev_scope ( info , atsr - > segment ,
atsru - > devices , atsru - > devices_cnt ) )
break ;
}
}
2021-02-04 01:44:00 +00:00
list_for_each_entry ( satcu , & dmar_satc_units , list ) {
satc = container_of ( satcu - > hdr , struct acpi_dmar_satc , header ) ;
if ( info - > event = = BUS_NOTIFY_ADD_DEVICE ) {
ret = dmar_insert_dev_scope ( info , ( void * ) ( satc + 1 ) ,
( void * ) satc + satc - > header . length ,
satc - > segment , satcu - > devices ,
satcu - > devices_cnt ) ;
if ( ret > 0 )
break ;
else if ( ret < 0 )
return ret ;
} else if ( info - > event = = BUS_NOTIFY_REMOVED_DEVICE ) {
if ( dmar_remove_dev_scope ( info , satc - > segment ,
satcu - > devices , satcu - > devices_cnt ) )
break ;
}
}
2014-02-19 06:07:35 +00:00
return 0 ;
}
2014-02-19 06:07:37 +00:00
static int intel_iommu_memory_notifier ( struct notifier_block * nb ,
unsigned long val , void * v )
{
struct memory_notify * mhp = v ;
2023-08-09 12:48:05 +00:00
unsigned long start_vpfn = mm_to_dma_pfn_start ( mhp - > start_pfn ) ;
unsigned long last_vpfn = mm_to_dma_pfn_end ( mhp - > start_pfn +
2020-05-16 06:21:01 +00:00
mhp - > nr_pages - 1 ) ;
2014-02-19 06:07:37 +00:00
switch ( val ) {
case MEM_GOING_ONLINE :
2020-05-16 06:21:01 +00:00
if ( iommu_domain_identity_map ( si_domain ,
start_vpfn , last_vpfn ) ) {
pr_warn ( " Failed to build identity map for [%lx-%lx] \n " ,
start_vpfn , last_vpfn ) ;
2014-02-19 06:07:37 +00:00
return NOTIFY_BAD ;
}
break ;
case MEM_OFFLINE :
case MEM_CANCEL_ONLINE :
2020-05-16 06:21:01 +00:00
{
2014-02-19 06:07:37 +00:00
struct dmar_drhd_unit * drhd ;
struct intel_iommu * iommu ;
2021-12-17 15:31:00 +00:00
LIST_HEAD ( freelist ) ;
2014-02-19 06:07:37 +00:00
2021-12-17 15:31:00 +00:00
domain_unmap ( si_domain , start_vpfn , last_vpfn , & freelist ) ;
2014-03-05 17:09:32 +00:00
2014-02-19 06:07:37 +00:00
rcu_read_lock ( ) ;
for_each_active_iommu ( iommu , drhd )
2015-07-21 13:20:32 +00:00
iommu_flush_iotlb_psi ( iommu , si_domain ,
2020-05-16 06:21:01 +00:00
start_vpfn , mhp - > nr_pages ,
2021-12-17 15:31:00 +00:00
list_empty ( & freelist ) , 0 ) ;
2014-02-19 06:07:37 +00:00
rcu_read_unlock ( ) ;
2021-12-17 15:31:00 +00:00
put_pages_list ( & freelist ) ;
2014-02-19 06:07:37 +00:00
}
break ;
}
return NOTIFY_OK ;
}
static struct notifier_block intel_iommu_memory_nb = {
. notifier_call = intel_iommu_memory_notifier ,
. priority = 0
} ;
2017-03-28 15:04:52 +00:00
static void intel_disable_iommus ( void )
{
struct intel_iommu * iommu = NULL ;
struct dmar_drhd_unit * drhd ;
for_each_iommu ( iommu , drhd )
iommu_disable_translation ( iommu ) ;
}
2019-11-10 17:27:44 +00:00
void intel_iommu_shutdown ( void )
{
struct dmar_drhd_unit * drhd ;
struct intel_iommu * iommu = NULL ;
if ( no_iommu | | dmar_disabled )
return ;
down_write ( & dmar_global_lock ) ;
/* Disable PMRs explicitly here. */
for_each_iommu ( iommu , drhd )
iommu_disable_protect_mem_regions ( iommu ) ;
/* Make sure the IOMMUs are switched off */
intel_disable_iommus ( ) ;
up_write ( & dmar_global_lock ) ;
}
2023-12-18 07:34:45 +00:00
static struct intel_iommu * dev_to_intel_iommu ( struct device * dev )
2017-02-28 12:57:18 +00:00
{
2017-08-14 15:19:26 +00:00
struct iommu_device * iommu_dev = dev_to_iommu_device ( dev ) ;
return container_of ( iommu_dev , struct intel_iommu , iommu ) ;
2017-02-28 12:57:18 +00:00
}
2021-06-10 02:01:10 +00:00
static ssize_t version_show ( struct device * dev ,
struct device_attribute * attr , char * buf )
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
{
2017-02-28 12:57:18 +00:00
struct intel_iommu * iommu = dev_to_intel_iommu ( dev ) ;
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
u32 ver = readl ( iommu - > reg + DMAR_VER_REG ) ;
2023-03-22 12:34:21 +00:00
return sysfs_emit ( buf , " %d:%d \n " ,
DMAR_VER_MAJOR ( ver ) , DMAR_VER_MINOR ( ver ) ) ;
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
}
2021-06-10 02:01:10 +00:00
static DEVICE_ATTR_RO ( version ) ;
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
2021-06-10 02:01:10 +00:00
static ssize_t address_show ( struct device * dev ,
struct device_attribute * attr , char * buf )
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
{
2017-02-28 12:57:18 +00:00
struct intel_iommu * iommu = dev_to_intel_iommu ( dev ) ;
2023-03-22 12:34:21 +00:00
return sysfs_emit ( buf , " %llx \n " , iommu - > reg_phys ) ;
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
}
2021-06-10 02:01:10 +00:00
static DEVICE_ATTR_RO ( address ) ;
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
2021-06-10 02:01:10 +00:00
static ssize_t cap_show ( struct device * dev ,
struct device_attribute * attr , char * buf )
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
{
2017-02-28 12:57:18 +00:00
struct intel_iommu * iommu = dev_to_intel_iommu ( dev ) ;
2023-03-22 12:34:21 +00:00
return sysfs_emit ( buf , " %llx \n " , iommu - > cap ) ;
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
}
2021-06-10 02:01:10 +00:00
static DEVICE_ATTR_RO ( cap ) ;
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
2021-06-10 02:01:10 +00:00
static ssize_t ecap_show ( struct device * dev ,
struct device_attribute * attr , char * buf )
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
{
2017-02-28 12:57:18 +00:00
struct intel_iommu * iommu = dev_to_intel_iommu ( dev ) ;
2023-03-22 12:34:21 +00:00
return sysfs_emit ( buf , " %llx \n " , iommu - > ecap ) ;
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
}
2021-06-10 02:01:10 +00:00
static DEVICE_ATTR_RO ( ecap ) ;
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
2021-06-10 02:01:10 +00:00
static ssize_t domains_supported_show ( struct device * dev ,
struct device_attribute * attr , char * buf )
2015-07-14 21:24:53 +00:00
{
2017-02-28 12:57:18 +00:00
struct intel_iommu * iommu = dev_to_intel_iommu ( dev ) ;
2023-03-22 12:34:21 +00:00
return sysfs_emit ( buf , " %ld \n " , cap_ndoms ( iommu - > cap ) ) ;
2015-07-14 21:24:53 +00:00
}
2021-06-10 02:01:10 +00:00
static DEVICE_ATTR_RO ( domains_supported ) ;
2015-07-14 21:24:53 +00:00
2021-06-10 02:01:10 +00:00
static ssize_t domains_used_show ( struct device * dev ,
struct device_attribute * attr , char * buf )
2015-07-14 21:24:53 +00:00
{
2017-02-28 12:57:18 +00:00
struct intel_iommu * iommu = dev_to_intel_iommu ( dev ) ;
2023-03-22 12:34:21 +00:00
return sysfs_emit ( buf , " %d \n " ,
bitmap_weight ( iommu - > domain_ids ,
cap_ndoms ( iommu - > cap ) ) ) ;
2015-07-14 21:24:53 +00:00
}
2021-06-10 02:01:10 +00:00
static DEVICE_ATTR_RO ( domains_used ) ;
2015-07-14 21:24:53 +00:00
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
static struct attribute * intel_iommu_attrs [ ] = {
& dev_attr_version . attr ,
& dev_attr_address . attr ,
& dev_attr_cap . attr ,
& dev_attr_ecap . attr ,
2015-07-14 21:24:53 +00:00
& dev_attr_domains_supported . attr ,
& dev_attr_domains_used . attr ,
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
NULL ,
} ;
static struct attribute_group intel_iommu_group = {
. name = " intel-iommu " ,
. attrs = intel_iommu_attrs ,
} ;
const struct attribute_group * intel_iommu_groups [ ] = {
& intel_iommu_group ,
NULL ,
} ;
2023-12-18 07:34:45 +00:00
static bool has_external_pci ( void )
2018-10-23 07:45:01 +00:00
{
struct pci_dev * pdev = NULL ;
2019-09-06 06:14:50 +00:00
for_each_pci_dev ( pdev )
2022-12-01 04:01:26 +00:00
if ( pdev - > external_facing ) {
pci_dev_put ( pdev ) ;
2019-09-06 06:14:50 +00:00
return true ;
2022-12-01 04:01:26 +00:00
}
2018-10-23 07:45:01 +00:00
2019-09-06 06:14:50 +00:00
return false ;
}
2018-10-23 07:45:01 +00:00
2019-09-06 06:14:50 +00:00
static int __init platform_optin_force_iommu ( void )
{
2020-07-07 22:46:03 +00:00
if ( ! dmar_platform_optin ( ) | | no_platform_optin | | ! has_external_pci ( ) )
2018-10-23 07:45:01 +00:00
return 0 ;
if ( no_iommu | | dmar_disabled )
pr_info ( " Intel-IOMMU force enabled due to platform opt in \n " ) ;
/*
* If Intel - IOMMU is disabled by default , we will apply identity
* map for all devices except those marked as being untrusted .
*/
if ( dmar_disabled )
2020-01-15 03:03:59 +00:00
iommu_set_default_passthrough ( false ) ;
2018-10-23 07:45:01 +00:00
dmar_disabled = 0 ;
no_iommu = 0 ;
return 1 ;
}
2019-05-25 05:41:31 +00:00
static int __init probe_acpi_namespace_devices ( void )
{
struct dmar_drhd_unit * drhd ;
2019-06-03 14:05:19 +00:00
/* To avoid a -Wunused-but-set-variable warning. */
struct intel_iommu * iommu __maybe_unused ;
2019-05-25 05:41:31 +00:00
struct device * dev ;
int i , ret = 0 ;
for_each_active_iommu ( iommu , drhd ) {
for_each_active_dev_scope ( drhd - > devices ,
drhd - > devices_cnt , i , dev ) {
struct acpi_device_physical_node * pn ;
struct acpi_device * adev ;
if ( dev - > bus ! = & acpi_bus_type )
continue ;
adev = to_acpi_device ( dev ) ;
mutex_lock ( & adev - > physical_node_lock ) ;
list_for_each_entry ( pn ,
& adev - > physical_node_list , node ) {
ret = iommu_probe_device ( pn - > dev ) ;
if ( ret )
break ;
}
mutex_unlock ( & adev - > physical_node_lock ) ;
if ( ret )
return ret ;
}
}
return 0 ;
}
2022-07-12 00:08:49 +00:00
static __init int tboot_force_iommu ( void )
{
if ( ! tboot_enabled ( ) )
return 0 ;
if ( no_iommu | | dmar_disabled )
pr_warn ( " Forcing Intel-IOMMU to enabled \n " ) ;
dmar_disabled = 0 ;
no_iommu = 0 ;
return 1 ;
}
2007-10-21 23:41:49 +00:00
int __init intel_iommu_init ( void )
{
2014-01-06 06:18:27 +00:00
int ret = - ENODEV ;
2013-04-23 08:35:03 +00:00
struct dmar_drhd_unit * drhd ;
2014-01-06 06:18:18 +00:00
struct intel_iommu * iommu ;
2007-10-21 23:41:49 +00:00
2018-10-23 07:45:01 +00:00
/*
* Intel IOMMU is required for a TXT / tboot launch or platform
* opt in , so enforce that .
*/
2020-11-10 07:19:08 +00:00
force_on = ( ! intel_iommu_tboot_noforce & & tboot_force_iommu ( ) ) | |
platform_optin_force_iommu ( ) ;
2009-07-01 02:31:10 +00:00
iommu/vt-d: Introduce a rwsem to protect global data structures
Introduce a global rwsem dmar_global_lock, which will be used to
protect DMAR related global data structures from DMAR/PCI/memory
device hotplug operations in process context.
DMA and interrupt remapping related data structures are read most,
and only change when memory/PCI/DMAR hotplug event happens.
So a global rwsem solution is adopted for balance between simplicity
and performance.
For interrupt remapping driver, function intel_irq_remapping_supported(),
dmar_table_init(), intel_enable_irq_remapping(), disable_irq_remapping(),
reenable_irq_remapping() and enable_drhd_fault_handling() etc
are called during booting, suspending and resuming with interrupt
disabled, so no need to take the global lock.
For interrupt remapping entry allocation, the locking model is:
down_read(&dmar_global_lock);
/* Find corresponding iommu */
iommu = map_hpet_to_ir(id);
if (iommu)
/*
* Allocate remapping entry and mark entry busy,
* the IOMMU won't be hot-removed until the
* allocated entry has been released.
*/
index = alloc_irte(iommu, irq, 1);
up_read(&dmar_global_lock);
For DMA remmaping driver, we only uses the dmar_global_lock rwsem to
protect functions which are only called in process context. For any
function which may be called in interrupt context, we will use RCU
to protect them in following patches.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:33 +00:00
down_write ( & dmar_global_lock ) ;
2009-07-01 02:31:10 +00:00
if ( dmar_table_init ( ) ) {
if ( force_on )
panic ( " tboot: Failed to initialize DMAR table \n " ) ;
2014-01-06 06:18:27 +00:00
goto out_free_dmar ;
2009-07-01 02:31:10 +00:00
}
2007-10-21 23:41:49 +00:00
2011-08-24 00:05:19 +00:00
if ( dmar_dev_scope_init ( ) < 0 ) {
2009-07-01 02:31:10 +00:00
if ( force_on )
panic ( " tboot: Failed to initialize DMAR device scope \n " ) ;
2014-01-06 06:18:27 +00:00
goto out_free_dmar ;
2009-07-01 02:31:10 +00:00
}
2008-07-10 18:16:37 +00:00
2017-10-06 13:00:53 +00:00
up_write ( & dmar_global_lock ) ;
/*
* The bus notifier takes the dmar_global_lock , so lockdep will
* complain later when we register it under the lock .
*/
dmar_register_bus_notifier ( ) ;
down_write ( & dmar_global_lock ) ;
2020-03-14 03:39:59 +00:00
if ( ! no_iommu )
intel_iommu_debugfs_init ( ) ;
2017-03-28 15:04:52 +00:00
if ( no_iommu | | dmar_disabled ) {
2017-04-26 16:18:35 +00:00
/*
* We exit the function here to ensure IOMMU ' s remapping and
* mempool aren ' t setup , which means that the IOMMU ' s PMRs
* won ' t be disabled via the call to init_dmars ( ) . So disable
* it explicitly here . The PMRs were setup by tboot prior to
* calling SENTER , but the kernel is expected to reset / tear
* down the PMRs .
*/
if ( intel_iommu_tboot_noforce ) {
for_each_iommu ( iommu , drhd )
iommu_disable_protect_mem_regions ( iommu ) ;
}
2017-03-28 15:04:52 +00:00
/*
* Make sure the IOMMUs are switched off , even when we
* boot into a kexec kernel and the previous kernel left
* them enabled
*/
intel_disable_iommus ( ) ;
2014-01-06 06:18:27 +00:00
goto out_free_dmar ;
2017-03-28 15:04:52 +00:00
}
2008-07-10 18:16:43 +00:00
2011-08-24 00:05:20 +00:00
if ( list_empty ( & dmar_rmrr_units ) )
2015-06-12 07:57:06 +00:00
pr_info ( " No RMRR found \n " ) ;
2011-08-24 00:05:20 +00:00
if ( list_empty ( & dmar_atsr_units ) )
2015-06-12 07:57:06 +00:00
pr_info ( " No ATSR found \n " ) ;
2011-08-24 00:05:20 +00:00
2021-02-04 01:44:00 +00:00
if ( list_empty ( & dmar_satc_units ) )
pr_info ( " No SATC found \n " ) ;
2007-10-21 23:41:49 +00:00
init_no_remapping_devices ( ) ;
2011-05-03 07:08:37 +00:00
ret = init_dmars ( ) ;
2007-10-21 23:41:49 +00:00
if ( ret ) {
2009-07-01 02:31:10 +00:00
if ( force_on )
panic ( " tboot: Failed to initialize DMARs \n " ) ;
2015-06-12 07:57:06 +00:00
pr_err ( " Initialization failed \n " ) ;
2020-11-24 08:20:56 +00:00
goto out_free_dmar ;
2007-10-21 23:41:49 +00:00
}
iommu/vt-d: Introduce a rwsem to protect global data structures
Introduce a global rwsem dmar_global_lock, which will be used to
protect DMAR related global data structures from DMAR/PCI/memory
device hotplug operations in process context.
DMA and interrupt remapping related data structures are read most,
and only change when memory/PCI/DMAR hotplug event happens.
So a global rwsem solution is adopted for balance between simplicity
and performance.
For interrupt remapping driver, function intel_irq_remapping_supported(),
dmar_table_init(), intel_enable_irq_remapping(), disable_irq_remapping(),
reenable_irq_remapping() and enable_drhd_fault_handling() etc
are called during booting, suspending and resuming with interrupt
disabled, so no need to take the global lock.
For interrupt remapping entry allocation, the locking model is:
down_read(&dmar_global_lock);
/* Find corresponding iommu */
iommu = map_hpet_to_ir(id);
if (iommu)
/*
* Allocate remapping entry and mark entry busy,
* the IOMMU won't be hot-removed until the
* allocated entry has been released.
*/
index = alloc_irte(iommu, irq, 1);
up_read(&dmar_global_lock);
For DMA remmaping driver, we only uses the dmar_global_lock rwsem to
protect functions which are only called in process context. For any
function which may be called in interrupt context, we will use RCU
to protect them in following patches.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:33 +00:00
up_write ( & dmar_global_lock ) ;
2007-10-21 23:41:49 +00:00
2011-03-23 21:16:14 +00:00
init_iommu_pm_ops ( ) ;
2008-12-03 14:14:02 +00:00
2020-03-05 20:00:46 +00:00
down_read ( & dmar_global_lock ) ;
2017-02-01 15:56:46 +00:00
for_each_active_iommu ( iommu , drhd ) {
2021-04-01 15:52:54 +00:00
/*
* The flush queue implementation does not perform
* page - selective invalidations that are required for efficient
* TLB flushes in virtual environments . The benefit of batching
* is likely to be much lower than the overhead of synchronizing
* the virtual and physical IOMMU page - tables .
*/
2023-02-16 13:08:16 +00:00
if ( cap_caching_mode ( iommu - > cap ) & &
! first_level_by_default ( IOMMU_DOMAIN_DMA ) ) {
2021-07-12 11:12:18 +00:00
pr_info_once ( " IOMMU batching disallowed due to virtualization \n " ) ;
2021-07-12 11:12:20 +00:00
iommu_set_dma_strict ( ) ;
2021-04-01 15:52:54 +00:00
}
2017-02-01 15:56:46 +00:00
iommu_device_sysfs_add ( & iommu - > iommu , NULL ,
intel_iommu_groups ,
" %s " , iommu - > name ) ;
2021-04-01 13:56:26 +00:00
iommu_device_register ( & iommu - > iommu , & intel_iommu_ops , NULL ) ;
2023-01-31 07:37:40 +00:00
iommu_pmu_register ( iommu ) ;
2017-02-01 15:56:46 +00:00
}
2020-03-05 20:00:46 +00:00
up_read ( & dmar_global_lock ) ;
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
2014-02-19 06:07:37 +00:00
if ( si_domain & & ! hw_pass_through )
register_memory_notifier ( & intel_iommu_memory_nb ) ;
2019-05-25 05:41:25 +00:00
2019-06-12 00:28:49 +00:00
down_read ( & dmar_global_lock ) ;
2019-05-25 05:41:31 +00:00
if ( probe_acpi_namespace_devices ( ) )
pr_warn ( " ACPI name space devices didn't probe correctly \n " ) ;
2019-05-25 05:41:25 +00:00
/* Finally, we enable the DMA remapping hardware. */
for_each_iommu ( iommu , drhd ) {
2019-06-12 00:28:47 +00:00
if ( ! drhd - > ignored & & ! translation_pre_enabled ( iommu ) )
2019-05-25 05:41:25 +00:00
iommu_enable_translation ( iommu ) ;
iommu_disable_protect_mem_regions ( iommu ) ;
}
2020-03-05 20:00:46 +00:00
up_read ( & dmar_global_lock ) ;
2019-05-25 05:41:25 +00:00
pr_info ( " Intel(R) Virtualization Technology for Directed I/O \n " ) ;
2011-11-23 18:42:14 +00:00
intel_iommu_enabled = 1 ;
2007-10-21 23:41:49 +00:00
return 0 ;
2014-01-06 06:18:27 +00:00
out_free_dmar :
intel_iommu_free_dmars ( ) ;
iommu/vt-d: Introduce a rwsem to protect global data structures
Introduce a global rwsem dmar_global_lock, which will be used to
protect DMAR related global data structures from DMAR/PCI/memory
device hotplug operations in process context.
DMA and interrupt remapping related data structures are read most,
and only change when memory/PCI/DMAR hotplug event happens.
So a global rwsem solution is adopted for balance between simplicity
and performance.
For interrupt remapping driver, function intel_irq_remapping_supported(),
dmar_table_init(), intel_enable_irq_remapping(), disable_irq_remapping(),
reenable_irq_remapping() and enable_drhd_fault_handling() etc
are called during booting, suspending and resuming with interrupt
disabled, so no need to take the global lock.
For interrupt remapping entry allocation, the locking model is:
down_read(&dmar_global_lock);
/* Find corresponding iommu */
iommu = map_hpet_to_ir(id);
if (iommu)
/*
* Allocate remapping entry and mark entry busy,
* the IOMMU won't be hot-removed until the
* allocated entry has been released.
*/
index = alloc_irte(iommu, irq, 1);
up_read(&dmar_global_lock);
For DMA remmaping driver, we only uses the dmar_global_lock rwsem to
protect functions which are only called in process context. For any
function which may be called in interrupt context, we will use RCU
to protect them in following patches.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19 06:07:33 +00:00
up_write ( & dmar_global_lock ) ;
2014-01-06 06:18:27 +00:00
return ret ;
2007-10-21 23:41:49 +00:00
}
2007-10-21 23:41:55 +00:00
2019-08-26 08:50:56 +00:00
static int domain_context_clear_one_cb ( struct pci_dev * pdev , u16 alias , void * opaque )
{
2021-07-12 07:13:15 +00:00
struct device_domain_info * info = opaque ;
2019-08-26 08:50:56 +00:00
2021-07-12 07:13:15 +00:00
domain_context_clear_one ( info , PCI_BUS_NUM ( alias ) , alias & 0xff ) ;
2019-08-26 08:50:56 +00:00
return 0 ;
}
/*
* NB - intel - iommu lacks any sort of reference counting for the users of
* dependent devices . If multiple endpoints have intersecting dependent
* devices , unbinding the driver from any one of them will possibly leave
* the others unable to operate .
*/
2021-07-12 07:13:15 +00:00
static void domain_context_clear ( struct device_domain_info * info )
2019-08-26 08:50:56 +00:00
{
2023-11-22 03:26:05 +00:00
if ( ! dev_is_pci ( info - > dev ) )
domain_context_clear_one ( info , info - > bus , info - > devfn ) ;
2019-08-26 08:50:56 +00:00
2021-07-12 07:13:15 +00:00
pci_for_each_dma_alias ( to_pci_dev ( info - > dev ) ,
& domain_context_clear_one_cb , info ) ;
2019-08-26 08:50:56 +00:00
}
2022-11-22 00:29:44 +00:00
/*
* Clear the page table pointer in context or pasid table entries so that
* all DMA requests without PASID from the device are blocked . If the page
* table has been set , clean up the data structures .
*/
2023-10-26 04:42:13 +00:00
void device_block_translation ( struct device * dev )
2022-11-22 00:29:44 +00:00
{
struct device_domain_info * info = dev_iommu_priv_get ( dev ) ;
struct intel_iommu * iommu = info - > iommu ;
unsigned long flags ;
2022-11-22 00:29:46 +00:00
iommu_disable_pci_caps ( info ) ;
2022-11-22 00:29:44 +00:00
if ( ! dev_is_real_dma_subdevice ( dev ) ) {
if ( sm_supported ( iommu ) )
intel_pasid_tear_down_entry ( iommu , dev ,
2023-08-09 12:47:54 +00:00
IOMMU_NO_PASID , false ) ;
2022-11-22 00:29:44 +00:00
else
domain_context_clear ( info ) ;
}
if ( ! info - > domain )
return ;
spin_lock_irqsave ( & info - > domain - > lock , flags ) ;
list_del ( & info - > link ) ;
spin_unlock_irqrestore ( & info - > domain - > lock , flags ) ;
domain_detach_iommu ( info - > domain , iommu ) ;
info - > domain = NULL ;
}
2019-07-22 14:21:05 +00:00
static int md_domain_init ( struct dmar_domain * domain , int guest_width )
{
int adjust_width ;
/* calculate AGAW */
domain - > gaw = guest_width ;
adjust_width = guestwidth_to_adjustwidth ( guest_width ) ;
domain - > agaw = width_to_agaw ( adjust_width ) ;
iommu/vt-d: Use bitfields for DMAR capabilities
IOTLB device presence, iommu coherency and snooping are boolean
capabilities. Use them as bits and keep them adjacent.
Structure layout before the reorg.
$ pahole -C dmar_domain drivers/iommu/intel/dmar.o
struct dmar_domain {
int nid; /* 0 4 */
unsigned int iommu_refcnt[128]; /* 4 512 */
/* --- cacheline 8 boundary (512 bytes) was 4 bytes ago --- */
u16 iommu_did[128]; /* 516 256 */
/* --- cacheline 12 boundary (768 bytes) was 4 bytes ago --- */
bool has_iotlb_device; /* 772 1 */
/* XXX 3 bytes hole, try to pack */
struct list_head devices; /* 776 16 */
struct list_head subdevices; /* 792 16 */
struct iova_domain iovad __attribute__((__aligned__(8)));
/* 808 2320 */
/* --- cacheline 48 boundary (3072 bytes) was 56 bytes ago --- */
struct dma_pte * pgd; /* 3128 8 */
/* --- cacheline 49 boundary (3136 bytes) --- */
int gaw; /* 3136 4 */
int agaw; /* 3140 4 */
int flags; /* 3144 4 */
int iommu_coherency; /* 3148 4 */
int iommu_snooping; /* 3152 4 */
int iommu_count; /* 3156 4 */
int iommu_superpage; /* 3160 4 */
/* XXX 4 bytes hole, try to pack */
u64 max_addr; /* 3168 8 */
u32 default_pasid; /* 3176 4 */
/* XXX 4 bytes hole, try to pack */
struct iommu_domain domain; /* 3184 72 */
/* size: 3256, cachelines: 51, members: 18 */
/* sum members: 3245, holes: 3, sum holes: 11 */
/* forced alignments: 1 */
/* last cacheline: 56 bytes */
} __attribute__((__aligned__(8)));
After arranging it for natural padding and to make flags as u8 bits, it
saves 8 bytes for the struct.
struct dmar_domain {
int nid; /* 0 4 */
unsigned int iommu_refcnt[128]; /* 4 512 */
/* --- cacheline 8 boundary (512 bytes) was 4 bytes ago --- */
u16 iommu_did[128]; /* 516 256 */
/* --- cacheline 12 boundary (768 bytes) was 4 bytes ago --- */
u8 has_iotlb_device:1; /* 772: 0 1 */
u8 iommu_coherency:1; /* 772: 1 1 */
u8 iommu_snooping:1; /* 772: 2 1 */
/* XXX 5 bits hole, try to pack */
/* XXX 3 bytes hole, try to pack */
struct list_head devices; /* 776 16 */
struct list_head subdevices; /* 792 16 */
struct iova_domain iovad __attribute__((__aligned__(8)));
/* 808 2320 */
/* --- cacheline 48 boundary (3072 bytes) was 56 bytes ago --- */
struct dma_pte * pgd; /* 3128 8 */
/* --- cacheline 49 boundary (3136 bytes) --- */
int gaw; /* 3136 4 */
int agaw; /* 3140 4 */
int flags; /* 3144 4 */
int iommu_count; /* 3148 4 */
int iommu_superpage; /* 3152 4 */
/* XXX 4 bytes hole, try to pack */
u64 max_addr; /* 3160 8 */
u32 default_pasid; /* 3168 4 */
/* XXX 4 bytes hole, try to pack */
struct iommu_domain domain; /* 3176 72 */
/* size: 3248, cachelines: 51, members: 18 */
/* sum members: 3236, holes: 3, sum holes: 11 */
/* sum bitfield members: 3 bits, bit holes: 1, sum bit holes: 5 bits */
/* forced alignments: 1 */
/* last cacheline: 48 bytes */
} __attribute__((__aligned__(8)));
Signed-off-by: Parav Pandit <parav@nvidia.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210530075053.264218-1-parav@nvidia.com
Link: https://lore.kernel.org/r/20210610020115.1637656-20-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-06-10 02:01:11 +00:00
domain - > iommu_coherency = false ;
2019-07-22 14:21:05 +00:00
domain - > iommu_superpage = 0 ;
domain - > max_addr = 0 ;
/* always allocate the top pgd */
2023-01-23 20:35:59 +00:00
domain - > pgd = alloc_pgtable_page ( domain - > nid , GFP_ATOMIC ) ;
2019-07-22 14:21:05 +00:00
if ( ! domain - > pgd )
return - ENOMEM ;
domain_flush_cache ( domain , domain - > pgd , PAGE_SIZE ) ;
return 0 ;
}
2022-11-22 00:29:45 +00:00
static int blocking_domain_attach_dev ( struct iommu_domain * domain ,
struct device * dev )
{
device_block_translation ( dev ) ;
return 0 ;
}
static struct iommu_domain blocking_domain = {
2023-09-27 23:47:32 +00:00
. type = IOMMU_DOMAIN_BLOCKED ,
2022-11-22 00:29:45 +00:00
. ops = & ( const struct iommu_domain_ops ) {
. attach_dev = blocking_domain_attach_dev ,
}
} ;
2015-03-26 12:43:08 +00:00
static struct iommu_domain * intel_iommu_domain_alloc ( unsigned type )
2008-09-09 15:37:29 +00:00
{
2008-12-03 13:52:32 +00:00
struct dmar_domain * dmar_domain ;
2015-03-26 12:43:08 +00:00
struct iommu_domain * domain ;
2019-05-25 05:41:27 +00:00
switch ( type ) {
2019-05-25 05:41:28 +00:00
case IOMMU_DOMAIN_DMA :
2019-05-25 05:41:27 +00:00
case IOMMU_DOMAIN_UNMANAGED :
2021-10-14 05:38:33 +00:00
dmar_domain = alloc_domain ( type ) ;
2019-05-25 05:41:27 +00:00
if ( ! dmar_domain ) {
pr_err ( " Can't allocate dmar_domain \n " ) ;
return NULL ;
}
2019-07-22 14:21:05 +00:00
if ( md_domain_init ( dmar_domain , DEFAULT_DOMAIN_ADDRESS_WIDTH ) ) {
2019-05-25 05:41:27 +00:00
pr_err ( " Domain initialization failed \n " ) ;
domain_exit ( dmar_domain ) ;
return NULL ;
}
2019-05-25 05:41:28 +00:00
2019-05-25 05:41:27 +00:00
domain = & dmar_domain - > domain ;
domain - > geometry . aperture_start = 0 ;
domain - > geometry . aperture_end =
__DOMAIN_MAX_ADDR ( dmar_domain - > gaw ) ;
domain - > geometry . force_aperture = true ;
return domain ;
case IOMMU_DOMAIN_IDENTITY :
return & si_domain - > domain ;
2022-10-31 00:59:11 +00:00
case IOMMU_DOMAIN_SVA :
return intel_svm_domain_alloc ( ) ;
2019-05-25 05:41:27 +00:00
default :
2015-03-26 12:43:08 +00:00
return NULL ;
2008-09-09 15:37:29 +00:00
}
2012-01-26 18:40:54 +00:00
2019-05-25 05:41:27 +00:00
return NULL ;
2008-09-09 15:37:29 +00:00
}
2023-09-28 07:15:28 +00:00
static struct iommu_domain *
2023-10-26 04:39:34 +00:00
intel_iommu_domain_alloc_user ( struct device * dev , u32 flags ,
struct iommu_domain * parent ,
const struct iommu_user_data * user_data )
2023-09-28 07:15:28 +00:00
{
2023-10-26 04:42:15 +00:00
struct device_domain_info * info = dev_iommu_priv_get ( dev ) ;
bool dirty_tracking = flags & IOMMU_HWPT_ALLOC_DIRTY_TRACKING ;
bool nested_parent = flags & IOMMU_HWPT_ALLOC_NEST_PARENT ;
struct intel_iommu * iommu = info - > iommu ;
2024-02-19 11:15:52 +00:00
struct dmar_domain * dmar_domain ;
2023-09-28 07:15:28 +00:00
struct iommu_domain * domain ;
2023-10-26 04:42:15 +00:00
/* Must be NESTING domain */
if ( parent ) {
if ( ! nested_supported ( iommu ) | | flags )
return ERR_PTR ( - EOPNOTSUPP ) ;
return intel_nested_domain_alloc ( parent , user_data ) ;
}
2023-09-28 07:15:28 +00:00
2023-10-24 13:51:03 +00:00
if ( flags &
( ~ ( IOMMU_HWPT_ALLOC_NEST_PARENT | IOMMU_HWPT_ALLOC_DIRTY_TRACKING ) ) )
2023-09-28 07:15:28 +00:00
return ERR_PTR ( - EOPNOTSUPP ) ;
2023-10-26 04:42:15 +00:00
if ( nested_parent & & ! nested_supported ( iommu ) )
2023-10-26 04:39:34 +00:00
return ERR_PTR ( - EOPNOTSUPP ) ;
2023-10-26 04:42:15 +00:00
if ( user_data | | ( dirty_tracking & & ! ssads_supported ( iommu ) ) )
2023-10-24 13:51:03 +00:00
return ERR_PTR ( - EOPNOTSUPP ) ;
2023-09-28 07:15:28 +00:00
/*
2023-10-26 04:42:15 +00:00
* domain_alloc_user op needs to fully initialize a domain before
* return , so uses iommu_domain_alloc ( ) here for simple .
2023-09-28 07:15:28 +00:00
*/
domain = iommu_domain_alloc ( dev - > bus ) ;
if ( ! domain )
2023-10-26 04:42:15 +00:00
return ERR_PTR ( - ENOMEM ) ;
2024-02-19 11:15:52 +00:00
dmar_domain = to_dmar_domain ( domain ) ;
if ( nested_parent ) {
dmar_domain - > nested_parent = true ;
INIT_LIST_HEAD ( & dmar_domain - > s1_domains ) ;
spin_lock_init ( & dmar_domain - > s1_lock ) ;
}
2023-10-24 13:51:03 +00:00
2023-10-26 04:42:15 +00:00
if ( dirty_tracking ) {
2024-02-19 11:15:52 +00:00
if ( dmar_domain - > use_first_level ) {
2023-10-24 13:51:03 +00:00
iommu_domain_free ( domain ) ;
return ERR_PTR ( - EOPNOTSUPP ) ;
}
domain - > dirty_ops = & intel_dirty_ops ;
}
2023-09-28 07:15:28 +00:00
return domain ;
}
2015-03-26 12:43:08 +00:00
static void intel_iommu_domain_free ( struct iommu_domain * domain )
2008-09-09 15:37:29 +00:00
{
2024-02-19 11:15:52 +00:00
struct dmar_domain * dmar_domain = to_dmar_domain ( domain ) ;
WARN_ON ( dmar_domain - > nested_parent & &
! list_empty ( & dmar_domain - > s1_domains ) ) ;
2023-09-27 23:47:32 +00:00
if ( domain ! = & si_domain - > domain )
2024-02-19 11:15:52 +00:00
domain_exit ( dmar_domain ) ;
2008-09-09 15:37:29 +00:00
}
2023-10-26 04:42:13 +00:00
int prepare_domain_attach_device ( struct iommu_domain * domain ,
struct device * dev )
2008-09-09 15:37:29 +00:00
{
2023-12-18 07:34:42 +00:00
struct device_domain_info * info = dev_iommu_priv_get ( dev ) ;
2015-03-26 12:43:08 +00:00
struct dmar_domain * dmar_domain = to_dmar_domain ( domain ) ;
2023-12-18 07:34:42 +00:00
struct intel_iommu * iommu = info - > iommu ;
2008-12-08 15:10:23 +00:00
int addr_width ;
2008-12-08 15:09:29 +00:00
2022-05-10 02:34:04 +00:00
if ( dmar_domain - > force_snooping & & ! ecap_sc_support ( iommu - > ecap ) )
2022-10-17 23:02:21 +00:00
return - EINVAL ;
2022-05-10 02:34:04 +00:00
2023-10-24 13:51:03 +00:00
if ( domain - > dirty_ops & & ! ssads_supported ( iommu ) )
return - EINVAL ;
2008-12-08 15:10:23 +00:00
/* check if this iommu agaw is sufficient for max mapped address */
addr_width = agaw_to_width ( iommu - > agaw ) ;
2010-05-17 07:20:45 +00:00
if ( addr_width > cap_mgaw ( iommu - > cap ) )
addr_width = cap_mgaw ( iommu - > cap ) ;
2022-10-17 23:02:21 +00:00
if ( dmar_domain - > max_addr > ( 1LL < < addr_width ) )
return - EINVAL ;
2010-05-17 07:20:45 +00:00
dmar_domain - > gaw = addr_width ;
/*
* Knock out extra levels of page tables if necessary
*/
while ( iommu - > agaw < dmar_domain - > agaw ) {
struct dma_pte * pte ;
pte = dmar_domain - > pgd ;
if ( dma_pte_present ( pte ) ) {
2021-06-10 02:01:15 +00:00
dmar_domain - > pgd = phys_to_virt ( dma_pte_addr ( pte ) ) ;
2010-11-02 07:05:51 +00:00
free_pgtable_page ( pte ) ;
2010-05-17 07:20:45 +00:00
}
dmar_domain - > agaw - - ;
}
2008-12-08 15:10:23 +00:00
2019-03-25 01:30:31 +00:00
return 0 ;
}
static int intel_iommu_attach_device ( struct iommu_domain * domain ,
struct device * dev )
{
2022-11-22 00:29:48 +00:00
struct device_domain_info * info = dev_iommu_priv_get ( dev ) ;
2019-03-25 01:30:31 +00:00
int ret ;
2022-11-22 00:29:48 +00:00
if ( info - > domain )
device_block_translation ( dev ) ;
2019-03-25 01:30:31 +00:00
ret = prepare_domain_attach_device ( domain , dev ) ;
if ( ret )
return ret ;
2022-11-22 00:29:47 +00:00
return dmar_domain_attach_device ( to_dmar_domain ( domain ) , dev ) ;
2008-12-08 15:09:29 +00:00
}
2008-12-08 14:51:37 +00:00
2010-01-20 16:17:37 +00:00
static int intel_iommu_map ( struct iommu_domain * domain ,
unsigned long iova , phys_addr_t hpa ,
2019-09-08 16:56:38 +00:00
size_t size , int iommu_prot , gfp_t gfp )
2008-12-08 15:09:29 +00:00
{
2015-03-26 12:43:08 +00:00
struct dmar_domain * dmar_domain = to_dmar_domain ( domain ) ;
2008-12-08 15:10:23 +00:00
u64 max_addr ;
2008-12-03 14:04:09 +00:00
int prot = 0 ;
2008-12-08 15:10:23 +00:00
2008-12-03 14:04:09 +00:00
if ( iommu_prot & IOMMU_READ )
prot | = DMA_PTE_READ ;
if ( iommu_prot & IOMMU_WRITE )
prot | = DMA_PTE_WRITE ;
2022-05-10 02:34:05 +00:00
if ( dmar_domain - > set_pte_snp )
2009-03-18 07:33:07 +00:00
prot | = DMA_PTE_SNP ;
2008-12-03 14:04:09 +00:00
2009-06-27 23:51:17 +00:00
max_addr = iova + size ;
2008-12-03 14:04:09 +00:00
if ( dmar_domain - > max_addr < max_addr ) {
2008-12-08 15:10:23 +00:00
u64 end ;
/* check if minimum agaw is sufficient for mapped address */
2010-05-17 07:19:52 +00:00
end = __DOMAIN_MAX_ADDR ( dmar_domain - > gaw ) + 1 ;
2008-12-08 15:10:23 +00:00
if ( end < max_addr ) {
2015-06-12 07:57:06 +00:00
pr_err ( " %s: iommu width (%d) is not "
2008-12-08 15:10:23 +00:00
" sufficient for the mapped address (%llx) \n " ,
2010-05-17 07:19:52 +00:00
__func__ , dmar_domain - > gaw , max_addr ) ;
2008-12-08 15:10:23 +00:00
return - EFAULT ;
}
2008-12-03 14:04:09 +00:00
dmar_domain - > max_addr = max_addr ;
2008-12-08 15:10:23 +00:00
}
2009-06-28 13:22:28 +00:00
/* Round up size to next multiple of PAGE_SIZE, if it and
the low bits of hpa would take us onto the next page */
2009-06-28 14:03:06 +00:00
size = aligned_nrpages ( hpa , size ) ;
2021-02-04 01:43:58 +00:00
return __domain_mapping ( dmar_domain , iova > > VTD_PAGE_SHIFT ,
2023-01-23 20:36:00 +00:00
hpa > > VTD_PAGE_SHIFT , size , prot , gfp ) ;
2008-09-09 15:37:29 +00:00
}
2021-07-20 02:06:14 +00:00
static int intel_iommu_map_pages ( struct iommu_domain * domain ,
unsigned long iova , phys_addr_t paddr ,
size_t pgsize , size_t pgcount ,
int prot , gfp_t gfp , size_t * mapped )
{
unsigned long pgshift = __ffs ( pgsize ) ;
size_t size = pgcount < < pgshift ;
int ret ;
if ( pgsize ! = SZ_4K & & pgsize ! = SZ_2M & & pgsize ! = SZ_1G )
return - EINVAL ;
if ( ! IS_ALIGNED ( iova | paddr , pgsize ) )
return - EINVAL ;
ret = intel_iommu_map ( domain , iova , paddr , size , prot , gfp ) ;
if ( ! ret & & mapped )
* mapped = size ;
return ret ;
}
2011-11-10 09:32:25 +00:00
static size_t intel_iommu_unmap ( struct iommu_domain * domain ,
2019-07-02 15:44:06 +00:00
unsigned long iova , size_t size ,
struct iommu_iotlb_gather * gather )
2008-09-09 15:37:29 +00:00
{
2015-03-26 12:43:08 +00:00
struct dmar_domain * dmar_domain = to_dmar_domain ( domain ) ;
2014-03-05 17:09:32 +00:00
unsigned long start_pfn , last_pfn ;
2020-11-24 08:20:51 +00:00
int level = 0 ;
2014-03-19 16:07:49 +00:00
/* Cope with horrid API which requires us to unmap more than the
size argument if it happens to be a large - page mapping . */
2023-04-13 04:06:43 +00:00
if ( unlikely ( ! pfn_to_dma_pte ( dmar_domain , iova > > VTD_PAGE_SHIFT ,
& level , GFP_ATOMIC ) ) )
return 0 ;
2014-03-19 16:07:49 +00:00
if ( size < VTD_PAGE_SIZE < < level_to_offset_bits ( level ) )
size = VTD_PAGE_SIZE < < level_to_offset_bits ( level ) ;
2009-07-08 10:52:52 +00:00
2014-03-05 17:09:32 +00:00
start_pfn = iova > > VTD_PAGE_SHIFT ;
last_pfn = ( iova + size - 1 ) > > VTD_PAGE_SHIFT ;
2021-12-17 15:31:00 +00:00
domain_unmap ( dmar_domain , start_pfn , last_pfn , & gather - > freelist ) ;
2008-12-08 15:10:23 +00:00
2009-06-27 23:51:17 +00:00
if ( dmar_domain - > max_addr = = iova + size )
dmar_domain - > max_addr = iova ;
2010-01-20 16:17:37 +00:00
2023-02-16 13:08:14 +00:00
/*
* We do not use page - selective IOTLB invalidation in flush queue ,
* so there is no need to track page and sync iotlb .
*/
if ( ! iommu_iotlb_gather_queued ( gather ) )
iommu_iotlb_gather_add_page ( domain , gather , iova , size ) ;
2020-11-24 08:20:51 +00:00
2014-03-19 16:07:49 +00:00
return size ;
2008-09-09 15:37:29 +00:00
}
2021-07-20 02:06:14 +00:00
static size_t intel_iommu_unmap_pages ( struct iommu_domain * domain ,
unsigned long iova ,
size_t pgsize , size_t pgcount ,
struct iommu_iotlb_gather * gather )
{
unsigned long pgshift = __ffs ( pgsize ) ;
size_t size = pgcount < < pgshift ;
return intel_iommu_unmap ( domain , iova , size , gather ) ;
}
2020-11-24 08:20:51 +00:00
static void intel_iommu_tlb_sync ( struct iommu_domain * domain ,
struct iommu_iotlb_gather * gather )
{
struct dmar_domain * dmar_domain = to_dmar_domain ( domain ) ;
unsigned long iova_pfn = IOVA_PFN ( gather - > start ) ;
size_t size = gather - > end - gather - > start ;
2022-07-12 00:09:05 +00:00
struct iommu_domain_info * info ;
2020-11-27 01:33:08 +00:00
unsigned long start_pfn ;
2020-11-24 08:20:51 +00:00
unsigned long nrpages ;
2022-07-12 00:09:05 +00:00
unsigned long i ;
2020-11-24 08:20:51 +00:00
nrpages = aligned_nrpages ( gather - > start , size ) ;
2023-08-09 12:48:05 +00:00
start_pfn = mm_to_dma_pfn_start ( iova_pfn ) ;
2020-11-24 08:20:51 +00:00
2022-07-12 00:09:05 +00:00
xa_for_each ( & dmar_domain - > iommu_array , i , info )
iommu_flush_iotlb_psi ( info - > iommu , dmar_domain ,
2021-12-17 15:31:00 +00:00
start_pfn , nrpages ,
list_empty ( & gather - > freelist ) , 0 ) ;
2020-11-24 08:20:51 +00:00
2024-02-19 11:15:54 +00:00
if ( dmar_domain - > nested_parent )
parent_domain_flush ( dmar_domain , start_pfn , nrpages ,
list_empty ( & gather - > freelist ) ) ;
2021-12-17 15:31:00 +00:00
put_pages_list ( & gather - > freelist ) ;
2020-11-24 08:20:51 +00:00
}
2008-12-03 14:06:57 +00:00
static phys_addr_t intel_iommu_iova_to_phys ( struct iommu_domain * domain ,
2013-03-28 19:53:58 +00:00
dma_addr_t iova )
2008-09-09 15:37:29 +00:00
{
2015-03-26 12:43:08 +00:00
struct dmar_domain * dmar_domain = to_dmar_domain ( domain ) ;
2008-09-09 15:37:29 +00:00
struct dma_pte * pte ;
2014-03-19 16:07:49 +00:00
int level = 0 ;
2008-12-08 15:09:29 +00:00
u64 phys = 0 ;
2008-09-09 15:37:29 +00:00
2023-01-23 20:36:00 +00:00
pte = pfn_to_dma_pte ( dmar_domain , iova > > VTD_PAGE_SHIFT , & level ,
GFP_ATOMIC ) ;
2020-02-26 20:30:06 +00:00
if ( pte & & dma_pte_present ( pte ) )
phys = dma_pte_addr ( pte ) +
( iova & ( BIT_MASK ( level_to_offset_bits ( level ) +
VTD_PAGE_SHIFT ) - 1 ) ) ;
2008-09-09 15:37:29 +00:00
2008-12-08 15:09:29 +00:00
return phys ;
2008-09-09 15:37:29 +00:00
}
2008-12-03 14:14:02 +00:00
2022-05-10 02:34:05 +00:00
static bool domain_support_force_snooping ( struct dmar_domain * domain )
{
struct device_domain_info * info ;
bool support = true ;
2022-07-12 00:09:02 +00:00
assert_spin_locked ( & domain - > lock ) ;
2022-05-10 02:34:05 +00:00
list_for_each_entry ( info , & domain - > devices , link ) {
if ( ! ecap_sc_support ( info - > iommu - > ecap ) ) {
support = false ;
break ;
}
}
return support ;
}
static void domain_set_force_snooping ( struct dmar_domain * domain )
{
struct device_domain_info * info ;
2022-07-12 00:09:02 +00:00
assert_spin_locked ( & domain - > lock ) ;
2022-05-10 02:34:05 +00:00
/*
* Second level page table supports per - PTE snoop control . The
* iommu_map ( ) interface will handle this by setting SNP bit .
*/
2022-11-22 00:29:49 +00:00
if ( ! domain - > use_first_level ) {
2022-05-10 02:34:05 +00:00
domain - > set_pte_snp = true ;
return ;
}
list_for_each_entry ( info , & domain - > devices , link )
intel_pasid_setup_page_snoop_control ( info - > iommu , info - > dev ,
2023-08-09 12:47:54 +00:00
IOMMU_NO_PASID ) ;
2022-05-10 02:34:05 +00:00
}
2022-04-11 15:16:05 +00:00
static bool intel_iommu_enforce_cache_coherency ( struct iommu_domain * domain )
{
struct dmar_domain * dmar_domain = to_dmar_domain ( domain ) ;
2022-08-23 06:15:56 +00:00
unsigned long flags ;
2022-04-11 15:16:05 +00:00
2022-05-10 02:34:05 +00:00
if ( dmar_domain - > force_snooping )
return true ;
2022-08-23 06:15:56 +00:00
spin_lock_irqsave ( & dmar_domain - > lock , flags ) ;
2023-11-22 03:26:02 +00:00
if ( ! domain_support_force_snooping ( dmar_domain ) | |
( ! dmar_domain - > use_first_level & & dmar_domain - > has_mappings ) ) {
2022-08-23 06:15:56 +00:00
spin_unlock_irqrestore ( & dmar_domain - > lock , flags ) ;
2022-04-11 15:16:05 +00:00
return false ;
2022-05-10 02:34:05 +00:00
}
domain_set_force_snooping ( dmar_domain ) ;
2022-04-11 15:16:05 +00:00
dmar_domain - > force_snooping = true ;
2022-08-23 06:15:56 +00:00
spin_unlock_irqrestore ( & dmar_domain - > lock , flags ) ;
2022-05-10 02:34:05 +00:00
2022-04-11 15:16:05 +00:00
return true ;
}
2022-08-15 15:26:49 +00:00
static bool intel_iommu_capable ( struct device * dev , enum iommu_cap cap )
2009-03-18 07:33:06 +00:00
{
2022-11-29 20:29:24 +00:00
struct device_domain_info * info = dev_iommu_priv_get ( dev ) ;
switch ( cap ) {
case IOMMU_CAP_CACHE_COHERENCY :
2023-05-04 21:10:55 +00:00
case IOMMU_CAP_DEFERRED_FLUSH :
2022-04-11 15:16:07 +00:00
return true ;
2022-11-29 20:29:24 +00:00
case IOMMU_CAP_PRE_BOOT_PROTECTION :
2022-04-25 12:42:03 +00:00
return dmar_platform_optin ( ) ;
2022-11-29 20:29:24 +00:00
case IOMMU_CAP_ENFORCE_CACHE_COHERENCY :
return ecap_sc_support ( info - > iommu - > ecap ) ;
2023-10-24 13:51:03 +00:00
case IOMMU_CAP_DIRTY_TRACKING :
return ssads_supported ( info - > iommu ) ;
2022-11-29 20:29:24 +00:00
default :
return false ;
}
2009-03-18 07:33:06 +00:00
}
2020-04-29 13:36:54 +00:00
static struct iommu_device * intel_iommu_probe_device ( struct device * dev )
2012-05-30 20:19:19 +00:00
{
2022-03-01 02:01:52 +00:00
struct pci_dev * pdev = dev_is_pci ( dev ) ? to_pci_dev ( dev ) : NULL ;
struct device_domain_info * info ;
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
struct intel_iommu * iommu ;
2022-03-01 02:01:52 +00:00
u8 bus , devfn ;
2022-11-22 00:29:43 +00:00
int ret ;
2011-10-21 19:56:11 +00:00
2023-12-18 07:34:42 +00:00
iommu = device_lookup_iommu ( dev , & bus , & devfn ) ;
2022-08-15 16:20:02 +00:00
if ( ! iommu | | ! iommu - > iommu . ops )
2020-04-29 13:36:54 +00:00
return ERR_PTR ( - ENODEV ) ;
2012-08-04 18:08:55 +00:00
2022-03-01 02:01:52 +00:00
info = kzalloc ( sizeof ( * info ) , GFP_KERNEL ) ;
if ( ! info )
return ERR_PTR ( - ENOMEM ) ;
if ( dev_is_real_dma_subdevice ( dev ) ) {
info - > bus = pdev - > bus - > number ;
info - > devfn = pdev - > devfn ;
info - > segment = pci_domain_nr ( pdev - > bus ) ;
} else {
info - > bus = bus ;
info - > devfn = devfn ;
info - > segment = iommu - > segment ;
}
info - > dev = dev ;
info - > iommu = iommu ;
if ( dev_is_pci ( dev ) ) {
if ( ecap_dev_iotlb_support ( iommu - > ecap ) & &
pci_ats_supported ( pdev ) & &
2022-12-01 04:01:24 +00:00
dmar_ats_supported ( pdev , iommu ) ) {
2022-03-01 02:01:52 +00:00
info - > ats_supported = 1 ;
2022-12-01 04:01:24 +00:00
info - > dtlb_extra_inval = dev_needs_extra_dtlb_flush ( pdev ) ;
2023-04-13 04:06:32 +00:00
/*
* For IOMMU that supports device IOTLB throttling
* ( DIT ) , we assign PFSID to the invalidation desc
* of a VF such that IOMMU HW can gauge queue depth
* at PF level . If DIT is not set , PFSID will be
* treated as reserved , which should be set to 0.
*/
if ( ecap_dit ( iommu - > ecap ) )
info - > pfsid = pci_dev_id ( pci_physfn ( pdev ) ) ;
info - > ats_qdep = pci_ats_queue_depth ( pdev ) ;
2022-12-01 04:01:24 +00:00
}
2022-03-01 02:01:52 +00:00
if ( sm_supported ( iommu ) ) {
if ( pasid_supported ( iommu ) ) {
int features = pci_pasid_features ( pdev ) ;
if ( features > = 0 )
info - > pasid_supported = features | 1 ;
}
if ( info - > ats_supported & & ecap_prs ( iommu - > ecap ) & &
pci_pri_supported ( pdev ) )
info - > pri_supported = 1 ;
}
}
dev_iommu_priv_set ( dev , info ) ;
2024-04-11 03:07:44 +00:00
if ( pdev & & pci_ats_supported ( pdev ) ) {
ret = device_rbtree_insert ( iommu , info ) ;
if ( ret )
goto free ;
}
2019-05-25 05:41:32 +00:00
2022-11-22 00:29:43 +00:00
if ( sm_supported ( iommu ) & & ! dev_is_real_dma_subdevice ( dev ) ) {
ret = intel_pasid_alloc_table ( dev ) ;
if ( ret ) {
dev_err ( dev , " PASID table allocation failed \n " ) ;
2024-02-27 02:14:40 +00:00
goto clear_rbtree ;
2022-11-22 00:29:43 +00:00
}
}
2023-10-16 03:28:29 +00:00
intel_iommu_debugfs_create_dev ( info ) ;
2020-04-29 13:36:54 +00:00
return & iommu - > iommu ;
2024-02-27 02:14:40 +00:00
clear_rbtree :
device_rbtree_remove ( info ) ;
free :
kfree ( info ) ;
return ERR_PTR ( ret ) ;
2012-05-30 20:19:19 +00:00
}
2011-10-21 19:56:11 +00:00
2020-04-29 13:36:54 +00:00
static void intel_iommu_release_device ( struct device * dev )
2012-05-30 20:19:19 +00:00
{
2022-03-01 02:01:52 +00:00
struct device_domain_info * info = dev_iommu_priv_get ( dev ) ;
2024-02-27 02:14:41 +00:00
struct intel_iommu * iommu = info - > iommu ;
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
2024-02-27 02:14:41 +00:00
mutex_lock ( & iommu - > iopf_lock ) ;
2024-04-11 03:07:44 +00:00
if ( dev_is_pci ( dev ) & & pci_ats_supported ( to_pci_dev ( dev ) ) )
device_rbtree_remove ( info ) ;
2024-02-27 02:14:41 +00:00
mutex_unlock ( & iommu - > iopf_lock ) ;
2024-03-05 12:21:18 +00:00
if ( sm_supported ( iommu ) & & ! dev_is_real_dma_subdevice ( dev ) & &
! context_copied ( iommu , info - > bus , info - > devfn ) )
intel_pasid_teardown_sm_context ( dev ) ;
2022-11-22 00:29:43 +00:00
intel_pasid_free_table ( dev ) ;
2023-10-16 03:28:29 +00:00
intel_iommu_debugfs_remove_dev ( info ) ;
2022-03-01 02:01:52 +00:00
kfree ( info ) ;
2020-05-06 01:59:47 +00:00
set_dma_ops ( dev , NULL ) ;
}
iommu/vt-d: Make use of IOMMU sysfs support
Register our DRHD IOMMUs, cross link devices, and provide a base set
of attributes for the IOMMU. Note that IRQ remapping support parses
the DMAR table very early in boot, well before the iommu_class can
reasonably be setup, so our registration is split between
intel_iommu_init(), which occurs later, and alloc_iommu(), which
typically occurs much earlier, but may happen at any time later
with IOMMU hot-add support.
On a typical desktop system, this provides the following (pruned):
$ find /sys | grep dmar
/sys/devices/virtual/iommu/dmar0
/sys/devices/virtual/iommu/dmar0/devices
/sys/devices/virtual/iommu/dmar0/devices/0000:00:02.0
/sys/devices/virtual/iommu/dmar0/intel-iommu
/sys/devices/virtual/iommu/dmar0/intel-iommu/cap
/sys/devices/virtual/iommu/dmar0/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar0/intel-iommu/address
/sys/devices/virtual/iommu/dmar0/intel-iommu/version
/sys/devices/virtual/iommu/dmar1
/sys/devices/virtual/iommu/dmar1/devices
/sys/devices/virtual/iommu/dmar1/devices/0000:00:00.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:01.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:16.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1a.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1b.0
/sys/devices/virtual/iommu/dmar1/devices/0000:00:1c.0
...
/sys/devices/virtual/iommu/dmar1/intel-iommu
/sys/devices/virtual/iommu/dmar1/intel-iommu/cap
/sys/devices/virtual/iommu/dmar1/intel-iommu/ecap
/sys/devices/virtual/iommu/dmar1/intel-iommu/address
/sys/devices/virtual/iommu/dmar1/intel-iommu/version
/sys/class/iommu/dmar0
/sys/class/iommu/dmar1
(devices also link back to the dmar units)
This makes address, version, capabilities, and extended capabilities
available, just like printed on boot. I've tried not to duplicate
data that can be found in the DMAR table, with the exception of the
address, which provides an easy way to associate the sysfs device with
a DRHD entry in the DMAR. It's tempting to add scopes and RMRR data
here, but the full DMAR table is already exposed under /sys/firmware/
and therefore already provides a way for userspace to learn such
details.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-06-12 22:12:31 +00:00
2020-05-06 01:59:47 +00:00
static void intel_iommu_probe_finalize ( struct device * dev )
{
2021-08-11 12:21:33 +00:00
set_dma_ops ( dev , NULL ) ;
iommu_setup_dma_ops ( dev , 0 , U64_MAX ) ;
2011-10-21 19:56:11 +00:00
}
2017-01-19 20:57:53 +00:00
static void intel_iommu_get_resv_regions ( struct device * device ,
struct list_head * head )
{
2019-06-03 06:53:31 +00:00
int prot = DMA_PTE_READ | DMA_PTE_WRITE ;
2017-01-19 20:57:53 +00:00
struct iommu_resv_region * reg ;
struct dmar_rmrr_unit * rmrr ;
struct device * i_dev ;
int i ;
2022-10-19 00:44:45 +00:00
rcu_read_lock ( ) ;
2017-01-19 20:57:53 +00:00
for_each_rmrr_units ( rmrr ) {
for_each_active_dev_scope ( rmrr - > devices , rmrr - > devices_cnt ,
i , i_dev ) {
2019-06-03 06:53:31 +00:00
struct iommu_resv_region * resv ;
2019-06-03 06:53:36 +00:00
enum iommu_resv_type type ;
2019-06-03 06:53:31 +00:00
size_t length ;
2019-06-03 06:53:34 +00:00
if ( i_dev ! = device & &
! is_downstream_to_pci_bridge ( device , i_dev ) )
2017-01-19 20:57:53 +00:00
continue ;
2019-06-03 06:53:31 +00:00
length = rmrr - > end_address - rmrr - > base_address + 1 ;
2019-06-03 06:53:36 +00:00
type = device_rmrr_is_relaxable ( device ) ?
IOMMU_RESV_DIRECT_RELAXABLE : IOMMU_RESV_DIRECT ;
2019-06-03 06:53:31 +00:00
resv = iommu_alloc_resv_region ( rmrr - > base_address ,
2022-10-19 00:44:44 +00:00
length , prot , type ,
2022-10-19 00:44:45 +00:00
GFP_ATOMIC ) ;
2019-06-03 06:53:31 +00:00
if ( ! resv )
break ;
list_add_tail ( & resv - > list , head ) ;
2017-01-19 20:57:53 +00:00
}
}
2022-10-19 00:44:45 +00:00
rcu_read_unlock ( ) ;
2017-01-19 20:57:53 +00:00
2019-05-25 05:41:24 +00:00
# ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
if ( dev_is_pci ( device ) ) {
struct pci_dev * pdev = to_pci_dev ( device ) ;
if ( ( pdev - > class > > 8 ) = = PCI_CLASS_BRIDGE_ISA ) {
2019-12-13 05:36:42 +00:00
reg = iommu_alloc_resv_region ( 0 , 1UL < < 24 , prot ,
2022-10-19 00:44:44 +00:00
IOMMU_RESV_DIRECT_RELAXABLE ,
GFP_KERNEL ) ;
2019-05-25 05:41:24 +00:00
if ( reg )
list_add_tail ( & reg - > list , head ) ;
}
}
# endif /* CONFIG_INTEL_IOMMU_FLOPPY_WA */
2017-01-19 20:57:53 +00:00
reg = iommu_alloc_resv_region ( IOAPIC_RANGE_START ,
IOAPIC_RANGE_END - IOAPIC_RANGE_START + 1 ,
2022-10-19 00:44:44 +00:00
0 , IOMMU_RESV_MSI , GFP_KERNEL ) ;
2017-01-19 20:57:53 +00:00
if ( ! reg )
return ;
list_add_tail ( & reg - > list , head ) ;
}
2019-12-26 23:56:18 +00:00
static struct iommu_group * intel_iommu_device_group ( struct device * dev )
{
if ( dev_is_pci ( dev ) )
return pci_device_group ( dev ) ;
return generic_device_group ( dev ) ;
}
2021-06-10 02:01:02 +00:00
static int intel_iommu_enable_sva ( struct device * dev )
{
2022-03-01 02:01:52 +00:00
struct device_domain_info * info = dev_iommu_priv_get ( dev ) ;
2021-06-11 13:50:24 +00:00
struct intel_iommu * iommu ;
2021-06-10 02:01:02 +00:00
2021-06-11 13:50:24 +00:00
if ( ! info | | dmar_disabled )
return - EINVAL ;
iommu = info - > iommu ;
if ( ! iommu )
2021-06-10 02:01:02 +00:00
return - EINVAL ;
if ( ! ( iommu - > flags & VTD_FLAG_SVM_CAPABLE ) )
return - ENODEV ;
2023-04-13 04:06:30 +00:00
if ( ! info - > pasid_enabled | | ! info - > ats_enabled )
2021-06-10 02:01:02 +00:00
return - EINVAL ;
2023-04-13 04:06:30 +00:00
/*
* Devices having device - specific I / O fault handling should not
* support PCI / PRI . The IOMMU side has no means to check the
* capability of device - specific IOPF . Therefore , IOMMU can only
* default that if the device driver enables SVA on a non - PRI
* device , it will handle IOPF in its own way .
*/
if ( ! info - > pri_supported )
return 0 ;
2023-02-16 13:08:13 +00:00
2023-04-13 04:06:30 +00:00
/* Devices supporting PRI should have it enabled. */
if ( ! info - > pri_enabled )
2021-06-10 02:01:02 +00:00
return - EINVAL ;
2021-06-10 02:01:03 +00:00
2023-04-13 04:06:31 +00:00
return 0 ;
2021-06-10 02:01:02 +00:00
}
2023-04-13 04:06:31 +00:00
static int intel_iommu_enable_iopf ( struct device * dev )
2021-06-10 02:01:02 +00:00
{
2023-04-13 04:06:33 +00:00
struct pci_dev * pdev = dev_is_pci ( dev ) ? to_pci_dev ( dev ) : NULL ;
2022-03-01 02:01:52 +00:00
struct device_domain_info * info = dev_iommu_priv_get ( dev ) ;
2023-04-13 04:06:31 +00:00
struct intel_iommu * iommu ;
2021-06-10 02:01:03 +00:00
int ret ;
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if ( ! pdev | | ! info | | ! info - > ats_enabled | | ! info - > pri_supported )
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return - ENODEV ;
2023-04-13 04:06:33 +00:00
if ( info - > pri_enabled )
return - EBUSY ;
2023-04-13 04:06:31 +00:00
iommu = info - > iommu ;
if ( ! iommu )
return - EINVAL ;
2023-04-13 04:06:33 +00:00
/* PASID is required in PRG Response Message. */
if ( info - > pasid_enabled & & ! pci_prg_resp_pasid_required ( pdev ) )
return - EINVAL ;
ret = pci_reset_pri ( pdev ) ;
if ( ret )
return ret ;
2021-06-10 02:01:03 +00:00
ret = iopf_queue_add_device ( iommu - > iopf_queue , dev ) ;
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if ( ret )
return ret ;
ret = iommu_register_device_fault_handler ( dev , iommu_queue_iopf , dev ) ;
if ( ret )
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goto iopf_remove_device ;
ret = pci_enable_pri ( pdev , PRQ_DEPTH ) ;
2023-02-16 13:08:13 +00:00
if ( ret )
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goto iopf_unregister_handler ;
info - > pri_enabled = 1 ;
return 0 ;
iopf_unregister_handler :
iommu_unregister_device_fault_handler ( dev ) ;
iopf_remove_device :
iopf_queue_remove_device ( iommu - > iopf_queue , dev ) ;
2021-06-10 02:01:02 +00:00
2021-06-10 02:01:03 +00:00
return ret ;
2021-06-10 02:01:02 +00:00
}
2023-04-13 04:06:31 +00:00
static int intel_iommu_disable_iopf ( struct device * dev )
2019-03-25 01:30:30 +00:00
{
2022-03-01 02:01:52 +00:00
struct device_domain_info * info = dev_iommu_priv_get ( dev ) ;
2021-06-10 02:01:02 +00:00
struct intel_iommu * iommu = info - > iommu ;
2021-04-01 15:47:13 +00:00
2023-04-13 04:06:33 +00:00
if ( ! info - > pri_enabled )
return - EINVAL ;
/*
* PCIe spec states that by clearing PRI enable bit , the Page
* Request Interface will not issue new page requests , but has
* outstanding page requests that have been transmitted or are
* queued for transmission . This is supposed to be called after
* the device driver has stopped DMA , all PASIDs have been
* unbound and the outstanding PRQs have been drained .
*/
pci_disable_pri ( to_pci_dev ( dev ) ) ;
info - > pri_enabled = 0 ;
2020-05-16 06:20:53 +00:00
2023-04-13 04:06:34 +00:00
/*
* With PRI disabled and outstanding PRQs drained , unregistering
* fault handler and removing device from iopf queue should never
* fail .
*/
WARN_ON ( iommu_unregister_device_fault_handler ( dev ) ) ;
WARN_ON ( iopf_queue_remove_device ( iommu - > iopf_queue , dev ) ) ;
2021-06-10 02:01:02 +00:00
2023-04-13 04:06:34 +00:00
return 0 ;
2019-03-25 01:30:30 +00:00
}
static int
intel_iommu_dev_enable_feat ( struct device * dev , enum iommu_dev_features feat )
{
2021-06-10 02:01:02 +00:00
switch ( feat ) {
case IOMMU_DEV_FEAT_IOPF :
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return intel_iommu_enable_iopf ( dev ) ;
2021-04-01 15:47:13 +00:00
2021-06-10 02:01:02 +00:00
case IOMMU_DEV_FEAT_SVA :
return intel_iommu_enable_sva ( dev ) ;
2020-05-16 06:20:53 +00:00
2021-06-10 02:01:02 +00:00
default :
return - ENODEV ;
2020-05-16 06:20:53 +00:00
}
2019-03-25 01:30:30 +00:00
}
static int
intel_iommu_dev_disable_feat ( struct device * dev , enum iommu_dev_features feat )
{
2021-06-10 02:01:02 +00:00
switch ( feat ) {
case IOMMU_DEV_FEAT_IOPF :
2023-04-13 04:06:31 +00:00
return intel_iommu_disable_iopf ( dev ) ;
2021-06-10 02:01:02 +00:00
case IOMMU_DEV_FEAT_SVA :
2023-04-13 04:06:31 +00:00
return 0 ;
2021-06-10 02:01:02 +00:00
default :
return - ENODEV ;
}
2019-03-25 01:30:30 +00:00
}
2022-02-16 02:52:48 +00:00
static bool intel_iommu_is_attach_deferred ( struct device * dev )
2019-03-25 01:30:33 +00:00
{
2022-03-01 02:01:52 +00:00
struct device_domain_info * info = dev_iommu_priv_get ( dev ) ;
2019-03-25 01:30:33 +00:00
2022-03-01 02:01:52 +00:00
return translation_pre_enabled ( info - > iommu ) & & ! info - > domain ;
2020-01-02 00:18:15 +00:00
}
2020-06-22 23:13:42 +00:00
/*
* Check that the device does not live on an external facing PCI port that is
* marked as untrusted . Such devices should not be able to apply quirks and
* thus not be able to bypass the IOMMU restrictions .
*/
static bool risky_device ( struct pci_dev * pdev )
{
if ( pdev - > untrusted ) {
pci_info ( pdev ,
" Skipping IOMMU quirk for dev [%04X:%04X] on untrusted PCI link \n " ,
pdev - > vendor , pdev - > device ) ;
pci_info ( pdev , " Please check with your BIOS/Platform vendor about this \n " ) ;
return true ;
}
return false ;
}
2023-09-28 14:31:35 +00:00
static int intel_iommu_iotlb_sync_map ( struct iommu_domain * domain ,
unsigned long iova , size_t size )
2021-02-04 01:43:58 +00:00
{
struct dmar_domain * dmar_domain = to_dmar_domain ( domain ) ;
unsigned long pages = aligned_nrpages ( iova , size ) ;
unsigned long pfn = iova > > VTD_PAGE_SHIFT ;
2022-07-12 00:09:05 +00:00
struct iommu_domain_info * info ;
unsigned long i ;
2021-02-04 01:43:58 +00:00
2022-07-12 00:09:05 +00:00
xa_for_each ( & dmar_domain - > iommu_array , i , info )
__mapping_notify_one ( info - > iommu , dmar_domain , pfn , pages ) ;
2023-09-28 14:31:35 +00:00
return 0 ;
2021-02-04 01:43:58 +00:00
}
2022-10-31 00:59:11 +00:00
static void intel_iommu_remove_dev_pasid ( struct device * dev , ioasid_t pasid )
{
2023-12-18 07:34:42 +00:00
struct device_domain_info * info = dev_iommu_priv_get ( dev ) ;
2023-08-09 12:48:00 +00:00
struct dev_pasid_info * curr , * dev_pasid = NULL ;
2023-12-18 07:34:42 +00:00
struct intel_iommu * iommu = info - > iommu ;
2023-08-09 12:48:00 +00:00
struct dmar_domain * dmar_domain ;
2022-10-31 00:59:11 +00:00
struct iommu_domain * domain ;
2023-08-09 12:48:00 +00:00
unsigned long flags ;
2022-10-31 00:59:11 +00:00
domain = iommu_get_domain_for_dev_pasid ( dev , pasid , 0 ) ;
2023-08-09 12:47:58 +00:00
if ( WARN_ON_ONCE ( ! domain ) )
goto out_tear_down ;
/*
* The SVA implementation needs to handle its own stuffs like the mm
* notification . Before consolidating that code into iommu core , let
* the intel sva code handle it .
*/
if ( domain - > type = = IOMMU_DOMAIN_SVA ) {
intel_svm_remove_dev_pasid ( dev , pasid ) ;
goto out_tear_down ;
2022-10-31 00:59:11 +00:00
}
2023-08-09 12:48:00 +00:00
dmar_domain = to_dmar_domain ( domain ) ;
spin_lock_irqsave ( & dmar_domain - > lock , flags ) ;
list_for_each_entry ( curr , & dmar_domain - > dev_pasids , link_domain ) {
if ( curr - > dev = = dev & & curr - > pasid = = pasid ) {
list_del ( & curr - > link_domain ) ;
dev_pasid = curr ;
2022-10-31 00:59:11 +00:00
break ;
}
}
2023-08-09 12:48:00 +00:00
WARN_ON_ONCE ( ! dev_pasid ) ;
spin_unlock_irqrestore ( & dmar_domain - > lock , flags ) ;
2022-10-31 00:59:11 +00:00
2023-08-09 12:48:00 +00:00
domain_detach_iommu ( dmar_domain , iommu ) ;
2023-10-16 03:28:29 +00:00
intel_iommu_debugfs_remove_dev_pasid ( dev_pasid ) ;
2023-08-09 12:48:00 +00:00
kfree ( dev_pasid ) ;
2023-08-09 12:47:58 +00:00
out_tear_down :
2022-10-31 00:59:11 +00:00
intel_pasid_tear_down_entry ( iommu , dev , pasid , false ) ;
2023-08-09 12:47:58 +00:00
intel_drain_pasid_prq ( dev , pasid ) ;
2022-10-31 00:59:11 +00:00
}
2023-08-09 12:48:00 +00:00
static int intel_iommu_set_dev_pasid ( struct iommu_domain * domain ,
struct device * dev , ioasid_t pasid )
{
struct device_domain_info * info = dev_iommu_priv_get ( dev ) ;
struct dmar_domain * dmar_domain = to_dmar_domain ( domain ) ;
struct intel_iommu * iommu = info - > iommu ;
struct dev_pasid_info * dev_pasid ;
unsigned long flags ;
int ret ;
if ( ! pasid_supported ( iommu ) | | dev_is_real_dma_subdevice ( dev ) )
return - EOPNOTSUPP ;
2023-10-24 13:51:03 +00:00
if ( domain - > dirty_ops )
return - EINVAL ;
2023-08-09 12:48:00 +00:00
if ( context_copied ( iommu , info - > bus , info - > devfn ) )
return - EBUSY ;
ret = prepare_domain_attach_device ( domain , dev ) ;
if ( ret )
return ret ;
dev_pasid = kzalloc ( sizeof ( * dev_pasid ) , GFP_KERNEL ) ;
if ( ! dev_pasid )
return - ENOMEM ;
ret = domain_attach_iommu ( dmar_domain , iommu ) ;
if ( ret )
goto out_free ;
if ( domain_type_is_si ( dmar_domain ) )
2023-12-18 07:34:43 +00:00
ret = intel_pasid_setup_pass_through ( iommu , dev , pasid ) ;
2023-08-09 12:48:00 +00:00
else if ( dmar_domain - > use_first_level )
ret = domain_setup_first_level ( iommu , dmar_domain ,
dev , pasid ) ;
else
ret = intel_pasid_setup_second_level ( iommu , dmar_domain ,
dev , pasid ) ;
if ( ret )
goto out_detach_iommu ;
dev_pasid - > dev = dev ;
dev_pasid - > pasid = pasid ;
spin_lock_irqsave ( & dmar_domain - > lock , flags ) ;
list_add ( & dev_pasid - > link_domain , & dmar_domain - > dev_pasids ) ;
spin_unlock_irqrestore ( & dmar_domain - > lock , flags ) ;
2023-10-16 03:28:29 +00:00
if ( domain - > type & __IOMMU_DOMAIN_PAGING )
intel_iommu_debugfs_create_dev_pasid ( dev_pasid ) ;
2023-08-09 12:48:00 +00:00
return 0 ;
out_detach_iommu :
domain_detach_iommu ( dmar_domain , iommu ) ;
out_free :
kfree ( dev_pasid ) ;
return ret ;
2022-10-31 00:59:11 +00:00
}
2023-08-18 10:10:33 +00:00
static void * intel_iommu_hw_info ( struct device * dev , u32 * length , u32 * type )
{
struct device_domain_info * info = dev_iommu_priv_get ( dev ) ;
struct intel_iommu * iommu = info - > iommu ;
struct iommu_hw_info_vtd * vtd ;
vtd = kzalloc ( sizeof ( * vtd ) , GFP_KERNEL ) ;
if ( ! vtd )
return ERR_PTR ( - ENOMEM ) ;
2023-10-26 04:42:16 +00:00
vtd - > flags = IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17 ;
2023-08-18 10:10:33 +00:00
vtd - > cap_reg = iommu - > cap ;
vtd - > ecap_reg = iommu - > ecap ;
* length = sizeof ( * vtd ) ;
* type = IOMMU_HW_INFO_TYPE_INTEL_VTD ;
return vtd ;
}
2024-02-19 11:15:58 +00:00
/*
* Set dirty tracking for the device list of a domain . The caller must
* hold the domain - > lock when calling it .
*/
static int device_set_dirty_tracking ( struct list_head * devices , bool enable )
{
struct device_domain_info * info ;
int ret = 0 ;
list_for_each_entry ( info , devices , link ) {
ret = intel_pasid_setup_dirty_tracking ( info - > iommu , info - > dev ,
IOMMU_NO_PASID , enable ) ;
if ( ret )
break ;
}
return ret ;
}
2024-02-19 11:15:59 +00:00
static int parent_domain_set_dirty_tracking ( struct dmar_domain * domain ,
bool enable )
{
struct dmar_domain * s1_domain ;
unsigned long flags ;
int ret ;
spin_lock ( & domain - > s1_lock ) ;
list_for_each_entry ( s1_domain , & domain - > s1_domains , s2_link ) {
spin_lock_irqsave ( & s1_domain - > lock , flags ) ;
ret = device_set_dirty_tracking ( & s1_domain - > devices , enable ) ;
spin_unlock_irqrestore ( & s1_domain - > lock , flags ) ;
if ( ret )
goto err_unwind ;
}
spin_unlock ( & domain - > s1_lock ) ;
return 0 ;
err_unwind :
list_for_each_entry ( s1_domain , & domain - > s1_domains , s2_link ) {
spin_lock_irqsave ( & s1_domain - > lock , flags ) ;
device_set_dirty_tracking ( & s1_domain - > devices ,
domain - > dirty_tracking ) ;
spin_unlock_irqrestore ( & s1_domain - > lock , flags ) ;
}
spin_unlock ( & domain - > s1_lock ) ;
return ret ;
}
2023-10-24 13:51:03 +00:00
static int intel_iommu_set_dirty_tracking ( struct iommu_domain * domain ,
bool enable )
{
struct dmar_domain * dmar_domain = to_dmar_domain ( domain ) ;
int ret ;
spin_lock ( & dmar_domain - > lock ) ;
if ( dmar_domain - > dirty_tracking = = enable )
goto out_unlock ;
2024-02-19 11:15:58 +00:00
ret = device_set_dirty_tracking ( & dmar_domain - > devices , enable ) ;
if ( ret )
goto err_unwind ;
2023-10-24 13:51:03 +00:00
2024-02-19 11:15:59 +00:00
if ( dmar_domain - > nested_parent ) {
ret = parent_domain_set_dirty_tracking ( dmar_domain , enable ) ;
if ( ret )
goto err_unwind ;
}
2023-10-24 13:51:03 +00:00
dmar_domain - > dirty_tracking = enable ;
out_unlock :
spin_unlock ( & dmar_domain - > lock ) ;
return 0 ;
err_unwind :
2024-02-19 11:15:58 +00:00
device_set_dirty_tracking ( & dmar_domain - > devices ,
dmar_domain - > dirty_tracking ) ;
2023-10-24 13:51:03 +00:00
spin_unlock ( & dmar_domain - > lock ) ;
return ret ;
}
static int intel_iommu_read_and_clear_dirty ( struct iommu_domain * domain ,
unsigned long iova , size_t size ,
unsigned long flags ,
struct iommu_dirty_bitmap * dirty )
{
struct dmar_domain * dmar_domain = to_dmar_domain ( domain ) ;
unsigned long end = iova + size - 1 ;
unsigned long pgsize ;
/*
* IOMMUFD core calls into a dirty tracking disabled domain without an
* IOVA bitmap set in order to clean dirty bits in all PTEs that might
* have occurred when we stopped dirty tracking . This ensures that we
* never inherit dirtied bits from a previous cycle .
*/
if ( ! dmar_domain - > dirty_tracking & & dirty - > bitmap )
return - EINVAL ;
do {
struct dma_pte * pte ;
int lvl = 0 ;
pte = pfn_to_dma_pte ( dmar_domain , iova > > VTD_PAGE_SHIFT , & lvl ,
GFP_ATOMIC ) ;
pgsize = level_size ( lvl ) < < VTD_PAGE_SHIFT ;
if ( ! pte | | ! dma_pte_present ( pte ) ) {
iova + = pgsize ;
continue ;
}
if ( dma_sl_pte_test_and_clear_dirty ( pte , flags ) )
iommu_dirty_bitmap_record ( dirty , iova , pgsize ) ;
iova + = pgsize ;
} while ( iova < end ) ;
return 0 ;
}
2023-11-22 03:26:08 +00:00
static const struct iommu_dirty_ops intel_dirty_ops = {
2023-10-24 13:51:03 +00:00
. set_dirty_tracking = intel_iommu_set_dirty_tracking ,
. read_and_clear_dirty = intel_iommu_read_and_clear_dirty ,
} ;
2017-02-01 12:23:08 +00:00
const struct iommu_ops intel_iommu_ops = {
2023-09-27 23:47:33 +00:00
. blocked_domain = & blocking_domain ,
2024-03-05 12:21:18 +00:00
. release_domain = & blocking_domain ,
2017-01-19 20:57:53 +00:00
. capable = intel_iommu_capable ,
2023-08-18 10:10:33 +00:00
. hw_info = intel_iommu_hw_info ,
2017-01-19 20:57:53 +00:00
. domain_alloc = intel_iommu_domain_alloc ,
2023-09-28 07:15:28 +00:00
. domain_alloc_user = intel_iommu_domain_alloc_user ,
2020-04-29 13:36:54 +00:00
. probe_device = intel_iommu_probe_device ,
2020-05-06 01:59:47 +00:00
. probe_finalize = intel_iommu_probe_finalize ,
2020-04-29 13:36:54 +00:00
. release_device = intel_iommu_release_device ,
2017-01-19 20:57:53 +00:00
. get_resv_regions = intel_iommu_get_resv_regions ,
2019-12-26 23:56:18 +00:00
. device_group = intel_iommu_device_group ,
2019-03-25 01:30:30 +00:00
. dev_enable_feat = intel_iommu_dev_enable_feat ,
. dev_disable_feat = intel_iommu_dev_disable_feat ,
2019-05-25 05:41:32 +00:00
. is_attach_deferred = intel_iommu_is_attach_deferred ,
2020-04-29 13:36:42 +00:00
. def_domain_type = device_def_domain_type ,
2022-10-31 00:59:11 +00:00
. remove_dev_pasid = intel_iommu_remove_dev_pasid ,
2021-07-20 02:06:13 +00:00
. pgsize_bitmap = SZ_4K ,
2020-05-16 06:20:47 +00:00
# ifdef CONFIG_INTEL_IOMMU_SVM
2020-07-24 01:49:24 +00:00
. page_response = intel_svm_page_response ,
2020-05-16 06:20:47 +00:00
# endif
2022-02-16 02:52:49 +00:00
. default_domain_ops = & ( const struct iommu_domain_ops ) {
. attach_dev = intel_iommu_attach_device ,
2023-08-09 12:48:00 +00:00
. set_dev_pasid = intel_iommu_set_dev_pasid ,
2022-02-16 02:52:49 +00:00
. map_pages = intel_iommu_map_pages ,
. unmap_pages = intel_iommu_unmap_pages ,
. iotlb_sync_map = intel_iommu_iotlb_sync_map ,
. flush_iotlb_all = intel_flush_iotlb_all ,
. iotlb_sync = intel_iommu_tlb_sync ,
. iova_to_phys = intel_iommu_iova_to_phys ,
. free = intel_iommu_domain_free ,
2022-04-11 15:16:05 +00:00
. enforce_cache_coherency = intel_iommu_enforce_cache_coherency ,
2022-02-16 02:52:49 +00:00
}
2008-12-03 14:14:02 +00:00
} ;
2009-02-13 23:18:03 +00:00
2019-09-09 11:00:10 +00:00
static void quirk_iommu_igfx ( struct pci_dev * dev )
2013-01-20 22:50:13 +00:00
{
2020-06-22 23:13:42 +00:00
if ( risky_device ( dev ) )
return ;
2019-02-08 22:06:00 +00:00
pci_info ( dev , " Disabling IOMMU for graphics on this chipset \n " ) ;
2013-01-20 22:50:13 +00:00
dmar_map_gfx = 0 ;
}
2019-09-09 11:00:10 +00:00
/* G4x/GM45 integrated gfx dmar support is totally busted. */
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x2a40 , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x2e00 , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x2e10 , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x2e20 , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x2e30 , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x2e40 , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x2e90 , quirk_iommu_igfx ) ;
/* Broadwell igfx malfunctions with dmar */
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x1606 , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x160B , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x160E , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x1602 , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x160A , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x160D , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x1616 , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x161B , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x161E , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x1612 , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x161A , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x161D , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x1626 , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x162B , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x162E , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x1622 , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x162A , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x162D , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x1636 , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x163B , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x163E , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x1632 , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x163A , quirk_iommu_igfx ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x163D , quirk_iommu_igfx ) ;
2013-01-20 22:50:13 +00:00
2012-12-21 23:05:21 +00:00
static void quirk_iommu_rwbf ( struct pci_dev * dev )
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{
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if ( risky_device ( dev ) )
return ;
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/*
* Mobile 4 Series Chipset neglects to set RWBF capability ,
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* but needs it . Same seems to hold for the desktop versions .
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*/
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pci_info ( dev , " Forcing write-buffer flush capability \n " ) ;
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rwbf_quirk = 1 ;
}
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x2a40 , quirk_iommu_rwbf ) ;
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DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x2e00 , quirk_iommu_rwbf ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x2e10 , quirk_iommu_rwbf ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x2e20 , quirk_iommu_rwbf ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x2e30 , quirk_iommu_rwbf ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x2e40 , quirk_iommu_rwbf ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x2e90 , quirk_iommu_rwbf ) ;
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# define GGC 0x52
# define GGC_MEMORY_SIZE_MASK (0xf << 8)
# define GGC_MEMORY_SIZE_NONE (0x0 << 8)
# define GGC_MEMORY_SIZE_1M (0x1 << 8)
# define GGC_MEMORY_SIZE_2M (0x3 << 8)
# define GGC_MEMORY_VT_ENABLED (0x8 << 8)
# define GGC_MEMORY_SIZE_2M_VT (0x9 << 8)
# define GGC_MEMORY_SIZE_3M_VT (0xa << 8)
# define GGC_MEMORY_SIZE_4M_VT (0xb << 8)
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static void quirk_calpella_no_shadow_gtt ( struct pci_dev * dev )
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{
unsigned short ggc ;
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if ( risky_device ( dev ) )
return ;
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if ( pci_read_config_word ( dev , GGC , & ggc ) )
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return ;
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if ( ! ( ggc & GGC_MEMORY_VT_ENABLED ) ) {
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pci_info ( dev , " BIOS has allocated no shadow GTT; disabling IOMMU for graphics \n " ) ;
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dmar_map_gfx = 0 ;
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} else if ( dmar_map_gfx ) {
/* we have to ensure the gfx device is idle before we flush */
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pci_info ( dev , " Disabling batched IOTLB flush on Ironlake \n " ) ;
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iommu_set_dma_strict ( ) ;
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}
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}
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x0040 , quirk_calpella_no_shadow_gtt ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x0044 , quirk_calpella_no_shadow_gtt ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x0062 , quirk_calpella_no_shadow_gtt ) ;
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , 0x006a , quirk_calpella_no_shadow_gtt ) ;
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static void quirk_igfx_skip_te_disable ( struct pci_dev * dev )
{
unsigned short ver ;
if ( ! IS_GFX_DEVICE ( dev ) )
return ;
ver = ( dev - > device > > 8 ) & 0xff ;
if ( ver ! = 0x45 & & ver ! = 0x46 & & ver ! = 0x4c & &
ver ! = 0x4e & & ver ! = 0x8a & & ver ! = 0x98 & &
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ver ! = 0x9a & & ver ! = 0xa7 & & ver ! = 0x7d )
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return ;
if ( risky_device ( dev ) )
return ;
pci_info ( dev , " Skip IOMMU disabling for graphics \n " ) ;
iommu_skip_te_disable = 1 ;
}
DECLARE_PCI_FIXUP_HEADER ( PCI_VENDOR_ID_INTEL , PCI_ANY_ID , quirk_igfx_skip_te_disable ) ;
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/* On Tylersburg chipsets, some BIOSes have been known to enable the
ISOCH DMAR unit for the Azalia sound device , but not give it any
TLB entries , which causes it to deadlock . Check for that . We do
this in a function called from init_dmars ( ) , instead of in a PCI
quirk , because we don ' t want to print the obnoxious " BIOS broken "
message if VT - d is actually disabled .
*/
static void __init check_tylersburg_isoch ( void )
{
struct pci_dev * pdev ;
uint32_t vtisochctrl ;
/* If there's no Azalia in the system anyway, forget it. */
pdev = pci_get_device ( PCI_VENDOR_ID_INTEL , 0x3a3e , NULL ) ;
if ( ! pdev )
return ;
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if ( risky_device ( pdev ) ) {
pci_dev_put ( pdev ) ;
return ;
}
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pci_dev_put ( pdev ) ;
/* System Management Registers. Might be hidden, in which case
we can ' t do the sanity check . But that ' s OK , because the
known - broken BIOSes _don ' t_ actually hide it , so far . */
pdev = pci_get_device ( PCI_VENDOR_ID_INTEL , 0x342e , NULL ) ;
if ( ! pdev )
return ;
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if ( risky_device ( pdev ) ) {
pci_dev_put ( pdev ) ;
return ;
}
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if ( pci_read_config_dword ( pdev , 0x188 , & vtisochctrl ) ) {
pci_dev_put ( pdev ) ;
return ;
}
pci_dev_put ( pdev ) ;
/* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
if ( vtisochctrl & 1 )
return ;
/* Drop all bits other than the number of TLB entries */
vtisochctrl & = 0x1c ;
/* If we have the recommended number of TLB entries (16), fine. */
if ( vtisochctrl = = 0x10 )
return ;
/* Zero TLB entries? You get to ride the short bus to school. */
if ( ! vtisochctrl ) {
WARN ( 1 , " Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space. \n "
" BIOS vendor: %s; Ver: %s; Product Version: %s \n " ,
dmi_get_system_info ( DMI_BIOS_VENDOR ) ,
dmi_get_system_info ( DMI_BIOS_VERSION ) ,
dmi_get_system_info ( DMI_PRODUCT_VERSION ) ) ;
iommu_identity_mapping | = IDENTMAP_AZALIA ;
return ;
}
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pr_warn ( " Recommended TLB entries for ISOCH unit is 16; your BIOS set %d \n " ,
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vtisochctrl ) ;
}
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/*
* Here we deal with a device TLB defect where device may inadvertently issue ATS
* invalidation completion before posted writes initiated with translated address
* that utilized translations matching the invalidation address range , violating
* the invalidation completion ordering .
* Therefore , any use cases that cannot guarantee DMA is stopped before unmap is
* vulnerable to this defect . In other words , any dTLB invalidation initiated not
* under the control of the trusted / privileged host device driver must use this
* quirk .
* Device TLBs are invalidated under the following six conditions :
* 1. Device driver does DMA API unmap IOVA
* 2. Device driver unbind a PASID from a process , sva_unbind_device ( )
* 3. PASID is torn down , after PASID cache is flushed . e . g . process
* exit_mmap ( ) due to crash
* 4. Under SVA usage , called by mmu_notifier . invalidate_range ( ) where
* VM has to free pages that were unmapped
* 5. Userspace driver unmaps a DMA buffer
* 6. Cache invalidation in vSVA usage ( upcoming )
*
* For # 1 and # 2 , device drivers are responsible for stopping DMA traffic
* before unmap / unbind . For # 3 , iommu driver gets mmu_notifier to
* invalidate TLB the same way as normal user unmap which will use this quirk .
* The dTLB invalidation after PASID cache flush does not need this quirk .
*
* As a reminder , # 6 will * NEED * this quirk as we enable nested translation .
*/
void quirk_extra_dev_tlb_flush ( struct device_domain_info * info ,
unsigned long address , unsigned long mask ,
u32 pasid , u16 qdep )
{
u16 sid ;
if ( likely ( ! info - > dtlb_extra_inval ) )
return ;
sid = PCI_DEVID ( info - > bus , info - > devfn ) ;
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if ( pasid = = IOMMU_NO_PASID ) {
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qi_flush_dev_iotlb ( info - > iommu , sid , info - > pfsid ,
qdep , address , mask ) ;
} else {
qi_flush_dev_iotlb_pasid ( info - > iommu , sid , info - > pfsid ,
pasid , qdep , address , mask ) ;
}
}
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# define ecmd_get_status_code(res) (((res) & 0xff) >> 1)
/*
* Function to submit a command to the enhanced command interface . The
* valid enhanced command descriptions are defined in Table 47 of the
* VT - d spec . The VT - d hardware implementation may support some but not
* all commands , which can be determined by checking the Enhanced
* Command Capability Register .
*
* Return values :
* - 0 : Command successful without any error ;
* - Negative : software error value ;
* - Nonzero positive : failure status code defined in Table 48.
*/
int ecmd_submit_sync ( struct intel_iommu * iommu , u8 ecmd , u64 oa , u64 ob )
{
unsigned long flags ;
u64 res ;
int ret ;
if ( ! cap_ecmds ( iommu - > cap ) )
return - ENODEV ;
raw_spin_lock_irqsave ( & iommu - > register_lock , flags ) ;
res = dmar_readq ( iommu - > reg + DMAR_ECRSP_REG ) ;
if ( res & DMA_ECMD_ECRSP_IP ) {
ret = - EBUSY ;
goto err ;
}
/*
* Unconditionally write the operand B , because
* - There is no side effect if an ecmd doesn ' t require an
* operand B , but we set the register to some value .
* - It ' s not invoked in any critical path . The extra MMIO
* write doesn ' t bring any performance concerns .
*/
dmar_writeq ( iommu - > reg + DMAR_ECEO_REG , ob ) ;
dmar_writeq ( iommu - > reg + DMAR_ECMD_REG , ecmd | ( oa < < DMA_ECMD_OA_SHIFT ) ) ;
IOMMU_WAIT_OP ( iommu , DMAR_ECRSP_REG , dmar_readq ,
! ( res & DMA_ECMD_ECRSP_IP ) , res ) ;
if ( res & DMA_ECMD_ECRSP_IP ) {
ret = - ETIMEDOUT ;
goto err ;
}
ret = ecmd_get_status_code ( res ) ;
err :
raw_spin_unlock_irqrestore ( & iommu - > register_lock , flags ) ;
return ret ;
}