arm64: dts: ti: Add initial support for J721S2 SoC
The J721S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive ADAS applications and
industrial applications requiring AI at the network edge. This SoC extends
the Jacinto 7 family of SoCs with focus on lowering system costs and power
while providing interfaces, memory architecture and compute performance for
single and multi-sensor applications.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep capable
dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x
floating point Vector DSP.
* 3D GPU: Automotive grade IMG BXS-4-64
* Vision Processing Accelerator (VPAC) with image signal processor and
Depth and Motion Processing Accelerator (DMPAC)
* Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface.
* Two Ethernet ports with RGMII support.
* Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems,
* Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller,
QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL
management.
* Chips and Media Wave521CL H.264/H.265 encode/decode engine
See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021)
for further details: http://www.ti.com/lit/pdf/spruj28
Introduce basic support for the J721S2 SoC.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20211207080904.14324-4-a-govindraju@ti.com
2021-12-07 08:09:02 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals
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*
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* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_mcu_wakeup {
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sms: system-controller@44083000 {
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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mboxes= <&secure_proxy_main 11>,
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<&secure_proxy_main 13>;
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reg-names = "debug_messages";
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reg = <0x00 0x44083000 0x00 0x1000>;
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k3_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <2>;
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};
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k3_clks: clock-controller {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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k3_reset: reset-controller {
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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chipid@43000014 {
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compatible = "ti,am654-chipid";
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reg = <0x00 0x43000014 0x00 0x4>;
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};
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mcu_ram: sram@41c00000 {
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compatible = "mmio-sram";
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reg = <0x00 0x41c00000 0x00 0x100000>;
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ranges = <0x00 0x00 0x41c00000 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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wkup_pmx0: pinctrl@4301c000 {
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compatible = "pinctrl-single";
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/* Proxy 0 addressing */
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reg = <0x00 0x4301c000 0x00 0x178>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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wkup_gpio_intr: interrupt-controller@42200000 {
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compatible = "ti,sci-intr";
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reg = <0x00 0x42200000 0x00 0x400>;
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ti,intr-trigger-type = <1>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <1>;
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ti,sci = <&sms>;
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ti,sci-dev-id = <125>;
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ti,interrupt-ranges = <16 928 16>;
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};
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mcu_conf: syscon@40f00000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x0 0x40f00000 0x0 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x40f00000 0x20000>;
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phy_gmii_sel: phy@4040 {
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compatible = "ti,am654-phy-gmii-sel";
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reg = <0x4040 0x4>;
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#phy-cells = <1>;
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};
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};
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wkup_uart0: serial@42300000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x42300000 0x00 0x200>;
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interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
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current-speed = <115200>;
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clocks = <&k3_clks 359 3>;
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clock-names = "fclk";
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power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
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};
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mcu_uart0: serial@40a00000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x40a00000 0x00 0x200>;
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interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
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current-speed = <115200>;
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clocks = <&k3_clks 149 3>;
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clock-names = "fclk";
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power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
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};
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wkup_gpio0: gpio@42110000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x00 0x42110000 0x00 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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2022-02-03 13:26:47 +00:00
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interrupt-parent = <&wkup_gpio_intr>;
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arm64: dts: ti: Add initial support for J721S2 SoC
The J721S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive ADAS applications and
industrial applications requiring AI at the network edge. This SoC extends
the Jacinto 7 family of SoCs with focus on lowering system costs and power
while providing interfaces, memory architecture and compute performance for
single and multi-sensor applications.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep capable
dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x
floating point Vector DSP.
* 3D GPU: Automotive grade IMG BXS-4-64
* Vision Processing Accelerator (VPAC) with image signal processor and
Depth and Motion Processing Accelerator (DMPAC)
* Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface.
* Two Ethernet ports with RGMII support.
* Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems,
* Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller,
QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL
management.
* Chips and Media Wave521CL H.264/H.265 encode/decode engine
See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021)
for further details: http://www.ti.com/lit/pdf/spruj28
Introduce basic support for the J721S2 SoC.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20211207080904.14324-4-a-govindraju@ti.com
2021-12-07 08:09:02 +00:00
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interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <89>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 115 0>;
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clock-names = "gpio";
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};
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wkup_gpio1: gpio@42100000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x00 0x42100000 0x00 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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2022-02-03 13:26:47 +00:00
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interrupt-parent = <&wkup_gpio_intr>;
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arm64: dts: ti: Add initial support for J721S2 SoC
The J721S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive ADAS applications and
industrial applications requiring AI at the network edge. This SoC extends
the Jacinto 7 family of SoCs with focus on lowering system costs and power
while providing interfaces, memory architecture and compute performance for
single and multi-sensor applications.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep capable
dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x
floating point Vector DSP.
* 3D GPU: Automotive grade IMG BXS-4-64
* Vision Processing Accelerator (VPAC) with image signal processor and
Depth and Motion Processing Accelerator (DMPAC)
* Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface.
* Two Ethernet ports with RGMII support.
* Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems,
* Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller,
QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL
management.
* Chips and Media Wave521CL H.264/H.265 encode/decode engine
See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021)
for further details: http://www.ti.com/lit/pdf/spruj28
Introduce basic support for the J721S2 SoC.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20211207080904.14324-4-a-govindraju@ti.com
2021-12-07 08:09:02 +00:00
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interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <89>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 116 0>;
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clock-names = "gpio";
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};
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wkup_i2c0: i2c@42120000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x00 0x42120000 0x00 0x100>;
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interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&k3_clks 223 1>;
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clock-names = "fck";
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power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
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};
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mcu_i2c0: i2c@40b00000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x00 0x40b00000 0x00 0x100>;
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interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&k3_clks 221 1>;
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clock-names = "fck";
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power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
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};
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mcu_i2c1: i2c@40b10000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x00 0x40b10000 0x00 0x100>;
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interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&k3_clks 222 1>;
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clock-names = "fck";
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power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
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};
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mcu_mcan0: can@40528000 {
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compatible = "bosch,m_can";
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reg = <0x00 0x40528000 0x00 0x200>,
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<0x00 0x40500000 0x00 0x8000>;
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reg-names = "m_can", "message_ram";
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power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 207 0>, <&k3_clks 207 1>;
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clock-names = "hclk", "cclk";
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interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
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};
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mcu_mcan1: can@40568000 {
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compatible = "bosch,m_can";
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reg = <0x00 0x40568000 0x00 0x200>,
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<0x00 0x40540000 0x00 0x8000>;
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reg-names = "m_can", "message_ram";
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power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 208 0>, <&k3_clks 208 1>;
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clock-names = "hclk", "cclk";
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interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
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};
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mcu_navss: bus@28380000{
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
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dma-coherent;
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dma-ranges;
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ti,sci-dev-id = <267>;
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mcu_ringacc: ringacc@2b800000 {
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compatible = "ti,am654-navss-ringacc";
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reg = <0x0 0x2b800000 0x0 0x400000>,
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<0x0 0x2b000000 0x0 0x400000>,
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<0x0 0x28590000 0x0 0x100>,
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<0x0 0x2a500000 0x0 0x40000>;
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reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
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ti,num-rings = <286>;
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ti,sci-rm-range-gp-rings = <0x1>;
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ti,sci = <&sms>;
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ti,sci-dev-id = <272>;
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msi-parent = <&main_udmass_inta>;
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};
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mcu_udmap: dma-controller@285c0000 {
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compatible = "ti,j721e-navss-mcu-udmap";
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reg = <0x0 0x285c0000 0x0 0x100>,
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<0x0 0x2a800000 0x0 0x40000>,
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<0x0 0x2aa00000 0x0 0x40000>;
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reg-names = "gcfg", "rchanrt", "tchanrt";
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msi-parent = <&main_udmass_inta>;
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|
|
#dma-cells = <1>;
|
|
|
|
|
|
|
|
|
|
ti,sci = <&sms>;
|
|
|
|
|
ti,sci-dev-id = <273>;
|
|
|
|
|
ti,ringacc = <&mcu_ringacc>;
|
|
|
|
|
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
|
|
|
|
|
<0x0f>; /* TX_HCHAN */
|
|
|
|
|
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
|
|
|
|
|
<0x0b>; /* RX_HCHAN */
|
|
|
|
|
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcu_cpsw: ethernet@46000000 {
|
|
|
|
|
compatible = "ti,j721e-cpsw-nuss";
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
reg = <0x0 0x46000000 0x0 0x200000>;
|
|
|
|
|
reg-names = "cpsw_nuss";
|
|
|
|
|
ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
|
|
|
|
|
dma-coherent;
|
|
|
|
|
clocks = <&k3_clks 29 28>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
|
|
|
|
|
dmas = <&mcu_udmap 0xf000>,
|
|
|
|
|
<&mcu_udmap 0xf001>,
|
|
|
|
|
<&mcu_udmap 0xf002>,
|
|
|
|
|
<&mcu_udmap 0xf003>,
|
|
|
|
|
<&mcu_udmap 0xf004>,
|
|
|
|
|
<&mcu_udmap 0xf005>,
|
|
|
|
|
<&mcu_udmap 0xf006>,
|
|
|
|
|
<&mcu_udmap 0xf007>,
|
|
|
|
|
<&mcu_udmap 0x7000>;
|
|
|
|
|
dma-names = "tx0", "tx1", "tx2", "tx3",
|
|
|
|
|
"tx4", "tx5", "tx6", "tx7",
|
|
|
|
|
"rx";
|
|
|
|
|
|
|
|
|
|
ethernet-ports {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
cpsw_port1: port@1 {
|
|
|
|
|
reg = <1>;
|
|
|
|
|
ti,mac-only;
|
|
|
|
|
label = "port1";
|
|
|
|
|
ti,syscon-efuse = <&mcu_conf 0x200>;
|
|
|
|
|
phys = <&phy_gmii_sel 1>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
davinci_mdio: mdio@f00 {
|
|
|
|
|
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
|
|
|
|
reg = <0x0 0xf00 0x0 0x100>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clocks = <&k3_clks 29 28>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
bus_freq = <1000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpts@3d000 {
|
|
|
|
|
compatible = "ti,am65-cpts";
|
|
|
|
|
reg = <0x0 0x3d000 0x0 0x400>;
|
|
|
|
|
clocks = <&k3_clks 29 3>;
|
|
|
|
|
clock-names = "cpts";
|
|
|
|
|
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "cpts";
|
|
|
|
|
ti,cpts-ext-ts-inputs = <4>;
|
|
|
|
|
ti,cpts-periodic-outputs = <2>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|