303 lines
7.9 KiB
Plaintext
303 lines
7.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for J721S2 SoC Family MCU/WAKEUP Domain peripherals
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*
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* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_mcu_wakeup {
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sms: system-controller@44083000 {
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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mboxes= <&secure_proxy_main 11>,
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<&secure_proxy_main 13>;
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reg-names = "debug_messages";
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reg = <0x00 0x44083000 0x00 0x1000>;
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k3_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <2>;
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};
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k3_clks: clock-controller {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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k3_reset: reset-controller {
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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chipid@43000014 {
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compatible = "ti,am654-chipid";
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reg = <0x00 0x43000014 0x00 0x4>;
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};
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mcu_ram: sram@41c00000 {
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compatible = "mmio-sram";
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reg = <0x00 0x41c00000 0x00 0x100000>;
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ranges = <0x00 0x00 0x41c00000 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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wkup_pmx0: pinctrl@4301c000 {
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compatible = "pinctrl-single";
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/* Proxy 0 addressing */
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reg = <0x00 0x4301c000 0x00 0x178>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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wkup_gpio_intr: interrupt-controller@42200000 {
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compatible = "ti,sci-intr";
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reg = <0x00 0x42200000 0x00 0x400>;
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ti,intr-trigger-type = <1>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <1>;
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ti,sci = <&sms>;
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ti,sci-dev-id = <125>;
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ti,interrupt-ranges = <16 928 16>;
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};
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mcu_conf: syscon@40f00000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x0 0x40f00000 0x0 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x40f00000 0x20000>;
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phy_gmii_sel: phy@4040 {
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compatible = "ti,am654-phy-gmii-sel";
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reg = <0x4040 0x4>;
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#phy-cells = <1>;
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};
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};
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wkup_uart0: serial@42300000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x42300000 0x00 0x200>;
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interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
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current-speed = <115200>;
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clocks = <&k3_clks 359 3>;
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clock-names = "fclk";
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power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
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};
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mcu_uart0: serial@40a00000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x40a00000 0x00 0x200>;
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interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
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current-speed = <115200>;
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clocks = <&k3_clks 149 3>;
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clock-names = "fclk";
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power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
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};
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wkup_gpio0: gpio@42110000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x00 0x42110000 0x00 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&wkup_gpio_intr>;
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interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <89>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 115 0>;
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clock-names = "gpio";
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};
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wkup_gpio1: gpio@42100000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x00 0x42100000 0x00 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&wkup_gpio_intr>;
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interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <89>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 116 0>;
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clock-names = "gpio";
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};
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wkup_i2c0: i2c@42120000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x00 0x42120000 0x00 0x100>;
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interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&k3_clks 223 1>;
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clock-names = "fck";
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power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
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};
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mcu_i2c0: i2c@40b00000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x00 0x40b00000 0x00 0x100>;
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interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&k3_clks 221 1>;
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clock-names = "fck";
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power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
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};
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mcu_i2c1: i2c@40b10000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x00 0x40b10000 0x00 0x100>;
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interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&k3_clks 222 1>;
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clock-names = "fck";
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power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
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};
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mcu_mcan0: can@40528000 {
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compatible = "bosch,m_can";
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reg = <0x00 0x40528000 0x00 0x200>,
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<0x00 0x40500000 0x00 0x8000>;
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reg-names = "m_can", "message_ram";
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power-domains = <&k3_pds 207 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 207 0>, <&k3_clks 207 1>;
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clock-names = "hclk", "cclk";
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interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
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};
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mcu_mcan1: can@40568000 {
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compatible = "bosch,m_can";
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reg = <0x00 0x40568000 0x00 0x200>,
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<0x00 0x40540000 0x00 0x8000>;
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reg-names = "m_can", "message_ram";
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power-domains = <&k3_pds 208 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 208 0>, <&k3_clks 208 1>;
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clock-names = "hclk", "cclk";
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interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
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};
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mcu_navss: bus@28380000{
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
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dma-coherent;
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dma-ranges;
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ti,sci-dev-id = <267>;
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mcu_ringacc: ringacc@2b800000 {
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compatible = "ti,am654-navss-ringacc";
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reg = <0x0 0x2b800000 0x0 0x400000>,
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<0x0 0x2b000000 0x0 0x400000>,
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<0x0 0x28590000 0x0 0x100>,
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<0x0 0x2a500000 0x0 0x40000>;
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reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
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ti,num-rings = <286>;
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ti,sci-rm-range-gp-rings = <0x1>;
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ti,sci = <&sms>;
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ti,sci-dev-id = <272>;
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msi-parent = <&main_udmass_inta>;
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};
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mcu_udmap: dma-controller@285c0000 {
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compatible = "ti,j721e-navss-mcu-udmap";
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reg = <0x0 0x285c0000 0x0 0x100>,
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<0x0 0x2a800000 0x0 0x40000>,
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<0x0 0x2aa00000 0x0 0x40000>;
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reg-names = "gcfg", "rchanrt", "tchanrt";
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msi-parent = <&main_udmass_inta>;
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#dma-cells = <1>;
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ti,sci = <&sms>;
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ti,sci-dev-id = <273>;
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ti,ringacc = <&mcu_ringacc>;
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ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
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<0x0f>; /* TX_HCHAN */
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ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
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<0x0b>; /* RX_HCHAN */
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ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
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};
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};
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mcu_cpsw: ethernet@46000000 {
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compatible = "ti,j721e-cpsw-nuss";
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#address-cells = <2>;
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#size-cells = <2>;
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reg = <0x0 0x46000000 0x0 0x200000>;
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reg-names = "cpsw_nuss";
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ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
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dma-coherent;
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clocks = <&k3_clks 29 28>;
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clock-names = "fck";
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power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
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dmas = <&mcu_udmap 0xf000>,
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<&mcu_udmap 0xf001>,
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<&mcu_udmap 0xf002>,
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<&mcu_udmap 0xf003>,
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<&mcu_udmap 0xf004>,
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<&mcu_udmap 0xf005>,
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<&mcu_udmap 0xf006>,
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<&mcu_udmap 0xf007>,
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<&mcu_udmap 0x7000>;
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dma-names = "tx0", "tx1", "tx2", "tx3",
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"tx4", "tx5", "tx6", "tx7",
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"rx";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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cpsw_port1: port@1 {
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reg = <1>;
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ti,mac-only;
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label = "port1";
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ti,syscon-efuse = <&mcu_conf 0x200>;
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phys = <&phy_gmii_sel 1>;
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};
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};
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davinci_mdio: mdio@f00 {
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compatible = "ti,cpsw-mdio","ti,davinci_mdio";
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reg = <0x0 0xf00 0x0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&k3_clks 29 28>;
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clock-names = "fck";
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bus_freq = <1000000>;
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};
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cpts@3d000 {
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compatible = "ti,am65-cpts";
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reg = <0x0 0x3d000 0x0 0x400>;
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clocks = <&k3_clks 29 3>;
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clock-names = "cpts";
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interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cpts";
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ti,cpts-ext-ts-inputs = <4>;
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ti,cpts-periodic-outputs = <2>;
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};
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};
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};
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