2009-04-30 07:02:49 +00:00
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/*
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* SuperH Timer Support - MTU2
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*
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* Copyright (C) 2009 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/irq.h>
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#include <linux/err.h>
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#include <linux/clockchips.h>
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2009-05-03 08:57:17 +00:00
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#include <linux/sh_timer.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2011-07-03 17:36:22 +00:00
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#include <linux/module.h>
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2012-03-13 21:40:14 +00:00
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#include <linux/pm_domain.h>
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2012-08-13 12:00:16 +00:00
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#include <linux/pm_runtime.h>
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2009-04-30 07:02:49 +00:00
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2014-03-04 12:04:48 +00:00
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struct sh_mtu2_device;
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2014-03-04 11:58:30 +00:00
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struct sh_mtu2_channel {
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2014-03-04 12:04:48 +00:00
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struct sh_mtu2_device *mtu;
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2014-03-04 13:17:26 +00:00
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unsigned int index;
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2014-03-04 13:04:24 +00:00
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void __iomem *base;
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2014-03-04 11:58:30 +00:00
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int irq;
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2014-03-04 13:04:24 +00:00
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2014-03-04 11:58:30 +00:00
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struct clock_event_device ced;
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};
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2014-03-04 12:04:48 +00:00
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struct sh_mtu2_device {
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2014-03-04 11:58:30 +00:00
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struct platform_device *pdev;
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2009-04-30 07:02:49 +00:00
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void __iomem *mapbase;
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struct clk *clk;
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2014-03-04 11:58:30 +00:00
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2014-03-04 13:23:00 +00:00
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struct sh_mtu2_channel *channels;
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unsigned int num_channels;
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2014-03-04 17:05:45 +00:00
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bool legacy;
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bool has_clockevent;
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2009-04-30 07:02:49 +00:00
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};
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2012-05-25 04:38:54 +00:00
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static DEFINE_RAW_SPINLOCK(sh_mtu2_lock);
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2009-04-30 07:02:49 +00:00
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#define TSTR -1 /* shared register */
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#define TCR 0 /* channel register */
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#define TMDR 1 /* channel register */
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#define TIOR 2 /* channel register */
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#define TIER 3 /* channel register */
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#define TSR 4 /* channel register */
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#define TCNT 5 /* channel register */
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#define TGR 6 /* channel register */
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2014-03-04 14:16:25 +00:00
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#define TCR_CCLR_NONE (0 << 5)
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#define TCR_CCLR_TGRA (1 << 5)
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#define TCR_CCLR_TGRB (2 << 5)
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#define TCR_CCLR_SYNC (3 << 5)
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#define TCR_CCLR_TGRC (5 << 5)
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#define TCR_CCLR_TGRD (6 << 5)
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#define TCR_CCLR_MASK (7 << 5)
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#define TCR_CKEG_RISING (0 << 3)
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#define TCR_CKEG_FALLING (1 << 3)
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#define TCR_CKEG_BOTH (2 << 3)
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#define TCR_CKEG_MASK (3 << 3)
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/* Values 4 to 7 are channel-dependent */
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#define TCR_TPSC_P1 (0 << 0)
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#define TCR_TPSC_P4 (1 << 0)
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#define TCR_TPSC_P16 (2 << 0)
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#define TCR_TPSC_P64 (3 << 0)
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#define TCR_TPSC_CH0_TCLKA (4 << 0)
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#define TCR_TPSC_CH0_TCLKB (5 << 0)
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#define TCR_TPSC_CH0_TCLKC (6 << 0)
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#define TCR_TPSC_CH0_TCLKD (7 << 0)
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#define TCR_TPSC_CH1_TCLKA (4 << 0)
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#define TCR_TPSC_CH1_TCLKB (5 << 0)
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#define TCR_TPSC_CH1_P256 (6 << 0)
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#define TCR_TPSC_CH1_TCNT2 (7 << 0)
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#define TCR_TPSC_CH2_TCLKA (4 << 0)
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#define TCR_TPSC_CH2_TCLKB (5 << 0)
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#define TCR_TPSC_CH2_TCLKC (6 << 0)
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#define TCR_TPSC_CH2_P1024 (7 << 0)
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#define TCR_TPSC_CH34_P256 (4 << 0)
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#define TCR_TPSC_CH34_P1024 (5 << 0)
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#define TCR_TPSC_CH34_TCLKA (6 << 0)
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#define TCR_TPSC_CH34_TCLKB (7 << 0)
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#define TCR_TPSC_MASK (7 << 0)
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#define TMDR_BFE (1 << 6)
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#define TMDR_BFB (1 << 5)
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#define TMDR_BFA (1 << 4)
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#define TMDR_MD_NORMAL (0 << 0)
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#define TMDR_MD_PWM_1 (2 << 0)
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#define TMDR_MD_PWM_2 (3 << 0)
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#define TMDR_MD_PHASE_1 (4 << 0)
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#define TMDR_MD_PHASE_2 (5 << 0)
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#define TMDR_MD_PHASE_3 (6 << 0)
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#define TMDR_MD_PHASE_4 (7 << 0)
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#define TMDR_MD_PWM_SYNC (8 << 0)
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#define TMDR_MD_PWM_COMP_CREST (13 << 0)
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#define TMDR_MD_PWM_COMP_TROUGH (14 << 0)
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#define TMDR_MD_PWM_COMP_BOTH (15 << 0)
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#define TMDR_MD_MASK (15 << 0)
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#define TIOC_IOCH(n) ((n) << 4)
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#define TIOC_IOCL(n) ((n) << 0)
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#define TIOR_OC_RETAIN (0 << 0)
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#define TIOR_OC_0_CLEAR (1 << 0)
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#define TIOR_OC_0_SET (2 << 0)
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#define TIOR_OC_0_TOGGLE (3 << 0)
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#define TIOR_OC_1_CLEAR (5 << 0)
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#define TIOR_OC_1_SET (6 << 0)
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#define TIOR_OC_1_TOGGLE (7 << 0)
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#define TIOR_IC_RISING (8 << 0)
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#define TIOR_IC_FALLING (9 << 0)
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#define TIOR_IC_BOTH (10 << 0)
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#define TIOR_IC_TCNT (12 << 0)
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#define TIOR_MASK (15 << 0)
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#define TIER_TTGE (1 << 7)
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#define TIER_TTGE2 (1 << 6)
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#define TIER_TCIEU (1 << 5)
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#define TIER_TCIEV (1 << 4)
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#define TIER_TGIED (1 << 3)
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#define TIER_TGIEC (1 << 2)
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#define TIER_TGIEB (1 << 1)
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#define TIER_TGIEA (1 << 0)
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#define TSR_TCFD (1 << 7)
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#define TSR_TCFU (1 << 5)
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#define TSR_TCFV (1 << 4)
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#define TSR_TGFD (1 << 3)
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#define TSR_TGFC (1 << 2)
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#define TSR_TGFB (1 << 1)
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#define TSR_TGFA (1 << 0)
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2009-04-30 07:02:49 +00:00
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static unsigned long mtu2_reg_offs[] = {
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[TCR] = 0,
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[TMDR] = 1,
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[TIOR] = 2,
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[TIER] = 4,
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[TSR] = 5,
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[TCNT] = 6,
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[TGR] = 8,
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};
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2014-03-04 11:58:30 +00:00
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static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr)
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2009-04-30 07:02:49 +00:00
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{
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unsigned long offs;
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2014-03-04 17:05:45 +00:00
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if (reg_nr == TSTR) {
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if (ch->mtu->legacy)
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return ioread8(ch->mtu->mapbase);
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else
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return ioread8(ch->mtu->mapbase + 0x280);
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}
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2009-04-30 07:02:49 +00:00
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offs = mtu2_reg_offs[reg_nr];
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if ((reg_nr == TCNT) || (reg_nr == TGR))
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2014-03-04 13:04:24 +00:00
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return ioread16(ch->base + offs);
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2009-04-30 07:02:49 +00:00
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else
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2014-03-04 13:04:24 +00:00
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return ioread8(ch->base + offs);
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2009-04-30 07:02:49 +00:00
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}
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2014-03-04 11:58:30 +00:00
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static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr,
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2009-04-30 07:02:49 +00:00
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unsigned long value)
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{
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unsigned long offs;
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if (reg_nr == TSTR) {
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2014-03-04 17:05:45 +00:00
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if (ch->mtu->legacy)
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return iowrite8(value, ch->mtu->mapbase);
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else
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return iowrite8(value, ch->mtu->mapbase + 0x280);
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2009-04-30 07:02:49 +00:00
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}
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offs = mtu2_reg_offs[reg_nr];
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if ((reg_nr == TCNT) || (reg_nr == TGR))
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2014-03-04 13:04:24 +00:00
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iowrite16(value, ch->base + offs);
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2009-04-30 07:02:49 +00:00
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else
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2014-03-04 13:04:24 +00:00
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iowrite8(value, ch->base + offs);
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2009-04-30 07:02:49 +00:00
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}
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2014-03-04 11:58:30 +00:00
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static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start)
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2009-04-30 07:02:49 +00:00
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{
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unsigned long flags, value;
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/* start stop register shared by multiple timer channels */
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2012-05-25 04:38:54 +00:00
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raw_spin_lock_irqsave(&sh_mtu2_lock, flags);
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2014-03-04 11:58:30 +00:00
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value = sh_mtu2_read(ch, TSTR);
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2009-04-30 07:02:49 +00:00
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if (start)
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2014-03-04 13:17:26 +00:00
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value |= 1 << ch->index;
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2009-04-30 07:02:49 +00:00
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else
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2014-03-04 13:17:26 +00:00
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value &= ~(1 << ch->index);
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2009-04-30 07:02:49 +00:00
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2014-03-04 11:58:30 +00:00
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sh_mtu2_write(ch, TSTR, value);
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2012-05-25 04:38:54 +00:00
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raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags);
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2009-04-30 07:02:49 +00:00
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}
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2014-03-04 11:58:30 +00:00
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static int sh_mtu2_enable(struct sh_mtu2_channel *ch)
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2009-04-30 07:02:49 +00:00
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{
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2014-03-04 11:59:54 +00:00
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unsigned long periodic;
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unsigned long rate;
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2009-04-30 07:02:49 +00:00
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int ret;
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2014-03-04 11:58:30 +00:00
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pm_runtime_get_sync(&ch->mtu->pdev->dev);
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dev_pm_syscore_device(&ch->mtu->pdev->dev, true);
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2012-08-13 12:00:16 +00:00
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2009-04-30 07:02:49 +00:00
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/* enable clock */
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2014-03-04 11:58:30 +00:00
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ret = clk_enable(ch->mtu->clk);
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2009-04-30 07:02:49 +00:00
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if (ret) {
|
2014-03-04 13:17:26 +00:00
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dev_err(&ch->mtu->pdev->dev, "ch%u: cannot enable clock\n",
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ch->index);
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2009-04-30 07:02:49 +00:00
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return ret;
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}
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/* make sure channel is disabled */
|
2014-03-04 11:58:30 +00:00
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sh_mtu2_start_stop_ch(ch, 0);
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2009-04-30 07:02:49 +00:00
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2014-03-04 11:58:30 +00:00
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rate = clk_get_rate(ch->mtu->clk) / 64;
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2014-03-04 11:59:54 +00:00
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periodic = (rate + HZ/2) / HZ;
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2009-04-30 07:02:49 +00:00
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2014-03-04 14:16:25 +00:00
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/*
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* "Periodic Counter Operation"
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* Clear on TGRA compare match, divide clock by 64.
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*/
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sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64);
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sh_mtu2_write(ch, TIOR, TIOC_IOCH(TIOR_OC_0_CLEAR) |
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TIOC_IOCL(TIOR_OC_0_CLEAR));
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2014-03-04 11:58:30 +00:00
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sh_mtu2_write(ch, TGR, periodic);
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sh_mtu2_write(ch, TCNT, 0);
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2014-03-04 14:16:25 +00:00
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sh_mtu2_write(ch, TMDR, TMDR_MD_NORMAL);
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sh_mtu2_write(ch, TIER, TIER_TGIEA);
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2009-04-30 07:02:49 +00:00
|
|
|
|
|
|
|
/* enable channel */
|
2014-03-04 11:58:30 +00:00
|
|
|
sh_mtu2_start_stop_ch(ch, 1);
|
2009-04-30 07:02:49 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-03-04 11:58:30 +00:00
|
|
|
static void sh_mtu2_disable(struct sh_mtu2_channel *ch)
|
2009-04-30 07:02:49 +00:00
|
|
|
{
|
|
|
|
/* disable channel */
|
2014-03-04 11:58:30 +00:00
|
|
|
sh_mtu2_start_stop_ch(ch, 0);
|
2009-04-30 07:02:49 +00:00
|
|
|
|
|
|
|
/* stop clock */
|
2014-03-04 11:58:30 +00:00
|
|
|
clk_disable(ch->mtu->clk);
|
2012-08-13 12:00:16 +00:00
|
|
|
|
2014-03-04 11:58:30 +00:00
|
|
|
dev_pm_syscore_device(&ch->mtu->pdev->dev, false);
|
|
|
|
pm_runtime_put(&ch->mtu->pdev->dev);
|
2009-04-30 07:02:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
|
|
|
|
{
|
2014-03-04 11:58:30 +00:00
|
|
|
struct sh_mtu2_channel *ch = dev_id;
|
2009-04-30 07:02:49 +00:00
|
|
|
|
|
|
|
/* acknowledge interrupt */
|
2014-03-04 11:58:30 +00:00
|
|
|
sh_mtu2_read(ch, TSR);
|
2014-03-04 14:16:25 +00:00
|
|
|
sh_mtu2_write(ch, TSR, ~TSR_TGFA);
|
2009-04-30 07:02:49 +00:00
|
|
|
|
|
|
|
/* notify clockevent layer */
|
2014-03-04 11:58:30 +00:00
|
|
|
ch->ced.event_handler(&ch->ced);
|
2009-04-30 07:02:49 +00:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2014-03-04 11:58:30 +00:00
|
|
|
static struct sh_mtu2_channel *ced_to_sh_mtu2(struct clock_event_device *ced)
|
2009-04-30 07:02:49 +00:00
|
|
|
{
|
2014-03-04 11:58:30 +00:00
|
|
|
return container_of(ced, struct sh_mtu2_channel, ced);
|
2009-04-30 07:02:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
|
|
|
|
struct clock_event_device *ced)
|
|
|
|
{
|
2014-03-04 11:58:30 +00:00
|
|
|
struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);
|
2009-04-30 07:02:49 +00:00
|
|
|
int disabled = 0;
|
|
|
|
|
|
|
|
/* deal with old setting first */
|
|
|
|
switch (ced->mode) {
|
|
|
|
case CLOCK_EVT_MODE_PERIODIC:
|
2014-03-04 11:58:30 +00:00
|
|
|
sh_mtu2_disable(ch);
|
2009-04-30 07:02:49 +00:00
|
|
|
disabled = 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (mode) {
|
|
|
|
case CLOCK_EVT_MODE_PERIODIC:
|
2014-03-04 11:58:30 +00:00
|
|
|
dev_info(&ch->mtu->pdev->dev,
|
2014-03-04 13:17:26 +00:00
|
|
|
"ch%u: used for periodic clock events\n", ch->index);
|
2014-03-04 11:58:30 +00:00
|
|
|
sh_mtu2_enable(ch);
|
2009-04-30 07:02:49 +00:00
|
|
|
break;
|
|
|
|
case CLOCK_EVT_MODE_UNUSED:
|
|
|
|
if (!disabled)
|
2014-03-04 11:58:30 +00:00
|
|
|
sh_mtu2_disable(ch);
|
2009-04-30 07:02:49 +00:00
|
|
|
break;
|
|
|
|
case CLOCK_EVT_MODE_SHUTDOWN:
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-08-05 23:43:41 +00:00
|
|
|
static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced)
|
|
|
|
{
|
2014-03-04 11:58:30 +00:00
|
|
|
pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
|
2012-08-05 23:43:41 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_mtu2_clock_event_resume(struct clock_event_device *ced)
|
|
|
|
{
|
2014-03-04 11:58:30 +00:00
|
|
|
pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
|
2012-08-05 23:43:41 +00:00
|
|
|
}
|
|
|
|
|
2014-03-04 11:58:30 +00:00
|
|
|
static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch,
|
2014-03-04 14:19:41 +00:00
|
|
|
const char *name)
|
2009-04-30 07:02:49 +00:00
|
|
|
{
|
2014-03-04 11:58:30 +00:00
|
|
|
struct clock_event_device *ced = &ch->ced;
|
2009-04-30 07:02:49 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ced->name = name;
|
|
|
|
ced->features = CLOCK_EVT_FEAT_PERIODIC;
|
2014-03-04 14:19:41 +00:00
|
|
|
ced->rating = 200;
|
2014-03-04 14:22:19 +00:00
|
|
|
ced->cpumask = cpu_possible_mask;
|
2009-04-30 07:02:49 +00:00
|
|
|
ced->set_mode = sh_mtu2_clock_event_mode;
|
2012-08-05 23:43:41 +00:00
|
|
|
ced->suspend = sh_mtu2_clock_event_suspend;
|
|
|
|
ced->resume = sh_mtu2_clock_event_resume;
|
2009-04-30 07:02:49 +00:00
|
|
|
|
2014-03-04 13:17:26 +00:00
|
|
|
dev_info(&ch->mtu->pdev->dev, "ch%u: used for clock events\n",
|
|
|
|
ch->index);
|
2010-02-25 07:37:46 +00:00
|
|
|
clockevents_register_device(ced);
|
|
|
|
|
2014-03-04 11:58:30 +00:00
|
|
|
ret = request_irq(ch->irq, sh_mtu2_interrupt,
|
2014-02-17 10:27:49 +00:00
|
|
|
IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
|
2014-03-04 11:58:30 +00:00
|
|
|
dev_name(&ch->mtu->pdev->dev), ch);
|
2009-04-30 07:02:49 +00:00
|
|
|
if (ret) {
|
2014-03-04 13:17:26 +00:00
|
|
|
dev_err(&ch->mtu->pdev->dev, "ch%u: failed to request irq %d\n",
|
|
|
|
ch->index, ch->irq);
|
2009-04-30 07:02:49 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-03-04 12:57:14 +00:00
|
|
|
static int sh_mtu2_register(struct sh_mtu2_channel *ch, const char *name,
|
2014-03-04 14:19:41 +00:00
|
|
|
bool clockevent)
|
2009-04-30 07:02:49 +00:00
|
|
|
{
|
2014-03-04 17:05:45 +00:00
|
|
|
if (clockevent) {
|
|
|
|
ch->mtu->has_clockevent = true;
|
2014-03-04 14:19:41 +00:00
|
|
|
sh_mtu2_register_clockevent(ch, name);
|
2014-03-04 17:05:45 +00:00
|
|
|
}
|
2009-04-30 07:02:49 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-03-04 17:05:45 +00:00
|
|
|
static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch, unsigned int index,
|
2014-03-04 12:11:23 +00:00
|
|
|
struct sh_mtu2_device *mtu)
|
|
|
|
{
|
2014-03-04 17:05:45 +00:00
|
|
|
static const unsigned int channel_offsets[] = {
|
|
|
|
0x300, 0x380, 0x000,
|
|
|
|
};
|
|
|
|
bool clockevent;
|
2014-03-04 12:11:23 +00:00
|
|
|
|
|
|
|
ch->mtu = mtu;
|
|
|
|
|
2014-03-04 17:05:45 +00:00
|
|
|
if (mtu->legacy) {
|
|
|
|
struct sh_timer_config *cfg = mtu->pdev->dev.platform_data;
|
|
|
|
|
|
|
|
clockevent = cfg->clockevent_rating != 0;
|
|
|
|
|
|
|
|
ch->irq = platform_get_irq(mtu->pdev, 0);
|
|
|
|
ch->base = mtu->mapbase - cfg->channel_offset;
|
|
|
|
ch->index = cfg->timer_bit;
|
|
|
|
} else {
|
|
|
|
char name[6];
|
|
|
|
|
|
|
|
clockevent = true;
|
|
|
|
|
|
|
|
sprintf(name, "tgi%ua", index);
|
|
|
|
ch->irq = platform_get_irq_byname(mtu->pdev, name);
|
|
|
|
ch->base = mtu->mapbase + channel_offsets[index];
|
|
|
|
ch->index = index;
|
|
|
|
}
|
|
|
|
|
2014-03-04 12:11:23 +00:00
|
|
|
if (ch->irq < 0) {
|
2014-03-04 17:05:45 +00:00
|
|
|
/* Skip channels with no declared interrupt. */
|
|
|
|
if (!mtu->legacy)
|
|
|
|
return 0;
|
|
|
|
|
2014-03-04 13:17:26 +00:00
|
|
|
dev_err(&mtu->pdev->dev, "ch%u: failed to get irq\n",
|
|
|
|
ch->index);
|
2014-03-04 12:11:23 +00:00
|
|
|
return ch->irq;
|
|
|
|
}
|
|
|
|
|
2014-03-04 17:05:45 +00:00
|
|
|
return sh_mtu2_register(ch, dev_name(&mtu->pdev->dev), clockevent);
|
2014-03-04 12:11:23 +00:00
|
|
|
}
|
|
|
|
|
2014-03-04 17:05:45 +00:00
|
|
|
static int sh_mtu2_map_memory(struct sh_mtu2_device *mtu)
|
2009-04-30 07:02:49 +00:00
|
|
|
{
|
|
|
|
struct resource *res;
|
|
|
|
|
2014-03-04 12:04:48 +00:00
|
|
|
res = platform_get_resource(mtu->pdev, IORESOURCE_MEM, 0);
|
2009-04-30 07:02:49 +00:00
|
|
|
if (!res) {
|
2014-03-04 12:04:48 +00:00
|
|
|
dev_err(&mtu->pdev->dev, "failed to get I/O memory\n");
|
2014-03-04 17:05:45 +00:00
|
|
|
return -ENXIO;
|
2009-04-30 07:02:49 +00:00
|
|
|
}
|
|
|
|
|
2014-03-04 17:05:45 +00:00
|
|
|
mtu->mapbase = ioremap_nocache(res->start, resource_size(res));
|
|
|
|
if (mtu->mapbase == NULL)
|
|
|
|
return -ENXIO;
|
|
|
|
|
2014-03-04 13:04:24 +00:00
|
|
|
/*
|
2014-03-04 17:05:45 +00:00
|
|
|
* In legacy platform device configuration (with one device per channel)
|
|
|
|
* the resource points to the channel base address.
|
2014-03-04 13:04:24 +00:00
|
|
|
*/
|
2014-03-04 17:05:45 +00:00
|
|
|
if (mtu->legacy) {
|
|
|
|
struct sh_timer_config *cfg = mtu->pdev->dev.platform_data;
|
|
|
|
mtu->mapbase += cfg->channel_offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_mtu2_unmap_memory(struct sh_mtu2_device *mtu)
|
|
|
|
{
|
|
|
|
if (mtu->legacy) {
|
|
|
|
struct sh_timer_config *cfg = mtu->pdev->dev.platform_data;
|
|
|
|
mtu->mapbase -= cfg->channel_offset;
|
2009-04-30 07:02:49 +00:00
|
|
|
}
|
|
|
|
|
2014-03-04 17:05:45 +00:00
|
|
|
iounmap(mtu->mapbase);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_mtu2_setup(struct sh_mtu2_device *mtu,
|
|
|
|
struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct sh_timer_config *cfg = pdev->dev.platform_data;
|
|
|
|
const struct platform_device_id *id = pdev->id_entry;
|
|
|
|
unsigned int i;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
mtu->pdev = pdev;
|
|
|
|
mtu->legacy = id->driver_data;
|
|
|
|
|
|
|
|
if (mtu->legacy && !cfg) {
|
|
|
|
dev_err(&mtu->pdev->dev, "missing platform data\n");
|
|
|
|
return -ENXIO;
|
|
|
|
}
|
2014-03-04 13:04:24 +00:00
|
|
|
|
2014-03-04 17:05:45 +00:00
|
|
|
/* Get hold of clock. */
|
2014-03-04 17:09:15 +00:00
|
|
|
mtu->clk = clk_get(&mtu->pdev->dev, mtu->legacy ? "mtu2_fck" : "fck");
|
2014-03-04 12:04:48 +00:00
|
|
|
if (IS_ERR(mtu->clk)) {
|
|
|
|
dev_err(&mtu->pdev->dev, "cannot get clock\n");
|
2014-03-04 17:05:45 +00:00
|
|
|
return PTR_ERR(mtu->clk);
|
2009-04-30 07:02:49 +00:00
|
|
|
}
|
|
|
|
|
2014-03-04 12:04:48 +00:00
|
|
|
ret = clk_prepare(mtu->clk);
|
2013-11-08 10:07:59 +00:00
|
|
|
if (ret < 0)
|
2014-03-04 17:05:45 +00:00
|
|
|
goto err_clk_put;
|
2013-11-08 10:07:59 +00:00
|
|
|
|
2014-03-04 17:05:45 +00:00
|
|
|
/* Map the memory resource. */
|
|
|
|
ret = sh_mtu2_map_memory(mtu);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&mtu->pdev->dev, "failed to remap I/O memory\n");
|
|
|
|
goto err_clk_unprepare;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Allocate and setup the channels. */
|
|
|
|
if (mtu->legacy)
|
|
|
|
mtu->num_channels = 1;
|
|
|
|
else
|
|
|
|
mtu->num_channels = 3;
|
|
|
|
|
|
|
|
mtu->channels = kzalloc(sizeof(*mtu->channels) * mtu->num_channels,
|
|
|
|
GFP_KERNEL);
|
2014-03-04 13:23:00 +00:00
|
|
|
if (mtu->channels == NULL) {
|
|
|
|
ret = -ENOMEM;
|
2014-03-04 17:05:45 +00:00
|
|
|
goto err_unmap;
|
2014-03-04 13:23:00 +00:00
|
|
|
}
|
|
|
|
|
2014-03-04 17:05:45 +00:00
|
|
|
if (mtu->legacy) {
|
|
|
|
ret = sh_mtu2_setup_channel(&mtu->channels[0], 0, mtu);
|
|
|
|
if (ret < 0)
|
|
|
|
goto err_unmap;
|
|
|
|
} else {
|
|
|
|
for (i = 0; i < mtu->num_channels; ++i) {
|
|
|
|
ret = sh_mtu2_setup_channel(&mtu->channels[i], i, mtu);
|
|
|
|
if (ret < 0)
|
|
|
|
goto err_unmap;
|
|
|
|
}
|
|
|
|
}
|
2014-03-04 13:23:00 +00:00
|
|
|
|
2014-03-04 17:05:45 +00:00
|
|
|
platform_set_drvdata(pdev, mtu);
|
2013-11-08 10:07:59 +00:00
|
|
|
|
|
|
|
return 0;
|
2014-03-04 17:05:45 +00:00
|
|
|
|
|
|
|
err_unmap:
|
2014-03-04 13:23:00 +00:00
|
|
|
kfree(mtu->channels);
|
2014-03-04 17:05:45 +00:00
|
|
|
sh_mtu2_unmap_memory(mtu);
|
|
|
|
err_clk_unprepare:
|
2014-03-04 12:04:48 +00:00
|
|
|
clk_unprepare(mtu->clk);
|
2014-03-04 17:05:45 +00:00
|
|
|
err_clk_put:
|
2014-03-04 12:04:48 +00:00
|
|
|
clk_put(mtu->clk);
|
2009-04-30 07:02:49 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-12-21 23:11:38 +00:00
|
|
|
static int sh_mtu2_probe(struct platform_device *pdev)
|
2009-04-30 07:02:49 +00:00
|
|
|
{
|
2014-03-04 12:04:48 +00:00
|
|
|
struct sh_mtu2_device *mtu = platform_get_drvdata(pdev);
|
2009-04-30 07:02:49 +00:00
|
|
|
int ret;
|
2012-03-13 21:40:14 +00:00
|
|
|
|
2012-08-05 23:43:41 +00:00
|
|
|
if (!is_early_platform_device(pdev)) {
|
2012-08-13 12:00:16 +00:00
|
|
|
pm_runtime_set_active(&pdev->dev);
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
2012-08-05 23:43:41 +00:00
|
|
|
}
|
2009-04-30 07:02:49 +00:00
|
|
|
|
2014-03-04 12:04:48 +00:00
|
|
|
if (mtu) {
|
2010-03-10 07:26:25 +00:00
|
|
|
dev_info(&pdev->dev, "kept as earlytimer\n");
|
2012-08-13 12:00:16 +00:00
|
|
|
goto out;
|
2009-04-30 07:02:49 +00:00
|
|
|
}
|
|
|
|
|
2014-03-04 13:10:55 +00:00
|
|
|
mtu = kzalloc(sizeof(*mtu), GFP_KERNEL);
|
2014-03-04 12:04:48 +00:00
|
|
|
if (mtu == NULL) {
|
2009-04-30 07:02:49 +00:00
|
|
|
dev_err(&pdev->dev, "failed to allocate driver data\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2014-03-04 12:04:48 +00:00
|
|
|
ret = sh_mtu2_setup(mtu, pdev);
|
2009-04-30 07:02:49 +00:00
|
|
|
if (ret) {
|
2014-03-04 12:04:48 +00:00
|
|
|
kfree(mtu);
|
2012-08-13 12:00:16 +00:00
|
|
|
pm_runtime_idle(&pdev->dev);
|
|
|
|
return ret;
|
2009-04-30 07:02:49 +00:00
|
|
|
}
|
2012-08-13 12:00:16 +00:00
|
|
|
if (is_early_platform_device(pdev))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
out:
|
2014-03-04 17:05:45 +00:00
|
|
|
if (mtu->has_clockevent)
|
2012-08-13 12:00:16 +00:00
|
|
|
pm_runtime_irq_safe(&pdev->dev);
|
|
|
|
else
|
|
|
|
pm_runtime_idle(&pdev->dev);
|
|
|
|
|
|
|
|
return 0;
|
2009-04-30 07:02:49 +00:00
|
|
|
}
|
|
|
|
|
2012-12-21 23:11:38 +00:00
|
|
|
static int sh_mtu2_remove(struct platform_device *pdev)
|
2009-04-30 07:02:49 +00:00
|
|
|
{
|
|
|
|
return -EBUSY; /* cannot unregister clockevent */
|
|
|
|
}
|
|
|
|
|
2014-03-04 17:05:45 +00:00
|
|
|
static const struct platform_device_id sh_mtu2_id_table[] = {
|
|
|
|
{ "sh_mtu2", 1 },
|
|
|
|
{ "sh-mtu2", 0 },
|
|
|
|
{ },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(platform, sh_mtu2_id_table);
|
|
|
|
|
2009-04-30 07:02:49 +00:00
|
|
|
static struct platform_driver sh_mtu2_device_driver = {
|
|
|
|
.probe = sh_mtu2_probe,
|
2012-12-21 23:11:38 +00:00
|
|
|
.remove = sh_mtu2_remove,
|
2009-04-30 07:02:49 +00:00
|
|
|
.driver = {
|
|
|
|
.name = "sh_mtu2",
|
2014-03-04 17:05:45 +00:00
|
|
|
},
|
|
|
|
.id_table = sh_mtu2_id_table,
|
2009-04-30 07:02:49 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static int __init sh_mtu2_init(void)
|
|
|
|
{
|
|
|
|
return platform_driver_register(&sh_mtu2_device_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit sh_mtu2_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&sh_mtu2_device_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
early_platform_init("earlytimer", &sh_mtu2_device_driver);
|
2013-03-05 06:40:42 +00:00
|
|
|
subsys_initcall(sh_mtu2_init);
|
2009-04-30 07:02:49 +00:00
|
|
|
module_exit(sh_mtu2_exit);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Magnus Damm");
|
|
|
|
MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|