2020-03-25 17:31:21 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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*/
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2021-09-30 08:31:49 +00:00
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#include <linux/delay.h>
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2020-03-25 17:31:22 +00:00
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#include <linux/device.h>
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2020-10-06 19:33:17 +00:00
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#include <linux/io.h>
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2020-03-25 17:31:21 +00:00
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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2021-09-30 08:31:49 +00:00
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#include <linux/reset-controller.h>
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2020-03-25 17:31:22 +00:00
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#include <linux/soc/mediatek/mtk-mmsys.h>
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2021-03-17 18:17:10 +00:00
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#include "mtk-mmsys.h"
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2021-04-05 20:03:53 +00:00
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#include "mt8167-mmsys.h"
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2021-03-30 11:04:23 +00:00
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#include "mt8183-mmsys.h"
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2022-02-22 05:28:01 +00:00
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#include "mt8186-mmsys.h"
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2021-08-02 08:59:33 +00:00
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#include "mt8192-mmsys.h"
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2022-04-19 09:41:36 +00:00
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#include "mt8195-mmsys.h"
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2021-05-19 16:18:46 +00:00
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#include "mt8365-mmsys.h"
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2020-03-25 17:31:21 +00:00
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2020-04-01 20:17:35 +00:00
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static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
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.clk_driver = "clk-mt2701-mm",
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2021-03-17 18:17:10 +00:00
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.routes = mmsys_default_routing_table,
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.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
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2020-04-01 20:17:35 +00:00
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};
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2022-04-19 09:41:36 +00:00
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static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
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.num_drv_data = 1,
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.drv_data = {
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&mt2701_mmsys_driver_data,
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},
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};
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2020-04-01 20:17:34 +00:00
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static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
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.clk_driver = "clk-mt2712-mm",
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2021-03-17 18:17:10 +00:00
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.routes = mmsys_default_routing_table,
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.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
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2020-04-01 20:17:34 +00:00
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};
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2022-04-19 09:41:36 +00:00
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static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
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.num_drv_data = 1,
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.drv_data = {
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&mt2712_mmsys_driver_data,
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},
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};
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2020-05-18 11:31:55 +00:00
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static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
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.clk_driver = "clk-mt6779-mm",
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};
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2022-04-19 09:41:36 +00:00
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static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
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.num_drv_data = 1,
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.drv_data = {
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&mt6779_mmsys_driver_data,
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},
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};
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2020-05-18 11:31:54 +00:00
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static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
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.clk_driver = "clk-mt6797-mm",
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};
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2022-04-19 09:41:36 +00:00
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static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
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.num_drv_data = 1,
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.drv_data = {
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&mt6797_mmsys_driver_data,
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},
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};
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2021-04-05 20:03:53 +00:00
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static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
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.clk_driver = "clk-mt8167-mm",
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.routes = mt8167_mmsys_routing_table,
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.num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
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};
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2022-04-19 09:41:36 +00:00
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static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
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.num_drv_data = 1,
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.drv_data = {
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&mt8167_mmsys_driver_data,
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},
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};
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2020-03-25 17:31:21 +00:00
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static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
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.clk_driver = "clk-mt8173-mm",
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2021-03-17 18:17:10 +00:00
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.routes = mmsys_default_routing_table,
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.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
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2022-02-17 08:26:25 +00:00
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.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
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2020-03-25 17:31:21 +00:00
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};
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2022-04-19 09:41:36 +00:00
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static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
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.num_drv_data = 1,
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.drv_data = {
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&mt8173_mmsys_driver_data,
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},
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};
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2020-05-18 11:31:53 +00:00
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static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
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.clk_driver = "clk-mt8183-mm",
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2021-03-30 11:04:23 +00:00
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.routes = mmsys_mt8183_routing_table,
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.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
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2022-02-17 08:26:25 +00:00
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.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
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2020-05-18 11:31:53 +00:00
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};
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2022-04-19 09:41:36 +00:00
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static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
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.num_drv_data = 1,
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.drv_data = {
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&mt8183_mmsys_driver_data,
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},
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};
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2022-02-22 05:28:01 +00:00
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static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
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.clk_driver = "clk-mt8186-mm",
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.routes = mmsys_mt8186_routing_table,
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.num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
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2022-02-17 08:26:26 +00:00
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.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
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2022-02-22 05:28:01 +00:00
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};
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2022-04-19 09:41:36 +00:00
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static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
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.num_drv_data = 1,
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.drv_data = {
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&mt8186_mmsys_driver_data,
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},
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};
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2021-08-02 08:59:33 +00:00
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static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
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.clk_driver = "clk-mt8192-mm",
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.routes = mmsys_mt8192_routing_table,
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.num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
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2022-03-23 09:19:32 +00:00
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.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
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2021-08-02 08:59:33 +00:00
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};
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2022-04-19 09:41:36 +00:00
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static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
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.num_drv_data = 1,
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.drv_data = {
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&mt8192_mmsys_driver_data,
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},
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};
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static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
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.io_start = 0x1c01a000,
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.clk_driver = "clk-mt8195-vdo0",
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.routes = mmsys_mt8195_routing_table,
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.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
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};
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static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
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.io_start = 0x1c100000,
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.clk_driver = "clk-mt8195-vdo1",
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};
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static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
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.num_drv_data = 2,
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.drv_data = {
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&mt8195_vdosys0_driver_data,
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&mt8195_vdosys1_driver_data,
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},
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};
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2021-05-19 16:18:46 +00:00
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static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
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.clk_driver = "clk-mt8365-mm",
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.routes = mt8365_mmsys_routing_table,
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.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
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};
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2022-04-19 09:41:36 +00:00
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static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {
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.num_drv_data = 1,
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.drv_data = {
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&mt8365_mmsys_driver_data,
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},
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};
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2021-03-17 18:17:09 +00:00
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struct mtk_mmsys {
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void __iomem *regs;
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const struct mtk_mmsys_driver_data *data;
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2021-09-30 08:31:49 +00:00
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spinlock_t lock; /* protects mmsys_sw_rst_b reg */
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struct reset_controller_dev rcdev;
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2022-04-19 09:41:36 +00:00
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phys_addr_t io_start;
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2021-03-17 18:17:09 +00:00
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};
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2022-04-19 09:41:36 +00:00
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static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
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const struct mtk_mmsys_match_data *match)
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{
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int i;
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for (i = 0; i < match->num_drv_data; i++)
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if (mmsys->io_start == match->drv_data[i]->io_start)
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return i;
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return -EINVAL;
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}
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2020-03-25 17:31:22 +00:00
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void mtk_mmsys_ddp_connect(struct device *dev,
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enum mtk_ddp_comp_id cur,
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enum mtk_ddp_comp_id next)
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{
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2021-03-17 18:17:09 +00:00
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struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
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2021-03-17 18:17:10 +00:00
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const struct mtk_mmsys_routes *routes = mmsys->data->routes;
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u32 reg;
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int i;
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for (i = 0; i < mmsys->data->num_routes; i++)
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if (cur == routes[i].from_comp && next == routes[i].to_comp) {
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2021-07-29 07:05:49 +00:00
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reg = readl_relaxed(mmsys->regs + routes[i].addr);
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reg &= ~routes[i].mask;
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reg |= routes[i].val;
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2021-03-17 18:17:10 +00:00
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writel_relaxed(reg, mmsys->regs + routes[i].addr);
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}
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2020-03-25 17:31:22 +00:00
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}
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EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
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void mtk_mmsys_ddp_disconnect(struct device *dev,
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enum mtk_ddp_comp_id cur,
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enum mtk_ddp_comp_id next)
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{
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2021-03-17 18:17:09 +00:00
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struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
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2021-03-17 18:17:10 +00:00
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const struct mtk_mmsys_routes *routes = mmsys->data->routes;
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u32 reg;
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int i;
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for (i = 0; i < mmsys->data->num_routes; i++)
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if (cur == routes[i].from_comp && next == routes[i].to_comp) {
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2021-07-29 07:05:49 +00:00
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reg = readl_relaxed(mmsys->regs + routes[i].addr);
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reg &= ~routes[i].mask;
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2021-03-17 18:17:10 +00:00
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writel_relaxed(reg, mmsys->regs + routes[i].addr);
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}
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2020-03-25 17:31:22 +00:00
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}
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EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
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2021-09-30 08:31:49 +00:00
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static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
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bool assert)
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{
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struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&mmsys->lock, flags);
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2022-02-17 08:26:25 +00:00
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reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset);
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2021-09-30 08:31:49 +00:00
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if (assert)
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reg &= ~BIT(id);
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else
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reg |= BIT(id);
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2022-02-17 08:26:25 +00:00
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writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset);
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2021-09-30 08:31:49 +00:00
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spin_unlock_irqrestore(&mmsys->lock, flags);
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return 0;
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}
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static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
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{
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return mtk_mmsys_reset_update(rcdev, id, true);
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}
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static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
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{
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return mtk_mmsys_reset_update(rcdev, id, false);
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}
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static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id)
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{
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int ret;
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ret = mtk_mmsys_reset_assert(rcdev, id);
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if (ret)
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return ret;
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usleep_range(1000, 1100);
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return mtk_mmsys_reset_deassert(rcdev, id);
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}
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static const struct reset_control_ops mtk_mmsys_reset_ops = {
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.assert = mtk_mmsys_reset_assert,
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.deassert = mtk_mmsys_reset_deassert,
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.reset = mtk_mmsys_reset,
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};
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2020-03-25 17:31:21 +00:00
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static int mtk_mmsys_probe(struct platform_device *pdev)
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{
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2020-03-25 17:31:22 +00:00
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struct device *dev = &pdev->dev;
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2020-03-25 17:31:21 +00:00
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struct platform_device *clks;
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2020-03-25 17:31:23 +00:00
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struct platform_device *drm;
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2022-04-19 09:41:36 +00:00
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const struct mtk_mmsys_match_data *match_data;
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2021-03-17 18:17:09 +00:00
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struct mtk_mmsys *mmsys;
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2022-04-19 09:41:36 +00:00
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struct resource *res;
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2020-03-25 17:31:22 +00:00
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int ret;
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2021-03-17 18:17:09 +00:00
|
|
|
mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
|
|
|
|
if (!mmsys)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
mmsys->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
|
|
if (IS_ERR(mmsys->regs)) {
|
|
|
|
ret = PTR_ERR(mmsys->regs);
|
2020-10-06 19:33:18 +00:00
|
|
|
dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
|
2020-03-25 17:31:22 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2021-09-30 08:31:49 +00:00
|
|
|
spin_lock_init(&mmsys->lock);
|
|
|
|
|
|
|
|
mmsys->rcdev.owner = THIS_MODULE;
|
|
|
|
mmsys->rcdev.nr_resets = 32;
|
|
|
|
mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
|
|
|
|
mmsys->rcdev.of_node = pdev->dev.of_node;
|
|
|
|
ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2022-04-19 09:41:36 +00:00
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!res) {
|
|
|
|
dev_err(dev, "Couldn't get mmsys resource\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
mmsys->io_start = res->start;
|
|
|
|
|
|
|
|
match_data = of_device_get_match_data(dev);
|
|
|
|
if (match_data->num_drv_data > 1) {
|
|
|
|
/* This SoC has multiple mmsys channels */
|
|
|
|
ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(dev, "Couldn't get match driver data\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
mmsys->data = match_data->drv_data[ret];
|
|
|
|
} else {
|
|
|
|
dev_dbg(dev, "Using single mmsys channel\n");
|
|
|
|
mmsys->data = match_data->drv_data[0];
|
|
|
|
}
|
|
|
|
|
2021-03-17 18:17:09 +00:00
|
|
|
platform_set_drvdata(pdev, mmsys);
|
2020-03-25 17:31:21 +00:00
|
|
|
|
2021-03-17 18:17:09 +00:00
|
|
|
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
|
2020-03-25 17:31:21 +00:00
|
|
|
PLATFORM_DEVID_AUTO, NULL, 0);
|
|
|
|
if (IS_ERR(clks))
|
|
|
|
return PTR_ERR(clks);
|
|
|
|
|
2020-03-25 17:31:23 +00:00
|
|
|
drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
|
|
|
|
PLATFORM_DEVID_AUTO, NULL, 0);
|
2020-05-06 14:13:17 +00:00
|
|
|
if (IS_ERR(drm)) {
|
|
|
|
platform_device_unregister(clks);
|
2020-03-25 17:31:23 +00:00
|
|
|
return PTR_ERR(drm);
|
2020-05-06 14:13:17 +00:00
|
|
|
}
|
2020-03-25 17:31:23 +00:00
|
|
|
|
2020-03-25 17:31:21 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id of_match_mtk_mmsys[] = {
|
2020-04-01 20:17:35 +00:00
|
|
|
{
|
|
|
|
.compatible = "mediatek,mt2701-mmsys",
|
2022-04-19 09:41:36 +00:00
|
|
|
.data = &mt2701_mmsys_match_data,
|
2020-04-01 20:17:35 +00:00
|
|
|
},
|
2020-04-01 20:17:34 +00:00
|
|
|
{
|
|
|
|
.compatible = "mediatek,mt2712-mmsys",
|
2022-04-19 09:41:36 +00:00
|
|
|
.data = &mt2712_mmsys_match_data,
|
2020-04-01 20:17:34 +00:00
|
|
|
},
|
2020-05-18 11:31:55 +00:00
|
|
|
{
|
|
|
|
.compatible = "mediatek,mt6779-mmsys",
|
2022-04-19 09:41:36 +00:00
|
|
|
.data = &mt6779_mmsys_match_data,
|
2020-05-18 11:31:55 +00:00
|
|
|
},
|
2020-05-18 11:31:54 +00:00
|
|
|
{
|
|
|
|
.compatible = "mediatek,mt6797-mmsys",
|
2022-04-19 09:41:36 +00:00
|
|
|
.data = &mt6797_mmsys_match_data,
|
2020-05-18 11:31:54 +00:00
|
|
|
},
|
2021-04-05 20:03:53 +00:00
|
|
|
{
|
|
|
|
.compatible = "mediatek,mt8167-mmsys",
|
2022-04-19 09:41:36 +00:00
|
|
|
.data = &mt8167_mmsys_match_data,
|
2021-04-05 20:03:53 +00:00
|
|
|
},
|
2020-03-25 17:31:21 +00:00
|
|
|
{
|
|
|
|
.compatible = "mediatek,mt8173-mmsys",
|
2022-04-19 09:41:36 +00:00
|
|
|
.data = &mt8173_mmsys_match_data,
|
2020-03-25 17:31:21 +00:00
|
|
|
},
|
2020-05-18 11:31:53 +00:00
|
|
|
{
|
|
|
|
.compatible = "mediatek,mt8183-mmsys",
|
2022-04-19 09:41:36 +00:00
|
|
|
.data = &mt8183_mmsys_match_data,
|
2020-05-18 11:31:53 +00:00
|
|
|
},
|
2022-02-22 05:28:01 +00:00
|
|
|
{
|
|
|
|
.compatible = "mediatek,mt8186-mmsys",
|
2022-04-19 09:41:36 +00:00
|
|
|
.data = &mt8186_mmsys_match_data,
|
2022-02-22 05:28:01 +00:00
|
|
|
},
|
2021-08-02 08:59:33 +00:00
|
|
|
{
|
|
|
|
.compatible = "mediatek,mt8192-mmsys",
|
2022-04-19 09:41:36 +00:00
|
|
|
.data = &mt8192_mmsys_match_data,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "mediatek,mt8195-mmsys",
|
|
|
|
.data = &mt8195_mmsys_match_data,
|
2021-08-02 08:59:33 +00:00
|
|
|
},
|
2021-05-19 16:18:46 +00:00
|
|
|
{
|
|
|
|
.compatible = "mediatek,mt8365-mmsys",
|
2022-04-19 09:41:36 +00:00
|
|
|
.data = &mt8365_mmsys_match_data,
|
2021-05-19 16:18:46 +00:00
|
|
|
},
|
2020-03-25 17:31:21 +00:00
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_driver mtk_mmsys_drv = {
|
|
|
|
.driver = {
|
|
|
|
.name = "mtk-mmsys",
|
|
|
|
.of_match_table = of_match_mtk_mmsys,
|
|
|
|
},
|
|
|
|
.probe = mtk_mmsys_probe,
|
|
|
|
};
|
|
|
|
|
|
|
|
builtin_platform_driver(mtk_mmsys_drv);
|