License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2008-10-23 05:26:29 +00:00
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#ifndef _ASM_X86_CPUFEATURE_H
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#define _ASM_X86_CPUFEATURE_H
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2008-01-30 12:30:07 +00:00
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2016-01-26 21:12:04 +00:00
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#include <asm/processor.h>
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2013-03-20 14:07:24 +00:00
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2008-02-04 15:48:00 +00:00
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#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
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2010-05-12 00:47:07 +00:00
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#include <asm/asm.h>
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2008-02-04 15:48:00 +00:00
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#include <linux/bitops.h>
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2015-12-07 09:39:40 +00:00
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enum cpuid_leafs
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{
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CPUID_1_EDX = 0,
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CPUID_8000_0001_EDX,
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CPUID_8086_0001_EDX,
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CPUID_LNX_1,
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CPUID_1_ECX,
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CPUID_C000_0001_EDX,
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CPUID_8000_0001_ECX,
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CPUID_LNX_2,
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CPUID_LNX_3,
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CPUID_7_0_EBX,
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CPUID_D_1_EAX,
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CPUID_F_0_EDX,
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CPUID_F_1_EDX,
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CPUID_8000_0008_EBX,
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CPUID_6_EAX,
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CPUID_8000_000A_EDX,
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x86/cpufeature, x86/mm/pkeys: Add protection keys related CPUID definitions
There are two CPUID bits for protection keys. One is for whether
the CPU contains the feature, and the other will appear set once
the OS enables protection keys. Specifically:
Bit 04: OSPKE. If 1, OS has set CR4.PKE to enable
Protection keys (and the RDPKRU/WRPKRU instructions)
This is because userspace can not see CR4 contents, but it can
see CPUID contents.
X86_FEATURE_PKU is referred to as "PKU" in the hardware documentation:
CPUID.(EAX=07H,ECX=0H):ECX.PKU [bit 3]
X86_FEATURE_OSPKE is "OSPKU":
CPUID.(EAX=07H,ECX=0H):ECX.OSPKE [bit 4]
These are the first CPU features which need to look at the
ECX word in CPUID leaf 0x7, so this patch also includes
fetching that word in to the cpuinfo->x86_capability[] array.
Add it to the disabled-features mask when its config option is
off. Even though we are not using it here, we also extend the
REQUIRED_MASK_BIT_SET() macro to keep it mirroring the
DISABLED_MASK_BIT_SET() version.
This means that in almost all code, you should use:
cpu_has(c, X86_FEATURE_PKU)
and *not* the CONFIG option.
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Dave Hansen <dave@sr71.net>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rik van Riel <riel@redhat.com>
Cc: linux-mm@kvack.org
Link: http://lkml.kernel.org/r/20160212210201.7714C250@viggo.jf.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-02-12 21:02:01 +00:00
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CPUID_7_ECX,
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2016-05-11 12:58:26 +00:00
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CPUID_8000_0007_EBX,
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2018-01-25 16:14:09 +00:00
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CPUID_7_EDX,
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2015-12-07 09:39:40 +00:00
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};
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2013-10-30 15:09:45 +00:00
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#ifdef CONFIG_X86_FEATURE_NAMES
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2008-02-04 15:48:00 +00:00
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extern const char * const x86_cap_flags[NCAPINTS*32];
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extern const char * const x86_power_flags[32];
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2013-10-30 15:09:45 +00:00
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#define X86_CAP_FMT "%s"
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#define x86_cap_flag(flag) x86_cap_flags[flag]
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#else
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#define X86_CAP_FMT "%d:%d"
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#define x86_cap_flag(flag) ((flag) >> 5), ((flag) & 31)
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#endif
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2008-02-04 15:48:00 +00:00
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2014-06-24 11:25:03 +00:00
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/*
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* In order to save room, we index into this array by doing
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* X86_BUG_<name> - NCAPINTS*32.
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*/
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extern const char * const x86_bug_flags[NBUGINTS*32];
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2008-02-26 07:34:21 +00:00
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#define test_cpu_cap(c, bit) \
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test_bit(bit, (unsigned long *)((c)->x86_capability))
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2016-06-29 20:01:10 +00:00
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/*
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* There are 32 bits/features in each mask word. The high bits
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* (selected with (bit>>5) give us the word number and the low 5
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* bits give us the bit/feature number inside the word.
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* (1UL<<((bit)&31) gives us a mask for the feature_bit so we can
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* see if it is set in the mask word.
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*/
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#define CHECK_BIT_IN_MASK_WORD(maskname, word, bit) \
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(((bit)>>5)==(word) && (1UL<<((bit)&31) & maskname##word ))
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#define REQUIRED_MASK_BIT_SET(feature_bit) \
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( CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 0, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 1, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 2, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 3, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 4, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 5, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 6, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 7, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 8, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 9, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 10, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 11, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 12, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 13, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 14, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 15, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \
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2018-01-25 16:14:09 +00:00
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CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \
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2016-06-29 20:01:10 +00:00
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REQUIRED_MASK_CHECK || \
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2018-01-25 16:14:09 +00:00
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BUILD_BUG_ON_ZERO(NCAPINTS != 19))
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2011-03-12 11:50:10 +00:00
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2016-06-29 20:01:10 +00:00
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#define DISABLED_MASK_BIT_SET(feature_bit) \
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( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 1, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 2, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 3, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 4, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 5, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 6, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 7, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 8, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 9, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 10, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 11, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 12, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 13, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 14, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 15, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) || \
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \
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2018-01-25 16:14:09 +00:00
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CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \
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2016-06-29 20:01:10 +00:00
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DISABLED_MASK_CHECK || \
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2018-01-25 16:14:09 +00:00
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BUILD_BUG_ON_ZERO(NCAPINTS != 19))
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x86: Introduce disabled-features
I believe the REQUIRED_MASK aproach was taken so that it was
easier to consult in assembly (arch/x86/kernel/verify_cpu.S).
DISABLED_MASK does not have the same restriction, but I
implemented it the same way for consistency.
We have a REQUIRED_MASK... which does two things:
1. Keeps a list of cpuid bits to check in very early boot and
refuse to boot if those are not present.
2. Consulted during cpu_has() checks, which allows us to
optimize out things at compile-time. In other words, if we
*KNOW* we will not boot with the feature off, then we can
safely assume that it will be present forever.
But, we don't have a similar mechanism for CPU features which
may be present but that we know we will not use. We simply
use our existing mechanisms to repeatedly check the status of
the bit at runtime (well, the alternatives patching helps here
but it does not provide compile-time optimization).
Adding a feature to disabled-features.h allows the bit to be
checked via a new macro: cpu_feature_enabled(). Note that
for features in DISABLED_MASK, checks with this macro have
all of the benefits of an #ifdef. Before, we would have done
this in a header:
#ifdef CONFIG_X86_INTEL_MPX
#define cpu_has_mpx cpu_has(X86_FEATURE_MPX)
#else
#define cpu_has_mpx 0
#endif
and this in the code:
if (cpu_has_mpx)
do_some_mpx_thing();
Now, just add your feature to DISABLED_MASK and you can do this
everywhere, and get the same benefits you would have from
#ifdefs:
if (cpu_feature_enabled(X86_FEATURE_MPX))
do_some_mpx_thing();
We need a new function and *not* a modification to cpu_has()
because there are cases where we actually need to check the CPU
itself, despite what features the kernel supports. The best
example of this is a hypervisor which has no control over what
features its guests are using and where the guest does not depend
on the host for support.
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Link: http://lkml.kernel.org/r/20140911211513.9E35E931@viggo.jf.intel.com
Acked-by: Borislav Petkov <bp@suse.de>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2014-09-11 21:15:13 +00:00
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2011-03-12 11:50:10 +00:00
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#define cpu_has(c, bit) \
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(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
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2008-02-26 07:34:21 +00:00
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test_cpu_cap(c, bit))
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2011-03-12 11:50:10 +00:00
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#define this_cpu_has(bit) \
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(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
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x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability))
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x86: Introduce disabled-features
I believe the REQUIRED_MASK aproach was taken so that it was
easier to consult in assembly (arch/x86/kernel/verify_cpu.S).
DISABLED_MASK does not have the same restriction, but I
implemented it the same way for consistency.
We have a REQUIRED_MASK... which does two things:
1. Keeps a list of cpuid bits to check in very early boot and
refuse to boot if those are not present.
2. Consulted during cpu_has() checks, which allows us to
optimize out things at compile-time. In other words, if we
*KNOW* we will not boot with the feature off, then we can
safely assume that it will be present forever.
But, we don't have a similar mechanism for CPU features which
may be present but that we know we will not use. We simply
use our existing mechanisms to repeatedly check the status of
the bit at runtime (well, the alternatives patching helps here
but it does not provide compile-time optimization).
Adding a feature to disabled-features.h allows the bit to be
checked via a new macro: cpu_feature_enabled(). Note that
for features in DISABLED_MASK, checks with this macro have
all of the benefits of an #ifdef. Before, we would have done
this in a header:
#ifdef CONFIG_X86_INTEL_MPX
#define cpu_has_mpx cpu_has(X86_FEATURE_MPX)
#else
#define cpu_has_mpx 0
#endif
and this in the code:
if (cpu_has_mpx)
do_some_mpx_thing();
Now, just add your feature to DISABLED_MASK and you can do this
everywhere, and get the same benefits you would have from
#ifdefs:
if (cpu_feature_enabled(X86_FEATURE_MPX))
do_some_mpx_thing();
We need a new function and *not* a modification to cpu_has()
because there are cases where we actually need to check the CPU
itself, despite what features the kernel supports. The best
example of this is a hypervisor which has no control over what
features its guests are using and where the guest does not depend
on the host for support.
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Link: http://lkml.kernel.org/r/20140911211513.9E35E931@viggo.jf.intel.com
Acked-by: Borislav Petkov <bp@suse.de>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2014-09-11 21:15:13 +00:00
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/*
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* This macro is for detection of features which need kernel
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* infrastructure to be used. It may *not* directly test the CPU
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* itself. Use the cpu_has() family if you want true runtime
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* testing of CPU features, like in hypervisor code where you are
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* supporting a possible guest feature where host support for it
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* is not relevant.
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*/
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#define cpu_feature_enabled(bit) \
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2016-02-15 23:19:18 +00:00
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(__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : static_cpu_has(bit))
|
x86: Introduce disabled-features
I believe the REQUIRED_MASK aproach was taken so that it was
easier to consult in assembly (arch/x86/kernel/verify_cpu.S).
DISABLED_MASK does not have the same restriction, but I
implemented it the same way for consistency.
We have a REQUIRED_MASK... which does two things:
1. Keeps a list of cpuid bits to check in very early boot and
refuse to boot if those are not present.
2. Consulted during cpu_has() checks, which allows us to
optimize out things at compile-time. In other words, if we
*KNOW* we will not boot with the feature off, then we can
safely assume that it will be present forever.
But, we don't have a similar mechanism for CPU features which
may be present but that we know we will not use. We simply
use our existing mechanisms to repeatedly check the status of
the bit at runtime (well, the alternatives patching helps here
but it does not provide compile-time optimization).
Adding a feature to disabled-features.h allows the bit to be
checked via a new macro: cpu_feature_enabled(). Note that
for features in DISABLED_MASK, checks with this macro have
all of the benefits of an #ifdef. Before, we would have done
this in a header:
#ifdef CONFIG_X86_INTEL_MPX
#define cpu_has_mpx cpu_has(X86_FEATURE_MPX)
#else
#define cpu_has_mpx 0
#endif
and this in the code:
if (cpu_has_mpx)
do_some_mpx_thing();
Now, just add your feature to DISABLED_MASK and you can do this
everywhere, and get the same benefits you would have from
#ifdefs:
if (cpu_feature_enabled(X86_FEATURE_MPX))
do_some_mpx_thing();
We need a new function and *not* a modification to cpu_has()
because there are cases where we actually need to check the CPU
itself, despite what features the kernel supports. The best
example of this is a hypervisor which has no control over what
features its guests are using and where the guest does not depend
on the host for support.
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Link: http://lkml.kernel.org/r/20140911211513.9E35E931@viggo.jf.intel.com
Acked-by: Borislav Petkov <bp@suse.de>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2014-09-11 21:15:13 +00:00
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|
2008-01-30 12:30:07 +00:00
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#define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit)
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2008-01-30 12:30:55 +00:00
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#define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability))
|
2017-10-13 21:56:42 +00:00
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extern void setup_clear_cpu_cap(unsigned int bit);
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extern void clear_cpu_cap(struct cpuinfo_x86 *c, unsigned int bit);
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|
2008-01-30 12:33:20 +00:00
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#define setup_force_cpu_cap(bit) do { \
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|
set_cpu_cap(&boot_cpu_data, bit); \
|
2009-05-10 06:47:42 +00:00
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|
set_bit(bit, (unsigned long *)cpu_caps_set); \
|
2008-01-30 12:33:20 +00:00
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} while (0)
|
2008-01-30 12:30:55 +00:00
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|
2017-12-04 14:07:32 +00:00
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#define setup_force_cpu_bug(bit) setup_force_cpu_cap(bit)
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2016-01-27 08:43:25 +00:00
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|
#if defined(CC_HAVE_ASM_GOTO) && defined(CONFIG_X86_FAST_FEATURE_TESTS)
|
2010-05-12 00:47:07 +00:00
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|
/*
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* Static testing of CPU features. Used the same as boot_cpu_has().
|
2016-01-27 08:43:25 +00:00
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|
* These will statically patch the target code for additional
|
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* performance.
|
2010-05-12 00:47:07 +00:00
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*/
|
2016-01-26 21:12:05 +00:00
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|
static __always_inline __pure bool _static_cpu_has(u16 bit)
|
2013-06-09 10:07:33 +00:00
|
|
|
{
|
2016-01-27 08:45:25 +00:00
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|
asm_volatile_goto("1: jmp 6f\n"
|
2013-06-09 10:07:33 +00:00
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"2:\n"
|
2014-12-27 09:41:52 +00:00
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".skip -(((5f-4f) - (2b-1b)) > 0) * "
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"((5f-4f) - (2b-1b)),0x90\n"
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"3:\n"
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2013-06-09 10:07:33 +00:00
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".section .altinstructions,\"a\"\n"
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" .long 1b - .\n" /* src offset */
|
2014-12-27 09:41:52 +00:00
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" .long 4f - .\n" /* repl offset */
|
2013-06-09 10:07:33 +00:00
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" .word %P1\n" /* always replace */
|
2014-12-27 09:41:52 +00:00
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" .byte 3b - 1b\n" /* src len */
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" .byte 5f - 4f\n" /* repl len */
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" .byte 3b - 2b\n" /* pad len */
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2013-06-09 10:07:33 +00:00
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".previous\n"
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".section .altinstr_replacement,\"ax\"\n"
|
x86/alternatives: Make JMPs more robust
Up until now we had to pay attention to relative JMPs in alternatives
about how their relative offset gets computed so that the jump target
is still correct. Or, as it is the case for near CALLs (opcode e8), we
still have to go and readjust the offset at patching time.
What is more, the static_cpu_has_safe() facility had to forcefully
generate 5-byte JMPs since we couldn't rely on the compiler to generate
properly sized ones so we had to force the longest ones. Worse than
that, sometimes it would generate a replacement JMP which is longer than
the original one, thus overwriting the beginning of the next instruction
at patching time.
So, in order to alleviate all that and make using JMPs more
straight-forward we go and pad the original instruction in an
alternative block with NOPs at build time, should the replacement(s) be
longer. This way, alternatives users shouldn't pay special attention
so that original and replacement instruction sizes are fine but the
assembler would simply add padding where needed and not do anything
otherwise.
As a second aspect, we go and recompute JMPs at patching time so that we
can try to make 5-byte JMPs into two-byte ones if possible. If not, we
still have to recompute the offsets as the replacement JMP gets put far
away in the .altinstr_replacement section leading to a wrong offset if
copied verbatim.
For example, on a locally generated kernel image
old insn VA: 0xffffffff810014bd, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff810014bd: eb 21 jmp ffffffff810014e0
repl insn: size: 5
ffffffff81d0b23c: e9 b1 62 2f ff jmpq ffffffff810014f2
gets corrected to a 2-byte JMP:
apply_alternatives: feat: 3*32+21, old: (ffffffff810014bd, len: 2), repl: (ffffffff81d0b23c, len: 5)
alt_insn: e9 b1 62 2f ff
recompute_jumps: next_rip: ffffffff81d0b241, tgt_rip: ffffffff810014f2, new_displ: 0x00000033, ret len: 2
converted to: eb 33 90 90 90
and a 5-byte JMP:
old insn VA: 0xffffffff81001516, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff81001516: eb 30 jmp ffffffff81001548
repl insn: size: 5
ffffffff81d0b241: e9 10 63 2f ff jmpq ffffffff81001556
gets shortened into a two-byte one:
apply_alternatives: feat: 3*32+21, old: (ffffffff81001516, len: 2), repl: (ffffffff81d0b241, len: 5)
alt_insn: e9 10 63 2f ff
recompute_jumps: next_rip: ffffffff81d0b246, tgt_rip: ffffffff81001556, new_displ: 0x0000003e, ret len: 2
converted to: eb 3e 90 90 90
... and so on.
This leads to a net win of around
40ish replacements * 3 bytes savings =~ 120 bytes of I$
on an AMD guest which means some savings of precious instruction cache
bandwidth. The padding to the shorter 2-byte JMPs are single-byte NOPs
which on smart microarchitectures means discarding NOPs at decode time
and thus freeing up execution bandwidth.
Signed-off-by: Borislav Petkov <bp@suse.de>
2015-01-05 12:48:41 +00:00
|
|
|
"4: jmp %l[t_no]\n"
|
2014-12-27 09:41:52 +00:00
|
|
|
"5:\n"
|
2013-06-09 10:07:33 +00:00
|
|
|
".previous\n"
|
|
|
|
|
".section .altinstructions,\"a\"\n"
|
|
|
|
|
" .long 1b - .\n" /* src offset */
|
|
|
|
|
" .long 0\n" /* no replacement */
|
|
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|
|
" .word %P0\n" /* feature bit */
|
2014-12-27 09:41:52 +00:00
|
|
|
" .byte 3b - 1b\n" /* src len */
|
2013-06-09 10:07:33 +00:00
|
|
|
" .byte 0\n" /* repl len */
|
2014-12-27 09:41:52 +00:00
|
|
|
" .byte 0\n" /* pad len */
|
2013-06-09 10:07:33 +00:00
|
|
|
".previous\n"
|
2016-01-27 08:45:25 +00:00
|
|
|
".section .altinstr_aux,\"ax\"\n"
|
|
|
|
|
"6:\n"
|
|
|
|
|
" testb %[bitnum],%[cap_byte]\n"
|
|
|
|
|
" jnz %l[t_yes]\n"
|
|
|
|
|
" jmp %l[t_no]\n"
|
|
|
|
|
".previous\n"
|
|
|
|
|
: : "i" (bit), "i" (X86_FEATURE_ALWAYS),
|
|
|
|
|
[bitnum] "i" (1 << (bit & 7)),
|
|
|
|
|
[cap_byte] "m" (((const char *)boot_cpu_data.x86_capability)[bit >> 3])
|
|
|
|
|
: : t_yes, t_no);
|
|
|
|
|
t_yes:
|
2013-06-09 10:07:33 +00:00
|
|
|
return true;
|
|
|
|
|
t_no:
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2016-01-26 21:12:05 +00:00
|
|
|
#define static_cpu_has(bit) \
|
2013-06-09 10:07:33 +00:00
|
|
|
( \
|
|
|
|
|
__builtin_constant_p(boot_cpu_has(bit)) ? \
|
|
|
|
|
boot_cpu_has(bit) : \
|
2016-01-26 21:12:05 +00:00
|
|
|
_static_cpu_has(bit) \
|
2013-06-09 10:07:33 +00:00
|
|
|
)
|
2010-05-27 19:02:00 +00:00
|
|
|
#else
|
|
|
|
|
/*
|
2016-01-27 08:43:25 +00:00
|
|
|
* Fall back to dynamic for gcc versions which don't support asm goto. Should be
|
|
|
|
|
* a minority now anyway.
|
2010-05-27 19:02:00 +00:00
|
|
|
*/
|
2013-06-09 10:07:33 +00:00
|
|
|
#define static_cpu_has(bit) boot_cpu_has(bit)
|
2010-05-27 19:02:00 +00:00
|
|
|
#endif
|
2010-05-12 00:47:07 +00:00
|
|
|
|
2014-06-17 22:06:23 +00:00
|
|
|
#define cpu_has_bug(c, bit) cpu_has(c, (bit))
|
|
|
|
|
#define set_cpu_bug(c, bit) set_cpu_cap(c, (bit))
|
|
|
|
|
#define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit))
|
2013-03-20 14:07:23 +00:00
|
|
|
|
2014-06-17 22:06:23 +00:00
|
|
|
#define static_cpu_has_bug(bit) static_cpu_has((bit))
|
|
|
|
|
#define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit))
|
2016-12-09 18:29:08 +00:00
|
|
|
#define boot_cpu_set_bug(bit) set_cpu_cap(&boot_cpu_data, (bit))
|
2013-03-20 14:07:23 +00:00
|
|
|
|
2014-06-17 22:06:23 +00:00
|
|
|
#define MAX_CPU_FEATURES (NCAPINTS * 32)
|
|
|
|
|
#define cpu_have_feature boot_cpu_has
|
2014-02-08 12:34:10 +00:00
|
|
|
|
2014-06-17 22:06:23 +00:00
|
|
|
#define CPU_FEATURE_TYPEFMT "x86,ven%04Xfam%04Xmod%04X"
|
|
|
|
|
#define CPU_FEATURE_TYPEVAL boot_cpu_data.x86_vendor, boot_cpu_data.x86, \
|
|
|
|
|
boot_cpu_data.x86_model
|
2014-02-08 12:34:10 +00:00
|
|
|
|
2008-02-04 15:48:00 +00:00
|
|
|
#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
|
2008-10-23 05:26:29 +00:00
|
|
|
#endif /* _ASM_X86_CPUFEATURE_H */
|