License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0 */
|
perf: Do the big rename: Performance Counters -> Performance Events
Bye-bye Performance Counters, welcome Performance Events!
In the past few months the perfcounters subsystem has grown out its
initial role of counting hardware events, and has become (and is
becoming) a much broader generic event enumeration, reporting, logging,
monitoring, analysis facility.
Naming its core object 'perf_counter' and naming the subsystem
'perfcounters' has become more and more of a misnomer. With pending
code like hw-breakpoints support the 'counter' name is less and
less appropriate.
All in one, we've decided to rename the subsystem to 'performance
events' and to propagate this rename through all fields, variables
and API names. (in an ABI compatible fashion)
The word 'event' is also a bit shorter than 'counter' - which makes
it slightly more convenient to write/handle as well.
Thanks goes to Stephane Eranian who first observed this misnomer and
suggested a rename.
User-space tooling and ABI compatibility is not affected - this patch
should be function-invariant. (Also, defconfigs were not touched to
keep the size down.)
This patch has been generated via the following script:
FILES=$(find * -type f | grep -vE 'oprofile|[^K]config')
sed -i \
-e 's/PERF_EVENT_/PERF_RECORD_/g' \
-e 's/PERF_COUNTER/PERF_EVENT/g' \
-e 's/perf_counter/perf_event/g' \
-e 's/nb_counters/nb_events/g' \
-e 's/swcounter/swevent/g' \
-e 's/tpcounter_event/tp_event/g' \
$FILES
for N in $(find . -name perf_counter.[ch]); do
M=$(echo $N | sed 's/perf_counter/perf_event/g')
mv $N $M
done
FILES=$(find . -name perf_event.*)
sed -i \
-e 's/COUNTER_MASK/REG_MASK/g' \
-e 's/COUNTER/EVENT/g' \
-e 's/\<event\>/event_id/g' \
-e 's/counter/event/g' \
-e 's/Counter/Event/g' \
$FILES
... to keep it as correct as possible. This script can also be
used by anyone who has pending perfcounters patches - it converts
a Linux kernel tree over to the new naming. We tried to time this
change to the point in time where the amount of pending patches
is the smallest: the end of the merge window.
Namespace clashes were fixed up in a preparatory patch - and some
stylistic fallout will be fixed up in a subsequent patch.
( NOTE: 'counters' are still the proper terminology when we deal
with hardware registers - and these sed scripts are a bit
over-eager in renaming them. I've undone some of that, but
in case there's something left where 'counter' would be
better than 'event' we can undo that on an individual basis
instead of touching an otherwise nicely automated patch. )
Suggested-by: Stephane Eranian <eranian@google.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Paul Mackerras <paulus@samba.org>
Reviewed-by: Arjan van de Ven <arjan@linux.intel.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: <linux-arch@vger.kernel.org>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-09-21 10:02:48 +00:00
|
|
|
#ifndef _ASM_X86_PERF_EVENT_H
|
|
|
|
#define _ASM_X86_PERF_EVENT_H
|
2007-10-15 11:57:47 +00:00
|
|
|
|
2008-12-17 08:09:13 +00:00
|
|
|
/*
|
perf: Do the big rename: Performance Counters -> Performance Events
Bye-bye Performance Counters, welcome Performance Events!
In the past few months the perfcounters subsystem has grown out its
initial role of counting hardware events, and has become (and is
becoming) a much broader generic event enumeration, reporting, logging,
monitoring, analysis facility.
Naming its core object 'perf_counter' and naming the subsystem
'perfcounters' has become more and more of a misnomer. With pending
code like hw-breakpoints support the 'counter' name is less and
less appropriate.
All in one, we've decided to rename the subsystem to 'performance
events' and to propagate this rename through all fields, variables
and API names. (in an ABI compatible fashion)
The word 'event' is also a bit shorter than 'counter' - which makes
it slightly more convenient to write/handle as well.
Thanks goes to Stephane Eranian who first observed this misnomer and
suggested a rename.
User-space tooling and ABI compatibility is not affected - this patch
should be function-invariant. (Also, defconfigs were not touched to
keep the size down.)
This patch has been generated via the following script:
FILES=$(find * -type f | grep -vE 'oprofile|[^K]config')
sed -i \
-e 's/PERF_EVENT_/PERF_RECORD_/g' \
-e 's/PERF_COUNTER/PERF_EVENT/g' \
-e 's/perf_counter/perf_event/g' \
-e 's/nb_counters/nb_events/g' \
-e 's/swcounter/swevent/g' \
-e 's/tpcounter_event/tp_event/g' \
$FILES
for N in $(find . -name perf_counter.[ch]); do
M=$(echo $N | sed 's/perf_counter/perf_event/g')
mv $N $M
done
FILES=$(find . -name perf_event.*)
sed -i \
-e 's/COUNTER_MASK/REG_MASK/g' \
-e 's/COUNTER/EVENT/g' \
-e 's/\<event\>/event_id/g' \
-e 's/counter/event/g' \
-e 's/Counter/Event/g' \
$FILES
... to keep it as correct as possible. This script can also be
used by anyone who has pending perfcounters patches - it converts
a Linux kernel tree over to the new naming. We tried to time this
change to the point in time where the amount of pending patches
is the smallest: the end of the merge window.
Namespace clashes were fixed up in a preparatory patch - and some
stylistic fallout will be fixed up in a subsequent patch.
( NOTE: 'counters' are still the proper terminology when we deal
with hardware registers - and these sed scripts are a bit
over-eager in renaming them. I've undone some of that, but
in case there's something left where 'counter' would be
better than 'event' we can undo that on an individual basis
instead of touching an otherwise nicely automated patch. )
Suggested-by: Stephane Eranian <eranian@google.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Paul Mackerras <paulus@samba.org>
Reviewed-by: Arjan van de Ven <arjan@linux.intel.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: <linux-arch@vger.kernel.org>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-09-21 10:02:48 +00:00
|
|
|
* Performance event hw details:
|
2008-12-17 08:09:13 +00:00
|
|
|
*/
|
|
|
|
|
2012-06-20 18:46:33 +00:00
|
|
|
#define INTEL_PMC_MAX_GENERIC 32
|
2019-04-02 19:45:05 +00:00
|
|
|
#define INTEL_PMC_MAX_FIXED 4
|
2012-06-20 18:46:33 +00:00
|
|
|
#define INTEL_PMC_IDX_FIXED 32
|
2008-12-17 08:09:13 +00:00
|
|
|
|
2008-12-17 12:09:20 +00:00
|
|
|
#define X86_PMC_IDX_MAX 64
|
|
|
|
|
2008-12-03 09:39:53 +00:00
|
|
|
#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
|
|
|
|
#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
|
2007-10-15 11:57:47 +00:00
|
|
|
|
2008-12-03 09:39:53 +00:00
|
|
|
#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
|
|
|
|
#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
|
2007-10-15 11:57:47 +00:00
|
|
|
|
2010-03-30 09:28:21 +00:00
|
|
|
#define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
|
|
|
|
#define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
|
|
|
|
#define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16)
|
|
|
|
#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17)
|
|
|
|
#define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18)
|
2012-02-26 14:55:40 +00:00
|
|
|
#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL (1ULL << 19)
|
2010-03-30 09:28:21 +00:00
|
|
|
#define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20)
|
|
|
|
#define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21)
|
|
|
|
#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22)
|
|
|
|
#define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
|
|
|
|
#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
|
|
|
|
|
2013-06-18 00:36:48 +00:00
|
|
|
#define HSW_IN_TX (1ULL << 32)
|
|
|
|
#define HSW_IN_TX_CHECKPOINTED (1ULL << 33)
|
perf/x86/intel: Support adaptive PEBS v4
Adaptive PEBS is a new way to report PEBS sampling information. Instead
of a fixed size record for all PEBS events it allows to configure the
PEBS record to only include the information needed. Events can then opt
in to use such an extended record, or stay with a basic record which
only contains the IP.
The major new feature is to support LBRs in PEBS record.
Besides normal LBR, this allows (much faster) large PEBS, while still
supporting callstacks through callstack LBR. So essentially a lot of
profiling can now be done without frequent interrupts, dropping the
overhead significantly.
The main requirement still is to use a period, and not use frequency
mode, because frequency mode requires reevaluating the frequency on each
overflow.
The floating point state (XMM) is also supported, which allows efficient
profiling of FP function arguments.
Introduce specific drain function to handle variable length records.
Use a new callback to parse the new record format, and also handle the
STATUS field now being at a different offset.
Add code to set up the configuration register. Since there is only a
single register, all events either get the full super set of all events,
or only the basic record.
Originally-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: acme@kernel.org
Cc: jolsa@kernel.org
Link: https://lkml.kernel.org/r/20190402194509.2832-6-kan.liang@linux.intel.com
[ Renamed GPRS => GP. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-04-02 19:45:02 +00:00
|
|
|
#define ICL_EVENTSEL_ADAPTIVE (1ULL << 34)
|
|
|
|
#define ICL_FIXED_0_ADAPTIVE (1ULL << 32)
|
2013-06-18 00:36:48 +00:00
|
|
|
|
2013-02-06 17:26:29 +00:00
|
|
|
#define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36)
|
2013-02-06 17:26:26 +00:00
|
|
|
#define AMD64_EVENTSEL_GUESTONLY (1ULL << 40)
|
|
|
|
#define AMD64_EVENTSEL_HOSTONLY (1ULL << 41)
|
2011-10-05 12:01:17 +00:00
|
|
|
|
2013-02-06 17:26:29 +00:00
|
|
|
#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37
|
|
|
|
#define AMD64_EVENTSEL_INT_CORE_SEL_MASK \
|
|
|
|
(0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
|
|
|
|
|
2010-03-30 09:28:21 +00:00
|
|
|
#define AMD64_EVENTSEL_EVENT \
|
|
|
|
(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
|
|
|
|
#define INTEL_ARCH_EVENT_MASK \
|
|
|
|
(ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
|
|
|
|
|
2018-09-27 15:51:55 +00:00
|
|
|
#define AMD64_L3_SLICE_SHIFT 48
|
|
|
|
#define AMD64_L3_SLICE_MASK \
|
2020-03-13 23:10:24 +00:00
|
|
|
(0xFULL << AMD64_L3_SLICE_SHIFT)
|
|
|
|
#define AMD64_L3_SLICEID_MASK \
|
|
|
|
(0x7ULL << AMD64_L3_SLICE_SHIFT)
|
2018-09-27 15:51:55 +00:00
|
|
|
|
|
|
|
#define AMD64_L3_THREAD_SHIFT 56
|
|
|
|
#define AMD64_L3_THREAD_MASK \
|
2020-03-13 23:10:24 +00:00
|
|
|
(0xFFULL << AMD64_L3_THREAD_SHIFT)
|
|
|
|
#define AMD64_L3_F19H_THREAD_MASK \
|
|
|
|
(0x3ULL << AMD64_L3_THREAD_SHIFT)
|
|
|
|
|
|
|
|
#define AMD64_L3_EN_ALL_CORES BIT_ULL(47)
|
|
|
|
#define AMD64_L3_EN_ALL_SLICES BIT_ULL(46)
|
|
|
|
|
|
|
|
#define AMD64_L3_COREID_SHIFT 42
|
|
|
|
#define AMD64_L3_COREID_MASK \
|
|
|
|
(0x7ULL << AMD64_L3_COREID_SHIFT)
|
2018-09-27 15:51:55 +00:00
|
|
|
|
2010-03-30 09:28:21 +00:00
|
|
|
#define X86_RAW_EVENT_MASK \
|
|
|
|
(ARCH_PERFMON_EVENTSEL_EVENT | \
|
|
|
|
ARCH_PERFMON_EVENTSEL_UMASK | \
|
|
|
|
ARCH_PERFMON_EVENTSEL_EDGE | \
|
|
|
|
ARCH_PERFMON_EVENTSEL_INV | \
|
|
|
|
ARCH_PERFMON_EVENTSEL_CMASK)
|
2014-08-11 19:27:10 +00:00
|
|
|
#define X86_ALL_EVENT_FLAGS \
|
|
|
|
(ARCH_PERFMON_EVENTSEL_EDGE | \
|
|
|
|
ARCH_PERFMON_EVENTSEL_INV | \
|
|
|
|
ARCH_PERFMON_EVENTSEL_CMASK | \
|
|
|
|
ARCH_PERFMON_EVENTSEL_ANY | \
|
|
|
|
ARCH_PERFMON_EVENTSEL_PIN_CONTROL | \
|
|
|
|
HSW_IN_TX | \
|
|
|
|
HSW_IN_TX_CHECKPOINTED)
|
2010-03-30 09:28:21 +00:00
|
|
|
#define AMD64_RAW_EVENT_MASK \
|
|
|
|
(X86_RAW_EVENT_MASK | \
|
|
|
|
AMD64_EVENTSEL_EVENT)
|
2013-02-06 17:26:29 +00:00
|
|
|
#define AMD64_RAW_EVENT_MASK_NB \
|
|
|
|
(AMD64_EVENTSEL_EVENT | \
|
|
|
|
ARCH_PERFMON_EVENTSEL_UMASK)
|
2011-09-21 09:30:17 +00:00
|
|
|
#define AMD64_NUM_COUNTERS 4
|
2012-06-20 18:46:35 +00:00
|
|
|
#define AMD64_NUM_COUNTERS_CORE 6
|
2013-02-06 17:26:29 +00:00
|
|
|
#define AMD64_NUM_COUNTERS_NB 4
|
2009-10-06 14:42:08 +00:00
|
|
|
|
2011-09-21 09:30:17 +00:00
|
|
|
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
|
2008-12-03 09:39:53 +00:00
|
|
|
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
|
2011-09-21 09:30:17 +00:00
|
|
|
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
|
2007-10-15 11:57:47 +00:00
|
|
|
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
|
2008-12-03 09:39:53 +00:00
|
|
|
(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
|
|
|
|
|
2011-09-21 09:30:17 +00:00
|
|
|
#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
|
2011-11-10 12:57:26 +00:00
|
|
|
#define ARCH_PERFMON_EVENTS_COUNT 7
|
2007-10-15 11:57:47 +00:00
|
|
|
|
perf/x86/intel: Support adaptive PEBS v4
Adaptive PEBS is a new way to report PEBS sampling information. Instead
of a fixed size record for all PEBS events it allows to configure the
PEBS record to only include the information needed. Events can then opt
in to use such an extended record, or stay with a basic record which
only contains the IP.
The major new feature is to support LBRs in PEBS record.
Besides normal LBR, this allows (much faster) large PEBS, while still
supporting callstacks through callstack LBR. So essentially a lot of
profiling can now be done without frequent interrupts, dropping the
overhead significantly.
The main requirement still is to use a period, and not use frequency
mode, because frequency mode requires reevaluating the frequency on each
overflow.
The floating point state (XMM) is also supported, which allows efficient
profiling of FP function arguments.
Introduce specific drain function to handle variable length records.
Use a new callback to parse the new record format, and also handle the
STATUS field now being at a different offset.
Add code to set up the configuration register. Since there is only a
single register, all events either get the full super set of all events,
or only the basic record.
Originally-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: acme@kernel.org
Cc: jolsa@kernel.org
Link: https://lkml.kernel.org/r/20190402194509.2832-6-kan.liang@linux.intel.com
[ Renamed GPRS => GP. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-04-02 19:45:02 +00:00
|
|
|
#define PEBS_DATACFG_MEMINFO BIT_ULL(0)
|
|
|
|
#define PEBS_DATACFG_GP BIT_ULL(1)
|
|
|
|
#define PEBS_DATACFG_XMMS BIT_ULL(2)
|
|
|
|
#define PEBS_DATACFG_LBRS BIT_ULL(3)
|
|
|
|
#define PEBS_DATACFG_LBR_SHIFT 24
|
|
|
|
|
2008-12-17 08:09:13 +00:00
|
|
|
/*
|
|
|
|
* Intel "Architectural Performance Monitoring" CPUID
|
|
|
|
* detection/enumeration details:
|
|
|
|
*/
|
2007-10-15 11:57:47 +00:00
|
|
|
union cpuid10_eax {
|
|
|
|
struct {
|
|
|
|
unsigned int version_id:8;
|
2010-03-29 16:36:50 +00:00
|
|
|
unsigned int num_counters:8;
|
2007-10-15 11:57:47 +00:00
|
|
|
unsigned int bit_width:8;
|
|
|
|
unsigned int mask_length:8;
|
|
|
|
} split;
|
|
|
|
unsigned int full;
|
|
|
|
};
|
|
|
|
|
2011-11-10 12:57:26 +00:00
|
|
|
union cpuid10_ebx {
|
|
|
|
struct {
|
|
|
|
unsigned int no_unhalted_core_cycles:1;
|
|
|
|
unsigned int no_instructions_retired:1;
|
|
|
|
unsigned int no_unhalted_reference_cycles:1;
|
|
|
|
unsigned int no_llc_reference:1;
|
|
|
|
unsigned int no_llc_misses:1;
|
|
|
|
unsigned int no_branch_instruction_retired:1;
|
|
|
|
unsigned int no_branch_misses_retired:1;
|
|
|
|
} split;
|
|
|
|
unsigned int full;
|
|
|
|
};
|
|
|
|
|
2008-12-17 09:51:15 +00:00
|
|
|
union cpuid10_edx {
|
|
|
|
struct {
|
2010-06-03 19:00:31 +00:00
|
|
|
unsigned int num_counters_fixed:5;
|
|
|
|
unsigned int bit_width_fixed:8;
|
|
|
|
unsigned int reserved:19;
|
2008-12-17 09:51:15 +00:00
|
|
|
} split;
|
|
|
|
unsigned int full;
|
|
|
|
};
|
|
|
|
|
2020-07-03 12:49:14 +00:00
|
|
|
/*
|
|
|
|
* Intel Architectural LBR CPUID detection/enumeration details:
|
|
|
|
*/
|
|
|
|
union cpuid28_eax {
|
|
|
|
struct {
|
|
|
|
/* Supported LBR depth values */
|
|
|
|
unsigned int lbr_depth_mask:8;
|
|
|
|
unsigned int reserved:22;
|
|
|
|
/* Deep C-state Reset */
|
|
|
|
unsigned int lbr_deep_c_reset:1;
|
|
|
|
/* IP values contain LIP */
|
|
|
|
unsigned int lbr_lip:1;
|
|
|
|
} split;
|
|
|
|
unsigned int full;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cpuid28_ebx {
|
|
|
|
struct {
|
|
|
|
/* CPL Filtering Supported */
|
|
|
|
unsigned int lbr_cpl:1;
|
|
|
|
/* Branch Filtering Supported */
|
|
|
|
unsigned int lbr_filter:1;
|
|
|
|
/* Call-stack Mode Supported */
|
|
|
|
unsigned int lbr_call_stack:1;
|
|
|
|
} split;
|
|
|
|
unsigned int full;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cpuid28_ecx {
|
|
|
|
struct {
|
|
|
|
/* Mispredict Bit Supported */
|
|
|
|
unsigned int lbr_mispred:1;
|
|
|
|
/* Timed LBRs Supported */
|
|
|
|
unsigned int lbr_timed_lbr:1;
|
|
|
|
/* Branch Type Field Supported */
|
|
|
|
unsigned int lbr_br_type:1;
|
|
|
|
} split;
|
|
|
|
unsigned int full;
|
|
|
|
};
|
|
|
|
|
2011-11-10 12:57:27 +00:00
|
|
|
struct x86_pmu_capability {
|
|
|
|
int version;
|
|
|
|
int num_counters_gp;
|
|
|
|
int num_counters_fixed;
|
|
|
|
int bit_width_gp;
|
|
|
|
int bit_width_fixed;
|
|
|
|
unsigned int events_mask;
|
|
|
|
int events_mask_len;
|
|
|
|
};
|
2008-12-17 09:51:15 +00:00
|
|
|
|
|
|
|
/*
|
perf: Do the big rename: Performance Counters -> Performance Events
Bye-bye Performance Counters, welcome Performance Events!
In the past few months the perfcounters subsystem has grown out its
initial role of counting hardware events, and has become (and is
becoming) a much broader generic event enumeration, reporting, logging,
monitoring, analysis facility.
Naming its core object 'perf_counter' and naming the subsystem
'perfcounters' has become more and more of a misnomer. With pending
code like hw-breakpoints support the 'counter' name is less and
less appropriate.
All in one, we've decided to rename the subsystem to 'performance
events' and to propagate this rename through all fields, variables
and API names. (in an ABI compatible fashion)
The word 'event' is also a bit shorter than 'counter' - which makes
it slightly more convenient to write/handle as well.
Thanks goes to Stephane Eranian who first observed this misnomer and
suggested a rename.
User-space tooling and ABI compatibility is not affected - this patch
should be function-invariant. (Also, defconfigs were not touched to
keep the size down.)
This patch has been generated via the following script:
FILES=$(find * -type f | grep -vE 'oprofile|[^K]config')
sed -i \
-e 's/PERF_EVENT_/PERF_RECORD_/g' \
-e 's/PERF_COUNTER/PERF_EVENT/g' \
-e 's/perf_counter/perf_event/g' \
-e 's/nb_counters/nb_events/g' \
-e 's/swcounter/swevent/g' \
-e 's/tpcounter_event/tp_event/g' \
$FILES
for N in $(find . -name perf_counter.[ch]); do
M=$(echo $N | sed 's/perf_counter/perf_event/g')
mv $N $M
done
FILES=$(find . -name perf_event.*)
sed -i \
-e 's/COUNTER_MASK/REG_MASK/g' \
-e 's/COUNTER/EVENT/g' \
-e 's/\<event\>/event_id/g' \
-e 's/counter/event/g' \
-e 's/Counter/Event/g' \
$FILES
... to keep it as correct as possible. This script can also be
used by anyone who has pending perfcounters patches - it converts
a Linux kernel tree over to the new naming. We tried to time this
change to the point in time where the amount of pending patches
is the smallest: the end of the merge window.
Namespace clashes were fixed up in a preparatory patch - and some
stylistic fallout will be fixed up in a subsequent patch.
( NOTE: 'counters' are still the proper terminology when we deal
with hardware registers - and these sed scripts are a bit
over-eager in renaming them. I've undone some of that, but
in case there's something left where 'counter' would be
better than 'event' we can undo that on an individual basis
instead of touching an otherwise nicely automated patch. )
Suggested-by: Stephane Eranian <eranian@google.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Paul Mackerras <paulus@samba.org>
Reviewed-by: Arjan van de Ven <arjan@linux.intel.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: <linux-arch@vger.kernel.org>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-09-21 10:02:48 +00:00
|
|
|
* Fixed-purpose performance events:
|
2008-12-17 09:51:15 +00:00
|
|
|
*/
|
|
|
|
|
2020-07-23 17:11:12 +00:00
|
|
|
/* RDPMC offset for Fixed PMCs */
|
|
|
|
#define INTEL_PMC_FIXED_RDPMC_BASE (1 << 30)
|
2020-07-23 17:11:13 +00:00
|
|
|
#define INTEL_PMC_FIXED_RDPMC_METRICS (1 << 29)
|
2020-07-23 17:11:12 +00:00
|
|
|
|
2008-12-17 12:09:20 +00:00
|
|
|
/*
|
2020-07-23 17:11:06 +00:00
|
|
|
* All the fixed-mode PMCs are configured via this single MSR:
|
2008-12-17 12:09:20 +00:00
|
|
|
*/
|
2011-12-10 23:28:51 +00:00
|
|
|
#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
|
2008-12-17 12:09:20 +00:00
|
|
|
|
|
|
|
/*
|
2020-07-23 17:11:06 +00:00
|
|
|
* There is no event-code assigned to the fixed-mode PMCs.
|
|
|
|
*
|
|
|
|
* For a fixed-mode PMC, which has an equivalent event on a general-purpose
|
|
|
|
* PMC, the event-code of the equivalent event is used for the fixed-mode PMC,
|
|
|
|
* e.g., Instr_Retired.Any and CPU_CLK_Unhalted.Core.
|
|
|
|
*
|
|
|
|
* For a fixed-mode PMC, which doesn't have an equivalent event, a
|
|
|
|
* pseudo-encoding is used, e.g., CPU_CLK_Unhalted.Ref and TOPDOWN.SLOTS.
|
|
|
|
* The pseudo event-code for a fixed-mode PMC must be 0x00.
|
|
|
|
* The pseudo umask-code is 0xX. The X equals the index of the fixed
|
|
|
|
* counter + 1, e.g., the fixed counter 2 has the pseudo-encoding 0x0300.
|
|
|
|
*
|
|
|
|
* The counts are available in separate MSRs:
|
2008-12-17 12:09:20 +00:00
|
|
|
*/
|
|
|
|
|
2008-12-17 09:51:15 +00:00
|
|
|
/* Instr_Retired.Any: */
|
2011-12-10 23:28:51 +00:00
|
|
|
#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
|
2012-06-20 18:46:33 +00:00
|
|
|
#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0)
|
2008-12-17 09:51:15 +00:00
|
|
|
|
|
|
|
/* CPU_CLK_Unhalted.Core: */
|
2011-12-10 23:28:51 +00:00
|
|
|
#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
|
2012-06-20 18:46:33 +00:00
|
|
|
#define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1)
|
2008-12-17 09:51:15 +00:00
|
|
|
|
2020-07-23 17:11:06 +00:00
|
|
|
/* CPU_CLK_Unhalted.Ref: event=0x00,umask=0x3 (pseudo-encoding) */
|
2011-12-10 23:28:51 +00:00
|
|
|
#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
|
2012-06-20 18:46:33 +00:00
|
|
|
#define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2)
|
|
|
|
#define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
|
2008-12-17 09:51:15 +00:00
|
|
|
|
2020-07-23 17:11:06 +00:00
|
|
|
/* TOPDOWN.SLOTS: event=0x00,umask=0x4 (pseudo-encoding) */
|
|
|
|
#define MSR_ARCH_PERFMON_FIXED_CTR3 0x30c
|
|
|
|
#define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3)
|
|
|
|
#define INTEL_PMC_MSK_FIXED_SLOTS (1ULL << INTEL_PMC_IDX_FIXED_SLOTS)
|
|
|
|
|
2009-07-21 13:56:48 +00:00
|
|
|
/*
|
|
|
|
* We model BTS tracing as another fixed-mode PMC.
|
|
|
|
*
|
2020-07-23 17:11:07 +00:00
|
|
|
* We choose the value 47 for the fixed index of BTS, since lower
|
perf: Do the big rename: Performance Counters -> Performance Events
Bye-bye Performance Counters, welcome Performance Events!
In the past few months the perfcounters subsystem has grown out its
initial role of counting hardware events, and has become (and is
becoming) a much broader generic event enumeration, reporting, logging,
monitoring, analysis facility.
Naming its core object 'perf_counter' and naming the subsystem
'perfcounters' has become more and more of a misnomer. With pending
code like hw-breakpoints support the 'counter' name is less and
less appropriate.
All in one, we've decided to rename the subsystem to 'performance
events' and to propagate this rename through all fields, variables
and API names. (in an ABI compatible fashion)
The word 'event' is also a bit shorter than 'counter' - which makes
it slightly more convenient to write/handle as well.
Thanks goes to Stephane Eranian who first observed this misnomer and
suggested a rename.
User-space tooling and ABI compatibility is not affected - this patch
should be function-invariant. (Also, defconfigs were not touched to
keep the size down.)
This patch has been generated via the following script:
FILES=$(find * -type f | grep -vE 'oprofile|[^K]config')
sed -i \
-e 's/PERF_EVENT_/PERF_RECORD_/g' \
-e 's/PERF_COUNTER/PERF_EVENT/g' \
-e 's/perf_counter/perf_event/g' \
-e 's/nb_counters/nb_events/g' \
-e 's/swcounter/swevent/g' \
-e 's/tpcounter_event/tp_event/g' \
$FILES
for N in $(find . -name perf_counter.[ch]); do
M=$(echo $N | sed 's/perf_counter/perf_event/g')
mv $N $M
done
FILES=$(find . -name perf_event.*)
sed -i \
-e 's/COUNTER_MASK/REG_MASK/g' \
-e 's/COUNTER/EVENT/g' \
-e 's/\<event\>/event_id/g' \
-e 's/counter/event/g' \
-e 's/Counter/Event/g' \
$FILES
... to keep it as correct as possible. This script can also be
used by anyone who has pending perfcounters patches - it converts
a Linux kernel tree over to the new naming. We tried to time this
change to the point in time where the amount of pending patches
is the smallest: the end of the merge window.
Namespace clashes were fixed up in a preparatory patch - and some
stylistic fallout will be fixed up in a subsequent patch.
( NOTE: 'counters' are still the proper terminology when we deal
with hardware registers - and these sed scripts are a bit
over-eager in renaming them. I've undone some of that, but
in case there's something left where 'counter' would be
better than 'event' we can undo that on an individual basis
instead of touching an otherwise nicely automated patch. )
Suggested-by: Stephane Eranian <eranian@google.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Paul Mackerras <paulus@samba.org>
Reviewed-by: Arjan van de Ven <arjan@linux.intel.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: <linux-arch@vger.kernel.org>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-09-21 10:02:48 +00:00
|
|
|
* values are used by actual fixed events and higher values are used
|
2009-07-21 13:56:48 +00:00
|
|
|
* to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
|
|
|
|
*/
|
2020-07-23 17:11:07 +00:00
|
|
|
#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 15)
|
2020-07-23 17:11:05 +00:00
|
|
|
|
perf/x86/intel: Generic support for hardware TopDown metrics
Intro
=====
The TopDown Microarchitecture Analysis (TMA) Method is a structured
analysis methodology to identify critical performance bottlenecks in
out-of-order processors. Current perf has supported the method.
The method works well, but there is one problem. To collect the TopDown
events, several GP counters have to be used. If a user wants to collect
other events at the same time, the multiplexing probably be triggered,
which impacts the accuracy.
To free up the scarce GP counters, the hardware TopDown metrics feature
is introduced from Ice Lake. The hardware implements an additional
"metrics" register and a new Fixed Counter 3 that measures pipeline
"slots". The TopDown events can be calculated from them instead.
Events
======
The level 1 TopDown has four metrics. There is no event-code assigned to
the TopDown metrics. Four metric events are exported as separate perf
events, which map to the internal "metrics" counter register. Those
events do not exist in hardware, but can be allocated by the scheduler.
For the event mapping, a special 0x00 event code is used, which is
reserved for fake events. The metric events start from umask 0x10.
When setting up the metric events, they point to the Fixed Counter 3.
They have to be specially handled.
- Add the update_topdown_event() callback to read the additional metrics
MSR and generate the metrics.
- Add the set_topdown_event_period() callback to initialize metrics MSR
and the fixed counter 3.
- Add a variable n_metric_event to track the number of the accepted
metrics events. The sharing between multiple users of the same metric
without multiplexing is not allowed.
- Only enable/disable the fixed counter 3 when there are no other active
TopDown events, which avoid the unnecessary writing of the fixed
control register.
- Disable the PMU when reading the metrics event. The metrics MSR and
the fixed counter 3 are read separately. The values may be modified by
an NMI.
All four metric events don't support sampling. Since they will be
handled specially for event update, a flag PERF_X86_EVENT_TOPDOWN is
introduced to indicate this case.
The slots event can support both sampling and counting.
For counting, the flag is also applied.
For sampling, it will be handled normally as other normal events.
Groups
======
The slots event is required in a Topdown group.
To avoid reading the METRICS register multiple times, the metrics and
slots value can only be updated by slots event in a group.
All active slots and metrics events will be updated one time.
Therefore, the slots event must be before any metric events in a Topdown
group.
NMI
======
The METRICS related register may be overflow. The bit 48 of the STATUS
register will be set. If so, PERF_METRICS and Fixed counter 3 are
required to be reset. The patch also update all active slots and
metrics events in the NMI handler.
The update_topdown_event() has to read two registers separately. The
values may be modified by an NMI. PMU has to be disabled before calling
the function.
RDPMC
======
RDPMC is temporarily disabled. A later patch will enable it.
Suggested-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200723171117.9918-9-kan.liang@linux.intel.com
2020-07-23 17:11:11 +00:00
|
|
|
/*
|
|
|
|
* The PERF_METRICS MSR is modeled as several magic fixed-mode PMCs, one for
|
|
|
|
* each TopDown metric event.
|
|
|
|
*
|
|
|
|
* Internally the TopDown metric events are mapped to the FxCtr 3 (SLOTS).
|
|
|
|
*/
|
|
|
|
#define INTEL_PMC_IDX_METRIC_BASE (INTEL_PMC_IDX_FIXED + 16)
|
|
|
|
#define INTEL_PMC_IDX_TD_RETIRING (INTEL_PMC_IDX_METRIC_BASE + 0)
|
|
|
|
#define INTEL_PMC_IDX_TD_BAD_SPEC (INTEL_PMC_IDX_METRIC_BASE + 1)
|
|
|
|
#define INTEL_PMC_IDX_TD_FE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 2)
|
|
|
|
#define INTEL_PMC_IDX_TD_BE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 3)
|
|
|
|
#define INTEL_PMC_IDX_METRIC_END INTEL_PMC_IDX_TD_BE_BOUND
|
|
|
|
#define INTEL_PMC_MSK_TOPDOWN ((0xfull << INTEL_PMC_IDX_METRIC_BASE) | \
|
|
|
|
INTEL_PMC_MSK_FIXED_SLOTS)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* There is no event-code assigned to the TopDown events.
|
|
|
|
*
|
|
|
|
* For the slots event, use the pseudo code of the fixed counter 3.
|
|
|
|
*
|
|
|
|
* For the metric events, the pseudo event-code is 0x00.
|
|
|
|
* The pseudo umask-code starts from the middle of the pseudo event
|
|
|
|
* space, 0x80.
|
|
|
|
*/
|
|
|
|
#define INTEL_TD_SLOTS 0x0400 /* TOPDOWN.SLOTS */
|
|
|
|
/* Level 1 metrics */
|
|
|
|
#define INTEL_TD_METRIC_RETIRING 0x8000 /* Retiring metric */
|
|
|
|
#define INTEL_TD_METRIC_BAD_SPEC 0x8100 /* Bad speculation metric */
|
|
|
|
#define INTEL_TD_METRIC_FE_BOUND 0x8200 /* FE bound metric */
|
|
|
|
#define INTEL_TD_METRIC_BE_BOUND 0x8300 /* BE bound metric */
|
|
|
|
#define INTEL_TD_METRIC_MAX INTEL_TD_METRIC_BE_BOUND
|
|
|
|
#define INTEL_TD_METRIC_NUM 4
|
|
|
|
|
|
|
|
static inline bool is_metric_idx(int idx)
|
|
|
|
{
|
|
|
|
return (unsigned)(idx - INTEL_PMC_IDX_METRIC_BASE) < INTEL_TD_METRIC_NUM;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool is_topdown_idx(int idx)
|
|
|
|
{
|
|
|
|
return is_metric_idx(idx) || idx == INTEL_PMC_IDX_FIXED_SLOTS;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define INTEL_PMC_OTHER_TOPDOWN_BITS(bit) \
|
|
|
|
(~(0x1ull << bit) & INTEL_PMC_MSK_TOPDOWN)
|
|
|
|
|
2020-07-23 17:11:05 +00:00
|
|
|
#define GLOBAL_STATUS_COND_CHG BIT_ULL(63)
|
|
|
|
#define GLOBAL_STATUS_BUFFER_OVF_BIT 62
|
|
|
|
#define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(GLOBAL_STATUS_BUFFER_OVF_BIT)
|
|
|
|
#define GLOBAL_STATUS_UNC_OVF BIT_ULL(61)
|
|
|
|
#define GLOBAL_STATUS_ASIF BIT_ULL(60)
|
|
|
|
#define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59)
|
|
|
|
#define GLOBAL_STATUS_LBRS_FROZEN_BIT 58
|
|
|
|
#define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(GLOBAL_STATUS_LBRS_FROZEN_BIT)
|
|
|
|
#define GLOBAL_STATUS_TRACE_TOPAPMI_BIT 55
|
|
|
|
#define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(GLOBAL_STATUS_TRACE_TOPAPMI_BIT)
|
perf/x86/intel: Generic support for hardware TopDown metrics
Intro
=====
The TopDown Microarchitecture Analysis (TMA) Method is a structured
analysis methodology to identify critical performance bottlenecks in
out-of-order processors. Current perf has supported the method.
The method works well, but there is one problem. To collect the TopDown
events, several GP counters have to be used. If a user wants to collect
other events at the same time, the multiplexing probably be triggered,
which impacts the accuracy.
To free up the scarce GP counters, the hardware TopDown metrics feature
is introduced from Ice Lake. The hardware implements an additional
"metrics" register and a new Fixed Counter 3 that measures pipeline
"slots". The TopDown events can be calculated from them instead.
Events
======
The level 1 TopDown has four metrics. There is no event-code assigned to
the TopDown metrics. Four metric events are exported as separate perf
events, which map to the internal "metrics" counter register. Those
events do not exist in hardware, but can be allocated by the scheduler.
For the event mapping, a special 0x00 event code is used, which is
reserved for fake events. The metric events start from umask 0x10.
When setting up the metric events, they point to the Fixed Counter 3.
They have to be specially handled.
- Add the update_topdown_event() callback to read the additional metrics
MSR and generate the metrics.
- Add the set_topdown_event_period() callback to initialize metrics MSR
and the fixed counter 3.
- Add a variable n_metric_event to track the number of the accepted
metrics events. The sharing between multiple users of the same metric
without multiplexing is not allowed.
- Only enable/disable the fixed counter 3 when there are no other active
TopDown events, which avoid the unnecessary writing of the fixed
control register.
- Disable the PMU when reading the metrics event. The metrics MSR and
the fixed counter 3 are read separately. The values may be modified by
an NMI.
All four metric events don't support sampling. Since they will be
handled specially for event update, a flag PERF_X86_EVENT_TOPDOWN is
introduced to indicate this case.
The slots event can support both sampling and counting.
For counting, the flag is also applied.
For sampling, it will be handled normally as other normal events.
Groups
======
The slots event is required in a Topdown group.
To avoid reading the METRICS register multiple times, the metrics and
slots value can only be updated by slots event in a group.
All active slots and metrics events will be updated one time.
Therefore, the slots event must be before any metric events in a Topdown
group.
NMI
======
The METRICS related register may be overflow. The bit 48 of the STATUS
register will be set. If so, PERF_METRICS and Fixed counter 3 are
required to be reset. The patch also update all active slots and
metrics events in the NMI handler.
The update_topdown_event() has to read two registers separately. The
values may be modified by an NMI. PMU has to be disabled before calling
the function.
RDPMC
======
RDPMC is temporarily disabled. A later patch will enable it.
Suggested-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200723171117.9918-9-kan.liang@linux.intel.com
2020-07-23 17:11:11 +00:00
|
|
|
#define GLOBAL_STATUS_PERF_METRICS_OVF_BIT 48
|
2015-05-10 19:22:41 +00:00
|
|
|
|
2020-07-23 17:11:13 +00:00
|
|
|
#define GLOBAL_CTRL_EN_PERF_METRICS 48
|
2020-06-13 08:09:49 +00:00
|
|
|
/*
|
|
|
|
* We model guest LBR event tracing as another fixed-mode PMC like BTS.
|
|
|
|
*
|
|
|
|
* We choose bit 58 because it's used to indicate LBR stack frozen state
|
|
|
|
* for architectural perfmon v4, also we unconditionally mask that bit in
|
|
|
|
* the handle_pmi_common(), so it'll never be set in the overflow handling.
|
|
|
|
*
|
|
|
|
* With this fake counter assigned, the guest LBR event user (such as KVM),
|
|
|
|
* can program the LBR registers on its own, and we don't actually do anything
|
|
|
|
* with then in the host context.
|
|
|
|
*/
|
|
|
|
#define INTEL_PMC_IDX_FIXED_VLBR (GLOBAL_STATUS_LBRS_FROZEN_BIT)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Pseudo-encoding the guest LBR event as event=0x00,umask=0x1b,
|
|
|
|
* since it would claim bit 58 which is effectively Fixed26.
|
|
|
|
*/
|
|
|
|
#define INTEL_FIXED_VLBR_EVENT 0x1b00
|
|
|
|
|
perf/x86/intel: Support adaptive PEBS v4
Adaptive PEBS is a new way to report PEBS sampling information. Instead
of a fixed size record for all PEBS events it allows to configure the
PEBS record to only include the information needed. Events can then opt
in to use such an extended record, or stay with a basic record which
only contains the IP.
The major new feature is to support LBRs in PEBS record.
Besides normal LBR, this allows (much faster) large PEBS, while still
supporting callstacks through callstack LBR. So essentially a lot of
profiling can now be done without frequent interrupts, dropping the
overhead significantly.
The main requirement still is to use a period, and not use frequency
mode, because frequency mode requires reevaluating the frequency on each
overflow.
The floating point state (XMM) is also supported, which allows efficient
profiling of FP function arguments.
Introduce specific drain function to handle variable length records.
Use a new callback to parse the new record format, and also handle the
STATUS field now being at a different offset.
Add code to set up the configuration register. Since there is only a
single register, all events either get the full super set of all events,
or only the basic record.
Originally-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: acme@kernel.org
Cc: jolsa@kernel.org
Link: https://lkml.kernel.org/r/20190402194509.2832-6-kan.liang@linux.intel.com
[ Renamed GPRS => GP. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-04-02 19:45:02 +00:00
|
|
|
/*
|
|
|
|
* Adaptive PEBS v4
|
|
|
|
*/
|
|
|
|
|
|
|
|
struct pebs_basic {
|
|
|
|
u64 format_size;
|
|
|
|
u64 ip;
|
|
|
|
u64 applicable_counters;
|
|
|
|
u64 tsc;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pebs_meminfo {
|
|
|
|
u64 address;
|
|
|
|
u64 aux;
|
|
|
|
u64 latency;
|
|
|
|
u64 tsx_tuning;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pebs_gprs {
|
|
|
|
u64 flags, ip, ax, cx, dx, bx, sp, bp, si, di;
|
|
|
|
u64 r8, r9, r10, r11, r12, r13, r14, r15;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pebs_xmm {
|
|
|
|
u64 xmm[16*2]; /* two entries for each register */
|
|
|
|
};
|
|
|
|
|
2011-09-21 09:30:17 +00:00
|
|
|
/*
|
|
|
|
* IBS cpuid feature detection
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define IBS_CPUID_FEATURES 0x8000001b
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
|
|
|
|
* bit 0 is used to indicate the existence of IBS.
|
|
|
|
*/
|
|
|
|
#define IBS_CAPS_AVAIL (1U<<0)
|
|
|
|
#define IBS_CAPS_FETCHSAM (1U<<1)
|
|
|
|
#define IBS_CAPS_OPSAM (1U<<2)
|
|
|
|
#define IBS_CAPS_RDWROPCNT (1U<<3)
|
|
|
|
#define IBS_CAPS_OPCNT (1U<<4)
|
|
|
|
#define IBS_CAPS_BRNTRGT (1U<<5)
|
|
|
|
#define IBS_CAPS_OPCNTEXT (1U<<6)
|
2012-04-02 18:19:11 +00:00
|
|
|
#define IBS_CAPS_RIPINVALIDCHK (1U<<7)
|
2014-11-10 20:24:26 +00:00
|
|
|
#define IBS_CAPS_OPBRNFUSE (1U<<8)
|
|
|
|
#define IBS_CAPS_FETCHCTLEXTD (1U<<9)
|
|
|
|
#define IBS_CAPS_OPDATA4 (1U<<10)
|
2011-09-21 09:30:17 +00:00
|
|
|
|
|
|
|
#define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \
|
|
|
|
| IBS_CAPS_FETCHSAM \
|
|
|
|
| IBS_CAPS_OPSAM)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* IBS APIC setup
|
|
|
|
*/
|
|
|
|
#define IBSCTL 0x1cc
|
|
|
|
#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
|
|
|
|
#define IBSCTL_LVT_OFFSET_MASK 0x0F
|
|
|
|
|
perf/x86/amd/ibs: Fix sample bias for dispatched micro-ops
When counting dispatched micro-ops with cnt_ctl=1, in order to prevent
sample bias, IBS hardware preloads the least significant 7 bits of
current count (IbsOpCurCnt) with random values, such that, after the
interrupt is handled and counting resumes, the next sample taken
will be slightly perturbed.
The current count bitfield is in the IBS execution control h/w register,
alongside the maximum count field.
Currently, the IBS driver writes that register with the maximum count,
leaving zeroes to fill the current count field, thereby overwriting
the random bits the hardware preloaded for itself.
Fix the driver to actually retain and carry those random bits from the
read of the IBS control register, through to its write, instead of
overwriting the lower current count bits with zeroes.
Tested with:
perf record -c 100001 -e ibs_op/cnt_ctl=1/pp -a -C 0 taskset -c 0 <workload>
'perf annotate' output before:
15.70 65: addsd %xmm0,%xmm1
17.30 add $0x1,%rax
15.88 cmp %rdx,%rax
je 82
17.32 72: test $0x1,%al
jne 7c
7.52 movapd %xmm1,%xmm0
5.90 jmp 65
8.23 7c: sqrtsd %xmm1,%xmm0
12.15 jmp 65
'perf annotate' output after:
16.63 65: addsd %xmm0,%xmm1
16.82 add $0x1,%rax
16.81 cmp %rdx,%rax
je 82
16.69 72: test $0x1,%al
jne 7c
8.30 movapd %xmm1,%xmm0
8.13 jmp 65
8.24 7c: sqrtsd %xmm1,%xmm0
8.39 jmp 65
Tested on Family 15h and 17h machines.
Machines prior to family 10h Rev. C don't have the RDWROPCNT capability,
and have the IbsOpCurCnt bitfield reserved, so this patch shouldn't
affect their operation.
It is unknown why commit db98c5faf8cb ("perf/x86: Implement 64-bit
counter support for IBS") ignored the lower 4 bits of the IbsOpCurCnt
field; the number of preloaded random bits has always been 7, AFAICT.
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: "Arnaldo Carvalho de Melo" <acme@kernel.org>
Cc: <x86@kernel.org>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "Borislav Petkov" <bp@alien8.de>
Cc: Stephane Eranian <eranian@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: "Namhyung Kim" <namhyung@kernel.org>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Link: https://lkml.kernel.org/r/20190826195730.30614-1-kim.phillips@amd.com
2019-08-26 19:57:30 +00:00
|
|
|
/* IBS fetch bits/masks */
|
2010-09-22 15:45:39 +00:00
|
|
|
#define IBS_FETCH_RAND_EN (1ULL<<57)
|
|
|
|
#define IBS_FETCH_VAL (1ULL<<49)
|
|
|
|
#define IBS_FETCH_ENABLE (1ULL<<48)
|
|
|
|
#define IBS_FETCH_CNT 0xFFFF0000ULL
|
|
|
|
#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
|
2010-02-25 18:40:46 +00:00
|
|
|
|
perf/x86/amd/ibs: Fix sample bias for dispatched micro-ops
When counting dispatched micro-ops with cnt_ctl=1, in order to prevent
sample bias, IBS hardware preloads the least significant 7 bits of
current count (IbsOpCurCnt) with random values, such that, after the
interrupt is handled and counting resumes, the next sample taken
will be slightly perturbed.
The current count bitfield is in the IBS execution control h/w register,
alongside the maximum count field.
Currently, the IBS driver writes that register with the maximum count,
leaving zeroes to fill the current count field, thereby overwriting
the random bits the hardware preloaded for itself.
Fix the driver to actually retain and carry those random bits from the
read of the IBS control register, through to its write, instead of
overwriting the lower current count bits with zeroes.
Tested with:
perf record -c 100001 -e ibs_op/cnt_ctl=1/pp -a -C 0 taskset -c 0 <workload>
'perf annotate' output before:
15.70 65: addsd %xmm0,%xmm1
17.30 add $0x1,%rax
15.88 cmp %rdx,%rax
je 82
17.32 72: test $0x1,%al
jne 7c
7.52 movapd %xmm1,%xmm0
5.90 jmp 65
8.23 7c: sqrtsd %xmm1,%xmm0
12.15 jmp 65
'perf annotate' output after:
16.63 65: addsd %xmm0,%xmm1
16.82 add $0x1,%rax
16.81 cmp %rdx,%rax
je 82
16.69 72: test $0x1,%al
jne 7c
8.30 movapd %xmm1,%xmm0
8.13 jmp 65
8.24 7c: sqrtsd %xmm1,%xmm0
8.39 jmp 65
Tested on Family 15h and 17h machines.
Machines prior to family 10h Rev. C don't have the RDWROPCNT capability,
and have the IbsOpCurCnt bitfield reserved, so this patch shouldn't
affect their operation.
It is unknown why commit db98c5faf8cb ("perf/x86: Implement 64-bit
counter support for IBS") ignored the lower 4 bits of the IbsOpCurCnt
field; the number of preloaded random bits has always been 7, AFAICT.
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: "Arnaldo Carvalho de Melo" <acme@kernel.org>
Cc: <x86@kernel.org>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "Borislav Petkov" <bp@alien8.de>
Cc: Stephane Eranian <eranian@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: "Namhyung Kim" <namhyung@kernel.org>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Link: https://lkml.kernel.org/r/20190826195730.30614-1-kim.phillips@amd.com
2019-08-26 19:57:30 +00:00
|
|
|
/*
|
|
|
|
* IBS op bits/masks
|
|
|
|
* The lower 7 bits of the current count are random bits
|
|
|
|
* preloaded by hardware and ignored in software
|
|
|
|
*/
|
|
|
|
#define IBS_OP_CUR_CNT (0xFFF80ULL<<32)
|
|
|
|
#define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32)
|
2010-09-22 15:45:39 +00:00
|
|
|
#define IBS_OP_CNT_CTL (1ULL<<19)
|
|
|
|
#define IBS_OP_VAL (1ULL<<18)
|
|
|
|
#define IBS_OP_ENABLE (1ULL<<17)
|
|
|
|
#define IBS_OP_MAX_CNT 0x0000FFFFULL
|
|
|
|
#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
|
2020-09-08 21:47:39 +00:00
|
|
|
#define IBS_OP_MAX_CNT_EXT_MASK (0x7FULL<<20) /* separate upper 7 bits */
|
2012-04-02 18:19:11 +00:00
|
|
|
#define IBS_RIP_INVALID (1ULL<<38)
|
2009-07-21 13:56:48 +00:00
|
|
|
|
2012-05-11 09:44:59 +00:00
|
|
|
#ifdef CONFIG_X86_LOCAL_APIC
|
2011-09-21 09:30:18 +00:00
|
|
|
extern u32 get_ibs_caps(void);
|
2012-05-11 09:44:59 +00:00
|
|
|
#else
|
|
|
|
static inline u32 get_ibs_caps(void) { return 0; }
|
|
|
|
#endif
|
2011-09-21 09:30:18 +00:00
|
|
|
|
perf: Do the big rename: Performance Counters -> Performance Events
Bye-bye Performance Counters, welcome Performance Events!
In the past few months the perfcounters subsystem has grown out its
initial role of counting hardware events, and has become (and is
becoming) a much broader generic event enumeration, reporting, logging,
monitoring, analysis facility.
Naming its core object 'perf_counter' and naming the subsystem
'perfcounters' has become more and more of a misnomer. With pending
code like hw-breakpoints support the 'counter' name is less and
less appropriate.
All in one, we've decided to rename the subsystem to 'performance
events' and to propagate this rename through all fields, variables
and API names. (in an ABI compatible fashion)
The word 'event' is also a bit shorter than 'counter' - which makes
it slightly more convenient to write/handle as well.
Thanks goes to Stephane Eranian who first observed this misnomer and
suggested a rename.
User-space tooling and ABI compatibility is not affected - this patch
should be function-invariant. (Also, defconfigs were not touched to
keep the size down.)
This patch has been generated via the following script:
FILES=$(find * -type f | grep -vE 'oprofile|[^K]config')
sed -i \
-e 's/PERF_EVENT_/PERF_RECORD_/g' \
-e 's/PERF_COUNTER/PERF_EVENT/g' \
-e 's/perf_counter/perf_event/g' \
-e 's/nb_counters/nb_events/g' \
-e 's/swcounter/swevent/g' \
-e 's/tpcounter_event/tp_event/g' \
$FILES
for N in $(find . -name perf_counter.[ch]); do
M=$(echo $N | sed 's/perf_counter/perf_event/g')
mv $N $M
done
FILES=$(find . -name perf_event.*)
sed -i \
-e 's/COUNTER_MASK/REG_MASK/g' \
-e 's/COUNTER/EVENT/g' \
-e 's/\<event\>/event_id/g' \
-e 's/counter/event/g' \
-e 's/Counter/Event/g' \
$FILES
... to keep it as correct as possible. This script can also be
used by anyone who has pending perfcounters patches - it converts
a Linux kernel tree over to the new naming. We tried to time this
change to the point in time where the amount of pending patches
is the smallest: the end of the merge window.
Namespace clashes were fixed up in a preparatory patch - and some
stylistic fallout will be fixed up in a subsequent patch.
( NOTE: 'counters' are still the proper terminology when we deal
with hardware registers - and these sed scripts are a bit
over-eager in renaming them. I've undone some of that, but
in case there's something left where 'counter' would be
better than 'event' we can undo that on an individual basis
instead of touching an otherwise nicely automated patch. )
Suggested-by: Stephane Eranian <eranian@google.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Paul Mackerras <paulus@samba.org>
Reviewed-by: Arjan van de Ven <arjan@linux.intel.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: <linux-arch@vger.kernel.org>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-09-21 10:02:48 +00:00
|
|
|
#ifdef CONFIG_PERF_EVENTS
|
|
|
|
extern void perf_events_lapic_init(void);
|
2009-06-22 14:35:24 +00:00
|
|
|
|
2010-03-03 12:12:23 +00:00
|
|
|
/*
|
2012-07-10 07:42:15 +00:00
|
|
|
* Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
|
|
|
|
* unused and ABI specified to be 0, so nobody should care what we do with
|
|
|
|
* them.
|
|
|
|
*
|
|
|
|
* EXACT - the IP points to the exact instruction that triggered the
|
|
|
|
* event (HW bugs exempt).
|
|
|
|
* VM - original X86_VM_MASK; see set_linear_ip().
|
2010-03-03 12:12:23 +00:00
|
|
|
*/
|
|
|
|
#define PERF_EFLAGS_EXACT (1UL << 3)
|
2012-07-10 07:42:15 +00:00
|
|
|
#define PERF_EFLAGS_VM (1UL << 5)
|
2010-03-03 12:12:23 +00:00
|
|
|
|
2010-04-19 05:32:41 +00:00
|
|
|
struct pt_regs;
|
2019-04-02 19:44:59 +00:00
|
|
|
struct x86_perf_regs {
|
|
|
|
struct pt_regs regs;
|
|
|
|
u64 *xmm_regs;
|
|
|
|
};
|
|
|
|
|
2010-04-19 05:32:41 +00:00
|
|
|
extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
|
|
|
|
extern unsigned long perf_misc_flags(struct pt_regs *regs);
|
|
|
|
#define perf_misc_flags(regs) perf_misc_flags(regs)
|
2010-03-03 12:12:23 +00:00
|
|
|
|
2010-05-20 05:47:21 +00:00
|
|
|
#include <asm/stacktrace.h>
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We abuse bit 3 from flags to pass exact information, see perf_misc_flags
|
|
|
|
* and the comment with PERF_EFLAGS_EXACT.
|
|
|
|
*/
|
|
|
|
#define perf_arch_fetch_caller_regs(regs, __ip) { \
|
|
|
|
(regs)->ip = (__ip); \
|
2019-04-22 16:26:52 +00:00
|
|
|
(regs)->sp = (unsigned long)__builtin_frame_address(0); \
|
2010-05-20 05:47:21 +00:00
|
|
|
(regs)->cs = __KERNEL_CS; \
|
|
|
|
regs->flags = 0; \
|
|
|
|
}
|
|
|
|
|
2011-10-05 12:01:21 +00:00
|
|
|
struct perf_guest_switch_msr {
|
|
|
|
unsigned msr;
|
|
|
|
u64 host, guest;
|
|
|
|
};
|
|
|
|
|
2020-06-13 08:09:48 +00:00
|
|
|
struct x86_pmu_lbr {
|
|
|
|
unsigned int nr;
|
|
|
|
unsigned int from;
|
|
|
|
unsigned int to;
|
|
|
|
unsigned int info;
|
|
|
|
};
|
|
|
|
|
2011-11-10 12:57:27 +00:00
|
|
|
extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
|
2012-06-08 12:50:50 +00:00
|
|
|
extern void perf_check_microcode(void);
|
2018-09-19 17:29:07 +00:00
|
|
|
extern int x86_perf_rdpmc_index(struct perf_event *event);
|
2008-12-03 09:39:53 +00:00
|
|
|
#else
|
2011-11-10 12:57:27 +00:00
|
|
|
static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
|
|
|
|
{
|
|
|
|
memset(cap, 0, sizeof(*cap));
|
|
|
|
}
|
|
|
|
|
perf: Do the big rename: Performance Counters -> Performance Events
Bye-bye Performance Counters, welcome Performance Events!
In the past few months the perfcounters subsystem has grown out its
initial role of counting hardware events, and has become (and is
becoming) a much broader generic event enumeration, reporting, logging,
monitoring, analysis facility.
Naming its core object 'perf_counter' and naming the subsystem
'perfcounters' has become more and more of a misnomer. With pending
code like hw-breakpoints support the 'counter' name is less and
less appropriate.
All in one, we've decided to rename the subsystem to 'performance
events' and to propagate this rename through all fields, variables
and API names. (in an ABI compatible fashion)
The word 'event' is also a bit shorter than 'counter' - which makes
it slightly more convenient to write/handle as well.
Thanks goes to Stephane Eranian who first observed this misnomer and
suggested a rename.
User-space tooling and ABI compatibility is not affected - this patch
should be function-invariant. (Also, defconfigs were not touched to
keep the size down.)
This patch has been generated via the following script:
FILES=$(find * -type f | grep -vE 'oprofile|[^K]config')
sed -i \
-e 's/PERF_EVENT_/PERF_RECORD_/g' \
-e 's/PERF_COUNTER/PERF_EVENT/g' \
-e 's/perf_counter/perf_event/g' \
-e 's/nb_counters/nb_events/g' \
-e 's/swcounter/swevent/g' \
-e 's/tpcounter_event/tp_event/g' \
$FILES
for N in $(find . -name perf_counter.[ch]); do
M=$(echo $N | sed 's/perf_counter/perf_event/g')
mv $N $M
done
FILES=$(find . -name perf_event.*)
sed -i \
-e 's/COUNTER_MASK/REG_MASK/g' \
-e 's/COUNTER/EVENT/g' \
-e 's/\<event\>/event_id/g' \
-e 's/counter/event/g' \
-e 's/Counter/Event/g' \
$FILES
... to keep it as correct as possible. This script can also be
used by anyone who has pending perfcounters patches - it converts
a Linux kernel tree over to the new naming. We tried to time this
change to the point in time where the amount of pending patches
is the smallest: the end of the merge window.
Namespace clashes were fixed up in a preparatory patch - and some
stylistic fallout will be fixed up in a subsequent patch.
( NOTE: 'counters' are still the proper terminology when we deal
with hardware registers - and these sed scripts are a bit
over-eager in renaming them. I've undone some of that, but
in case there's something left where 'counter' would be
better than 'event' we can undo that on an individual basis
instead of touching an otherwise nicely automated patch. )
Suggested-by: Stephane Eranian <eranian@google.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Paul Mackerras <paulus@samba.org>
Reviewed-by: Arjan van de Ven <arjan@linux.intel.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: <linux-arch@vger.kernel.org>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-09-21 10:02:48 +00:00
|
|
|
static inline void perf_events_lapic_init(void) { }
|
2012-06-08 12:50:50 +00:00
|
|
|
static inline void perf_check_microcode(void) { }
|
2008-12-03 09:39:53 +00:00
|
|
|
#endif
|
|
|
|
|
2019-12-21 04:45:12 +00:00
|
|
|
#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL)
|
|
|
|
extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
|
2020-06-13 08:09:48 +00:00
|
|
|
extern int x86_perf_get_lbr(struct x86_pmu_lbr *lbr);
|
2019-12-21 04:45:12 +00:00
|
|
|
#else
|
|
|
|
static inline struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
|
|
|
|
{
|
|
|
|
*nr = 0;
|
|
|
|
return NULL;
|
|
|
|
}
|
2020-06-13 08:09:48 +00:00
|
|
|
static inline int x86_perf_get_lbr(struct x86_pmu_lbr *lbr)
|
|
|
|
{
|
|
|
|
return -1;
|
|
|
|
}
|
2019-12-21 04:45:12 +00:00
|
|
|
#endif
|
|
|
|
|
2016-03-29 14:43:10 +00:00
|
|
|
#ifdef CONFIG_CPU_SUP_INTEL
|
|
|
|
extern void intel_pt_handle_vmx(int on);
|
2019-12-21 04:45:12 +00:00
|
|
|
#else
|
|
|
|
static inline void intel_pt_handle_vmx(int on)
|
|
|
|
{
|
|
|
|
|
|
|
|
}
|
2016-03-29 14:43:10 +00:00
|
|
|
#endif
|
|
|
|
|
2012-02-29 13:57:32 +00:00
|
|
|
#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
|
|
|
|
extern void amd_pmu_enable_virt(void);
|
|
|
|
extern void amd_pmu_disable_virt(void);
|
|
|
|
#else
|
|
|
|
static inline void amd_pmu_enable_virt(void) { }
|
|
|
|
static inline void amd_pmu_disable_virt(void) { }
|
|
|
|
#endif
|
|
|
|
|
2012-08-07 13:20:38 +00:00
|
|
|
#define arch_perf_out_copy_user copy_from_user_nmi
|
|
|
|
|
perf: Do the big rename: Performance Counters -> Performance Events
Bye-bye Performance Counters, welcome Performance Events!
In the past few months the perfcounters subsystem has grown out its
initial role of counting hardware events, and has become (and is
becoming) a much broader generic event enumeration, reporting, logging,
monitoring, analysis facility.
Naming its core object 'perf_counter' and naming the subsystem
'perfcounters' has become more and more of a misnomer. With pending
code like hw-breakpoints support the 'counter' name is less and
less appropriate.
All in one, we've decided to rename the subsystem to 'performance
events' and to propagate this rename through all fields, variables
and API names. (in an ABI compatible fashion)
The word 'event' is also a bit shorter than 'counter' - which makes
it slightly more convenient to write/handle as well.
Thanks goes to Stephane Eranian who first observed this misnomer and
suggested a rename.
User-space tooling and ABI compatibility is not affected - this patch
should be function-invariant. (Also, defconfigs were not touched to
keep the size down.)
This patch has been generated via the following script:
FILES=$(find * -type f | grep -vE 'oprofile|[^K]config')
sed -i \
-e 's/PERF_EVENT_/PERF_RECORD_/g' \
-e 's/PERF_COUNTER/PERF_EVENT/g' \
-e 's/perf_counter/perf_event/g' \
-e 's/nb_counters/nb_events/g' \
-e 's/swcounter/swevent/g' \
-e 's/tpcounter_event/tp_event/g' \
$FILES
for N in $(find . -name perf_counter.[ch]); do
M=$(echo $N | sed 's/perf_counter/perf_event/g')
mv $N $M
done
FILES=$(find . -name perf_event.*)
sed -i \
-e 's/COUNTER_MASK/REG_MASK/g' \
-e 's/COUNTER/EVENT/g' \
-e 's/\<event\>/event_id/g' \
-e 's/counter/event/g' \
-e 's/Counter/Event/g' \
$FILES
... to keep it as correct as possible. This script can also be
used by anyone who has pending perfcounters patches - it converts
a Linux kernel tree over to the new naming. We tried to time this
change to the point in time where the amount of pending patches
is the smallest: the end of the merge window.
Namespace clashes were fixed up in a preparatory patch - and some
stylistic fallout will be fixed up in a subsequent patch.
( NOTE: 'counters' are still the proper terminology when we deal
with hardware registers - and these sed scripts are a bit
over-eager in renaming them. I've undone some of that, but
in case there's something left where 'counter' would be
better than 'event' we can undo that on an individual basis
instead of touching an otherwise nicely automated patch. )
Suggested-by: Stephane Eranian <eranian@google.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Paul Mackerras <paulus@samba.org>
Reviewed-by: Arjan van de Ven <arjan@linux.intel.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: <linux-arch@vger.kernel.org>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-09-21 10:02:48 +00:00
|
|
|
#endif /* _ASM_X86_PERF_EVENT_H */
|