2013-07-19 19:36:52 +00:00
|
|
|
/*
|
|
|
|
* Copyright © 2013 Intel Corporation
|
|
|
|
*
|
|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
|
|
* to deal in the Software without restriction, including without limitation
|
|
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
|
|
*
|
|
|
|
* The above copyright notice and this permission notice (including the next
|
|
|
|
* paragraph) shall be included in all copies or substantial portions of the
|
|
|
|
* Software.
|
|
|
|
*
|
|
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
|
|
|
* IN THE SOFTWARE.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include "i915_drv.h"
|
|
|
|
#include "intel_drv.h"
|
2015-02-10 11:05:47 +00:00
|
|
|
#include "i915_vgpu.h"
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2015-01-16 09:34:35 +00:00
|
|
|
#include <linux/pm_runtime.h>
|
|
|
|
|
2015-08-23 12:22:47 +00:00
|
|
|
#define FORCEWAKE_ACK_TIMEOUT_MS 50
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2015-10-22 12:34:56 +00:00
|
|
|
#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
|
2013-07-19 19:36:53 +00:00
|
|
|
|
2015-01-19 14:20:43 +00:00
|
|
|
static const char * const forcewake_domain_names[] = {
|
|
|
|
"render",
|
|
|
|
"blitter",
|
|
|
|
"media",
|
|
|
|
};
|
|
|
|
|
|
|
|
const char *
|
2015-01-16 09:34:41 +00:00
|
|
|
intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
|
2015-01-19 14:20:43 +00:00
|
|
|
{
|
2015-08-21 17:45:28 +00:00
|
|
|
BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
|
2015-01-19 14:20:43 +00:00
|
|
|
|
|
|
|
if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
|
|
|
|
return forcewake_domain_names[id];
|
|
|
|
|
|
|
|
WARN_ON(id);
|
|
|
|
|
|
|
|
return "unknown";
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
|
2013-07-19 19:36:52 +00:00
|
|
|
{
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
WARN_ON(!i915_mmio_reg_valid(d->reg_set));
|
2015-01-19 14:20:43 +00:00
|
|
|
__raw_i915_write32(d->i915, d->reg_set, d->val_reset);
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
|
|
|
|
2015-01-19 14:20:43 +00:00
|
|
|
static inline void
|
|
|
|
fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
|
2013-07-19 19:36:52 +00:00
|
|
|
{
|
drm/i915: Use consistent forcewake auto-release timeout across kernel configs
Because it is based on jiffies, current implementation releases the
forcewake at any time between straight away and between 1ms and 10ms,
depending on the kernel configuration (CONFIG_HZ).
This is probably not what has been desired, since the dynamics of keeping
parts of the GPU awake should not be correlated with this kernel
configuration parameter.
Change the auto-release mechanism to use hrtimers and set the timeout to
1ms with a 1ms of slack. This should make the GPU power consistent
across kernel configs, and timer slack should enable some timer coalescing
where multiple force-wake domains exist, or with unrelated timers.
For GlBench/T-Rex this decreases the number of forcewake releases from
~480 to ~300 per second, and for a heavy combined OGL/OCL test from
~670 to ~360 (HZ=1000 kernel).
Even though this reduction can be attributed to the average release period
extending from 0-1ms to 1-2ms, as discussed above, it will make the
forcewake timeout consistent for different CONFIG_HZ values.
Real life measurements with the above workload has shown that, with this
patch, both manage to auto-release the forcewake between 2-4 times per
10ms, even though the number of forcewake gets is dramatically different.
T-Rex requests between 5-10 explicit gets and 5-10 implict gets in each
10ms period, while the OGL/OCL test requests 250 and 380 times in the same
period.
The two data points together suggest that the nature of the forwake
accesses is bursty and that further changes and potential timeout
extensions, or moving the start of timeout from the first to the last
automatic forcewake grab, should be carefully measured for power and
performance effects.
v2:
* Commit spelling. (Dave Gordon)
* More discussion on numbers in the commit. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-04-07 16:04:32 +00:00
|
|
|
d->wake_count++;
|
|
|
|
hrtimer_start_range_ns(&d->timer,
|
|
|
|
ktime_set(0, NSEC_PER_MSEC),
|
|
|
|
NSEC_PER_MSEC,
|
|
|
|
HRTIMER_MODE_REL);
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
|
|
|
|
2015-01-19 14:20:43 +00:00
|
|
|
static inline void
|
|
|
|
fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
|
2013-07-19 19:36:52 +00:00
|
|
|
{
|
2015-01-19 14:20:43 +00:00
|
|
|
if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
|
|
|
|
FORCEWAKE_KERNEL) == 0,
|
2013-07-19 19:36:52 +00:00
|
|
|
FORCEWAKE_ACK_TIMEOUT_MS))
|
2015-01-19 14:20:43 +00:00
|
|
|
DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
|
|
|
|
intel_uncore_forcewake_domain_to_str(d->id));
|
|
|
|
}
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2015-01-19 14:20:43 +00:00
|
|
|
static inline void
|
|
|
|
fw_domain_get(const struct intel_uncore_forcewake_domain *d)
|
|
|
|
{
|
|
|
|
__raw_i915_write32(d->i915, d->reg_set, d->val_set);
|
|
|
|
}
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2015-01-19 14:20:43 +00:00
|
|
|
static inline void
|
|
|
|
fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
|
|
|
|
{
|
|
|
|
if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
|
|
|
|
FORCEWAKE_KERNEL),
|
2013-07-19 19:36:52 +00:00
|
|
|
FORCEWAKE_ACK_TIMEOUT_MS))
|
2015-01-19 14:20:43 +00:00
|
|
|
DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
|
|
|
|
intel_uncore_forcewake_domain_to_str(d->id));
|
|
|
|
}
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2015-01-19 14:20:43 +00:00
|
|
|
static inline void
|
|
|
|
fw_domain_put(const struct intel_uncore_forcewake_domain *d)
|
|
|
|
{
|
|
|
|
__raw_i915_write32(d->i915, d->reg_set, d->val_clear);
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
|
|
|
|
2015-01-19 14:20:43 +00:00
|
|
|
static inline void
|
|
|
|
fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
|
2013-07-19 19:36:52 +00:00
|
|
|
{
|
2015-01-19 14:20:43 +00:00
|
|
|
/* something from same cacheline, but not from the set register */
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
if (i915_mmio_reg_valid(d->reg_post))
|
2015-01-19 14:20:43 +00:00
|
|
|
__raw_posting_read(d->i915, d->reg_post);
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
|
|
|
|
2015-01-19 14:20:43 +00:00
|
|
|
static void
|
2015-01-16 09:34:41 +00:00
|
|
|
fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
|
2013-07-19 19:36:52 +00:00
|
|
|
{
|
2015-01-19 14:20:43 +00:00
|
|
|
struct intel_uncore_forcewake_domain *d;
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2016-04-07 16:04:33 +00:00
|
|
|
for_each_fw_domain_masked(d, fw_domains, dev_priv) {
|
2015-01-19 14:20:43 +00:00
|
|
|
fw_domain_wait_ack_clear(d);
|
|
|
|
fw_domain_get(d);
|
|
|
|
}
|
2016-04-07 16:04:34 +00:00
|
|
|
|
|
|
|
for_each_fw_domain_masked(d, fw_domains, dev_priv)
|
|
|
|
fw_domain_wait_ack(d);
|
2015-01-19 14:20:43 +00:00
|
|
|
}
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2015-01-19 14:20:43 +00:00
|
|
|
static void
|
2015-01-16 09:34:41 +00:00
|
|
|
fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
|
2015-01-19 14:20:43 +00:00
|
|
|
{
|
|
|
|
struct intel_uncore_forcewake_domain *d;
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2016-04-07 16:04:33 +00:00
|
|
|
for_each_fw_domain_masked(d, fw_domains, dev_priv) {
|
2015-01-19 14:20:43 +00:00
|
|
|
fw_domain_put(d);
|
|
|
|
fw_domain_posting_read(d);
|
|
|
|
}
|
|
|
|
}
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2015-01-19 14:20:43 +00:00
|
|
|
static void
|
|
|
|
fw_domains_posting_read(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct intel_uncore_forcewake_domain *d;
|
|
|
|
|
|
|
|
/* No need to do for all, just do for first found */
|
2016-04-07 16:04:33 +00:00
|
|
|
for_each_fw_domain(d, dev_priv) {
|
2015-01-19 14:20:43 +00:00
|
|
|
fw_domain_posting_read(d);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2015-01-16 09:34:41 +00:00
|
|
|
fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
|
2015-01-19 14:20:43 +00:00
|
|
|
{
|
|
|
|
struct intel_uncore_forcewake_domain *d;
|
|
|
|
|
2015-02-05 15:45:42 +00:00
|
|
|
if (dev_priv->uncore.fw_domains == 0)
|
|
|
|
return;
|
2015-01-28 12:43:24 +00:00
|
|
|
|
2016-04-07 16:04:33 +00:00
|
|
|
for_each_fw_domain_masked(d, fw_domains, dev_priv)
|
2015-01-19 14:20:43 +00:00
|
|
|
fw_domain_reset(d);
|
|
|
|
|
|
|
|
fw_domains_posting_read(dev_priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
/* w/a for a sporadic read returning 0 by waiting for the GT
|
|
|
|
* thread to wake up.
|
|
|
|
*/
|
|
|
|
if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
|
|
|
|
GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
|
|
|
|
DRM_ERROR("GT thread status wait timed out\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
|
2015-01-16 09:34:41 +00:00
|
|
|
enum forcewake_domains fw_domains)
|
2015-01-19 14:20:43 +00:00
|
|
|
{
|
|
|
|
fw_domains_get(dev_priv, fw_domains);
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2015-01-19 14:20:43 +00:00
|
|
|
/* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
|
2014-11-10 12:52:50 +00:00
|
|
|
__gen6_gt_wait_for_thread_c0(dev_priv);
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
u32 gtfifodbg;
|
2013-07-19 19:36:53 +00:00
|
|
|
|
|
|
|
gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
|
2013-11-13 23:59:59 +00:00
|
|
|
if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
|
|
|
|
__raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
|
|
|
|
2015-01-19 14:20:43 +00:00
|
|
|
static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
|
2015-01-16 09:34:41 +00:00
|
|
|
enum forcewake_domains fw_domains)
|
2013-07-19 19:36:52 +00:00
|
|
|
{
|
2015-01-19 14:20:43 +00:00
|
|
|
fw_domains_put(dev_priv, fw_domains);
|
2013-07-19 19:36:52 +00:00
|
|
|
gen6_gt_check_fifodbg(dev_priv);
|
|
|
|
}
|
|
|
|
|
2014-12-10 18:12:12 +00:00
|
|
|
static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
|
|
|
|
|
|
|
|
return count & GT_FIFO_FREE_ENTRIES_MASK;
|
|
|
|
}
|
|
|
|
|
2013-07-19 19:36:52 +00:00
|
|
|
static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
drm/i915/vlv: Update Wait for FIFO and wait for 20 free entries. v3
On VLV, FIFO will be shared by both SW and HW. So, we read the
free entries through register and update dev_priv variable
and wait for only 20 entries to be free
From Deepak's follow-up mail explaining why vlv is special:
"On SB, Out of 64 FIFO Entries, 20 Entries will be used by HW and
remaining 44 will be used by the SW,. I think due to this reason, we
have a threshold of 20 Entries."
"On VLV, HW and SW can access all 64 fifo entries, I don't think
having a threshold of 20 Entries is mandatory on VLV. Also, since both
SW and HW can access all 64 Entries. I think on VLV, we need to update
the fifo_count before waiting for the FIFO."
v2: Apply mask when we read the number of free FIFO entries (Ville).
v3: Mask applied after reading the register (Deepak).
Signed-off-by: Deepak S <deepak.s@intel.com>
[danvet: Add further explanation from Deepak to commit message.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-29 10:26:30 +00:00
|
|
|
/* On VLV, FIFO will be shared by both SW and HW.
|
|
|
|
* So, we need to read the FREE_ENTRIES everytime */
|
2016-04-07 08:08:05 +00:00
|
|
|
if (IS_VALLEYVIEW(dev_priv))
|
2014-12-10 18:12:12 +00:00
|
|
|
dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
|
drm/i915/vlv: Update Wait for FIFO and wait for 20 free entries. v3
On VLV, FIFO will be shared by both SW and HW. So, we read the
free entries through register and update dev_priv variable
and wait for only 20 entries to be free
From Deepak's follow-up mail explaining why vlv is special:
"On SB, Out of 64 FIFO Entries, 20 Entries will be used by HW and
remaining 44 will be used by the SW,. I think due to this reason, we
have a threshold of 20 Entries."
"On VLV, HW and SW can access all 64 fifo entries, I don't think
having a threshold of 20 Entries is mandatory on VLV. Also, since both
SW and HW can access all 64 Entries. I think on VLV, we need to update
the fifo_count before waiting for the FIFO."
v2: Apply mask when we read the number of free FIFO entries (Ville).
v3: Mask applied after reading the register (Deepak).
Signed-off-by: Deepak S <deepak.s@intel.com>
[danvet: Add further explanation from Deepak to commit message.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-29 10:26:30 +00:00
|
|
|
|
2013-07-19 19:36:52 +00:00
|
|
|
if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
|
|
|
|
int loop = 500;
|
2014-12-10 18:12:12 +00:00
|
|
|
u32 fifo = fifo_free_entries(dev_priv);
|
|
|
|
|
2013-07-19 19:36:52 +00:00
|
|
|
while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
|
|
|
|
udelay(10);
|
2014-12-10 18:12:12 +00:00
|
|
|
fifo = fifo_free_entries(dev_priv);
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
|
|
|
if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
|
|
|
|
++ret;
|
|
|
|
dev_priv->uncore.fifo_count = fifo;
|
|
|
|
}
|
|
|
|
dev_priv->uncore.fifo_count--;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
drm/i915: Use consistent forcewake auto-release timeout across kernel configs
Because it is based on jiffies, current implementation releases the
forcewake at any time between straight away and between 1ms and 10ms,
depending on the kernel configuration (CONFIG_HZ).
This is probably not what has been desired, since the dynamics of keeping
parts of the GPU awake should not be correlated with this kernel
configuration parameter.
Change the auto-release mechanism to use hrtimers and set the timeout to
1ms with a 1ms of slack. This should make the GPU power consistent
across kernel configs, and timer slack should enable some timer coalescing
where multiple force-wake domains exist, or with unrelated timers.
For GlBench/T-Rex this decreases the number of forcewake releases from
~480 to ~300 per second, and for a heavy combined OGL/OCL test from
~670 to ~360 (HZ=1000 kernel).
Even though this reduction can be attributed to the average release period
extending from 0-1ms to 1-2ms, as discussed above, it will make the
forcewake timeout consistent for different CONFIG_HZ values.
Real life measurements with the above workload has shown that, with this
patch, both manage to auto-release the forcewake between 2-4 times per
10ms, even though the number of forcewake gets is dramatically different.
T-Rex requests between 5-10 explicit gets and 5-10 implict gets in each
10ms period, while the OGL/OCL test requests 250 and 380 times in the same
period.
The two data points together suggest that the nature of the forwake
accesses is bursty and that further changes and potential timeout
extensions, or moving the start of timeout from the first to the last
automatic forcewake grab, should be carefully measured for power and
performance effects.
v2:
* Commit spelling. (Dave Gordon)
* More discussion on numbers in the commit. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-04-07 16:04:32 +00:00
|
|
|
static enum hrtimer_restart
|
|
|
|
intel_uncore_fw_release_timer(struct hrtimer *timer)
|
2014-11-04 17:07:04 +00:00
|
|
|
{
|
drm/i915: Use consistent forcewake auto-release timeout across kernel configs
Because it is based on jiffies, current implementation releases the
forcewake at any time between straight away and between 1ms and 10ms,
depending on the kernel configuration (CONFIG_HZ).
This is probably not what has been desired, since the dynamics of keeping
parts of the GPU awake should not be correlated with this kernel
configuration parameter.
Change the auto-release mechanism to use hrtimers and set the timeout to
1ms with a 1ms of slack. This should make the GPU power consistent
across kernel configs, and timer slack should enable some timer coalescing
where multiple force-wake domains exist, or with unrelated timers.
For GlBench/T-Rex this decreases the number of forcewake releases from
~480 to ~300 per second, and for a heavy combined OGL/OCL test from
~670 to ~360 (HZ=1000 kernel).
Even though this reduction can be attributed to the average release period
extending from 0-1ms to 1-2ms, as discussed above, it will make the
forcewake timeout consistent for different CONFIG_HZ values.
Real life measurements with the above workload has shown that, with this
patch, both manage to auto-release the forcewake between 2-4 times per
10ms, even though the number of forcewake gets is dramatically different.
T-Rex requests between 5-10 explicit gets and 5-10 implict gets in each
10ms period, while the OGL/OCL test requests 250 and 380 times in the same
period.
The two data points together suggest that the nature of the forwake
accesses is bursty and that further changes and potential timeout
extensions, or moving the start of timeout from the first to the last
automatic forcewake grab, should be carefully measured for power and
performance effects.
v2:
* Commit spelling. (Dave Gordon)
* More discussion on numbers in the commit. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-04-07 16:04:32 +00:00
|
|
|
struct intel_uncore_forcewake_domain *domain =
|
|
|
|
container_of(timer, struct intel_uncore_forcewake_domain, timer);
|
2016-10-04 08:29:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = domain->i915;
|
2015-01-16 09:34:37 +00:00
|
|
|
unsigned long irqflags;
|
2014-11-04 17:07:04 +00:00
|
|
|
|
2016-10-04 08:29:17 +00:00
|
|
|
assert_rpm_device_not_suspended(dev_priv);
|
2014-11-04 17:07:04 +00:00
|
|
|
|
2016-10-04 08:29:17 +00:00
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
|
2015-01-16 09:34:37 +00:00
|
|
|
if (WARN_ON(domain->wake_count == 0))
|
|
|
|
domain->wake_count++;
|
|
|
|
|
2016-10-04 08:29:17 +00:00
|
|
|
if (--domain->wake_count == 0) {
|
|
|
|
dev_priv->uncore.funcs.force_wake_put(dev_priv, domain->mask);
|
|
|
|
dev_priv->uncore.fw_domains_active &= ~domain->mask;
|
|
|
|
}
|
2015-01-16 09:34:37 +00:00
|
|
|
|
2016-10-04 08:29:17 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
drm/i915: Use consistent forcewake auto-release timeout across kernel configs
Because it is based on jiffies, current implementation releases the
forcewake at any time between straight away and between 1ms and 10ms,
depending on the kernel configuration (CONFIG_HZ).
This is probably not what has been desired, since the dynamics of keeping
parts of the GPU awake should not be correlated with this kernel
configuration parameter.
Change the auto-release mechanism to use hrtimers and set the timeout to
1ms with a 1ms of slack. This should make the GPU power consistent
across kernel configs, and timer slack should enable some timer coalescing
where multiple force-wake domains exist, or with unrelated timers.
For GlBench/T-Rex this decreases the number of forcewake releases from
~480 to ~300 per second, and for a heavy combined OGL/OCL test from
~670 to ~360 (HZ=1000 kernel).
Even though this reduction can be attributed to the average release period
extending from 0-1ms to 1-2ms, as discussed above, it will make the
forcewake timeout consistent for different CONFIG_HZ values.
Real life measurements with the above workload has shown that, with this
patch, both manage to auto-release the forcewake between 2-4 times per
10ms, even though the number of forcewake gets is dramatically different.
T-Rex requests between 5-10 explicit gets and 5-10 implict gets in each
10ms period, while the OGL/OCL test requests 250 and 380 times in the same
period.
The two data points together suggest that the nature of the forwake
accesses is bursty and that further changes and potential timeout
extensions, or moving the start of timeout from the first to the last
automatic forcewake grab, should be carefully measured for power and
performance effects.
v2:
* Commit spelling. (Dave Gordon)
* More discussion on numbers in the commit. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-04-07 16:04:32 +00:00
|
|
|
|
|
|
|
return HRTIMER_NORESTART;
|
2014-11-04 17:07:04 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
|
|
|
|
bool restore)
|
2014-11-04 17:07:04 +00:00
|
|
|
{
|
2015-01-16 09:34:41 +00:00
|
|
|
unsigned long irqflags;
|
2015-01-16 09:34:37 +00:00
|
|
|
struct intel_uncore_forcewake_domain *domain;
|
2015-01-16 09:34:41 +00:00
|
|
|
int retry_count = 100;
|
2016-10-04 08:29:17 +00:00
|
|
|
enum forcewake_domains fw, active_domains;
|
2014-11-04 17:07:04 +00:00
|
|
|
|
2015-01-16 09:34:37 +00:00
|
|
|
/* Hold uncore.lock across reset to prevent any register access
|
|
|
|
* with forcewake not set correctly. Wait until all pending
|
|
|
|
* timers are run before holding.
|
|
|
|
*/
|
|
|
|
while (1) {
|
|
|
|
active_domains = 0;
|
2014-11-04 17:07:04 +00:00
|
|
|
|
2016-04-07 16:04:33 +00:00
|
|
|
for_each_fw_domain(domain, dev_priv) {
|
drm/i915: Use consistent forcewake auto-release timeout across kernel configs
Because it is based on jiffies, current implementation releases the
forcewake at any time between straight away and between 1ms and 10ms,
depending on the kernel configuration (CONFIG_HZ).
This is probably not what has been desired, since the dynamics of keeping
parts of the GPU awake should not be correlated with this kernel
configuration parameter.
Change the auto-release mechanism to use hrtimers and set the timeout to
1ms with a 1ms of slack. This should make the GPU power consistent
across kernel configs, and timer slack should enable some timer coalescing
where multiple force-wake domains exist, or with unrelated timers.
For GlBench/T-Rex this decreases the number of forcewake releases from
~480 to ~300 per second, and for a heavy combined OGL/OCL test from
~670 to ~360 (HZ=1000 kernel).
Even though this reduction can be attributed to the average release period
extending from 0-1ms to 1-2ms, as discussed above, it will make the
forcewake timeout consistent for different CONFIG_HZ values.
Real life measurements with the above workload has shown that, with this
patch, both manage to auto-release the forcewake between 2-4 times per
10ms, even though the number of forcewake gets is dramatically different.
T-Rex requests between 5-10 explicit gets and 5-10 implict gets in each
10ms period, while the OGL/OCL test requests 250 and 380 times in the same
period.
The two data points together suggest that the nature of the forwake
accesses is bursty and that further changes and potential timeout
extensions, or moving the start of timeout from the first to the last
automatic forcewake grab, should be carefully measured for power and
performance effects.
v2:
* Commit spelling. (Dave Gordon)
* More discussion on numbers in the commit. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-04-07 16:04:32 +00:00
|
|
|
if (hrtimer_cancel(&domain->timer) == 0)
|
2015-01-16 09:34:37 +00:00
|
|
|
continue;
|
2014-11-04 17:07:04 +00:00
|
|
|
|
drm/i915: Use consistent forcewake auto-release timeout across kernel configs
Because it is based on jiffies, current implementation releases the
forcewake at any time between straight away and between 1ms and 10ms,
depending on the kernel configuration (CONFIG_HZ).
This is probably not what has been desired, since the dynamics of keeping
parts of the GPU awake should not be correlated with this kernel
configuration parameter.
Change the auto-release mechanism to use hrtimers and set the timeout to
1ms with a 1ms of slack. This should make the GPU power consistent
across kernel configs, and timer slack should enable some timer coalescing
where multiple force-wake domains exist, or with unrelated timers.
For GlBench/T-Rex this decreases the number of forcewake releases from
~480 to ~300 per second, and for a heavy combined OGL/OCL test from
~670 to ~360 (HZ=1000 kernel).
Even though this reduction can be attributed to the average release period
extending from 0-1ms to 1-2ms, as discussed above, it will make the
forcewake timeout consistent for different CONFIG_HZ values.
Real life measurements with the above workload has shown that, with this
patch, both manage to auto-release the forcewake between 2-4 times per
10ms, even though the number of forcewake gets is dramatically different.
T-Rex requests between 5-10 explicit gets and 5-10 implict gets in each
10ms period, while the OGL/OCL test requests 250 and 380 times in the same
period.
The two data points together suggest that the nature of the forwake
accesses is bursty and that further changes and potential timeout
extensions, or moving the start of timeout from the first to the last
automatic forcewake grab, should be carefully measured for power and
performance effects.
v2:
* Commit spelling. (Dave Gordon)
* More discussion on numbers in the commit. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-04-07 16:04:32 +00:00
|
|
|
intel_uncore_fw_release_timer(&domain->timer);
|
2015-01-16 09:34:37 +00:00
|
|
|
}
|
2013-08-26 12:46:09 +00:00
|
|
|
|
2015-01-16 09:34:37 +00:00
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
|
2014-02-21 16:52:25 +00:00
|
|
|
|
2016-04-07 16:04:33 +00:00
|
|
|
for_each_fw_domain(domain, dev_priv) {
|
drm/i915: Use consistent forcewake auto-release timeout across kernel configs
Because it is based on jiffies, current implementation releases the
forcewake at any time between straight away and between 1ms and 10ms,
depending on the kernel configuration (CONFIG_HZ).
This is probably not what has been desired, since the dynamics of keeping
parts of the GPU awake should not be correlated with this kernel
configuration parameter.
Change the auto-release mechanism to use hrtimers and set the timeout to
1ms with a 1ms of slack. This should make the GPU power consistent
across kernel configs, and timer slack should enable some timer coalescing
where multiple force-wake domains exist, or with unrelated timers.
For GlBench/T-Rex this decreases the number of forcewake releases from
~480 to ~300 per second, and for a heavy combined OGL/OCL test from
~670 to ~360 (HZ=1000 kernel).
Even though this reduction can be attributed to the average release period
extending from 0-1ms to 1-2ms, as discussed above, it will make the
forcewake timeout consistent for different CONFIG_HZ values.
Real life measurements with the above workload has shown that, with this
patch, both manage to auto-release the forcewake between 2-4 times per
10ms, even though the number of forcewake gets is dramatically different.
T-Rex requests between 5-10 explicit gets and 5-10 implict gets in each
10ms period, while the OGL/OCL test requests 250 and 380 times in the same
period.
The two data points together suggest that the nature of the forwake
accesses is bursty and that further changes and potential timeout
extensions, or moving the start of timeout from the first to the last
automatic forcewake grab, should be carefully measured for power and
performance effects.
v2:
* Commit spelling. (Dave Gordon)
* More discussion on numbers in the commit. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-04-07 16:04:32 +00:00
|
|
|
if (hrtimer_active(&domain->timer))
|
2016-04-07 16:04:33 +00:00
|
|
|
active_domains |= domain->mask;
|
2015-01-16 09:34:37 +00:00
|
|
|
}
|
2014-03-15 19:20:29 +00:00
|
|
|
|
2015-01-16 09:34:37 +00:00
|
|
|
if (active_domains == 0)
|
|
|
|
break;
|
2013-08-26 12:46:09 +00:00
|
|
|
|
2015-01-16 09:34:37 +00:00
|
|
|
if (--retry_count == 0) {
|
|
|
|
DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
|
|
|
|
break;
|
|
|
|
}
|
2014-03-13 12:00:29 +00:00
|
|
|
|
2015-01-16 09:34:37 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
|
|
|
cond_resched();
|
|
|
|
}
|
2014-03-13 12:00:29 +00:00
|
|
|
|
2015-01-16 09:34:37 +00:00
|
|
|
WARN_ON(active_domains);
|
|
|
|
|
2016-10-04 08:29:17 +00:00
|
|
|
fw = dev_priv->uncore.fw_domains_active;
|
2015-01-16 09:34:37 +00:00
|
|
|
if (fw)
|
|
|
|
dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
|
2013-11-16 15:00:09 +00:00
|
|
|
|
2015-01-19 14:20:43 +00:00
|
|
|
fw_domains_reset(dev_priv, FORCEWAKE_ALL);
|
2014-11-04 17:07:04 +00:00
|
|
|
|
2014-03-13 12:00:29 +00:00
|
|
|
if (restore) { /* If reset with a user forcewake, try to restore */
|
|
|
|
if (fw)
|
|
|
|
dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
|
2014-03-13 12:00:29 +00:00
|
|
|
dev_priv->uncore.fifo_count =
|
2014-12-10 18:12:12 +00:00
|
|
|
fifo_free_entries(dev_priv);
|
2014-03-13 12:00:29 +00:00
|
|
|
}
|
|
|
|
|
2015-01-16 09:34:37 +00:00
|
|
|
if (!restore)
|
2015-01-16 09:34:40 +00:00
|
|
|
assert_forcewakes_inactive(dev_priv);
|
2015-01-16 09:34:37 +00:00
|
|
|
|
2014-03-13 12:00:29 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
2013-11-16 15:00:09 +00:00
|
|
|
}
|
|
|
|
|
2016-04-13 14:26:44 +00:00
|
|
|
static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
|
|
|
|
const unsigned int sets[4] = { 1, 1, 2, 2 };
|
|
|
|
const u32 cap = dev_priv->edram_cap;
|
|
|
|
|
|
|
|
return EDRAM_NUM_BANKS(cap) *
|
|
|
|
ways[EDRAM_WAYS_IDX(cap)] *
|
|
|
|
sets[EDRAM_SETS_IDX(cap)] *
|
|
|
|
1024 * 1024;
|
|
|
|
}
|
|
|
|
|
2016-04-13 14:26:43 +00:00
|
|
|
u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
|
2013-07-19 19:36:52 +00:00
|
|
|
{
|
2016-04-13 14:26:43 +00:00
|
|
|
if (!HAS_EDRAM(dev_priv))
|
|
|
|
return 0;
|
|
|
|
|
2016-04-13 14:26:44 +00:00
|
|
|
/* The needed capability bits for size calculation
|
|
|
|
* are not there with pre gen9 so return 128MB always.
|
2016-04-13 14:26:43 +00:00
|
|
|
*/
|
2016-04-13 14:26:44 +00:00
|
|
|
if (INTEL_GEN(dev_priv) < 9)
|
|
|
|
return 128 * 1024 * 1024;
|
2016-04-13 14:26:43 +00:00
|
|
|
|
2016-04-13 14:26:44 +00:00
|
|
|
return gen9_edram_size(dev_priv);
|
2016-04-13 14:26:43 +00:00
|
|
|
}
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2016-04-13 14:26:43 +00:00
|
|
|
static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
if (IS_HASWELL(dev_priv) ||
|
|
|
|
IS_BROADWELL(dev_priv) ||
|
|
|
|
INTEL_GEN(dev_priv) >= 9) {
|
|
|
|
dev_priv->edram_cap = __raw_i915_read32(dev_priv,
|
|
|
|
HSW_EDRAM_CAP);
|
|
|
|
|
|
|
|
/* NB: We can't write IDICR yet because we do not have gt funcs
|
2013-10-05 04:22:50 +00:00
|
|
|
* set up */
|
2016-04-13 14:26:43 +00:00
|
|
|
} else {
|
|
|
|
dev_priv->edram_cap = 0;
|
2013-10-05 04:22:50 +00:00
|
|
|
}
|
2016-04-13 14:26:43 +00:00
|
|
|
|
|
|
|
if (HAS_EDRAM(dev_priv))
|
|
|
|
DRM_INFO("Found %lluMB of eDRAM\n",
|
|
|
|
intel_uncore_edram_size(dev_priv) / (1024 * 1024));
|
2015-01-28 12:43:24 +00:00
|
|
|
}
|
|
|
|
|
2015-12-15 17:24:47 +00:00
|
|
|
static bool
|
2015-12-15 17:45:42 +00:00
|
|
|
fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
|
2015-12-15 17:24:47 +00:00
|
|
|
{
|
|
|
|
u32 dbg;
|
|
|
|
|
|
|
|
dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
|
|
|
|
if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2015-12-15 17:45:42 +00:00
|
|
|
static bool
|
|
|
|
vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
u32 cer;
|
|
|
|
|
|
|
|
cer = __raw_i915_read32(dev_priv, CLAIM_ER);
|
|
|
|
if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
__raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool
|
|
|
|
check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
|
|
|
|
return fpga_check_for_unclaimed_mmio(dev_priv);
|
|
|
|
|
|
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
|
|
|
return vlv_check_for_unclaimed_mmio(dev_priv);
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
|
2015-01-28 12:43:24 +00:00
|
|
|
bool restore_forcewake)
|
|
|
|
{
|
2015-12-15 17:24:47 +00:00
|
|
|
/* clear out unclaimed reg detection bit */
|
|
|
|
if (check_for_unclaimed_mmio(dev_priv))
|
|
|
|
DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2013-12-03 09:30:09 +00:00
|
|
|
/* clear out old GT FIFO errors */
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
|
2013-12-03 09:30:09 +00:00
|
|
|
__raw_i915_write32(dev_priv, GTFIFODBG,
|
|
|
|
__raw_i915_read32(dev_priv, GTFIFODBG));
|
|
|
|
|
2015-04-16 03:21:28 +00:00
|
|
|
/* WaDisableShadowRegForCpd:chv */
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_CHERRYVIEW(dev_priv)) {
|
2015-04-16 03:21:28 +00:00
|
|
|
__raw_i915_write32(dev_priv, GTFIFOCTL,
|
|
|
|
__raw_i915_read32(dev_priv, GTFIFOCTL) |
|
|
|
|
GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
|
|
|
|
GT_FIFO_CTL_RC6_POLICY_STALL);
|
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
|
2013-08-23 13:52:30 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
|
|
|
|
bool restore_forcewake)
|
2014-10-23 16:23:21 +00:00
|
|
|
{
|
2016-05-10 13:10:04 +00:00
|
|
|
__intel_uncore_early_sanitize(dev_priv, restore_forcewake);
|
|
|
|
i915_check_and_clear_faults(dev_priv);
|
2014-10-23 16:23:21 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
|
2013-08-23 13:52:30 +00:00
|
|
|
{
|
2016-05-10 13:10:04 +00:00
|
|
|
i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6);
|
2016-02-05 18:43:29 +00:00
|
|
|
|
2013-07-19 19:36:52 +00:00
|
|
|
/* BIOS often leaves RC6 enabled, but disable it for hw init */
|
2016-07-21 20:16:19 +00:00
|
|
|
intel_sanitize_gt_powersave(dev_priv);
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
|
|
|
|
2015-04-07 15:21:02 +00:00
|
|
|
static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
|
|
|
|
enum forcewake_domains fw_domains)
|
|
|
|
{
|
|
|
|
struct intel_uncore_forcewake_domain *domain;
|
|
|
|
|
|
|
|
fw_domains &= dev_priv->uncore.fw_domains;
|
|
|
|
|
2016-04-07 16:04:33 +00:00
|
|
|
for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
|
2015-04-07 15:21:02 +00:00
|
|
|
if (domain->wake_count++)
|
2016-04-07 16:04:33 +00:00
|
|
|
fw_domains &= ~domain->mask;
|
2015-04-07 15:21:02 +00:00
|
|
|
}
|
|
|
|
|
2016-10-04 08:29:17 +00:00
|
|
|
if (fw_domains) {
|
2015-04-07 15:21:02 +00:00
|
|
|
dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
|
2016-10-04 08:29:17 +00:00
|
|
|
dev_priv->uncore.fw_domains_active |= fw_domains;
|
|
|
|
}
|
2015-04-07 15:21:02 +00:00
|
|
|
}
|
|
|
|
|
2015-01-16 09:34:40 +00:00
|
|
|
/**
|
|
|
|
* intel_uncore_forcewake_get - grab forcewake domain references
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
* @fw_domains: forcewake domains to get reference on
|
|
|
|
*
|
|
|
|
* This function can be used get GT's forcewake domain references.
|
|
|
|
* Normal register access will handle the forcewake domains automatically.
|
|
|
|
* However if some sequence requires the GT to not power down a particular
|
|
|
|
* forcewake domains this function should be called at the beginning of the
|
|
|
|
* sequence. And subsequently the reference should be dropped by symmetric
|
|
|
|
* call to intel_unforce_forcewake_put(). Usually caller wants all the domains
|
|
|
|
* to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
|
2013-07-19 19:36:52 +00:00
|
|
|
*/
|
2015-01-16 09:34:40 +00:00
|
|
|
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
|
2015-01-16 09:34:41 +00:00
|
|
|
enum forcewake_domains fw_domains)
|
2013-07-19 19:36:52 +00:00
|
|
|
{
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
2013-10-06 00:57:11 +00:00
|
|
|
if (!dev_priv->uncore.funcs.force_wake_get)
|
|
|
|
return;
|
|
|
|
|
2015-12-15 18:10:34 +00:00
|
|
|
assert_rpm_wakelock_held(dev_priv);
|
2013-11-27 20:21:54 +00:00
|
|
|
|
2015-01-16 09:34:35 +00:00
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
|
2015-04-07 15:21:02 +00:00
|
|
|
__intel_uncore_forcewake_get(dev_priv, fw_domains);
|
2013-07-19 19:36:52 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
|
|
|
}
|
|
|
|
|
2015-01-16 09:34:40 +00:00
|
|
|
/**
|
2015-04-07 15:21:02 +00:00
|
|
|
* intel_uncore_forcewake_get__locked - grab forcewake domain references
|
2015-01-16 09:34:40 +00:00
|
|
|
* @dev_priv: i915 device instance
|
2015-04-07 15:21:02 +00:00
|
|
|
* @fw_domains: forcewake domains to get reference on
|
2015-01-16 09:34:40 +00:00
|
|
|
*
|
2015-04-07 15:21:02 +00:00
|
|
|
* See intel_uncore_forcewake_get(). This variant places the onus
|
|
|
|
* on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
|
2013-07-19 19:36:52 +00:00
|
|
|
*/
|
2015-04-07 15:21:02 +00:00
|
|
|
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
|
|
|
|
enum forcewake_domains fw_domains)
|
|
|
|
{
|
|
|
|
assert_spin_locked(&dev_priv->uncore.lock);
|
|
|
|
|
|
|
|
if (!dev_priv->uncore.funcs.force_wake_get)
|
|
|
|
return;
|
|
|
|
|
|
|
|
__intel_uncore_forcewake_get(dev_priv, fw_domains);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
|
|
|
|
enum forcewake_domains fw_domains)
|
2013-07-19 19:36:52 +00:00
|
|
|
{
|
2015-01-16 09:34:37 +00:00
|
|
|
struct intel_uncore_forcewake_domain *domain;
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2015-01-16 09:34:37 +00:00
|
|
|
fw_domains &= dev_priv->uncore.fw_domains;
|
|
|
|
|
2016-04-07 16:04:33 +00:00
|
|
|
for_each_fw_domain_masked(domain, fw_domains, dev_priv) {
|
2015-01-16 09:34:37 +00:00
|
|
|
if (WARN_ON(domain->wake_count == 0))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (--domain->wake_count)
|
|
|
|
continue;
|
|
|
|
|
2015-01-19 14:20:43 +00:00
|
|
|
fw_domain_arm_timer(domain);
|
2013-08-26 12:46:09 +00:00
|
|
|
}
|
2015-04-07 15:21:02 +00:00
|
|
|
}
|
2015-01-16 09:34:34 +00:00
|
|
|
|
2015-04-07 15:21:02 +00:00
|
|
|
/**
|
|
|
|
* intel_uncore_forcewake_put - release a forcewake domain reference
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
* @fw_domains: forcewake domains to put references
|
|
|
|
*
|
|
|
|
* This function drops the device-level forcewakes for specified
|
|
|
|
* domains obtained by intel_uncore_forcewake_get().
|
|
|
|
*/
|
|
|
|
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
|
|
|
|
enum forcewake_domains fw_domains)
|
|
|
|
{
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
if (!dev_priv->uncore.funcs.force_wake_put)
|
|
|
|
return;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
|
|
|
|
__intel_uncore_forcewake_put(dev_priv, fw_domains);
|
2013-07-19 19:36:52 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
|
|
|
}
|
|
|
|
|
2015-04-07 15:21:02 +00:00
|
|
|
/**
|
|
|
|
* intel_uncore_forcewake_put__locked - grab forcewake domain references
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
* @fw_domains: forcewake domains to get reference on
|
|
|
|
*
|
|
|
|
* See intel_uncore_forcewake_put(). This variant places the onus
|
|
|
|
* on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
|
|
|
|
*/
|
|
|
|
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
|
|
|
|
enum forcewake_domains fw_domains)
|
|
|
|
{
|
|
|
|
assert_spin_locked(&dev_priv->uncore.lock);
|
|
|
|
|
|
|
|
if (!dev_priv->uncore.funcs.force_wake_put)
|
|
|
|
return;
|
|
|
|
|
|
|
|
__intel_uncore_forcewake_put(dev_priv, fw_domains);
|
|
|
|
}
|
|
|
|
|
2015-01-16 09:34:40 +00:00
|
|
|
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
|
2014-02-21 16:52:26 +00:00
|
|
|
{
|
|
|
|
if (!dev_priv->uncore.funcs.force_wake_get)
|
|
|
|
return;
|
|
|
|
|
2016-10-04 08:29:17 +00:00
|
|
|
WARN_ON(dev_priv->uncore.fw_domains_active);
|
2014-02-21 16:52:26 +00:00
|
|
|
}
|
|
|
|
|
2013-07-19 19:36:52 +00:00
|
|
|
/* We give fast paths for the really cool registers */
|
2015-10-22 12:34:57 +00:00
|
|
|
#define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2016-04-12 13:37:29 +00:00
|
|
|
#define __gen6_reg_read_fw_domains(offset) \
|
|
|
|
({ \
|
|
|
|
enum forcewake_domains __fwd; \
|
|
|
|
if (NEEDS_FORCE_WAKE(offset)) \
|
|
|
|
__fwd = FORCEWAKE_RENDER; \
|
|
|
|
else \
|
|
|
|
__fwd = 0; \
|
|
|
|
__fwd; \
|
|
|
|
})
|
|
|
|
|
2016-10-04 08:29:29 +00:00
|
|
|
static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
|
2016-10-04 08:29:21 +00:00
|
|
|
{
|
|
|
|
if (offset < entry->start)
|
|
|
|
return -1;
|
|
|
|
else if (offset > entry->end)
|
|
|
|
return 1;
|
|
|
|
else
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-10-04 08:29:29 +00:00
|
|
|
/* Copied and "macroized" from lib/bsearch.c */
|
|
|
|
#define BSEARCH(key, base, num, cmp) ({ \
|
|
|
|
unsigned int start__ = 0, end__ = (num); \
|
|
|
|
typeof(base) result__ = NULL; \
|
|
|
|
while (start__ < end__) { \
|
|
|
|
unsigned int mid__ = start__ + (end__ - start__) / 2; \
|
|
|
|
int ret__ = (cmp)((key), (base) + mid__); \
|
|
|
|
if (ret__ < 0) { \
|
|
|
|
end__ = mid__; \
|
|
|
|
} else if (ret__ > 0) { \
|
|
|
|
start__ = mid__ + 1; \
|
|
|
|
} else { \
|
|
|
|
result__ = (base) + mid__; \
|
|
|
|
break; \
|
|
|
|
} \
|
|
|
|
} \
|
|
|
|
result__; \
|
|
|
|
})
|
|
|
|
|
2016-10-04 08:29:19 +00:00
|
|
|
static enum forcewake_domains
|
2016-10-04 08:29:23 +00:00
|
|
|
find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
|
2016-10-04 08:29:19 +00:00
|
|
|
{
|
2016-10-04 08:29:29 +00:00
|
|
|
const struct intel_forcewake_range *entry;
|
2016-10-04 08:29:19 +00:00
|
|
|
|
2016-10-04 08:29:29 +00:00
|
|
|
entry = BSEARCH(offset,
|
|
|
|
dev_priv->uncore.fw_domains_table,
|
|
|
|
dev_priv->uncore.fw_domains_table_entries,
|
2016-10-04 08:29:21 +00:00
|
|
|
fw_range_cmp);
|
2014-03-28 16:54:26 +00:00
|
|
|
|
2016-10-04 08:29:22 +00:00
|
|
|
return entry ? entry->domains : 0;
|
2016-10-04 08:29:19 +00:00
|
|
|
}
|
|
|
|
|
2016-10-04 08:29:20 +00:00
|
|
|
static void
|
2016-10-04 08:29:23 +00:00
|
|
|
intel_fw_table_check(struct drm_i915_private *dev_priv)
|
2016-10-04 08:29:20 +00:00
|
|
|
{
|
2016-10-04 08:29:23 +00:00
|
|
|
const struct intel_forcewake_range *ranges;
|
|
|
|
unsigned int num_ranges;
|
2016-10-04 08:29:20 +00:00
|
|
|
s32 prev;
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG))
|
|
|
|
return;
|
|
|
|
|
2016-10-04 08:29:23 +00:00
|
|
|
ranges = dev_priv->uncore.fw_domains_table;
|
|
|
|
if (!ranges)
|
|
|
|
return;
|
|
|
|
|
|
|
|
num_ranges = dev_priv->uncore.fw_domains_table_entries;
|
|
|
|
|
2016-10-04 08:29:20 +00:00
|
|
|
for (i = 0, prev = -1; i < num_ranges; i++, ranges++) {
|
|
|
|
WARN_ON_ONCE(prev >= (s32)ranges->start);
|
|
|
|
prev = ranges->start;
|
|
|
|
WARN_ON_ONCE(prev >= (s32)ranges->end);
|
|
|
|
prev = ranges->end;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-04 08:29:19 +00:00
|
|
|
#define GEN_FW_RANGE(s, e, d) \
|
|
|
|
{ .start = (s), .end = (e), .domains = (d) }
|
2014-05-23 15:30:16 +00:00
|
|
|
|
2016-10-04 08:29:24 +00:00
|
|
|
#define HAS_FWTABLE(dev_priv) \
|
|
|
|
(IS_GEN9(dev_priv) || \
|
|
|
|
IS_CHERRYVIEW(dev_priv) || \
|
|
|
|
IS_VALLEYVIEW(dev_priv))
|
|
|
|
|
2016-10-04 08:29:20 +00:00
|
|
|
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
|
2016-10-04 08:29:19 +00:00
|
|
|
static const struct intel_forcewake_range __vlv_fw_ranges[] = {
|
|
|
|
GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
|
|
|
|
GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
|
|
|
|
GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
|
|
|
|
GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
|
|
|
|
GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
|
2016-10-04 08:29:20 +00:00
|
|
|
GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
|
2016-10-04 08:29:19 +00:00
|
|
|
GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
|
|
|
|
};
|
2014-05-23 15:30:16 +00:00
|
|
|
|
2016-10-04 08:29:24 +00:00
|
|
|
#define __fwtable_reg_read_fw_domains(offset) \
|
2016-04-12 13:37:29 +00:00
|
|
|
({ \
|
|
|
|
enum forcewake_domains __fwd = 0; \
|
2016-10-04 08:29:22 +00:00
|
|
|
if (NEEDS_FORCE_WAKE((offset))) \
|
2016-10-04 08:29:23 +00:00
|
|
|
__fwd = find_fw_domain(dev_priv, offset); \
|
2016-04-12 13:37:29 +00:00
|
|
|
__fwd; \
|
|
|
|
})
|
|
|
|
|
2016-10-04 08:29:27 +00:00
|
|
|
/* *Must* be sorted by offset! See intel_shadow_table_check(). */
|
2016-04-12 13:37:29 +00:00
|
|
|
static const i915_reg_t gen8_shadowed_regs[] = {
|
2016-10-04 08:29:27 +00:00
|
|
|
RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
|
|
|
|
GEN6_RPNSWREQ, /* 0xA008 */
|
|
|
|
GEN6_RC_VIDEO_FREQ, /* 0xA00C */
|
|
|
|
RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */
|
|
|
|
RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */
|
|
|
|
RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
|
2016-04-12 13:37:29 +00:00
|
|
|
/* TODO: Other registers are not yet used */
|
|
|
|
};
|
|
|
|
|
2016-10-04 08:29:27 +00:00
|
|
|
static void intel_shadow_table_check(void)
|
|
|
|
{
|
|
|
|
const i915_reg_t *reg = gen8_shadowed_regs;
|
|
|
|
s32 prev;
|
|
|
|
u32 offset;
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG))
|
|
|
|
return;
|
|
|
|
|
|
|
|
for (i = 0, prev = -1; i < ARRAY_SIZE(gen8_shadowed_regs); i++, reg++) {
|
|
|
|
offset = i915_mmio_reg_offset(*reg);
|
|
|
|
WARN_ON_ONCE(prev >= (s32)offset);
|
|
|
|
prev = offset;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-04 08:29:29 +00:00
|
|
|
static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
|
2016-10-04 08:29:28 +00:00
|
|
|
{
|
2016-10-04 08:29:29 +00:00
|
|
|
u32 offset = i915_mmio_reg_offset(*reg);
|
2016-10-04 08:29:28 +00:00
|
|
|
|
2016-10-04 08:29:29 +00:00
|
|
|
if (key < offset)
|
2016-10-04 08:29:28 +00:00
|
|
|
return -1;
|
2016-10-04 08:29:29 +00:00
|
|
|
else if (key > offset)
|
2016-10-04 08:29:28 +00:00
|
|
|
return 1;
|
|
|
|
else
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-04-12 13:37:29 +00:00
|
|
|
static bool is_gen8_shadowed(u32 offset)
|
|
|
|
{
|
2016-10-04 08:29:29 +00:00
|
|
|
const i915_reg_t *regs = gen8_shadowed_regs;
|
2016-10-04 08:29:28 +00:00
|
|
|
|
2016-10-04 08:29:29 +00:00
|
|
|
return BSEARCH(offset, regs, ARRAY_SIZE(gen8_shadowed_regs),
|
|
|
|
mmio_reg_cmp);
|
2016-04-12 13:37:29 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#define __gen8_reg_write_fw_domains(offset) \
|
|
|
|
({ \
|
|
|
|
enum forcewake_domains __fwd; \
|
|
|
|
if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
|
|
|
|
__fwd = FORCEWAKE_RENDER; \
|
|
|
|
else \
|
|
|
|
__fwd = 0; \
|
|
|
|
__fwd; \
|
|
|
|
})
|
|
|
|
|
2016-10-04 08:29:20 +00:00
|
|
|
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
|
2016-10-04 08:29:19 +00:00
|
|
|
static const struct intel_forcewake_range __chv_fw_ranges[] = {
|
|
|
|
GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
|
2016-10-04 08:29:20 +00:00
|
|
|
GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
|
2016-10-04 08:29:19 +00:00
|
|
|
GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
|
2016-10-04 08:29:20 +00:00
|
|
|
GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
|
2016-10-04 08:29:19 +00:00
|
|
|
GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
|
2016-10-04 08:29:20 +00:00
|
|
|
GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
|
2016-10-04 08:29:19 +00:00
|
|
|
GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
|
2016-10-04 08:29:20 +00:00
|
|
|
GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
|
|
|
|
GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
|
2016-10-04 08:29:19 +00:00
|
|
|
GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
|
2016-10-04 08:29:20 +00:00
|
|
|
GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
|
|
|
|
GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
|
2016-10-04 08:29:19 +00:00
|
|
|
GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
|
|
|
|
GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
|
|
|
|
GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
|
|
|
|
GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
|
|
|
|
};
|
2014-03-28 16:54:26 +00:00
|
|
|
|
2016-10-04 08:29:26 +00:00
|
|
|
#define __fwtable_reg_write_fw_domains(offset) \
|
2016-04-12 13:37:29 +00:00
|
|
|
({ \
|
|
|
|
enum forcewake_domains __fwd = 0; \
|
2016-10-04 08:29:22 +00:00
|
|
|
if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
|
2016-10-04 08:29:23 +00:00
|
|
|
__fwd = find_fw_domain(dev_priv, offset); \
|
2016-04-12 13:37:29 +00:00
|
|
|
__fwd; \
|
|
|
|
})
|
|
|
|
|
2016-10-04 08:29:20 +00:00
|
|
|
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
|
2016-10-04 08:29:19 +00:00
|
|
|
static const struct intel_forcewake_range __gen9_fw_ranges[] = {
|
2016-10-04 08:29:22 +00:00
|
|
|
GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
|
2016-10-04 08:29:19 +00:00
|
|
|
GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
|
|
|
|
GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
|
2016-10-04 08:29:22 +00:00
|
|
|
GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
|
2016-10-04 08:29:19 +00:00
|
|
|
GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
|
2016-10-04 08:29:22 +00:00
|
|
|
GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
|
2016-10-04 08:29:19 +00:00
|
|
|
GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
|
2016-10-04 08:29:22 +00:00
|
|
|
GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
|
2016-10-04 08:29:20 +00:00
|
|
|
GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
|
2016-10-04 08:29:19 +00:00
|
|
|
GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
|
2016-10-04 08:29:22 +00:00
|
|
|
GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
|
2016-10-04 08:29:19 +00:00
|
|
|
GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
|
2016-10-04 08:29:22 +00:00
|
|
|
GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
|
2016-10-04 08:29:20 +00:00
|
|
|
GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
|
2016-10-04 08:29:22 +00:00
|
|
|
GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
|
2016-10-04 08:29:19 +00:00
|
|
|
GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
|
2016-10-04 08:29:22 +00:00
|
|
|
GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
|
2016-10-04 08:29:19 +00:00
|
|
|
GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
|
2016-10-04 08:29:22 +00:00
|
|
|
GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
|
2016-10-04 08:29:20 +00:00
|
|
|
GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
|
2016-10-04 08:29:22 +00:00
|
|
|
GEN_FW_RANGE(0xb480, 0xbfff, FORCEWAKE_BLITTER),
|
2016-10-04 08:29:19 +00:00
|
|
|
GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
|
2016-10-04 08:29:22 +00:00
|
|
|
GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
|
2016-10-04 08:29:20 +00:00
|
|
|
GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
|
2016-10-04 08:29:22 +00:00
|
|
|
GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
|
2016-10-04 08:29:19 +00:00
|
|
|
GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
|
2016-10-04 08:29:22 +00:00
|
|
|
GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
|
2016-10-04 08:29:19 +00:00
|
|
|
GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
|
2016-10-04 08:29:22 +00:00
|
|
|
GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
|
2016-10-04 08:29:20 +00:00
|
|
|
GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
|
2016-10-04 08:29:22 +00:00
|
|
|
GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
|
2016-10-04 08:29:19 +00:00
|
|
|
GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
|
|
|
|
};
|
2016-04-12 13:37:29 +00:00
|
|
|
|
2013-07-19 19:36:52 +00:00
|
|
|
static void
|
|
|
|
ilk_dummy_write(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
|
|
|
|
* the chip from rc6 before touching it for real. MI_MODE is masked,
|
|
|
|
* hence harmless to write 0 into. */
|
2013-07-19 19:36:53 +00:00
|
|
|
__raw_i915_write32(dev_priv, MI_MODE, 0);
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-01-08 13:51:19 +00:00
|
|
|
__unclaimed_reg_debug(struct drm_i915_private *dev_priv,
|
|
|
|
const i915_reg_t reg,
|
|
|
|
const bool read,
|
|
|
|
const bool before)
|
2013-07-19 19:36:52 +00:00
|
|
|
{
|
2016-10-03 12:45:14 +00:00
|
|
|
if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
|
|
|
|
"Unclaimed %s register 0x%x\n",
|
|
|
|
read ? "read from" : "write to",
|
2015-12-15 14:25:10 +00:00
|
|
|
i915_mmio_reg_offset(reg)))
|
2014-12-18 10:55:50 +00:00
|
|
|
i915.mmio_debug--; /* Only report the first N failures */
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
|
|
|
|
2016-01-08 13:51:19 +00:00
|
|
|
static inline void
|
|
|
|
unclaimed_reg_debug(struct drm_i915_private *dev_priv,
|
|
|
|
const i915_reg_t reg,
|
|
|
|
const bool read,
|
|
|
|
const bool before)
|
|
|
|
{
|
|
|
|
if (likely(!i915.mmio_debug))
|
|
|
|
return;
|
|
|
|
|
|
|
|
__unclaimed_reg_debug(dev_priv, reg, read, before);
|
|
|
|
}
|
|
|
|
|
2015-01-16 09:34:36 +00:00
|
|
|
#define GEN2_READ_HEADER(x) \
|
2013-10-05 04:24:53 +00:00
|
|
|
u##x val = 0; \
|
2015-12-15 18:10:33 +00:00
|
|
|
assert_rpm_wakelock_held(dev_priv);
|
2013-10-05 04:24:53 +00:00
|
|
|
|
2015-01-16 09:34:36 +00:00
|
|
|
#define GEN2_READ_FOOTER \
|
2013-10-05 04:24:53 +00:00
|
|
|
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
|
|
|
|
return val
|
|
|
|
|
2015-01-16 09:34:36 +00:00
|
|
|
#define __gen2_read(x) \
|
2013-10-05 04:22:51 +00:00
|
|
|
static u##x \
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN2_READ_HEADER(x); \
|
2013-10-05 04:22:53 +00:00
|
|
|
val = __raw_i915_read##x(dev_priv, reg); \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN2_READ_FOOTER; \
|
2013-10-05 04:22:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#define __gen5_read(x) \
|
|
|
|
static u##x \
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN2_READ_HEADER(x); \
|
2013-10-05 04:22:53 +00:00
|
|
|
ilk_dummy_write(dev_priv); \
|
|
|
|
val = __raw_i915_read##x(dev_priv, reg); \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN2_READ_FOOTER; \
|
2013-10-05 04:22:53 +00:00
|
|
|
}
|
|
|
|
|
2015-01-16 09:34:36 +00:00
|
|
|
__gen5_read(8)
|
|
|
|
__gen5_read(16)
|
|
|
|
__gen5_read(32)
|
|
|
|
__gen5_read(64)
|
|
|
|
__gen2_read(8)
|
|
|
|
__gen2_read(16)
|
|
|
|
__gen2_read(32)
|
|
|
|
__gen2_read(64)
|
|
|
|
|
|
|
|
#undef __gen5_read
|
|
|
|
#undef __gen2_read
|
|
|
|
|
|
|
|
#undef GEN2_READ_FOOTER
|
|
|
|
#undef GEN2_READ_HEADER
|
|
|
|
|
|
|
|
#define GEN6_READ_HEADER(x) \
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
u32 offset = i915_mmio_reg_offset(reg); \
|
2015-01-16 09:34:36 +00:00
|
|
|
unsigned long irqflags; \
|
|
|
|
u##x val = 0; \
|
2015-12-15 18:10:33 +00:00
|
|
|
assert_rpm_wakelock_held(dev_priv); \
|
2016-01-08 13:51:19 +00:00
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
|
|
|
|
unclaimed_reg_debug(dev_priv, reg, true, true)
|
2015-01-16 09:34:36 +00:00
|
|
|
|
|
|
|
#define GEN6_READ_FOOTER \
|
2016-01-08 13:51:19 +00:00
|
|
|
unclaimed_reg_debug(dev_priv, reg, true, false); \
|
2015-01-16 09:34:36 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
|
|
|
|
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
|
|
|
|
return val
|
|
|
|
|
2016-10-04 08:29:18 +00:00
|
|
|
static noinline void ___force_wake_auto(struct drm_i915_private *dev_priv,
|
|
|
|
enum forcewake_domains fw_domains)
|
2015-01-16 09:34:37 +00:00
|
|
|
{
|
|
|
|
struct intel_uncore_forcewake_domain *domain;
|
|
|
|
|
2016-10-04 08:29:18 +00:00
|
|
|
for_each_fw_domain_masked(domain, fw_domains, dev_priv)
|
|
|
|
fw_domain_arm_timer(domain);
|
|
|
|
|
|
|
|
dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
|
|
|
|
dev_priv->uncore.fw_domains_active |= fw_domains;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
|
|
|
|
enum forcewake_domains fw_domains)
|
|
|
|
{
|
2015-01-16 09:34:37 +00:00
|
|
|
if (WARN_ON(!fw_domains))
|
|
|
|
return;
|
|
|
|
|
2016-10-04 08:29:17 +00:00
|
|
|
/* Turn on all requested but inactive supported forcewake domains. */
|
|
|
|
fw_domains &= dev_priv->uncore.fw_domains;
|
|
|
|
fw_domains &= ~dev_priv->uncore.fw_domains_active;
|
2015-01-16 09:34:37 +00:00
|
|
|
|
2016-10-04 08:29:18 +00:00
|
|
|
if (fw_domains)
|
|
|
|
___force_wake_auto(dev_priv, fw_domains);
|
2015-01-16 09:34:37 +00:00
|
|
|
}
|
|
|
|
|
2013-10-05 04:22:53 +00:00
|
|
|
#define __gen6_read(x) \
|
|
|
|
static u##x \
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
|
2016-04-12 13:37:29 +00:00
|
|
|
enum forcewake_domains fw_engine; \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN6_READ_HEADER(x); \
|
2016-04-12 13:37:29 +00:00
|
|
|
fw_engine = __gen6_reg_read_fw_domains(offset); \
|
|
|
|
if (fw_engine) \
|
|
|
|
__force_wake_auto(dev_priv, fw_engine); \
|
2015-01-16 09:34:34 +00:00
|
|
|
val = __raw_i915_read##x(dev_priv, reg); \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN6_READ_FOOTER; \
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
|
|
|
|
2016-10-04 08:29:25 +00:00
|
|
|
#define __fwtable_read(x) \
|
2013-11-23 09:25:43 +00:00
|
|
|
static u##x \
|
2016-10-04 08:29:25 +00:00
|
|
|
fwtable_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
|
2016-04-12 13:37:29 +00:00
|
|
|
enum forcewake_domains fw_engine; \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN6_READ_HEADER(x); \
|
2016-10-04 08:29:24 +00:00
|
|
|
fw_engine = __fwtable_reg_read_fw_domains(offset); \
|
2015-10-22 12:34:59 +00:00
|
|
|
if (fw_engine) \
|
2016-03-24 14:31:47 +00:00
|
|
|
__force_wake_auto(dev_priv, fw_engine); \
|
2014-02-27 20:07:21 +00:00
|
|
|
val = __raw_i915_read##x(dev_priv, reg); \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN6_READ_FOOTER; \
|
2013-11-23 09:25:43 +00:00
|
|
|
}
|
|
|
|
|
2016-10-04 08:29:25 +00:00
|
|
|
__fwtable_read(8)
|
|
|
|
__fwtable_read(16)
|
|
|
|
__fwtable_read(32)
|
|
|
|
__fwtable_read(64)
|
2013-10-05 04:22:53 +00:00
|
|
|
__gen6_read(8)
|
|
|
|
__gen6_read(16)
|
|
|
|
__gen6_read(32)
|
|
|
|
__gen6_read(64)
|
|
|
|
|
2016-10-04 08:29:25 +00:00
|
|
|
#undef __fwtable_read
|
2013-10-05 04:22:53 +00:00
|
|
|
#undef __gen6_read
|
2015-01-16 09:34:36 +00:00
|
|
|
#undef GEN6_READ_FOOTER
|
|
|
|
#undef GEN6_READ_HEADER
|
2013-10-05 04:24:53 +00:00
|
|
|
|
2015-11-04 21:20:13 +00:00
|
|
|
#define VGPU_READ_HEADER(x) \
|
|
|
|
unsigned long irqflags; \
|
|
|
|
u##x val = 0; \
|
2015-12-15 18:10:33 +00:00
|
|
|
assert_rpm_device_not_suspended(dev_priv); \
|
2015-11-04 21:20:13 +00:00
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
|
|
|
|
|
|
|
|
#define VGPU_READ_FOOTER \
|
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
|
|
|
|
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
|
|
|
|
return val
|
|
|
|
|
|
|
|
#define __vgpu_read(x) \
|
|
|
|
static u##x \
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
|
2015-11-04 21:20:13 +00:00
|
|
|
VGPU_READ_HEADER(x); \
|
|
|
|
val = __raw_i915_read##x(dev_priv, reg); \
|
|
|
|
VGPU_READ_FOOTER; \
|
|
|
|
}
|
|
|
|
|
|
|
|
__vgpu_read(8)
|
|
|
|
__vgpu_read(16)
|
|
|
|
__vgpu_read(32)
|
|
|
|
__vgpu_read(64)
|
|
|
|
|
|
|
|
#undef __vgpu_read
|
|
|
|
#undef VGPU_READ_FOOTER
|
|
|
|
#undef VGPU_READ_HEADER
|
|
|
|
|
2015-01-16 09:34:36 +00:00
|
|
|
#define GEN2_WRITE_HEADER \
|
2013-10-05 04:24:53 +00:00
|
|
|
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
|
2015-12-15 18:10:33 +00:00
|
|
|
assert_rpm_wakelock_held(dev_priv); \
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2015-01-16 09:34:36 +00:00
|
|
|
#define GEN2_WRITE_FOOTER
|
2013-12-02 12:23:02 +00:00
|
|
|
|
2015-01-16 09:34:36 +00:00
|
|
|
#define __gen2_write(x) \
|
2013-10-05 04:22:51 +00:00
|
|
|
static void \
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN2_WRITE_HEADER; \
|
2013-10-05 04:22:54 +00:00
|
|
|
__raw_i915_write##x(dev_priv, reg, val); \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN2_WRITE_FOOTER; \
|
2013-10-05 04:22:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#define __gen5_write(x) \
|
|
|
|
static void \
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN2_WRITE_HEADER; \
|
2013-10-05 04:22:54 +00:00
|
|
|
ilk_dummy_write(dev_priv); \
|
|
|
|
__raw_i915_write##x(dev_priv, reg, val); \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN2_WRITE_FOOTER; \
|
2013-10-05 04:22:54 +00:00
|
|
|
}
|
|
|
|
|
2015-01-16 09:34:36 +00:00
|
|
|
__gen5_write(8)
|
|
|
|
__gen5_write(16)
|
|
|
|
__gen5_write(32)
|
|
|
|
__gen2_write(8)
|
|
|
|
__gen2_write(16)
|
|
|
|
__gen2_write(32)
|
|
|
|
|
|
|
|
#undef __gen5_write
|
|
|
|
#undef __gen2_write
|
|
|
|
|
|
|
|
#undef GEN2_WRITE_FOOTER
|
|
|
|
#undef GEN2_WRITE_HEADER
|
|
|
|
|
|
|
|
#define GEN6_WRITE_HEADER \
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
u32 offset = i915_mmio_reg_offset(reg); \
|
2015-01-16 09:34:36 +00:00
|
|
|
unsigned long irqflags; \
|
|
|
|
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
|
2015-12-15 18:10:33 +00:00
|
|
|
assert_rpm_wakelock_held(dev_priv); \
|
2016-01-08 13:51:19 +00:00
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
|
|
|
|
unclaimed_reg_debug(dev_priv, reg, false, true)
|
2015-01-16 09:34:36 +00:00
|
|
|
|
|
|
|
#define GEN6_WRITE_FOOTER \
|
2016-01-08 13:51:19 +00:00
|
|
|
unclaimed_reg_debug(dev_priv, reg, false, false); \
|
2015-01-16 09:34:36 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
|
|
|
|
|
2013-10-05 04:22:54 +00:00
|
|
|
#define __gen6_write(x) \
|
|
|
|
static void \
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
|
2013-10-05 04:22:54 +00:00
|
|
|
u32 __fifo_ret = 0; \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN6_WRITE_HEADER; \
|
2015-11-06 19:47:16 +00:00
|
|
|
if (NEEDS_FORCE_WAKE(offset)) { \
|
2013-10-05 04:22:54 +00:00
|
|
|
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
|
|
|
|
} \
|
|
|
|
__raw_i915_write##x(dev_priv, reg, val); \
|
|
|
|
if (unlikely(__fifo_ret)) { \
|
|
|
|
gen6_gt_check_fifodbg(dev_priv); \
|
|
|
|
} \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN6_WRITE_FOOTER; \
|
2013-10-05 04:22:54 +00:00
|
|
|
}
|
|
|
|
|
drm/i915/bdw: Handle forcewake for writes on gen8
GEN8 removes the GT FIFO which we've all come to know and love. Instead
it offers a wider range of optimized registers which always keep a
shadowed copy, and are fed to the GPU when it wakes.
How this is implemented in hardware is still somewhat of a mystery. As
far as I can tell, the basic design is as follows:
If the register is not optimized, you must use the old forcewake
mechanism to bring the GT out of sleep. [1]
If register is in the optimized list the write will signal that the
GT should begin to come out of whatever sleep state it is in.
While the GT is coming out of sleep, the requested write will be stored
in an intermediate shadow register.
Do to the fact that the implementation details are not clear, I see
several risks:
1. Order is not preserved as it is with GT FIFO. If we issue multiple
writes to optimized registers, where order matters, we may need to
serialize it with forcewake.
2. The optimized registers have only 1 shadowed slot, meaning if we
issue multiple writes to the same register, and those values need to
reach the GPU in order, forcewake will be required.
[1] We could implement a SW queue the way the GT FIFO used to work if
desired.
NOTE: Compile tested only until we get real silicon.
v2:
- Use a default case to make future platforms also work.
- Get rid of IS_BROADWELL since that's not yet defined, but we want to
MMIO as soon as possible.
v3: Apply suggestions from Mika's review:
- s/optimized/shadowed/
- invert the logic of the helper so that it does what it says (the
code itself was correct, just confusing to read).
v4:
- Squash in lost break.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-03 04:07:00 +00:00
|
|
|
#define __gen8_write(x) \
|
|
|
|
static void \
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
|
2016-04-12 13:37:29 +00:00
|
|
|
enum forcewake_domains fw_engine; \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN6_WRITE_HEADER; \
|
2016-04-12 13:37:29 +00:00
|
|
|
fw_engine = __gen8_reg_write_fw_domains(offset); \
|
|
|
|
if (fw_engine) \
|
|
|
|
__force_wake_auto(dev_priv, fw_engine); \
|
2015-01-16 09:34:37 +00:00
|
|
|
__raw_i915_write##x(dev_priv, reg, val); \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN6_WRITE_FOOTER; \
|
drm/i915/bdw: Handle forcewake for writes on gen8
GEN8 removes the GT FIFO which we've all come to know and love. Instead
it offers a wider range of optimized registers which always keep a
shadowed copy, and are fed to the GPU when it wakes.
How this is implemented in hardware is still somewhat of a mystery. As
far as I can tell, the basic design is as follows:
If the register is not optimized, you must use the old forcewake
mechanism to bring the GT out of sleep. [1]
If register is in the optimized list the write will signal that the
GT should begin to come out of whatever sleep state it is in.
While the GT is coming out of sleep, the requested write will be stored
in an intermediate shadow register.
Do to the fact that the implementation details are not clear, I see
several risks:
1. Order is not preserved as it is with GT FIFO. If we issue multiple
writes to optimized registers, where order matters, we may need to
serialize it with forcewake.
2. The optimized registers have only 1 shadowed slot, meaning if we
issue multiple writes to the same register, and those values need to
reach the GPU in order, forcewake will be required.
[1] We could implement a SW queue the way the GT FIFO used to work if
desired.
NOTE: Compile tested only until we get real silicon.
v2:
- Use a default case to make future platforms also work.
- Get rid of IS_BROADWELL since that's not yet defined, but we want to
MMIO as soon as possible.
v3: Apply suggestions from Mika's review:
- s/optimized/shadowed/
- invert the logic of the helper so that it does what it says (the
code itself was correct, just confusing to read).
v4:
- Squash in lost break.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-03 04:07:00 +00:00
|
|
|
}
|
|
|
|
|
2016-10-04 08:29:26 +00:00
|
|
|
#define __fwtable_write(x) \
|
2014-05-23 15:30:16 +00:00
|
|
|
static void \
|
2016-10-04 08:29:26 +00:00
|
|
|
fwtable_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
|
2016-04-12 13:37:29 +00:00
|
|
|
enum forcewake_domains fw_engine; \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN6_WRITE_HEADER; \
|
2016-10-04 08:29:26 +00:00
|
|
|
fw_engine = __fwtable_reg_write_fw_domains(offset); \
|
2015-10-22 12:34:59 +00:00
|
|
|
if (fw_engine) \
|
2016-03-24 14:31:47 +00:00
|
|
|
__force_wake_auto(dev_priv, fw_engine); \
|
2014-05-23 15:30:16 +00:00
|
|
|
__raw_i915_write##x(dev_priv, reg, val); \
|
2015-01-16 09:34:36 +00:00
|
|
|
GEN6_WRITE_FOOTER; \
|
2014-05-23 15:30:16 +00:00
|
|
|
}
|
|
|
|
|
2016-10-04 08:29:26 +00:00
|
|
|
__fwtable_write(8)
|
|
|
|
__fwtable_write(16)
|
|
|
|
__fwtable_write(32)
|
drm/i915/bdw: Handle forcewake for writes on gen8
GEN8 removes the GT FIFO which we've all come to know and love. Instead
it offers a wider range of optimized registers which always keep a
shadowed copy, and are fed to the GPU when it wakes.
How this is implemented in hardware is still somewhat of a mystery. As
far as I can tell, the basic design is as follows:
If the register is not optimized, you must use the old forcewake
mechanism to bring the GT out of sleep. [1]
If register is in the optimized list the write will signal that the
GT should begin to come out of whatever sleep state it is in.
While the GT is coming out of sleep, the requested write will be stored
in an intermediate shadow register.
Do to the fact that the implementation details are not clear, I see
several risks:
1. Order is not preserved as it is with GT FIFO. If we issue multiple
writes to optimized registers, where order matters, we may need to
serialize it with forcewake.
2. The optimized registers have only 1 shadowed slot, meaning if we
issue multiple writes to the same register, and those values need to
reach the GPU in order, forcewake will be required.
[1] We could implement a SW queue the way the GT FIFO used to work if
desired.
NOTE: Compile tested only until we get real silicon.
v2:
- Use a default case to make future platforms also work.
- Get rid of IS_BROADWELL since that's not yet defined, but we want to
MMIO as soon as possible.
v3: Apply suggestions from Mika's review:
- s/optimized/shadowed/
- invert the logic of the helper so that it does what it says (the
code itself was correct, just confusing to read).
v4:
- Squash in lost break.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-03 04:07:00 +00:00
|
|
|
__gen8_write(8)
|
|
|
|
__gen8_write(16)
|
|
|
|
__gen8_write(32)
|
2013-10-05 04:22:54 +00:00
|
|
|
__gen6_write(8)
|
|
|
|
__gen6_write(16)
|
|
|
|
__gen6_write(32)
|
|
|
|
|
2016-10-04 08:29:26 +00:00
|
|
|
#undef __fwtable_write
|
drm/i915/bdw: Handle forcewake for writes on gen8
GEN8 removes the GT FIFO which we've all come to know and love. Instead
it offers a wider range of optimized registers which always keep a
shadowed copy, and are fed to the GPU when it wakes.
How this is implemented in hardware is still somewhat of a mystery. As
far as I can tell, the basic design is as follows:
If the register is not optimized, you must use the old forcewake
mechanism to bring the GT out of sleep. [1]
If register is in the optimized list the write will signal that the
GT should begin to come out of whatever sleep state it is in.
While the GT is coming out of sleep, the requested write will be stored
in an intermediate shadow register.
Do to the fact that the implementation details are not clear, I see
several risks:
1. Order is not preserved as it is with GT FIFO. If we issue multiple
writes to optimized registers, where order matters, we may need to
serialize it with forcewake.
2. The optimized registers have only 1 shadowed slot, meaning if we
issue multiple writes to the same register, and those values need to
reach the GPU in order, forcewake will be required.
[1] We could implement a SW queue the way the GT FIFO used to work if
desired.
NOTE: Compile tested only until we get real silicon.
v2:
- Use a default case to make future platforms also work.
- Get rid of IS_BROADWELL since that's not yet defined, but we want to
MMIO as soon as possible.
v3: Apply suggestions from Mika's review:
- s/optimized/shadowed/
- invert the logic of the helper so that it does what it says (the
code itself was correct, just confusing to read).
v4:
- Squash in lost break.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-03 04:07:00 +00:00
|
|
|
#undef __gen8_write
|
2013-10-05 04:22:54 +00:00
|
|
|
#undef __gen6_write
|
2015-01-16 09:34:36 +00:00
|
|
|
#undef GEN6_WRITE_FOOTER
|
|
|
|
#undef GEN6_WRITE_HEADER
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2015-11-04 21:20:13 +00:00
|
|
|
#define VGPU_WRITE_HEADER \
|
|
|
|
unsigned long irqflags; \
|
|
|
|
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
|
2015-12-15 18:10:33 +00:00
|
|
|
assert_rpm_device_not_suspended(dev_priv); \
|
2015-11-04 21:20:13 +00:00
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
|
|
|
|
|
|
|
|
#define VGPU_WRITE_FOOTER \
|
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
|
|
|
|
|
|
|
|
#define __vgpu_write(x) \
|
|
|
|
static void vgpu_write##x(struct drm_i915_private *dev_priv, \
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
i915_reg_t reg, u##x val, bool trace) { \
|
2015-11-04 21:20:13 +00:00
|
|
|
VGPU_WRITE_HEADER; \
|
|
|
|
__raw_i915_write##x(dev_priv, reg, val); \
|
|
|
|
VGPU_WRITE_FOOTER; \
|
|
|
|
}
|
|
|
|
|
|
|
|
__vgpu_write(8)
|
|
|
|
__vgpu_write(16)
|
|
|
|
__vgpu_write(32)
|
|
|
|
|
|
|
|
#undef __vgpu_write
|
|
|
|
#undef VGPU_WRITE_FOOTER
|
|
|
|
#undef VGPU_WRITE_HEADER
|
|
|
|
|
2014-10-23 07:28:24 +00:00
|
|
|
#define ASSIGN_WRITE_MMIO_VFUNCS(x) \
|
|
|
|
do { \
|
|
|
|
dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
|
|
|
|
dev_priv->uncore.funcs.mmio_writew = x##_write16; \
|
|
|
|
dev_priv->uncore.funcs.mmio_writel = x##_write32; \
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
#define ASSIGN_READ_MMIO_VFUNCS(x) \
|
|
|
|
do { \
|
|
|
|
dev_priv->uncore.funcs.mmio_readb = x##_read8; \
|
|
|
|
dev_priv->uncore.funcs.mmio_readw = x##_read16; \
|
|
|
|
dev_priv->uncore.funcs.mmio_readl = x##_read32; \
|
|
|
|
dev_priv->uncore.funcs.mmio_readq = x##_read64; \
|
|
|
|
} while (0)
|
|
|
|
|
2015-01-19 14:20:43 +00:00
|
|
|
|
|
|
|
static void fw_domain_init(struct drm_i915_private *dev_priv,
|
2015-01-16 09:34:41 +00:00
|
|
|
enum forcewake_domain_id domain_id,
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
i915_reg_t reg_set,
|
|
|
|
i915_reg_t reg_ack)
|
2015-01-19 14:20:43 +00:00
|
|
|
{
|
|
|
|
struct intel_uncore_forcewake_domain *d;
|
|
|
|
|
|
|
|
if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
|
|
|
|
return;
|
|
|
|
|
|
|
|
d = &dev_priv->uncore.fw_domain[domain_id];
|
|
|
|
|
|
|
|
WARN_ON(d->wake_count);
|
|
|
|
|
|
|
|
d->wake_count = 0;
|
|
|
|
d->reg_set = reg_set;
|
|
|
|
d->reg_ack = reg_ack;
|
|
|
|
|
|
|
|
if (IS_GEN6(dev_priv)) {
|
|
|
|
d->val_reset = 0;
|
|
|
|
d->val_set = FORCEWAKE_KERNEL;
|
|
|
|
d->val_clear = 0;
|
|
|
|
} else {
|
2015-02-09 19:33:12 +00:00
|
|
|
/* WaRsClearFWBitsAtReset:bdw,skl */
|
2015-01-19 14:20:43 +00:00
|
|
|
d->val_reset = _MASKED_BIT_DISABLE(0xffff);
|
|
|
|
d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
|
|
|
|
d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
|
|
|
|
}
|
|
|
|
|
2015-12-09 20:29:35 +00:00
|
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
2015-01-19 14:20:43 +00:00
|
|
|
d->reg_post = FORCEWAKE_ACK_VLV;
|
|
|
|
else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
|
|
|
|
d->reg_post = ECOBUS;
|
|
|
|
|
|
|
|
d->i915 = dev_priv;
|
|
|
|
d->id = domain_id;
|
|
|
|
|
2016-04-07 16:04:33 +00:00
|
|
|
BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
|
|
|
|
BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
|
|
|
|
BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
|
|
|
|
|
|
|
|
d->mask = 1 << domain_id;
|
|
|
|
|
drm/i915: Use consistent forcewake auto-release timeout across kernel configs
Because it is based on jiffies, current implementation releases the
forcewake at any time between straight away and between 1ms and 10ms,
depending on the kernel configuration (CONFIG_HZ).
This is probably not what has been desired, since the dynamics of keeping
parts of the GPU awake should not be correlated with this kernel
configuration parameter.
Change the auto-release mechanism to use hrtimers and set the timeout to
1ms with a 1ms of slack. This should make the GPU power consistent
across kernel configs, and timer slack should enable some timer coalescing
where multiple force-wake domains exist, or with unrelated timers.
For GlBench/T-Rex this decreases the number of forcewake releases from
~480 to ~300 per second, and for a heavy combined OGL/OCL test from
~670 to ~360 (HZ=1000 kernel).
Even though this reduction can be attributed to the average release period
extending from 0-1ms to 1-2ms, as discussed above, it will make the
forcewake timeout consistent for different CONFIG_HZ values.
Real life measurements with the above workload has shown that, with this
patch, both manage to auto-release the forcewake between 2-4 times per
10ms, even though the number of forcewake gets is dramatically different.
T-Rex requests between 5-10 explicit gets and 5-10 implict gets in each
10ms period, while the OGL/OCL test requests 250 and 380 times in the same
period.
The two data points together suggest that the nature of the forwake
accesses is bursty and that further changes and potential timeout
extensions, or moving the start of timeout from the first to the last
automatic forcewake grab, should be carefully measured for power and
performance effects.
v2:
* Commit spelling. (Dave Gordon)
* More discussion on numbers in the commit. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-04-07 16:04:32 +00:00
|
|
|
hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
|
|
|
|
d->timer.function = intel_uncore_fw_release_timer;
|
2015-01-19 14:20:43 +00:00
|
|
|
|
|
|
|
dev_priv->uncore.fw_domains |= (1 << domain_id);
|
2015-01-28 12:43:24 +00:00
|
|
|
|
|
|
|
fw_domain_reset(d);
|
2015-01-19 14:20:43 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
|
2013-10-05 04:22:51 +00:00
|
|
|
{
|
2016-04-07 08:08:05 +00:00
|
|
|
if (INTEL_INFO(dev_priv)->gen <= 5)
|
2015-02-05 15:45:42 +00:00
|
|
|
return;
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_GEN9(dev_priv)) {
|
2015-01-19 14:20:43 +00:00
|
|
|
dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
|
|
|
|
dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
|
|
|
|
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
|
|
|
|
FORCEWAKE_RENDER_GEN9,
|
|
|
|
FORCEWAKE_ACK_RENDER_GEN9);
|
|
|
|
fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
|
|
|
|
FORCEWAKE_BLITTER_GEN9,
|
|
|
|
FORCEWAKE_ACK_BLITTER_GEN9);
|
|
|
|
fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
|
|
|
|
FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
|
2016-05-10 13:10:04 +00:00
|
|
|
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
|
2015-01-19 14:20:43 +00:00
|
|
|
dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
|
2016-05-10 13:10:04 +00:00
|
|
|
if (!IS_CHERRYVIEW(dev_priv))
|
2015-01-16 09:34:39 +00:00
|
|
|
dev_priv->uncore.funcs.force_wake_put =
|
|
|
|
fw_domains_put_with_fifo;
|
|
|
|
else
|
|
|
|
dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
|
2015-01-19 14:20:43 +00:00
|
|
|
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
|
|
|
|
FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
|
|
|
|
fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
|
|
|
|
FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
|
2016-05-10 13:10:04 +00:00
|
|
|
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
|
2015-01-19 14:20:43 +00:00
|
|
|
dev_priv->uncore.funcs.force_wake_get =
|
|
|
|
fw_domains_get_with_thread_status;
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_HASWELL(dev_priv))
|
2016-04-14 11:39:02 +00:00
|
|
|
dev_priv->uncore.funcs.force_wake_put =
|
|
|
|
fw_domains_put_with_fifo;
|
|
|
|
else
|
|
|
|
dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
|
2015-01-19 14:20:43 +00:00
|
|
|
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
|
|
|
|
FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
|
2016-05-10 13:10:04 +00:00
|
|
|
} else if (IS_IVYBRIDGE(dev_priv)) {
|
2013-10-05 04:22:51 +00:00
|
|
|
u32 ecobus;
|
|
|
|
|
|
|
|
/* IVB configs may use multi-threaded forcewake */
|
|
|
|
|
|
|
|
/* A small trick here - if the bios hasn't configured
|
|
|
|
* MT forcewake, and if the device is in RC6, then
|
|
|
|
* force_wake_mt_get will not wake the device and the
|
|
|
|
* ECOBUS read will return zero. Which will be
|
|
|
|
* (correctly) interpreted by the test below as MT
|
|
|
|
* forcewake being disabled.
|
|
|
|
*/
|
2015-01-19 14:20:43 +00:00
|
|
|
dev_priv->uncore.funcs.force_wake_get =
|
|
|
|
fw_domains_get_with_thread_status;
|
|
|
|
dev_priv->uncore.funcs.force_wake_put =
|
|
|
|
fw_domains_put_with_fifo;
|
|
|
|
|
2015-01-28 12:43:24 +00:00
|
|
|
/* We need to init first for ECOBUS access and then
|
|
|
|
* determine later if we want to reinit, in case of MT access is
|
2015-02-27 16:11:09 +00:00
|
|
|
* not working. In this stage we don't know which flavour this
|
|
|
|
* ivb is, so it is better to reset also the gen6 fw registers
|
|
|
|
* before the ecobus check.
|
2015-01-28 12:43:24 +00:00
|
|
|
*/
|
2015-02-27 16:11:09 +00:00
|
|
|
|
|
|
|
__raw_i915_write32(dev_priv, FORCEWAKE, 0);
|
|
|
|
__raw_posting_read(dev_priv, ECOBUS);
|
|
|
|
|
2015-01-19 14:20:43 +00:00
|
|
|
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
|
|
|
|
FORCEWAKE_MT, FORCEWAKE_MT_ACK);
|
2015-01-28 12:43:24 +00:00
|
|
|
|
2016-07-03 17:29:33 +00:00
|
|
|
spin_lock_irq(&dev_priv->uncore.lock);
|
2015-01-19 14:20:43 +00:00
|
|
|
fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
|
2013-10-05 04:22:51 +00:00
|
|
|
ecobus = __raw_i915_read32(dev_priv, ECOBUS);
|
2015-01-19 14:20:43 +00:00
|
|
|
fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
|
2016-07-03 17:29:33 +00:00
|
|
|
spin_unlock_irq(&dev_priv->uncore.lock);
|
2013-10-05 04:22:51 +00:00
|
|
|
|
2015-01-19 14:20:43 +00:00
|
|
|
if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
|
2013-10-05 04:22:51 +00:00
|
|
|
DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
|
|
|
|
DRM_INFO("when using vblank-synced partial screen updates.\n");
|
2015-01-19 14:20:43 +00:00
|
|
|
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
|
|
|
|
FORCEWAKE, FORCEWAKE_ACK);
|
2013-10-05 04:22:51 +00:00
|
|
|
}
|
2016-05-10 13:10:04 +00:00
|
|
|
} else if (IS_GEN6(dev_priv)) {
|
2013-10-05 04:22:51 +00:00
|
|
|
dev_priv->uncore.funcs.force_wake_get =
|
2015-01-19 14:20:43 +00:00
|
|
|
fw_domains_get_with_thread_status;
|
2013-10-05 04:22:51 +00:00
|
|
|
dev_priv->uncore.funcs.force_wake_put =
|
2015-01-19 14:20:43 +00:00
|
|
|
fw_domains_put_with_fifo;
|
|
|
|
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
|
|
|
|
FORCEWAKE, FORCEWAKE_ACK);
|
2013-10-05 04:22:51 +00:00
|
|
|
}
|
2015-02-05 15:45:42 +00:00
|
|
|
|
|
|
|
/* All future platforms are expected to require complex power gating */
|
|
|
|
WARN_ON(dev_priv->uncore.fw_domains == 0);
|
2015-01-28 12:43:24 +00:00
|
|
|
}
|
|
|
|
|
2016-10-04 08:29:23 +00:00
|
|
|
#define ASSIGN_FW_DOMAINS_TABLE(d) \
|
|
|
|
{ \
|
|
|
|
dev_priv->uncore.fw_domains_table = \
|
|
|
|
(struct intel_forcewake_range *)(d); \
|
|
|
|
dev_priv->uncore.fw_domains_table_entries = ARRAY_SIZE((d)); \
|
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
void intel_uncore_init(struct drm_i915_private *dev_priv)
|
2015-01-28 12:43:24 +00:00
|
|
|
{
|
2016-05-10 13:10:04 +00:00
|
|
|
i915_check_vgpu(dev_priv);
|
2015-02-10 11:05:47 +00:00
|
|
|
|
2016-04-13 14:26:43 +00:00
|
|
|
intel_uncore_edram_detect(dev_priv);
|
2016-05-10 13:10:04 +00:00
|
|
|
intel_uncore_fw_domains_init(dev_priv);
|
|
|
|
__intel_uncore_early_sanitize(dev_priv, false);
|
2013-10-05 04:22:51 +00:00
|
|
|
|
2015-12-16 07:26:48 +00:00
|
|
|
dev_priv->uncore.unclaimed_mmio_check = 1;
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
switch (INTEL_INFO(dev_priv)->gen) {
|
drm/i915/bdw: Handle forcewake for writes on gen8
GEN8 removes the GT FIFO which we've all come to know and love. Instead
it offers a wider range of optimized registers which always keep a
shadowed copy, and are fed to the GPU when it wakes.
How this is implemented in hardware is still somewhat of a mystery. As
far as I can tell, the basic design is as follows:
If the register is not optimized, you must use the old forcewake
mechanism to bring the GT out of sleep. [1]
If register is in the optimized list the write will signal that the
GT should begin to come out of whatever sleep state it is in.
While the GT is coming out of sleep, the requested write will be stored
in an intermediate shadow register.
Do to the fact that the implementation details are not clear, I see
several risks:
1. Order is not preserved as it is with GT FIFO. If we issue multiple
writes to optimized registers, where order matters, we may need to
serialize it with forcewake.
2. The optimized registers have only 1 shadowed slot, meaning if we
issue multiple writes to the same register, and those values need to
reach the GPU in order, forcewake will be required.
[1] We could implement a SW queue the way the GT FIFO used to work if
desired.
NOTE: Compile tested only until we get real silicon.
v2:
- Use a default case to make future platforms also work.
- Get rid of IS_BROADWELL since that's not yet defined, but we want to
MMIO as soon as possible.
v3: Apply suggestions from Mika's review:
- s/optimized/shadowed/
- invert the logic of the helper so that it does what it says (the
code itself was correct, just confusing to read).
v4:
- Squash in lost break.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-03 04:07:00 +00:00
|
|
|
default:
|
2014-11-20 13:42:55 +00:00
|
|
|
case 9:
|
2016-10-04 08:29:23 +00:00
|
|
|
ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
|
2016-10-04 08:29:26 +00:00
|
|
|
ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
|
2016-10-04 08:29:25 +00:00
|
|
|
ASSIGN_READ_MMIO_VFUNCS(fwtable);
|
2014-11-20 13:42:55 +00:00
|
|
|
break;
|
|
|
|
case 8:
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_CHERRYVIEW(dev_priv)) {
|
2016-10-04 08:29:23 +00:00
|
|
|
ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges);
|
2016-10-04 08:29:26 +00:00
|
|
|
ASSIGN_WRITE_MMIO_VFUNCS(fwtable);
|
2016-10-04 08:29:25 +00:00
|
|
|
ASSIGN_READ_MMIO_VFUNCS(fwtable);
|
2014-05-23 15:30:16 +00:00
|
|
|
|
|
|
|
} else {
|
2014-10-23 07:28:24 +00:00
|
|
|
ASSIGN_WRITE_MMIO_VFUNCS(gen8);
|
|
|
|
ASSIGN_READ_MMIO_VFUNCS(gen6);
|
2014-05-23 15:30:16 +00:00
|
|
|
}
|
drm/i915/bdw: Handle forcewake for writes on gen8
GEN8 removes the GT FIFO which we've all come to know and love. Instead
it offers a wider range of optimized registers which always keep a
shadowed copy, and are fed to the GPU when it wakes.
How this is implemented in hardware is still somewhat of a mystery. As
far as I can tell, the basic design is as follows:
If the register is not optimized, you must use the old forcewake
mechanism to bring the GT out of sleep. [1]
If register is in the optimized list the write will signal that the
GT should begin to come out of whatever sleep state it is in.
While the GT is coming out of sleep, the requested write will be stored
in an intermediate shadow register.
Do to the fact that the implementation details are not clear, I see
several risks:
1. Order is not preserved as it is with GT FIFO. If we issue multiple
writes to optimized registers, where order matters, we may need to
serialize it with forcewake.
2. The optimized registers have only 1 shadowed slot, meaning if we
issue multiple writes to the same register, and those values need to
reach the GPU in order, forcewake will be required.
[1] We could implement a SW queue the way the GT FIFO used to work if
desired.
NOTE: Compile tested only until we get real silicon.
v2:
- Use a default case to make future platforms also work.
- Get rid of IS_BROADWELL since that's not yet defined, but we want to
MMIO as soon as possible.
v3: Apply suggestions from Mika's review:
- s/optimized/shadowed/
- invert the logic of the helper so that it does what it says (the
code itself was correct, just confusing to read).
v4:
- Squash in lost break.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-03 04:07:00 +00:00
|
|
|
break;
|
2013-10-05 04:22:53 +00:00
|
|
|
case 7:
|
|
|
|
case 6:
|
2016-10-04 08:29:16 +00:00
|
|
|
ASSIGN_WRITE_MMIO_VFUNCS(gen6);
|
2013-11-23 09:25:43 +00:00
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_VALLEYVIEW(dev_priv)) {
|
2016-10-04 08:29:23 +00:00
|
|
|
ASSIGN_FW_DOMAINS_TABLE(__vlv_fw_ranges);
|
2016-10-04 08:29:25 +00:00
|
|
|
ASSIGN_READ_MMIO_VFUNCS(fwtable);
|
2013-11-23 09:25:43 +00:00
|
|
|
} else {
|
2014-10-23 07:28:24 +00:00
|
|
|
ASSIGN_READ_MMIO_VFUNCS(gen6);
|
2013-11-23 09:25:43 +00:00
|
|
|
}
|
2013-10-05 04:22:53 +00:00
|
|
|
break;
|
|
|
|
case 5:
|
2014-10-23 07:28:24 +00:00
|
|
|
ASSIGN_WRITE_MMIO_VFUNCS(gen5);
|
|
|
|
ASSIGN_READ_MMIO_VFUNCS(gen5);
|
2013-10-05 04:22:53 +00:00
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
case 3:
|
|
|
|
case 2:
|
2015-01-16 09:34:36 +00:00
|
|
|
ASSIGN_WRITE_MMIO_VFUNCS(gen2);
|
|
|
|
ASSIGN_READ_MMIO_VFUNCS(gen2);
|
2013-10-05 04:22:53 +00:00
|
|
|
break;
|
|
|
|
}
|
2014-10-23 16:23:21 +00:00
|
|
|
|
2016-10-04 08:29:23 +00:00
|
|
|
intel_fw_table_check(dev_priv);
|
2016-10-04 08:29:27 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 8)
|
|
|
|
intel_shadow_table_check();
|
2016-10-04 08:29:23 +00:00
|
|
|
|
2016-05-06 14:40:21 +00:00
|
|
|
if (intel_vgpu_active(dev_priv)) {
|
2015-02-10 11:05:53 +00:00
|
|
|
ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
|
|
|
|
ASSIGN_READ_MMIO_VFUNCS(vgpu);
|
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
i915_check_and_clear_faults(dev_priv);
|
2013-10-05 04:22:51 +00:00
|
|
|
}
|
2014-10-23 07:28:24 +00:00
|
|
|
#undef ASSIGN_WRITE_MMIO_VFUNCS
|
|
|
|
#undef ASSIGN_READ_MMIO_VFUNCS
|
2013-10-05 04:22:51 +00:00
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
void intel_uncore_fini(struct drm_i915_private *dev_priv)
|
2013-10-05 04:22:51 +00:00
|
|
|
{
|
|
|
|
/* Paranoia: make sure we have disabled everything before we exit. */
|
2016-05-10 13:10:04 +00:00
|
|
|
intel_uncore_sanitize(dev_priv);
|
|
|
|
intel_uncore_forcewake_reset(dev_priv, false);
|
2013-10-05 04:22:51 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 09:57:04 +00:00
|
|
|
#define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)
|
drm/i915: Use a macro to express the range of valid gens for reg_read
The reg_read whitelist has a gen bitmask to code the gens we're allowing
the register to be read on. Until now, it was a literal, but we can be
a bit more expressive.
To ease the review, a small test program:
$ cat bit-range.c
#include <stdio.h>
#include <stdint.h>
#define U32_C(x) x ## U
#define GENMASK(h, l) (((U32_C(1) << ((h) - (l) + 1)) - 1) << (l))
#define GEN_RANGE(l, h) GENMASK(h, l)
int main(int argc, char **argv)
{
printf("0x%08x\n", GEN_RANGE(1, 1));
printf("0x%08x\n", GEN_RANGE(1, 2));
printf("0x%08x\n", GEN_RANGE(4, 4));
printf("0x%08x\n", GEN_RANGE(4, 5));
printf("0x%08x\n", GEN_RANGE(1, 31));
printf("0x%08x\n", GEN_RANGE(4, 8));
return 0;
}
$ ./bit-range
0x00000002
0x00000006
0x00000010
0x00000030
0xfffffffe
0x000001f0
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-31 10:24:08 +00:00
|
|
|
|
2013-07-19 19:36:52 +00:00
|
|
|
static const struct register_whitelist {
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
i915_reg_t offset_ldw, offset_udw;
|
2013-07-19 19:36:52 +00:00
|
|
|
uint32_t size;
|
drm/i915: Use a macro to express the range of valid gens for reg_read
The reg_read whitelist has a gen bitmask to code the gens we're allowing
the register to be read on. Until now, it was a literal, but we can be
a bit more expressive.
To ease the review, a small test program:
$ cat bit-range.c
#include <stdio.h>
#include <stdint.h>
#define U32_C(x) x ## U
#define GENMASK(h, l) (((U32_C(1) << ((h) - (l) + 1)) - 1) << (l))
#define GEN_RANGE(l, h) GENMASK(h, l)
int main(int argc, char **argv)
{
printf("0x%08x\n", GEN_RANGE(1, 1));
printf("0x%08x\n", GEN_RANGE(1, 2));
printf("0x%08x\n", GEN_RANGE(4, 4));
printf("0x%08x\n", GEN_RANGE(4, 5));
printf("0x%08x\n", GEN_RANGE(1, 31));
printf("0x%08x\n", GEN_RANGE(4, 8));
return 0;
}
$ ./bit-range
0x00000002
0x00000006
0x00000010
0x00000030
0xfffffffe
0x000001f0
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-31 10:24:08 +00:00
|
|
|
/* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
|
|
|
|
uint32_t gen_bitmask;
|
2013-07-19 19:36:52 +00:00
|
|
|
} whitelist[] = {
|
2015-11-06 19:43:41 +00:00
|
|
|
{ .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
|
|
|
|
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
|
|
|
|
.size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
|
2013-07-19 19:36:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
int i915_reg_read_ioctl(struct drm_device *dev,
|
|
|
|
void *data, struct drm_file *file)
|
|
|
|
{
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2013-07-19 19:36:52 +00:00
|
|
|
struct drm_i915_reg_read *reg = data;
|
|
|
|
struct register_whitelist const *entry = whitelist;
|
2015-07-16 11:37:56 +00:00
|
|
|
unsigned size;
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
i915_reg_t offset_ldw, offset_udw;
|
2014-04-01 17:55:08 +00:00
|
|
|
int i, ret = 0;
|
2013-07-19 19:36:52 +00:00
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
|
2016-05-10 09:57:04 +00:00
|
|
|
(INTEL_INFO(dev)->gen_mask & entry->gen_bitmask))
|
2013-07-19 19:36:52 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i == ARRAY_SIZE(whitelist))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2015-07-16 11:37:56 +00:00
|
|
|
/* We use the low bits to encode extra flags as the register should
|
|
|
|
* be naturally aligned (and those that are not so aligned merely
|
|
|
|
* limit the available flags for that register).
|
|
|
|
*/
|
2015-11-06 19:43:41 +00:00
|
|
|
offset_ldw = entry->offset_ldw;
|
|
|
|
offset_udw = entry->offset_udw;
|
2015-07-16 11:37:56 +00:00
|
|
|
size = entry->size;
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
|
2015-07-16 11:37:56 +00:00
|
|
|
|
2014-04-01 17:55:08 +00:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
|
|
|
|
2015-07-16 11:37:56 +00:00
|
|
|
switch (size) {
|
|
|
|
case 8 | 1:
|
2015-11-06 19:43:41 +00:00
|
|
|
reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
|
2015-07-16 11:37:56 +00:00
|
|
|
break;
|
2013-07-19 19:36:52 +00:00
|
|
|
case 8:
|
2015-11-06 19:43:41 +00:00
|
|
|
reg->val = I915_READ64(offset_ldw);
|
2013-07-19 19:36:52 +00:00
|
|
|
break;
|
|
|
|
case 4:
|
2015-11-06 19:43:41 +00:00
|
|
|
reg->val = I915_READ(offset_ldw);
|
2013-07-19 19:36:52 +00:00
|
|
|
break;
|
|
|
|
case 2:
|
2015-11-06 19:43:41 +00:00
|
|
|
reg->val = I915_READ16(offset_ldw);
|
2013-07-19 19:36:52 +00:00
|
|
|
break;
|
|
|
|
case 1:
|
2015-11-06 19:43:41 +00:00
|
|
|
reg->val = I915_READ8(offset_ldw);
|
2013-07-19 19:36:52 +00:00
|
|
|
break;
|
|
|
|
default:
|
2014-04-01 17:55:08 +00:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto out;
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
|
|
|
|
2014-04-01 17:55:08 +00:00
|
|
|
out:
|
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
return ret;
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static int i915_reset_complete(struct pci_dev *pdev)
|
2013-07-19 19:36:52 +00:00
|
|
|
{
|
|
|
|
u8 gdrst;
|
2016-05-10 13:10:04 +00:00
|
|
|
pci_read_config_byte(pdev, I915_GDRST, &gdrst);
|
2014-11-21 19:54:25 +00:00
|
|
|
return (gdrst & GRDOM_RESET_STATUS) == 0;
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
|
2013-07-19 19:36:52 +00:00
|
|
|
{
|
2016-07-05 09:40:23 +00:00
|
|
|
struct pci_dev *pdev = dev_priv->drm.pdev;
|
2016-05-10 13:10:04 +00:00
|
|
|
|
2014-11-21 19:54:25 +00:00
|
|
|
/* assert reset for at least 20 usec */
|
2016-05-10 13:10:04 +00:00
|
|
|
pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
|
2014-11-21 19:54:25 +00:00
|
|
|
udelay(20);
|
2016-05-10 13:10:04 +00:00
|
|
|
pci_write_config_byte(pdev, I915_GDRST, 0);
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
return wait_for(i915_reset_complete(pdev), 500);
|
2014-11-21 19:54:25 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static int g4x_reset_complete(struct pci_dev *pdev)
|
2014-11-21 19:54:25 +00:00
|
|
|
{
|
|
|
|
u8 gdrst;
|
2016-05-10 13:10:04 +00:00
|
|
|
pci_read_config_byte(pdev, I915_GDRST, &gdrst);
|
2014-11-21 19:54:25 +00:00
|
|
|
return (gdrst & GRDOM_RESET_ENABLE) == 0;
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
|
2014-11-21 19:54:28 +00:00
|
|
|
{
|
2016-07-05 09:40:23 +00:00
|
|
|
struct pci_dev *pdev = dev_priv->drm.pdev;
|
2016-05-10 13:10:04 +00:00
|
|
|
pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
|
|
|
|
return wait_for(g4x_reset_complete(pdev), 500);
|
2014-11-21 19:54:28 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
|
2014-05-19 16:23:27 +00:00
|
|
|
{
|
2016-07-05 09:40:23 +00:00
|
|
|
struct pci_dev *pdev = dev_priv->drm.pdev;
|
2014-05-19 16:23:27 +00:00
|
|
|
int ret;
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
pci_write_config_byte(pdev, I915_GDRST,
|
2014-05-19 16:23:27 +00:00
|
|
|
GRDOM_RENDER | GRDOM_RESET_ENABLE);
|
2016-05-10 13:10:04 +00:00
|
|
|
ret = wait_for(g4x_reset_complete(pdev), 500);
|
2014-05-19 16:23:27 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* WaVcpClkGateDisableForMediaReset:ctg,elk */
|
|
|
|
I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
|
|
|
|
POSTING_READ(VDECCLK_GATE_D);
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
pci_write_config_byte(pdev, I915_GDRST,
|
2014-05-19 16:23:27 +00:00
|
|
|
GRDOM_MEDIA | GRDOM_RESET_ENABLE);
|
2016-05-10 13:10:04 +00:00
|
|
|
ret = wait_for(g4x_reset_complete(pdev), 500);
|
2014-05-19 16:23:27 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* WaVcpClkGateDisableForMediaReset:ctg,elk */
|
|
|
|
I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
|
|
|
|
POSTING_READ(VDECCLK_GATE_D);
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
pci_write_config_byte(pdev, I915_GDRST, 0);
|
2014-05-19 16:23:27 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static int ironlake_do_reset(struct drm_i915_private *dev_priv,
|
|
|
|
unsigned engine_mask)
|
2013-07-19 19:36:52 +00:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2015-09-18 17:03:27 +00:00
|
|
|
I915_WRITE(ILK_GDSR,
|
2014-05-19 16:23:25 +00:00
|
|
|
ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
|
2016-06-30 14:33:43 +00:00
|
|
|
ret = intel_wait_for_register(dev_priv,
|
|
|
|
ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
|
|
|
|
500);
|
2013-07-19 19:36:52 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2015-09-18 17:03:27 +00:00
|
|
|
I915_WRITE(ILK_GDSR,
|
2014-05-19 16:23:25 +00:00
|
|
|
ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
|
2016-06-30 14:33:43 +00:00
|
|
|
ret = intel_wait_for_register(dev_priv,
|
|
|
|
ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
|
|
|
|
500);
|
2014-05-19 16:23:26 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2015-09-18 17:03:27 +00:00
|
|
|
I915_WRITE(ILK_GDSR, 0);
|
2014-05-19 16:23:26 +00:00
|
|
|
|
|
|
|
return 0;
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
|
|
|
|
2016-03-16 15:54:00 +00:00
|
|
|
/* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
|
|
|
|
static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
|
|
|
|
u32 hw_domain_mask)
|
2013-07-19 19:36:52 +00:00
|
|
|
{
|
|
|
|
/* GEN6_GDRST is not in the gt power well, no need to check
|
|
|
|
* for fifo space for the write or forcewake the chip for
|
|
|
|
* the read
|
|
|
|
*/
|
2016-03-16 15:54:00 +00:00
|
|
|
__raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2016-03-16 15:54:00 +00:00
|
|
|
/* Spin waiting for the device to ack the reset requests */
|
2016-06-30 14:33:44 +00:00
|
|
|
return intel_wait_for_register_fw(dev_priv,
|
|
|
|
GEN6_GDRST, hw_domain_mask, 0,
|
|
|
|
500);
|
2016-03-16 15:54:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* gen6_reset_engines - reset individual engines
|
2016-05-10 13:10:04 +00:00
|
|
|
* @dev_priv: i915 device
|
2016-03-16 15:54:00 +00:00
|
|
|
* @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
|
|
|
|
*
|
|
|
|
* This function will reset the individual engines that are set in engine_mask.
|
|
|
|
* If you provide ALL_ENGINES as mask, full global domain reset will be issued.
|
|
|
|
*
|
|
|
|
* Note: It is responsibility of the caller to handle the difference between
|
|
|
|
* asking full domain reset versus reset for all available individual engines.
|
|
|
|
*
|
|
|
|
* Returns 0 on success, nonzero on error.
|
|
|
|
*/
|
2016-05-10 13:10:04 +00:00
|
|
|
static int gen6_reset_engines(struct drm_i915_private *dev_priv,
|
|
|
|
unsigned engine_mask)
|
2016-03-16 15:54:00 +00:00
|
|
|
{
|
|
|
|
struct intel_engine_cs *engine;
|
|
|
|
const u32 hw_engine_mask[I915_NUM_ENGINES] = {
|
|
|
|
[RCS] = GEN6_GRDOM_RENDER,
|
|
|
|
[BCS] = GEN6_GRDOM_BLT,
|
|
|
|
[VCS] = GEN6_GRDOM_MEDIA,
|
|
|
|
[VCS2] = GEN8_GRDOM_MEDIA2,
|
|
|
|
[VECS] = GEN6_GRDOM_VECS,
|
|
|
|
};
|
|
|
|
u32 hw_mask;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (engine_mask == ALL_ENGINES) {
|
|
|
|
hw_mask = GEN6_GRDOM_FULL;
|
|
|
|
} else {
|
2016-08-27 07:54:01 +00:00
|
|
|
unsigned int tmp;
|
|
|
|
|
2016-03-16 15:54:00 +00:00
|
|
|
hw_mask = 0;
|
2016-08-27 07:54:01 +00:00
|
|
|
for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
|
2016-03-16 15:54:00 +00:00
|
|
|
hw_mask |= hw_engine_mask[engine->id];
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = gen6_hw_domain_reset(dev_priv, hw_mask);
|
2013-07-19 19:36:52 +00:00
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
intel_uncore_forcewake_reset(dev_priv, true);
|
2014-03-05 16:08:18 +00:00
|
|
|
|
2013-07-19 19:36:52 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2016-06-30 14:32:44 +00:00
|
|
|
/**
|
|
|
|
* intel_wait_for_register_fw - wait until register matches expected state
|
|
|
|
* @dev_priv: the i915 device
|
|
|
|
* @reg: the register to read
|
|
|
|
* @mask: mask to apply to register value
|
|
|
|
* @value: expected value
|
|
|
|
* @timeout_ms: timeout in millisecond
|
|
|
|
*
|
|
|
|
* This routine waits until the target register @reg contains the expected
|
2016-07-15 19:48:05 +00:00
|
|
|
* @value after applying the @mask, i.e. it waits until ::
|
|
|
|
*
|
|
|
|
* (I915_READ_FW(reg) & mask) == value
|
|
|
|
*
|
2016-06-30 14:32:44 +00:00
|
|
|
* Otherwise, the wait will timeout after @timeout_ms milliseconds.
|
|
|
|
*
|
|
|
|
* Note that this routine assumes the caller holds forcewake asserted, it is
|
|
|
|
* not suitable for very long waits. See intel_wait_for_register() if you
|
|
|
|
* wish to wait without holding forcewake for the duration (i.e. you expect
|
|
|
|
* the wait to be slow).
|
|
|
|
*
|
|
|
|
* Returns 0 if the register matches the desired condition, or -ETIMEOUT.
|
|
|
|
*/
|
|
|
|
int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
|
|
|
|
i915_reg_t reg,
|
|
|
|
const u32 mask,
|
|
|
|
const u32 value,
|
|
|
|
const unsigned long timeout_ms)
|
|
|
|
{
|
|
|
|
#define done ((I915_READ_FW(reg) & mask) == value)
|
|
|
|
int ret = wait_for_us(done, 2);
|
|
|
|
if (ret)
|
|
|
|
ret = wait_for(done, timeout_ms);
|
|
|
|
return ret;
|
|
|
|
#undef done
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* intel_wait_for_register - wait until register matches expected state
|
|
|
|
* @dev_priv: the i915 device
|
|
|
|
* @reg: the register to read
|
|
|
|
* @mask: mask to apply to register value
|
|
|
|
* @value: expected value
|
|
|
|
* @timeout_ms: timeout in millisecond
|
|
|
|
*
|
|
|
|
* This routine waits until the target register @reg contains the expected
|
2016-07-15 19:48:05 +00:00
|
|
|
* @value after applying the @mask, i.e. it waits until ::
|
|
|
|
*
|
|
|
|
* (I915_READ(reg) & mask) == value
|
|
|
|
*
|
2016-06-30 14:32:44 +00:00
|
|
|
* Otherwise, the wait will timeout after @timeout_ms milliseconds.
|
|
|
|
*
|
|
|
|
* Returns 0 if the register matches the desired condition, or -ETIMEOUT.
|
|
|
|
*/
|
|
|
|
int intel_wait_for_register(struct drm_i915_private *dev_priv,
|
|
|
|
i915_reg_t reg,
|
|
|
|
const u32 mask,
|
|
|
|
const u32 value,
|
|
|
|
const unsigned long timeout_ms)
|
2015-06-18 09:51:40 +00:00
|
|
|
{
|
2016-06-30 14:32:44 +00:00
|
|
|
|
|
|
|
unsigned fw =
|
|
|
|
intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
intel_uncore_forcewake_get(dev_priv, fw);
|
|
|
|
ret = wait_for_us((I915_READ_FW(reg) & mask) == value, 2);
|
|
|
|
intel_uncore_forcewake_put(dev_priv, fw);
|
|
|
|
if (ret)
|
|
|
|
ret = wait_for((I915_READ_NOTRACE(reg) & mask) == value,
|
|
|
|
timeout_ms);
|
|
|
|
|
|
|
|
return ret;
|
2016-03-02 14:46:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int gen8_request_engine_reset(struct intel_engine_cs *engine)
|
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2016-03-02 14:46:24 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
|
|
|
|
_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
|
|
|
|
|
2016-06-30 14:32:44 +00:00
|
|
|
ret = intel_wait_for_register_fw(dev_priv,
|
|
|
|
RING_RESET_CTL(engine->mmio_base),
|
|
|
|
RESET_CTL_READY_TO_RESET,
|
|
|
|
RESET_CTL_READY_TO_RESET,
|
|
|
|
700);
|
2016-03-02 14:46:24 +00:00
|
|
|
if (ret)
|
|
|
|
DRM_ERROR("%s: reset request timeout\n", engine->name);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
|
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2016-03-02 14:46:24 +00:00
|
|
|
|
|
|
|
I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
|
|
|
|
_MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
|
2015-06-18 09:51:40 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static int gen8_reset_engines(struct drm_i915_private *dev_priv,
|
|
|
|
unsigned engine_mask)
|
2015-06-18 09:51:40 +00:00
|
|
|
{
|
|
|
|
struct intel_engine_cs *engine;
|
2016-08-27 07:54:01 +00:00
|
|
|
unsigned int tmp;
|
2015-06-18 09:51:40 +00:00
|
|
|
|
2016-08-27 07:54:01 +00:00
|
|
|
for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
|
2016-03-02 14:46:24 +00:00
|
|
|
if (gen8_request_engine_reset(engine))
|
2015-06-18 09:51:40 +00:00
|
|
|
goto not_ready;
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
return gen6_reset_engines(dev_priv, engine_mask);
|
2015-06-18 09:51:40 +00:00
|
|
|
|
|
|
|
not_ready:
|
2016-08-27 07:54:01 +00:00
|
|
|
for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
|
2016-03-02 14:46:24 +00:00
|
|
|
gen8_unrequest_engine_reset(engine);
|
2015-06-18 09:51:40 +00:00
|
|
|
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask);
|
|
|
|
|
|
|
|
static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
|
2013-07-19 19:36:52 +00:00
|
|
|
{
|
2015-06-18 10:42:08 +00:00
|
|
|
if (!i915.reset)
|
|
|
|
return NULL;
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
if (INTEL_INFO(dev_priv)->gen >= 8)
|
2016-03-16 15:54:00 +00:00
|
|
|
return gen8_reset_engines;
|
2016-05-10 13:10:04 +00:00
|
|
|
else if (INTEL_INFO(dev_priv)->gen >= 6)
|
2016-03-16 15:54:00 +00:00
|
|
|
return gen6_reset_engines;
|
2016-05-10 13:10:04 +00:00
|
|
|
else if (IS_GEN5(dev_priv))
|
2015-06-15 11:23:48 +00:00
|
|
|
return ironlake_do_reset;
|
2016-05-10 13:10:04 +00:00
|
|
|
else if (IS_G4X(dev_priv))
|
2015-06-15 11:23:48 +00:00
|
|
|
return g4x_do_reset;
|
2016-05-10 13:10:04 +00:00
|
|
|
else if (IS_G33(dev_priv))
|
2015-06-15 11:23:48 +00:00
|
|
|
return g33_do_reset;
|
2016-05-10 13:10:04 +00:00
|
|
|
else if (INTEL_INFO(dev_priv)->gen >= 3)
|
2015-06-15 11:23:48 +00:00
|
|
|
return i915_do_reset;
|
2014-06-03 08:08:26 +00:00
|
|
|
else
|
2015-06-15 11:23:48 +00:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
|
2015-06-15 11:23:48 +00:00
|
|
|
{
|
2016-05-10 13:10:04 +00:00
|
|
|
reset_func reset;
|
2015-11-05 11:11:38 +00:00
|
|
|
int ret;
|
2015-06-15 11:23:48 +00:00
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
reset = intel_get_gpu_reset(dev_priv);
|
2015-06-15 11:23:48 +00:00
|
|
|
if (reset == NULL)
|
2014-06-03 08:08:26 +00:00
|
|
|
return -ENODEV;
|
2015-06-15 11:23:48 +00:00
|
|
|
|
2015-11-05 11:11:38 +00:00
|
|
|
/* If the power well sleeps during the reset, the reset
|
|
|
|
* request may be dropped and never completes (causing -EIO).
|
|
|
|
*/
|
|
|
|
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
2016-05-10 13:10:04 +00:00
|
|
|
ret = reset(dev_priv, engine_mask);
|
2015-11-05 11:11:38 +00:00
|
|
|
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
|
|
|
|
|
|
|
return ret;
|
2015-06-15 11:23:48 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
|
2015-06-15 11:23:48 +00:00
|
|
|
{
|
2016-05-10 13:10:04 +00:00
|
|
|
return intel_get_gpu_reset(dev_priv) != NULL;
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
|
|
|
|
2016-04-04 17:50:56 +00:00
|
|
|
int intel_guc_reset(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
2016-05-13 14:36:30 +00:00
|
|
|
if (!HAS_GUC(dev_priv))
|
2016-04-04 17:50:56 +00:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
|
|
|
|
|
|
|
|
ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
|
|
|
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-12-15 14:25:07 +00:00
|
|
|
bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
|
2013-07-19 19:36:52 +00:00
|
|
|
{
|
2015-12-15 14:25:07 +00:00
|
|
|
return check_for_unclaimed_mmio(dev_priv);
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|
2015-12-16 07:26:48 +00:00
|
|
|
|
2016-01-08 13:51:20 +00:00
|
|
|
bool
|
2015-12-16 07:26:48 +00:00
|
|
|
intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
if (unlikely(i915.mmio_debug ||
|
|
|
|
dev_priv->uncore.unclaimed_mmio_check <= 0))
|
2016-01-08 13:51:20 +00:00
|
|
|
return false;
|
2015-12-16 07:26:48 +00:00
|
|
|
|
|
|
|
if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
|
|
|
|
DRM_DEBUG("Unclaimed register detected, "
|
|
|
|
"enabling oneshot unclaimed register reporting. "
|
|
|
|
"Please use i915.mmio_debug=N for more information.\n");
|
|
|
|
i915.mmio_debug++;
|
|
|
|
dev_priv->uncore.unclaimed_mmio_check--;
|
2016-01-08 13:51:20 +00:00
|
|
|
return true;
|
2015-12-16 07:26:48 +00:00
|
|
|
}
|
2016-01-08 13:51:20 +00:00
|
|
|
|
|
|
|
return false;
|
2015-12-16 07:26:48 +00:00
|
|
|
}
|
2016-04-12 13:37:31 +00:00
|
|
|
|
|
|
|
static enum forcewake_domains
|
|
|
|
intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
|
|
|
|
i915_reg_t reg)
|
|
|
|
{
|
2016-10-04 08:29:24 +00:00
|
|
|
u32 offset = i915_mmio_reg_offset(reg);
|
2016-04-12 13:37:31 +00:00
|
|
|
enum forcewake_domains fw_domains;
|
|
|
|
|
2016-10-04 08:29:24 +00:00
|
|
|
if (HAS_FWTABLE(dev_priv)) {
|
|
|
|
fw_domains = __fwtable_reg_read_fw_domains(offset);
|
|
|
|
} else if (INTEL_GEN(dev_priv) >= 6) {
|
|
|
|
fw_domains = __gen6_reg_read_fw_domains(offset);
|
|
|
|
} else {
|
|
|
|
WARN_ON(!IS_GEN(dev_priv, 2, 5));
|
|
|
|
fw_domains = 0;
|
2016-04-12 13:37:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
|
|
|
|
|
|
|
|
return fw_domains;
|
|
|
|
}
|
|
|
|
|
|
|
|
static enum forcewake_domains
|
|
|
|
intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
|
|
|
|
i915_reg_t reg)
|
|
|
|
{
|
2016-10-04 08:29:26 +00:00
|
|
|
u32 offset = i915_mmio_reg_offset(reg);
|
2016-04-12 13:37:31 +00:00
|
|
|
enum forcewake_domains fw_domains;
|
|
|
|
|
2016-10-04 08:29:26 +00:00
|
|
|
if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) {
|
|
|
|
fw_domains = __fwtable_reg_write_fw_domains(offset);
|
|
|
|
} else if (IS_GEN8(dev_priv)) {
|
|
|
|
fw_domains = __gen8_reg_write_fw_domains(offset);
|
|
|
|
} else if (IS_GEN(dev_priv, 6, 7)) {
|
2016-04-12 13:37:31 +00:00
|
|
|
fw_domains = FORCEWAKE_RENDER;
|
2016-10-04 08:29:26 +00:00
|
|
|
} else {
|
|
|
|
WARN_ON(!IS_GEN(dev_priv, 2, 5));
|
|
|
|
fw_domains = 0;
|
2016-04-12 13:37:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);
|
|
|
|
|
|
|
|
return fw_domains;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
|
|
|
|
* a register
|
|
|
|
* @dev_priv: pointer to struct drm_i915_private
|
|
|
|
* @reg: register in question
|
|
|
|
* @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
|
|
|
|
*
|
|
|
|
* Returns a set of forcewake domains required to be taken with for example
|
|
|
|
* intel_uncore_forcewake_get for the specified register to be accessible in the
|
|
|
|
* specified mode (read, write or read/write) with raw mmio accessors.
|
|
|
|
*
|
|
|
|
* NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
|
|
|
|
* callers to do FIFO management on their own or risk losing writes.
|
|
|
|
*/
|
|
|
|
enum forcewake_domains
|
|
|
|
intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
|
|
|
|
i915_reg_t reg, unsigned int op)
|
|
|
|
{
|
|
|
|
enum forcewake_domains fw_domains = 0;
|
|
|
|
|
|
|
|
WARN_ON(!op);
|
|
|
|
|
2016-10-04 08:29:24 +00:00
|
|
|
if (intel_vgpu_active(dev_priv))
|
|
|
|
return 0;
|
|
|
|
|
2016-04-12 13:37:31 +00:00
|
|
|
if (op & FW_REG_READ)
|
|
|
|
fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);
|
|
|
|
|
|
|
|
if (op & FW_REG_WRITE)
|
|
|
|
fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);
|
|
|
|
|
|
|
|
return fw_domains;
|
|
|
|
}
|