2015-03-03 10:51:06 +00:00
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#include "ddk750_reg.h"
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#include "ddk750_help.h"
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#include "ddk750_display.h"
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#include "ddk750_power.h"
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#include "ddk750_dvi.h"
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2015-06-02 10:14:30 +00:00
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#define primaryWaitVerticalSync(delay) waitNextVerticalSync(0, delay)
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2015-03-03 10:51:06 +00:00
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2015-10-09 20:47:44 +00:00
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static void setDisplayControl(int ctrl, int disp_state)
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2015-03-03 10:51:06 +00:00
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{
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/* state != 0 means turn on both timing & plane en_bit */
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2016-02-10 16:34:06 +00:00
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unsigned long reg, val, reserved;
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int cnt = 0;
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2015-03-03 10:51:06 +00:00
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2015-07-15 04:14:45 +00:00
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if (!ctrl) {
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2016-02-10 16:34:06 +00:00
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reg = PANEL_DISPLAY_CTRL;
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reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK;
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2015-07-15 04:14:45 +00:00
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} else {
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2016-02-10 16:34:06 +00:00
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reg = CRT_DISPLAY_CTRL;
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reserved = CRT_DISPLAY_CTRL_RESERVED_MASK;
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}
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2015-03-03 10:51:06 +00:00
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2016-02-10 16:34:06 +00:00
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val = PEEK32(reg);
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if (disp_state) {
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/*
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* Timing should be enabled first before enabling the
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* plane because changing at the same time does not
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* guarantee that the plane will also enabled or
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* disabled.
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*/
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2016-02-10 16:34:08 +00:00
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val |= DISPLAY_CTRL_TIMING;
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2016-02-10 16:34:06 +00:00
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POKE32(reg, val);
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2016-02-10 16:34:08 +00:00
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val |= DISPLAY_CTRL_PLANE;
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2016-02-10 16:34:06 +00:00
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/*
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* Somehow the register value on the plane is not set
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* until a few delay. Need to write and read it a
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* couple times
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*/
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do {
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cnt++;
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POKE32(reg, val);
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} while ((PEEK32(reg) & ~reserved) != (val & ~reserved));
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pr_debug("Set Plane enbit:after tried %d times\n", cnt);
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} else {
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/*
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* When turning off, there is no rule on the
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* programming sequence since whenever the clock is
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* off, then it does not matter whether the plane is
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* enabled or disabled. Note: Modifying the plane bit
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* will take effect on the next vertical sync. Need to
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* find out if it is necessary to wait for 1 vsync
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* before modifying the timing enable bit.
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*/
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2016-02-10 16:34:08 +00:00
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val &= ~DISPLAY_CTRL_PLANE;
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2016-02-10 16:34:06 +00:00
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POKE32(reg, val);
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2016-02-10 16:34:08 +00:00
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val &= ~DISPLAY_CTRL_TIMING;
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2016-02-10 16:34:06 +00:00
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POKE32(reg, val);
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2015-03-03 10:51:06 +00:00
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}
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}
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2015-06-02 10:14:30 +00:00
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static void waitNextVerticalSync(int ctrl, int delay)
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2015-03-03 10:51:06 +00:00
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{
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unsigned int status;
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2015-07-15 04:14:48 +00:00
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2015-07-15 04:14:35 +00:00
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if (!ctrl) {
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2015-03-03 10:51:06 +00:00
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/* primary controller */
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2015-07-15 04:14:30 +00:00
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/* Do not wait when the Primary PLL is off or display control is already off.
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This will prevent the software to wait forever. */
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2016-02-10 16:33:57 +00:00
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if (!(PEEK32(PANEL_PLL_CTRL) & PLL_CTRL_POWER) ||
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2016-02-10 16:34:08 +00:00
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!(PEEK32(PANEL_DISPLAY_CTRL) & DISPLAY_CTRL_TIMING)) {
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2015-03-03 10:51:06 +00:00
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return;
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}
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2015-07-15 04:14:45 +00:00
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while (delay-- > 0) {
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2015-07-15 04:14:30 +00:00
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/* Wait for end of vsync. */
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2015-07-15 04:14:45 +00:00
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do {
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2016-01-17 18:04:18 +00:00
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status = PEEK32(SYSTEM_CTRL);
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} while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
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2015-07-15 04:14:30 +00:00
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/* Wait for start of vsync. */
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2015-07-15 04:14:45 +00:00
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do {
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2016-01-17 18:04:18 +00:00
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status = PEEK32(SYSTEM_CTRL);
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} while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE));
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2015-07-15 04:14:30 +00:00
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}
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2015-03-03 10:51:06 +00:00
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2015-07-15 04:14:36 +00:00
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} else {
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2015-03-03 10:51:06 +00:00
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/* Do not wait when the Primary PLL is off or display control is already off.
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This will prevent the software to wait forever. */
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2016-02-10 16:33:57 +00:00
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if (!(PEEK32(CRT_PLL_CTRL) & PLL_CTRL_POWER) ||
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2016-02-10 16:34:08 +00:00
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!(PEEK32(CRT_DISPLAY_CTRL) & DISPLAY_CTRL_TIMING)) {
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2015-03-03 10:51:06 +00:00
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return;
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}
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2015-07-15 04:14:45 +00:00
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while (delay-- > 0) {
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2015-03-03 10:51:06 +00:00
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/* Wait for end of vsync. */
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2015-07-15 04:14:45 +00:00
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do {
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2016-01-17 18:04:18 +00:00
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status = PEEK32(SYSTEM_CTRL);
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} while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
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2015-03-03 10:51:06 +00:00
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/* Wait for start of vsync. */
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2015-07-15 04:14:45 +00:00
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do {
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2016-01-17 18:04:18 +00:00
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status = PEEK32(SYSTEM_CTRL);
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} while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE));
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2015-03-03 10:51:06 +00:00
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}
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}
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}
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2015-06-02 10:14:30 +00:00
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static void swPanelPowerSequence(int disp, int delay)
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2015-03-03 10:51:06 +00:00
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{
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unsigned int reg;
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/* disp should be 1 to open sequence */
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reg = PEEK32(PANEL_DISPLAY_CTRL);
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2016-02-10 16:34:08 +00:00
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reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0);
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2015-06-02 10:14:30 +00:00
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POKE32(PANEL_DISPLAY_CTRL, reg);
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2015-03-03 10:51:06 +00:00
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primaryWaitVerticalSync(delay);
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reg = PEEK32(PANEL_DISPLAY_CTRL);
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2016-02-10 16:34:08 +00:00
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reg |= (disp ? PANEL_DISPLAY_CTRL_DATA : 0);
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2015-06-02 10:14:30 +00:00
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POKE32(PANEL_DISPLAY_CTRL, reg);
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2015-03-03 10:51:06 +00:00
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primaryWaitVerticalSync(delay);
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reg = PEEK32(PANEL_DISPLAY_CTRL);
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2016-02-10 16:34:08 +00:00
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reg |= (disp ? PANEL_DISPLAY_CTRL_VBIASEN : 0);
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2015-06-02 10:14:30 +00:00
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POKE32(PANEL_DISPLAY_CTRL, reg);
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2015-03-03 10:51:06 +00:00
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primaryWaitVerticalSync(delay);
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reg = PEEK32(PANEL_DISPLAY_CTRL);
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2016-02-10 16:34:08 +00:00
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reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0);
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2015-06-02 10:14:30 +00:00
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POKE32(PANEL_DISPLAY_CTRL, reg);
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2015-03-03 10:51:06 +00:00
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primaryWaitVerticalSync(delay);
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}
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void ddk750_setLogicalDispOut(disp_output_t output)
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{
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unsigned int reg;
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2015-07-15 04:14:48 +00:00
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2015-07-15 04:14:35 +00:00
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if (output & PNL_2_USAGE) {
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2015-03-03 10:51:06 +00:00
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/* set panel path controller select */
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reg = PEEK32(PANEL_DISPLAY_CTRL);
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2016-02-10 16:34:10 +00:00
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reg &= ~PANEL_DISPLAY_CTRL_SELECT_MASK;
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reg |= (((output & PNL_2_MASK) >> PNL_2_OFFSET) <<
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PANEL_DISPLAY_CTRL_SELECT_SHIFT);
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2015-06-02 10:14:30 +00:00
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POKE32(PANEL_DISPLAY_CTRL, reg);
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2015-03-03 10:51:06 +00:00
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}
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2015-07-15 04:14:35 +00:00
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if (output & CRT_2_USAGE) {
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2015-03-03 10:51:06 +00:00
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/* set crt path controller select */
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reg = PEEK32(CRT_DISPLAY_CTRL);
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2016-02-10 16:34:19 +00:00
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reg &= ~CRT_DISPLAY_CTRL_SELECT_MASK;
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reg |= (((output & CRT_2_MASK) >> CRT_2_OFFSET) <<
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CRT_DISPLAY_CTRL_SELECT_SHIFT);
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2015-03-03 10:51:06 +00:00
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/*se blank off */
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2016-02-10 16:34:18 +00:00
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reg &= ~CRT_DISPLAY_CTRL_BLANK;
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2015-06-02 10:14:30 +00:00
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POKE32(CRT_DISPLAY_CTRL, reg);
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2015-03-03 10:51:06 +00:00
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}
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2015-07-15 04:14:35 +00:00
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if (output & PRI_TP_USAGE) {
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2015-03-03 10:51:06 +00:00
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/* set primary timing and plane en_bit */
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2015-10-09 20:51:30 +00:00
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setDisplayControl(0, (output & PRI_TP_MASK) >> PRI_TP_OFFSET);
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2015-03-03 10:51:06 +00:00
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}
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2015-07-15 04:14:35 +00:00
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if (output & SEC_TP_USAGE) {
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2015-03-03 10:51:06 +00:00
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/* set secondary timing and plane en_bit*/
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2015-10-09 20:51:30 +00:00
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setDisplayControl(1, (output & SEC_TP_MASK) >> SEC_TP_OFFSET);
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2015-03-03 10:51:06 +00:00
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}
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2015-07-15 04:14:35 +00:00
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if (output & PNL_SEQ_USAGE) {
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2015-03-03 10:51:06 +00:00
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/* set panel sequence */
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2015-10-09 20:51:30 +00:00
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swPanelPowerSequence((output & PNL_SEQ_MASK) >> PNL_SEQ_OFFSET, 4);
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2015-03-03 10:51:06 +00:00
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}
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2015-07-15 04:14:33 +00:00
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if (output & DAC_USAGE)
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2015-10-09 20:50:36 +00:00
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setDAC((output & DAC_MASK) >> DAC_OFFSET);
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2015-03-03 10:51:06 +00:00
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2015-07-15 04:14:33 +00:00
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if (output & DPMS_USAGE)
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2015-03-03 10:51:06 +00:00
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ddk750_setDPMS((output & DPMS_MASK) >> DPMS_OFFSET);
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}
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