2012-06-06 05:25:27 +00:00
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/*
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* DMA driver for Nvidia's Tegra20 APB DMA controller.
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*
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2013-11-11 20:09:35 +00:00
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* Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
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2012-06-06 05:25:27 +00:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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2013-01-21 10:09:00 +00:00
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#include <linux/err.h>
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2012-06-06 05:25:27 +00:00
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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2013-11-11 20:09:35 +00:00
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#include <linux/of_dma.h>
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2012-06-06 05:25:27 +00:00
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#include <linux/platform_device.h>
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2013-04-24 09:54:27 +00:00
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#include <linux/pm.h>
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2012-06-06 05:25:27 +00:00
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#include <linux/pm_runtime.h>
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2013-11-06 23:35:34 +00:00
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#include <linux/reset.h>
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2012-06-06 05:25:27 +00:00
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#include <linux/slab.h>
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#include "dmaengine.h"
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#define TEGRA_APBDMA_GENERAL 0x0
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#define TEGRA_APBDMA_GENERAL_ENABLE BIT(31)
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#define TEGRA_APBDMA_CONTROL 0x010
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#define TEGRA_APBDMA_IRQ_MASK 0x01c
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#define TEGRA_APBDMA_IRQ_MASK_SET 0x020
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/* CSR register */
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#define TEGRA_APBDMA_CHAN_CSR 0x00
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#define TEGRA_APBDMA_CSR_ENB BIT(31)
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#define TEGRA_APBDMA_CSR_IE_EOC BIT(30)
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#define TEGRA_APBDMA_CSR_HOLD BIT(29)
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#define TEGRA_APBDMA_CSR_DIR BIT(28)
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#define TEGRA_APBDMA_CSR_ONCE BIT(27)
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#define TEGRA_APBDMA_CSR_FLOW BIT(21)
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#define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT 16
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#define TEGRA_APBDMA_CSR_WCOUNT_MASK 0xFFFC
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/* STATUS register */
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#define TEGRA_APBDMA_CHAN_STATUS 0x004
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#define TEGRA_APBDMA_STATUS_BUSY BIT(31)
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#define TEGRA_APBDMA_STATUS_ISE_EOC BIT(30)
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#define TEGRA_APBDMA_STATUS_HALT BIT(29)
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#define TEGRA_APBDMA_STATUS_PING_PONG BIT(28)
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#define TEGRA_APBDMA_STATUS_COUNT_SHIFT 2
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#define TEGRA_APBDMA_STATUS_COUNT_MASK 0xFFFC
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2013-01-06 16:22:02 +00:00
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#define TEGRA_APBDMA_CHAN_CSRE 0x00C
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#define TEGRA_APBDMA_CHAN_CSRE_PAUSE (1 << 31)
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2012-06-06 05:25:27 +00:00
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/* AHB memory address */
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#define TEGRA_APBDMA_CHAN_AHBPTR 0x010
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/* AHB sequence register */
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#define TEGRA_APBDMA_CHAN_AHBSEQ 0x14
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#define TEGRA_APBDMA_AHBSEQ_INTR_ENB BIT(31)
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#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8 (0 << 28)
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#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16 (1 << 28)
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#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32 (2 << 28)
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#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64 (3 << 28)
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#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128 (4 << 28)
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#define TEGRA_APBDMA_AHBSEQ_DATA_SWAP BIT(27)
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#define TEGRA_APBDMA_AHBSEQ_BURST_1 (4 << 24)
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#define TEGRA_APBDMA_AHBSEQ_BURST_4 (5 << 24)
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#define TEGRA_APBDMA_AHBSEQ_BURST_8 (6 << 24)
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#define TEGRA_APBDMA_AHBSEQ_DBL_BUF BIT(19)
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#define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT 16
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#define TEGRA_APBDMA_AHBSEQ_WRAP_NONE 0
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/* APB address */
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#define TEGRA_APBDMA_CHAN_APBPTR 0x018
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/* APB sequence register */
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#define TEGRA_APBDMA_CHAN_APBSEQ 0x01c
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#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8 (0 << 28)
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#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16 (1 << 28)
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#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32 (2 << 28)
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#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64 (3 << 28)
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#define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128 (4 << 28)
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#define TEGRA_APBDMA_APBSEQ_DATA_SWAP BIT(27)
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#define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1 (1 << 16)
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2014-01-06 18:16:45 +00:00
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/* Tegra148 specific registers */
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#define TEGRA_APBDMA_CHAN_WCOUNT 0x20
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#define TEGRA_APBDMA_CHAN_WORD_TRANSFER 0x24
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2012-06-06 05:25:27 +00:00
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/*
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* If any burst is in flight and DMA paused then this is the time to complete
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* on-flight burst and update DMA status register.
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*/
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#define TEGRA_APBDMA_BURST_COMPLETE_TIME 20
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/* Channel base address offset from APBDMA base address */
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#define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET 0x1000
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struct tegra_dma;
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/*
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* tegra_dma_chip_data Tegra chip specific DMA data
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* @nr_channels: Number of channels available in the controller.
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2014-01-06 18:16:45 +00:00
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* @channel_reg_size: Channel register size/stride.
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2012-06-06 05:25:27 +00:00
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* @max_dma_count: Maximum DMA transfer count supported by DMA controller.
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2013-01-06 16:22:02 +00:00
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* @support_channel_pause: Support channel wise pause of dma.
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2014-01-06 18:16:45 +00:00
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* @support_separate_wcount_reg: Support separate word count register.
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2012-06-06 05:25:27 +00:00
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*/
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struct tegra_dma_chip_data {
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int nr_channels;
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2014-01-06 18:16:45 +00:00
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int channel_reg_size;
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2012-06-06 05:25:27 +00:00
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int max_dma_count;
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2013-01-06 16:22:02 +00:00
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bool support_channel_pause;
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2014-01-06 18:16:45 +00:00
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bool support_separate_wcount_reg;
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2012-06-06 05:25:27 +00:00
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};
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/* DMA channel registers */
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struct tegra_dma_channel_regs {
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unsigned long csr;
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unsigned long ahb_ptr;
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unsigned long apb_ptr;
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unsigned long ahb_seq;
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unsigned long apb_seq;
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2014-01-06 18:16:45 +00:00
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unsigned long wcount;
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2012-06-06 05:25:27 +00:00
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};
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/*
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* tegra_dma_sg_req: Dma request details to configure hardware. This
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* contains the details for one transfer to configure DMA hw.
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* The client's request for data transfer can be broken into multiple
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* sub-transfer as per requester details and hw support.
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* This sub transfer get added in the list of transfer and point to Tegra
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* DMA descriptor which manages the transfer details.
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*/
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struct tegra_dma_sg_req {
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struct tegra_dma_channel_regs ch_regs;
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int req_len;
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bool configured;
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bool last_sg;
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struct list_head node;
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struct tegra_dma_desc *dma_desc;
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};
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/*
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* tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
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* This descriptor keep track of transfer status, callbacks and request
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* counts etc.
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*/
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struct tegra_dma_desc {
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struct dma_async_tx_descriptor txd;
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int bytes_requested;
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int bytes_transferred;
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enum dma_status dma_status;
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struct list_head node;
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struct list_head tx_list;
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struct list_head cb_node;
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int cb_count;
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};
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struct tegra_dma_channel;
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typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
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bool to_terminate);
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/* tegra_dma_channel: Channel specific information */
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struct tegra_dma_channel {
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struct dma_chan dma_chan;
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2012-10-03 17:18:07 +00:00
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char name[30];
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2012-06-06 05:25:27 +00:00
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bool config_init;
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int id;
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int irq;
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2015-08-06 13:32:31 +00:00
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void __iomem *chan_addr;
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2012-06-06 05:25:27 +00:00
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spinlock_t lock;
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bool busy;
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struct tegra_dma *tdma;
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bool cyclic;
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/* Different lists for managing the requests */
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struct list_head free_sg_req;
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struct list_head pending_sg_req;
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struct list_head free_dma_desc;
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struct list_head cb_desc;
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/* ISR handler and tasklet for bottom half of isr handling */
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dma_isr_handler isr_handler;
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struct tasklet_struct tasklet;
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/* Channel-slave specific configuration */
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2013-11-11 20:09:35 +00:00
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unsigned int slave_id;
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2012-06-06 05:25:27 +00:00
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struct dma_slave_config dma_sconfig;
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2013-04-24 09:54:27 +00:00
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struct tegra_dma_channel_regs channel_reg;
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2012-06-06 05:25:27 +00:00
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};
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/* tegra_dma: Tegra DMA specific information */
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struct tegra_dma {
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struct dma_device dma_dev;
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struct device *dev;
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struct clk *dma_clk;
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2013-11-06 23:35:34 +00:00
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struct reset_control *rst;
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2012-06-06 05:25:27 +00:00
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spinlock_t global_lock;
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void __iomem *base_addr;
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2012-08-29 08:23:07 +00:00
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const struct tegra_dma_chip_data *chip_data;
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2012-06-06 05:25:27 +00:00
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2015-08-06 13:32:33 +00:00
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/*
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* Counter for managing global pausing of the DMA controller.
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* Only applicable for devices that don't support individual
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* channel pausing.
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*/
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u32 global_pause_count;
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2012-06-06 05:25:27 +00:00
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/* Some register need to be cache before suspend */
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u32 reg_gen;
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/* Last member of the structure */
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struct tegra_dma_channel channels[0];
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};
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static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
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{
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writel(val, tdma->base_addr + reg);
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}
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static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
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{
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return readl(tdma->base_addr + reg);
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}
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static inline void tdc_write(struct tegra_dma_channel *tdc,
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u32 reg, u32 val)
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{
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2015-08-06 13:32:31 +00:00
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writel(val, tdc->chan_addr + reg);
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2012-06-06 05:25:27 +00:00
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}
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static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
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{
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2015-08-06 13:32:31 +00:00
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return readl(tdc->chan_addr + reg);
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2012-06-06 05:25:27 +00:00
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}
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static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
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{
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return container_of(dc, struct tegra_dma_channel, dma_chan);
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}
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static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
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struct dma_async_tx_descriptor *td)
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{
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return container_of(td, struct tegra_dma_desc, txd);
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}
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static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
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{
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return &tdc->dma_chan.dev->device;
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}
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static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
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static int tegra_dma_runtime_suspend(struct device *dev);
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static int tegra_dma_runtime_resume(struct device *dev);
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/* Get DMA desc from free list, if not there then allocate it. */
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static struct tegra_dma_desc *tegra_dma_desc_get(
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struct tegra_dma_channel *tdc)
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{
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struct tegra_dma_desc *dma_desc;
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unsigned long flags;
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spin_lock_irqsave(&tdc->lock, flags);
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/* Do not allocate if desc are waiting for ack */
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list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
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if (async_tx_test_ack(&dma_desc->txd)) {
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list_del(&dma_desc->node);
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spin_unlock_irqrestore(&tdc->lock, flags);
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2013-01-09 09:56:22 +00:00
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dma_desc->txd.flags = 0;
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2012-06-06 05:25:27 +00:00
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return dma_desc;
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}
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}
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spin_unlock_irqrestore(&tdc->lock, flags);
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/* Allocate DMA desc */
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dma_desc = kzalloc(sizeof(*dma_desc), GFP_ATOMIC);
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if (!dma_desc) {
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dev_err(tdc2dev(tdc), "dma_desc alloc failed\n");
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return NULL;
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}
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dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
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dma_desc->txd.tx_submit = tegra_dma_tx_submit;
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dma_desc->txd.flags = 0;
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return dma_desc;
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}
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static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
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struct tegra_dma_desc *dma_desc)
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{
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unsigned long flags;
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spin_lock_irqsave(&tdc->lock, flags);
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if (!list_empty(&dma_desc->tx_list))
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list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
|
|
|
|
list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
|
|
|
|
spin_unlock_irqrestore(&tdc->lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
|
|
|
|
struct tegra_dma_channel *tdc)
|
|
|
|
{
|
|
|
|
struct tegra_dma_sg_req *sg_req = NULL;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&tdc->lock, flags);
|
|
|
|
if (!list_empty(&tdc->free_sg_req)) {
|
|
|
|
sg_req = list_first_entry(&tdc->free_sg_req,
|
|
|
|
typeof(*sg_req), node);
|
|
|
|
list_del(&sg_req->node);
|
|
|
|
spin_unlock_irqrestore(&tdc->lock, flags);
|
|
|
|
return sg_req;
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&tdc->lock, flags);
|
|
|
|
|
|
|
|
sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_ATOMIC);
|
|
|
|
if (!sg_req)
|
|
|
|
dev_err(tdc2dev(tdc), "sg_req alloc failed\n");
|
|
|
|
return sg_req;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_dma_slave_config(struct dma_chan *dc,
|
|
|
|
struct dma_slave_config *sconfig)
|
|
|
|
{
|
|
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
|
|
|
|
|
|
|
if (!list_empty(&tdc->pending_sg_req)) {
|
|
|
|
dev_err(tdc2dev(tdc), "Configuration not allowed\n");
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
|
2013-11-11 20:09:35 +00:00
|
|
|
if (!tdc->slave_id)
|
|
|
|
tdc->slave_id = sconfig->slave_id;
|
2012-06-06 05:25:27 +00:00
|
|
|
tdc->config_init = true;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
|
|
|
|
bool wait_for_burst_complete)
|
|
|
|
{
|
|
|
|
struct tegra_dma *tdma = tdc->tdma;
|
|
|
|
|
|
|
|
spin_lock(&tdma->global_lock);
|
2015-08-06 13:32:33 +00:00
|
|
|
|
|
|
|
if (tdc->tdma->global_pause_count == 0) {
|
|
|
|
tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
|
|
|
|
if (wait_for_burst_complete)
|
|
|
|
udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
|
|
|
|
}
|
|
|
|
|
|
|
|
tdc->tdma->global_pause_count++;
|
|
|
|
|
|
|
|
spin_unlock(&tdma->global_lock);
|
2012-06-06 05:25:27 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void tegra_dma_global_resume(struct tegra_dma_channel *tdc)
|
|
|
|
{
|
|
|
|
struct tegra_dma *tdma = tdc->tdma;
|
|
|
|
|
2015-08-06 13:32:33 +00:00
|
|
|
spin_lock(&tdma->global_lock);
|
|
|
|
|
|
|
|
if (WARN_ON(tdc->tdma->global_pause_count == 0))
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
if (--tdc->tdma->global_pause_count == 0)
|
|
|
|
tdma_write(tdma, TEGRA_APBDMA_GENERAL,
|
|
|
|
TEGRA_APBDMA_GENERAL_ENABLE);
|
|
|
|
|
|
|
|
out:
|
2012-06-06 05:25:27 +00:00
|
|
|
spin_unlock(&tdma->global_lock);
|
|
|
|
}
|
|
|
|
|
2013-01-06 16:22:02 +00:00
|
|
|
static void tegra_dma_pause(struct tegra_dma_channel *tdc,
|
|
|
|
bool wait_for_burst_complete)
|
|
|
|
{
|
|
|
|
struct tegra_dma *tdma = tdc->tdma;
|
|
|
|
|
|
|
|
if (tdma->chip_data->support_channel_pause) {
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,
|
|
|
|
TEGRA_APBDMA_CHAN_CSRE_PAUSE);
|
|
|
|
if (wait_for_burst_complete)
|
|
|
|
udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
|
|
|
|
} else {
|
|
|
|
tegra_dma_global_pause(tdc, wait_for_burst_complete);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tegra_dma_resume(struct tegra_dma_channel *tdc)
|
|
|
|
{
|
|
|
|
struct tegra_dma *tdma = tdc->tdma;
|
|
|
|
|
|
|
|
if (tdma->chip_data->support_channel_pause) {
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0);
|
|
|
|
} else {
|
|
|
|
tegra_dma_global_resume(tdc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-06-06 05:25:27 +00:00
|
|
|
static void tegra_dma_stop(struct tegra_dma_channel *tdc)
|
|
|
|
{
|
|
|
|
u32 csr;
|
|
|
|
u32 status;
|
|
|
|
|
|
|
|
/* Disable interrupts */
|
|
|
|
csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
|
|
|
|
csr &= ~TEGRA_APBDMA_CSR_IE_EOC;
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
|
|
|
|
|
|
|
|
/* Disable DMA */
|
|
|
|
csr &= ~TEGRA_APBDMA_CSR_ENB;
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
|
|
|
|
|
|
|
|
/* Clear interrupt status if it is there */
|
|
|
|
status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
|
|
|
|
if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
|
|
|
|
dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
|
|
|
|
}
|
|
|
|
tdc->busy = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tegra_dma_start(struct tegra_dma_channel *tdc,
|
|
|
|
struct tegra_dma_sg_req *sg_req)
|
|
|
|
{
|
|
|
|
struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
|
|
|
|
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);
|
2014-01-06 18:16:45 +00:00
|
|
|
if (tdc->tdma->chip_data->support_separate_wcount_reg)
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, ch_regs->wcount);
|
2012-06-06 05:25:27 +00:00
|
|
|
|
|
|
|
/* Start DMA */
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
|
|
|
|
ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
|
|
|
|
struct tegra_dma_sg_req *nsg_req)
|
|
|
|
{
|
|
|
|
unsigned long status;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The DMA controller reloads the new configuration for next transfer
|
|
|
|
* after last burst of current transfer completes.
|
|
|
|
* If there is no IEC status then this makes sure that last burst
|
|
|
|
* has not be completed. There may be case that last burst is on
|
|
|
|
* flight and so it can complete but because DMA is paused, it
|
|
|
|
* will not generates interrupt as well as not reload the new
|
|
|
|
* configuration.
|
|
|
|
* If there is already IEC status then interrupt handler need to
|
|
|
|
* load new configuration.
|
|
|
|
*/
|
2013-01-06 16:22:02 +00:00
|
|
|
tegra_dma_pause(tdc, false);
|
2012-06-06 05:25:27 +00:00
|
|
|
status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If interrupt is pending then do nothing as the ISR will handle
|
|
|
|
* the programing for new request.
|
|
|
|
*/
|
|
|
|
if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
|
|
|
|
dev_err(tdc2dev(tdc),
|
|
|
|
"Skipping new configuration as interrupt is pending\n");
|
2013-01-06 16:22:02 +00:00
|
|
|
tegra_dma_resume(tdc);
|
2012-06-06 05:25:27 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Safe to program new configuration */
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
|
2014-01-06 18:16:45 +00:00
|
|
|
if (tdc->tdma->chip_data->support_separate_wcount_reg)
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
|
|
|
|
nsg_req->ch_regs.wcount);
|
2012-06-06 05:25:27 +00:00
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
|
|
|
|
nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
|
|
|
|
nsg_req->configured = true;
|
|
|
|
|
2013-01-06 16:22:02 +00:00
|
|
|
tegra_dma_resume(tdc);
|
2012-06-06 05:25:27 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void tdc_start_head_req(struct tegra_dma_channel *tdc)
|
|
|
|
{
|
|
|
|
struct tegra_dma_sg_req *sg_req;
|
|
|
|
|
|
|
|
if (list_empty(&tdc->pending_sg_req))
|
|
|
|
return;
|
|
|
|
|
|
|
|
sg_req = list_first_entry(&tdc->pending_sg_req,
|
|
|
|
typeof(*sg_req), node);
|
|
|
|
tegra_dma_start(tdc, sg_req);
|
|
|
|
sg_req->configured = true;
|
|
|
|
tdc->busy = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
|
|
|
|
{
|
|
|
|
struct tegra_dma_sg_req *hsgreq;
|
|
|
|
struct tegra_dma_sg_req *hnsgreq;
|
|
|
|
|
|
|
|
if (list_empty(&tdc->pending_sg_req))
|
|
|
|
return;
|
|
|
|
|
|
|
|
hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
|
|
|
|
if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
|
|
|
|
hnsgreq = list_first_entry(&hsgreq->node,
|
|
|
|
typeof(*hnsgreq), node);
|
|
|
|
tegra_dma_configure_for_next(tdc, hnsgreq);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
|
|
|
|
struct tegra_dma_sg_req *sg_req, unsigned long status)
|
|
|
|
{
|
|
|
|
return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
|
|
|
|
{
|
|
|
|
struct tegra_dma_sg_req *sgreq;
|
|
|
|
struct tegra_dma_desc *dma_desc;
|
|
|
|
|
|
|
|
while (!list_empty(&tdc->pending_sg_req)) {
|
|
|
|
sgreq = list_first_entry(&tdc->pending_sg_req,
|
|
|
|
typeof(*sgreq), node);
|
2012-09-05 07:08:56 +00:00
|
|
|
list_move_tail(&sgreq->node, &tdc->free_sg_req);
|
2012-06-06 05:25:27 +00:00
|
|
|
if (sgreq->last_sg) {
|
|
|
|
dma_desc = sgreq->dma_desc;
|
|
|
|
dma_desc->dma_status = DMA_ERROR;
|
|
|
|
list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
|
|
|
|
|
|
|
|
/* Add in cb list if it is not there. */
|
|
|
|
if (!dma_desc->cb_count)
|
|
|
|
list_add_tail(&dma_desc->cb_node,
|
|
|
|
&tdc->cb_desc);
|
|
|
|
dma_desc->cb_count++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
tdc->isr_handler = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
|
|
|
|
struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
|
|
|
|
{
|
|
|
|
struct tegra_dma_sg_req *hsgreq = NULL;
|
|
|
|
|
|
|
|
if (list_empty(&tdc->pending_sg_req)) {
|
|
|
|
dev_err(tdc2dev(tdc), "Dma is running without req\n");
|
|
|
|
tegra_dma_stop(tdc);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check that head req on list should be in flight.
|
|
|
|
* If it is not in flight then abort transfer as
|
|
|
|
* looping of transfer can not continue.
|
|
|
|
*/
|
|
|
|
hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
|
|
|
|
if (!hsgreq->configured) {
|
|
|
|
tegra_dma_stop(tdc);
|
|
|
|
dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
|
|
|
|
tegra_dma_abort_all(tdc);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Configure next request */
|
|
|
|
if (!to_terminate)
|
|
|
|
tdc_configure_next_head_desc(tdc);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void handle_once_dma_done(struct tegra_dma_channel *tdc,
|
|
|
|
bool to_terminate)
|
|
|
|
{
|
|
|
|
struct tegra_dma_sg_req *sgreq;
|
|
|
|
struct tegra_dma_desc *dma_desc;
|
|
|
|
|
|
|
|
tdc->busy = false;
|
|
|
|
sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
|
|
|
|
dma_desc = sgreq->dma_desc;
|
|
|
|
dma_desc->bytes_transferred += sgreq->req_len;
|
|
|
|
|
|
|
|
list_del(&sgreq->node);
|
|
|
|
if (sgreq->last_sg) {
|
2013-10-16 15:34:50 +00:00
|
|
|
dma_desc->dma_status = DMA_COMPLETE;
|
2012-06-06 05:25:27 +00:00
|
|
|
dma_cookie_complete(&dma_desc->txd);
|
|
|
|
if (!dma_desc->cb_count)
|
|
|
|
list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
|
|
|
|
dma_desc->cb_count++;
|
|
|
|
list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
|
|
|
|
}
|
|
|
|
list_add_tail(&sgreq->node, &tdc->free_sg_req);
|
|
|
|
|
|
|
|
/* Do not start DMA if it is going to be terminate */
|
|
|
|
if (to_terminate || list_empty(&tdc->pending_sg_req))
|
|
|
|
return;
|
|
|
|
|
|
|
|
tdc_start_head_req(tdc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
|
|
|
|
bool to_terminate)
|
|
|
|
{
|
|
|
|
struct tegra_dma_sg_req *sgreq;
|
|
|
|
struct tegra_dma_desc *dma_desc;
|
|
|
|
bool st;
|
|
|
|
|
|
|
|
sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
|
|
|
|
dma_desc = sgreq->dma_desc;
|
|
|
|
dma_desc->bytes_transferred += sgreq->req_len;
|
|
|
|
|
|
|
|
/* Callback need to be call */
|
|
|
|
if (!dma_desc->cb_count)
|
|
|
|
list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
|
|
|
|
dma_desc->cb_count++;
|
|
|
|
|
|
|
|
/* If not last req then put at end of pending list */
|
|
|
|
if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
|
2012-09-05 07:08:56 +00:00
|
|
|
list_move_tail(&sgreq->node, &tdc->pending_sg_req);
|
2012-06-06 05:25:27 +00:00
|
|
|
sgreq->configured = false;
|
|
|
|
st = handle_continuous_head_request(tdc, sgreq, to_terminate);
|
|
|
|
if (!st)
|
|
|
|
dma_desc->dma_status = DMA_ERROR;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tegra_dma_tasklet(unsigned long data)
|
|
|
|
{
|
|
|
|
struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
|
|
|
|
dma_async_tx_callback callback = NULL;
|
|
|
|
void *callback_param = NULL;
|
|
|
|
struct tegra_dma_desc *dma_desc;
|
|
|
|
unsigned long flags;
|
|
|
|
int cb_count;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&tdc->lock, flags);
|
|
|
|
while (!list_empty(&tdc->cb_desc)) {
|
|
|
|
dma_desc = list_first_entry(&tdc->cb_desc,
|
|
|
|
typeof(*dma_desc), cb_node);
|
|
|
|
list_del(&dma_desc->cb_node);
|
|
|
|
callback = dma_desc->txd.callback;
|
|
|
|
callback_param = dma_desc->txd.callback_param;
|
|
|
|
cb_count = dma_desc->cb_count;
|
|
|
|
dma_desc->cb_count = 0;
|
|
|
|
spin_unlock_irqrestore(&tdc->lock, flags);
|
|
|
|
while (cb_count-- && callback)
|
|
|
|
callback(callback_param);
|
|
|
|
spin_lock_irqsave(&tdc->lock, flags);
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&tdc->lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct tegra_dma_channel *tdc = dev_id;
|
|
|
|
unsigned long status;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&tdc->lock, flags);
|
|
|
|
|
|
|
|
status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
|
|
|
|
if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
|
|
|
|
tdc->isr_handler(tdc, false);
|
|
|
|
tasklet_schedule(&tdc->tasklet);
|
|
|
|
spin_unlock_irqrestore(&tdc->lock, flags);
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&tdc->lock, flags);
|
|
|
|
dev_info(tdc2dev(tdc),
|
|
|
|
"Interrupt already served status 0x%08lx\n", status);
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
|
|
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
|
|
|
|
unsigned long flags;
|
|
|
|
dma_cookie_t cookie;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&tdc->lock, flags);
|
|
|
|
dma_desc->dma_status = DMA_IN_PROGRESS;
|
|
|
|
cookie = dma_cookie_assign(&dma_desc->txd);
|
|
|
|
list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
|
|
|
|
spin_unlock_irqrestore(&tdc->lock, flags);
|
|
|
|
return cookie;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tegra_dma_issue_pending(struct dma_chan *dc)
|
|
|
|
{
|
|
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&tdc->lock, flags);
|
|
|
|
if (list_empty(&tdc->pending_sg_req)) {
|
|
|
|
dev_err(tdc2dev(tdc), "No DMA request\n");
|
|
|
|
goto end;
|
|
|
|
}
|
|
|
|
if (!tdc->busy) {
|
|
|
|
tdc_start_head_req(tdc);
|
|
|
|
|
|
|
|
/* Continuous single mode: Configure next req */
|
|
|
|
if (tdc->cyclic) {
|
|
|
|
/*
|
|
|
|
* Wait for 1 burst time for configure DMA for
|
|
|
|
* next transfer.
|
|
|
|
*/
|
|
|
|
udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
|
|
|
|
tdc_configure_next_head_desc(tdc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
end:
|
|
|
|
spin_unlock_irqrestore(&tdc->lock, flags);
|
|
|
|
}
|
|
|
|
|
2014-12-08 06:00:17 +00:00
|
|
|
static int tegra_dma_terminate_all(struct dma_chan *dc)
|
2012-06-06 05:25:27 +00:00
|
|
|
{
|
|
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
|
|
|
struct tegra_dma_sg_req *sgreq;
|
|
|
|
struct tegra_dma_desc *dma_desc;
|
|
|
|
unsigned long flags;
|
|
|
|
unsigned long status;
|
2014-01-06 18:16:45 +00:00
|
|
|
unsigned long wcount;
|
2012-06-06 05:25:27 +00:00
|
|
|
bool was_busy;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&tdc->lock, flags);
|
|
|
|
if (list_empty(&tdc->pending_sg_req)) {
|
|
|
|
spin_unlock_irqrestore(&tdc->lock, flags);
|
2014-12-08 06:00:17 +00:00
|
|
|
return 0;
|
2012-06-06 05:25:27 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!tdc->busy)
|
|
|
|
goto skip_dma_stop;
|
|
|
|
|
|
|
|
/* Pause DMA before checking the queue status */
|
2013-01-06 16:22:02 +00:00
|
|
|
tegra_dma_pause(tdc, true);
|
2012-06-06 05:25:27 +00:00
|
|
|
|
|
|
|
status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
|
|
|
|
if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
|
|
|
|
dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
|
|
|
|
tdc->isr_handler(tdc, true);
|
|
|
|
status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
|
|
|
|
}
|
2014-01-06 18:16:45 +00:00
|
|
|
if (tdc->tdma->chip_data->support_separate_wcount_reg)
|
|
|
|
wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
|
|
|
|
else
|
|
|
|
wcount = status;
|
2012-06-06 05:25:27 +00:00
|
|
|
|
|
|
|
was_busy = tdc->busy;
|
|
|
|
tegra_dma_stop(tdc);
|
|
|
|
|
|
|
|
if (!list_empty(&tdc->pending_sg_req) && was_busy) {
|
|
|
|
sgreq = list_first_entry(&tdc->pending_sg_req,
|
|
|
|
typeof(*sgreq), node);
|
|
|
|
sgreq->dma_desc->bytes_transferred +=
|
2014-01-06 18:16:45 +00:00
|
|
|
get_current_xferred_count(tdc, sgreq, wcount);
|
2012-06-06 05:25:27 +00:00
|
|
|
}
|
2013-01-06 16:22:02 +00:00
|
|
|
tegra_dma_resume(tdc);
|
2012-06-06 05:25:27 +00:00
|
|
|
|
|
|
|
skip_dma_stop:
|
|
|
|
tegra_dma_abort_all(tdc);
|
|
|
|
|
|
|
|
while (!list_empty(&tdc->cb_desc)) {
|
|
|
|
dma_desc = list_first_entry(&tdc->cb_desc,
|
|
|
|
typeof(*dma_desc), cb_node);
|
|
|
|
list_del(&dma_desc->cb_node);
|
|
|
|
dma_desc->cb_count = 0;
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&tdc->lock, flags);
|
2014-12-08 06:00:17 +00:00
|
|
|
return 0;
|
2012-06-06 05:25:27 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
|
|
|
|
dma_cookie_t cookie, struct dma_tx_state *txstate)
|
|
|
|
{
|
|
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
|
|
|
struct tegra_dma_desc *dma_desc;
|
|
|
|
struct tegra_dma_sg_req *sg_req;
|
|
|
|
enum dma_status ret;
|
|
|
|
unsigned long flags;
|
2012-07-02 08:22:07 +00:00
|
|
|
unsigned int residual;
|
2012-06-06 05:25:27 +00:00
|
|
|
|
|
|
|
ret = dma_cookie_status(dc, cookie, txstate);
|
2013-10-16 15:34:50 +00:00
|
|
|
if (ret == DMA_COMPLETE)
|
2012-06-06 05:25:27 +00:00
|
|
|
return ret;
|
2013-05-27 12:14:39 +00:00
|
|
|
|
|
|
|
spin_lock_irqsave(&tdc->lock, flags);
|
2012-06-06 05:25:27 +00:00
|
|
|
|
|
|
|
/* Check on wait_ack desc status */
|
|
|
|
list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
|
|
|
|
if (dma_desc->txd.cookie == cookie) {
|
2012-07-02 08:22:07 +00:00
|
|
|
residual = dma_desc->bytes_requested -
|
|
|
|
(dma_desc->bytes_transferred %
|
|
|
|
dma_desc->bytes_requested);
|
|
|
|
dma_set_residue(txstate, residual);
|
2012-06-06 05:25:27 +00:00
|
|
|
ret = dma_desc->dma_status;
|
|
|
|
spin_unlock_irqrestore(&tdc->lock, flags);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check in pending list */
|
|
|
|
list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
|
|
|
|
dma_desc = sg_req->dma_desc;
|
|
|
|
if (dma_desc->txd.cookie == cookie) {
|
2012-07-02 08:22:07 +00:00
|
|
|
residual = dma_desc->bytes_requested -
|
|
|
|
(dma_desc->bytes_transferred %
|
|
|
|
dma_desc->bytes_requested);
|
|
|
|
dma_set_residue(txstate, residual);
|
2012-06-06 05:25:27 +00:00
|
|
|
ret = dma_desc->dma_status;
|
|
|
|
spin_unlock_irqrestore(&tdc->lock, flags);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie);
|
|
|
|
spin_unlock_irqrestore(&tdc->lock, flags);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int get_bus_width(struct tegra_dma_channel *tdc,
|
|
|
|
enum dma_slave_buswidth slave_bw)
|
|
|
|
{
|
|
|
|
switch (slave_bw) {
|
|
|
|
case DMA_SLAVE_BUSWIDTH_1_BYTE:
|
|
|
|
return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8;
|
|
|
|
case DMA_SLAVE_BUSWIDTH_2_BYTES:
|
|
|
|
return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
|
|
|
|
case DMA_SLAVE_BUSWIDTH_4_BYTES:
|
|
|
|
return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
|
|
|
|
case DMA_SLAVE_BUSWIDTH_8_BYTES:
|
|
|
|
return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
|
|
|
|
default:
|
|
|
|
dev_warn(tdc2dev(tdc),
|
|
|
|
"slave bw is not supported, using 32bits\n");
|
|
|
|
return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int get_burst_size(struct tegra_dma_channel *tdc,
|
|
|
|
u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
|
|
|
|
{
|
|
|
|
int burst_byte;
|
|
|
|
int burst_ahb_width;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* burst_size from client is in terms of the bus_width.
|
|
|
|
* convert them into AHB memory width which is 4 byte.
|
|
|
|
*/
|
|
|
|
burst_byte = burst_size * slave_bw;
|
|
|
|
burst_ahb_width = burst_byte / 4;
|
|
|
|
|
|
|
|
/* If burst size is 0 then calculate the burst size based on length */
|
|
|
|
if (!burst_ahb_width) {
|
|
|
|
if (len & 0xF)
|
|
|
|
return TEGRA_APBDMA_AHBSEQ_BURST_1;
|
|
|
|
else if ((len >> 4) & 0x1)
|
|
|
|
return TEGRA_APBDMA_AHBSEQ_BURST_4;
|
|
|
|
else
|
|
|
|
return TEGRA_APBDMA_AHBSEQ_BURST_8;
|
|
|
|
}
|
|
|
|
if (burst_ahb_width < 4)
|
|
|
|
return TEGRA_APBDMA_AHBSEQ_BURST_1;
|
|
|
|
else if (burst_ahb_width < 8)
|
|
|
|
return TEGRA_APBDMA_AHBSEQ_BURST_4;
|
|
|
|
else
|
|
|
|
return TEGRA_APBDMA_AHBSEQ_BURST_8;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int get_transfer_param(struct tegra_dma_channel *tdc,
|
|
|
|
enum dma_transfer_direction direction, unsigned long *apb_addr,
|
|
|
|
unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
|
|
|
|
enum dma_slave_buswidth *slave_bw)
|
|
|
|
{
|
|
|
|
|
|
|
|
switch (direction) {
|
|
|
|
case DMA_MEM_TO_DEV:
|
|
|
|
*apb_addr = tdc->dma_sconfig.dst_addr;
|
|
|
|
*apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
|
|
|
|
*burst_size = tdc->dma_sconfig.dst_maxburst;
|
|
|
|
*slave_bw = tdc->dma_sconfig.dst_addr_width;
|
|
|
|
*csr = TEGRA_APBDMA_CSR_DIR;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
case DMA_DEV_TO_MEM:
|
|
|
|
*apb_addr = tdc->dma_sconfig.src_addr;
|
|
|
|
*apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
|
|
|
|
*burst_size = tdc->dma_sconfig.src_maxburst;
|
|
|
|
*slave_bw = tdc->dma_sconfig.src_addr_width;
|
|
|
|
*csr = 0;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
default:
|
|
|
|
dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2014-01-06 18:16:45 +00:00
|
|
|
static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc,
|
|
|
|
struct tegra_dma_channel_regs *ch_regs, u32 len)
|
|
|
|
{
|
|
|
|
u32 len_field = (len - 4) & 0xFFFC;
|
|
|
|
|
|
|
|
if (tdc->tdma->chip_data->support_separate_wcount_reg)
|
|
|
|
ch_regs->wcount = len_field;
|
|
|
|
else
|
|
|
|
ch_regs->csr |= len_field;
|
|
|
|
}
|
|
|
|
|
2012-06-06 05:25:27 +00:00
|
|
|
static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
|
|
|
|
struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
|
|
|
|
enum dma_transfer_direction direction, unsigned long flags,
|
|
|
|
void *context)
|
|
|
|
{
|
|
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
|
|
|
struct tegra_dma_desc *dma_desc;
|
|
|
|
unsigned int i;
|
|
|
|
struct scatterlist *sg;
|
|
|
|
unsigned long csr, ahb_seq, apb_ptr, apb_seq;
|
|
|
|
struct list_head req_list;
|
|
|
|
struct tegra_dma_sg_req *sg_req = NULL;
|
|
|
|
u32 burst_size;
|
|
|
|
enum dma_slave_buswidth slave_bw;
|
|
|
|
|
|
|
|
if (!tdc->config_init) {
|
|
|
|
dev_err(tdc2dev(tdc), "dma channel is not configured\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
if (sg_len < 1) {
|
|
|
|
dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2015-08-06 13:32:32 +00:00
|
|
|
if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
|
|
|
|
&burst_size, &slave_bw) < 0)
|
2012-06-06 05:25:27 +00:00
|
|
|
return NULL;
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&req_list);
|
|
|
|
|
|
|
|
ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
|
|
|
|
ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
|
|
|
|
TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
|
|
|
|
ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
|
|
|
|
|
|
|
|
csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
|
2013-11-11 20:09:35 +00:00
|
|
|
csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
|
2012-06-06 05:25:27 +00:00
|
|
|
if (flags & DMA_PREP_INTERRUPT)
|
|
|
|
csr |= TEGRA_APBDMA_CSR_IE_EOC;
|
|
|
|
|
|
|
|
apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
|
|
|
|
|
|
|
|
dma_desc = tegra_dma_desc_get(tdc);
|
|
|
|
if (!dma_desc) {
|
|
|
|
dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
INIT_LIST_HEAD(&dma_desc->tx_list);
|
|
|
|
INIT_LIST_HEAD(&dma_desc->cb_node);
|
|
|
|
dma_desc->cb_count = 0;
|
|
|
|
dma_desc->bytes_requested = 0;
|
|
|
|
dma_desc->bytes_transferred = 0;
|
|
|
|
dma_desc->dma_status = DMA_IN_PROGRESS;
|
|
|
|
|
|
|
|
/* Make transfer requests */
|
|
|
|
for_each_sg(sgl, sg, sg_len, i) {
|
|
|
|
u32 len, mem;
|
|
|
|
|
2012-06-22 15:11:10 +00:00
|
|
|
mem = sg_dma_address(sg);
|
2012-06-06 05:25:27 +00:00
|
|
|
len = sg_dma_len(sg);
|
|
|
|
|
|
|
|
if ((len & 3) || (mem & 3) ||
|
|
|
|
(len > tdc->tdma->chip_data->max_dma_count)) {
|
|
|
|
dev_err(tdc2dev(tdc),
|
|
|
|
"Dma length/memory address is not supported\n");
|
|
|
|
tegra_dma_desc_put(tdc, dma_desc);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
sg_req = tegra_dma_sg_req_get(tdc);
|
|
|
|
if (!sg_req) {
|
|
|
|
dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
|
|
|
|
tegra_dma_desc_put(tdc, dma_desc);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
|
|
|
|
dma_desc->bytes_requested += len;
|
|
|
|
|
|
|
|
sg_req->ch_regs.apb_ptr = apb_ptr;
|
|
|
|
sg_req->ch_regs.ahb_ptr = mem;
|
2014-01-06 18:16:45 +00:00
|
|
|
sg_req->ch_regs.csr = csr;
|
|
|
|
tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
|
2012-06-06 05:25:27 +00:00
|
|
|
sg_req->ch_regs.apb_seq = apb_seq;
|
|
|
|
sg_req->ch_regs.ahb_seq = ahb_seq;
|
|
|
|
sg_req->configured = false;
|
|
|
|
sg_req->last_sg = false;
|
|
|
|
sg_req->dma_desc = dma_desc;
|
|
|
|
sg_req->req_len = len;
|
|
|
|
|
|
|
|
list_add_tail(&sg_req->node, &dma_desc->tx_list);
|
|
|
|
}
|
|
|
|
sg_req->last_sg = true;
|
|
|
|
if (flags & DMA_CTRL_ACK)
|
|
|
|
dma_desc->txd.flags = DMA_CTRL_ACK;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Make sure that mode should not be conflicting with currently
|
|
|
|
* configured mode.
|
|
|
|
*/
|
|
|
|
if (!tdc->isr_handler) {
|
|
|
|
tdc->isr_handler = handle_once_dma_done;
|
|
|
|
tdc->cyclic = false;
|
|
|
|
} else {
|
|
|
|
if (tdc->cyclic) {
|
|
|
|
dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
|
|
|
|
tegra_dma_desc_put(tdc, dma_desc);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return &dma_desc->txd;
|
|
|
|
}
|
|
|
|
|
2013-09-06 11:46:22 +00:00
|
|
|
static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
|
2012-06-06 05:25:27 +00:00
|
|
|
struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
|
|
|
|
size_t period_len, enum dma_transfer_direction direction,
|
2014-08-01 10:20:10 +00:00
|
|
|
unsigned long flags)
|
2012-06-06 05:25:27 +00:00
|
|
|
{
|
|
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
|
|
|
struct tegra_dma_desc *dma_desc = NULL;
|
|
|
|
struct tegra_dma_sg_req *sg_req = NULL;
|
|
|
|
unsigned long csr, ahb_seq, apb_ptr, apb_seq;
|
|
|
|
int len;
|
|
|
|
size_t remain_len;
|
|
|
|
dma_addr_t mem = buf_addr;
|
|
|
|
u32 burst_size;
|
|
|
|
enum dma_slave_buswidth slave_bw;
|
|
|
|
|
|
|
|
if (!buf_len || !period_len) {
|
|
|
|
dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!tdc->config_init) {
|
|
|
|
dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We allow to take more number of requests till DMA is
|
|
|
|
* not started. The driver will loop over all requests.
|
|
|
|
* Once DMA is started then new requests can be queued only after
|
|
|
|
* terminating the DMA.
|
|
|
|
*/
|
|
|
|
if (tdc->busy) {
|
|
|
|
dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We only support cycle transfer when buf_len is multiple of
|
|
|
|
* period_len.
|
|
|
|
*/
|
|
|
|
if (buf_len % period_len) {
|
|
|
|
dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
len = period_len;
|
|
|
|
if ((len & 3) || (buf_addr & 3) ||
|
|
|
|
(len > tdc->tdma->chip_data->max_dma_count)) {
|
|
|
|
dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2015-08-06 13:32:32 +00:00
|
|
|
if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
|
|
|
|
&burst_size, &slave_bw) < 0)
|
2012-06-06 05:25:27 +00:00
|
|
|
return NULL;
|
|
|
|
|
|
|
|
ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
|
|
|
|
ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
|
|
|
|
TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
|
|
|
|
ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
|
|
|
|
|
2013-01-09 09:56:22 +00:00
|
|
|
csr |= TEGRA_APBDMA_CSR_FLOW;
|
|
|
|
if (flags & DMA_PREP_INTERRUPT)
|
|
|
|
csr |= TEGRA_APBDMA_CSR_IE_EOC;
|
2013-11-11 20:09:35 +00:00
|
|
|
csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
|
2012-06-06 05:25:27 +00:00
|
|
|
|
|
|
|
apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
|
|
|
|
|
|
|
|
dma_desc = tegra_dma_desc_get(tdc);
|
|
|
|
if (!dma_desc) {
|
|
|
|
dev_err(tdc2dev(tdc), "not enough descriptors available\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&dma_desc->tx_list);
|
|
|
|
INIT_LIST_HEAD(&dma_desc->cb_node);
|
|
|
|
dma_desc->cb_count = 0;
|
|
|
|
|
|
|
|
dma_desc->bytes_transferred = 0;
|
|
|
|
dma_desc->bytes_requested = buf_len;
|
|
|
|
remain_len = buf_len;
|
|
|
|
|
|
|
|
/* Split transfer equal to period size */
|
|
|
|
while (remain_len) {
|
|
|
|
sg_req = tegra_dma_sg_req_get(tdc);
|
|
|
|
if (!sg_req) {
|
|
|
|
dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
|
|
|
|
tegra_dma_desc_put(tdc, dma_desc);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
|
|
|
|
sg_req->ch_regs.apb_ptr = apb_ptr;
|
|
|
|
sg_req->ch_regs.ahb_ptr = mem;
|
2014-01-06 18:16:45 +00:00
|
|
|
sg_req->ch_regs.csr = csr;
|
|
|
|
tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
|
2012-06-06 05:25:27 +00:00
|
|
|
sg_req->ch_regs.apb_seq = apb_seq;
|
|
|
|
sg_req->ch_regs.ahb_seq = ahb_seq;
|
|
|
|
sg_req->configured = false;
|
|
|
|
sg_req->last_sg = false;
|
|
|
|
sg_req->dma_desc = dma_desc;
|
|
|
|
sg_req->req_len = len;
|
|
|
|
|
|
|
|
list_add_tail(&sg_req->node, &dma_desc->tx_list);
|
|
|
|
remain_len -= len;
|
|
|
|
mem += len;
|
|
|
|
}
|
|
|
|
sg_req->last_sg = true;
|
2013-01-09 09:56:22 +00:00
|
|
|
if (flags & DMA_CTRL_ACK)
|
|
|
|
dma_desc->txd.flags = DMA_CTRL_ACK;
|
2012-06-06 05:25:27 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Make sure that mode should not be conflicting with currently
|
|
|
|
* configured mode.
|
|
|
|
*/
|
|
|
|
if (!tdc->isr_handler) {
|
|
|
|
tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
|
|
|
|
tdc->cyclic = true;
|
|
|
|
} else {
|
|
|
|
if (!tdc->cyclic) {
|
|
|
|
dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
|
|
|
|
tegra_dma_desc_put(tdc, dma_desc);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return &dma_desc->txd;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
|
|
|
|
{
|
|
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
2012-07-20 08:01:08 +00:00
|
|
|
struct tegra_dma *tdma = tdc->tdma;
|
|
|
|
int ret;
|
2012-06-06 05:25:27 +00:00
|
|
|
|
|
|
|
dma_cookie_init(&tdc->dma_chan);
|
|
|
|
tdc->config_init = false;
|
2015-11-13 16:39:38 +00:00
|
|
|
|
|
|
|
ret = pm_runtime_get_sync(tdma->dev);
|
2012-07-20 08:01:08 +00:00
|
|
|
if (ret < 0)
|
2015-11-13 16:39:38 +00:00
|
|
|
return ret;
|
|
|
|
|
|
|
|
return 0;
|
2012-06-06 05:25:27 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void tegra_dma_free_chan_resources(struct dma_chan *dc)
|
|
|
|
{
|
|
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
2012-07-20 08:01:08 +00:00
|
|
|
struct tegra_dma *tdma = tdc->tdma;
|
2012-06-06 05:25:27 +00:00
|
|
|
|
|
|
|
struct tegra_dma_desc *dma_desc;
|
|
|
|
struct tegra_dma_sg_req *sg_req;
|
|
|
|
struct list_head dma_desc_list;
|
|
|
|
struct list_head sg_req_list;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&dma_desc_list);
|
|
|
|
INIT_LIST_HEAD(&sg_req_list);
|
|
|
|
|
|
|
|
dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
|
|
|
|
|
|
|
|
if (tdc->busy)
|
|
|
|
tegra_dma_terminate_all(dc);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&tdc->lock, flags);
|
|
|
|
list_splice_init(&tdc->pending_sg_req, &sg_req_list);
|
|
|
|
list_splice_init(&tdc->free_sg_req, &sg_req_list);
|
|
|
|
list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
|
|
|
|
INIT_LIST_HEAD(&tdc->cb_desc);
|
|
|
|
tdc->config_init = false;
|
2013-05-11 16:30:53 +00:00
|
|
|
tdc->isr_handler = NULL;
|
2012-06-06 05:25:27 +00:00
|
|
|
spin_unlock_irqrestore(&tdc->lock, flags);
|
|
|
|
|
|
|
|
while (!list_empty(&dma_desc_list)) {
|
|
|
|
dma_desc = list_first_entry(&dma_desc_list,
|
|
|
|
typeof(*dma_desc), node);
|
|
|
|
list_del(&dma_desc->node);
|
|
|
|
kfree(dma_desc);
|
|
|
|
}
|
|
|
|
|
|
|
|
while (!list_empty(&sg_req_list)) {
|
|
|
|
sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
|
|
|
|
list_del(&sg_req->node);
|
|
|
|
kfree(sg_req);
|
|
|
|
}
|
2015-11-13 16:39:38 +00:00
|
|
|
pm_runtime_put(tdma->dev);
|
2013-11-11 20:09:35 +00:00
|
|
|
|
|
|
|
tdc->slave_id = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
|
|
|
|
struct of_dma *ofdma)
|
|
|
|
{
|
|
|
|
struct tegra_dma *tdma = ofdma->of_dma_data;
|
|
|
|
struct dma_chan *chan;
|
|
|
|
struct tegra_dma_channel *tdc;
|
|
|
|
|
|
|
|
chan = dma_get_any_slave_channel(&tdma->dma_dev);
|
|
|
|
if (!chan)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
tdc = to_tegra_dma_chan(chan);
|
|
|
|
tdc->slave_id = dma_spec->args[0];
|
|
|
|
|
|
|
|
return chan;
|
2012-06-06 05:25:27 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Tegra20 specific DMA controller information */
|
2012-08-29 08:31:18 +00:00
|
|
|
static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
|
2012-06-06 05:25:27 +00:00
|
|
|
.nr_channels = 16,
|
2014-01-06 18:16:45 +00:00
|
|
|
.channel_reg_size = 0x20,
|
2012-06-06 05:25:27 +00:00
|
|
|
.max_dma_count = 1024UL * 64,
|
2013-01-06 16:22:02 +00:00
|
|
|
.support_channel_pause = false,
|
2014-01-06 18:16:45 +00:00
|
|
|
.support_separate_wcount_reg = false,
|
2012-06-06 05:25:27 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/* Tegra30 specific DMA controller information */
|
2012-08-29 08:31:18 +00:00
|
|
|
static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
|
2012-06-06 05:25:27 +00:00
|
|
|
.nr_channels = 32,
|
2014-01-06 18:16:45 +00:00
|
|
|
.channel_reg_size = 0x20,
|
2012-06-06 05:25:27 +00:00
|
|
|
.max_dma_count = 1024UL * 64,
|
2013-01-06 16:22:02 +00:00
|
|
|
.support_channel_pause = false,
|
2014-01-06 18:16:45 +00:00
|
|
|
.support_separate_wcount_reg = false,
|
2012-06-06 05:25:27 +00:00
|
|
|
};
|
|
|
|
|
2013-01-06 16:22:03 +00:00
|
|
|
/* Tegra114 specific DMA controller information */
|
|
|
|
static const struct tegra_dma_chip_data tegra114_dma_chip_data = {
|
|
|
|
.nr_channels = 32,
|
2014-01-06 18:16:45 +00:00
|
|
|
.channel_reg_size = 0x20,
|
2013-01-06 16:22:03 +00:00
|
|
|
.max_dma_count = 1024UL * 64,
|
|
|
|
.support_channel_pause = true,
|
2014-01-06 18:16:45 +00:00
|
|
|
.support_separate_wcount_reg = false,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Tegra148 specific DMA controller information */
|
|
|
|
static const struct tegra_dma_chip_data tegra148_dma_chip_data = {
|
|
|
|
.nr_channels = 32,
|
|
|
|
.channel_reg_size = 0x40,
|
|
|
|
.max_dma_count = 1024UL * 64,
|
|
|
|
.support_channel_pause = true,
|
|
|
|
.support_separate_wcount_reg = true,
|
2013-01-06 16:22:03 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
2012-12-21 23:09:59 +00:00
|
|
|
static const struct of_device_id tegra_dma_of_match[] = {
|
2012-06-06 05:25:27 +00:00
|
|
|
{
|
2014-01-06 18:16:45 +00:00
|
|
|
.compatible = "nvidia,tegra148-apbdma",
|
|
|
|
.data = &tegra148_dma_chip_data,
|
|
|
|
}, {
|
2013-01-06 16:22:03 +00:00
|
|
|
.compatible = "nvidia,tegra114-apbdma",
|
|
|
|
.data = &tegra114_dma_chip_data,
|
|
|
|
}, {
|
2012-07-02 08:22:08 +00:00
|
|
|
.compatible = "nvidia,tegra30-apbdma",
|
2012-06-06 05:25:27 +00:00
|
|
|
.data = &tegra30_dma_chip_data,
|
|
|
|
}, {
|
2012-07-02 08:22:08 +00:00
|
|
|
.compatible = "nvidia,tegra20-apbdma",
|
2012-06-06 05:25:27 +00:00
|
|
|
.data = &tegra20_dma_chip_data,
|
|
|
|
}, {
|
|
|
|
},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
|
|
|
|
|
2012-11-19 18:22:55 +00:00
|
|
|
static int tegra_dma_probe(struct platform_device *pdev)
|
2012-06-06 05:25:27 +00:00
|
|
|
{
|
|
|
|
struct resource *res;
|
|
|
|
struct tegra_dma *tdma;
|
|
|
|
int ret;
|
|
|
|
int i;
|
2012-08-29 08:23:07 +00:00
|
|
|
const struct tegra_dma_chip_data *cdata = NULL;
|
2013-03-11 22:30:26 +00:00
|
|
|
const struct of_device_id *match;
|
2012-06-06 05:25:27 +00:00
|
|
|
|
2013-03-11 22:30:26 +00:00
|
|
|
match = of_match_device(tegra_dma_of_match, &pdev->dev);
|
|
|
|
if (!match) {
|
|
|
|
dev_err(&pdev->dev, "Error: No device match found\n");
|
|
|
|
return -ENODEV;
|
2012-06-06 05:25:27 +00:00
|
|
|
}
|
2013-03-11 22:30:26 +00:00
|
|
|
cdata = match->data;
|
2012-06-06 05:25:27 +00:00
|
|
|
|
|
|
|
tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
|
|
|
|
sizeof(struct tegra_dma_channel), GFP_KERNEL);
|
|
|
|
if (!tdma) {
|
|
|
|
dev_err(&pdev->dev, "Error: memory allocation failed\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
tdma->dev = &pdev->dev;
|
|
|
|
tdma->chip_data = cdata;
|
|
|
|
platform_set_drvdata(pdev, tdma);
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2013-01-21 10:09:00 +00:00
|
|
|
tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
|
|
|
|
if (IS_ERR(tdma->base_addr))
|
|
|
|
return PTR_ERR(tdma->base_addr);
|
2012-06-06 05:25:27 +00:00
|
|
|
|
|
|
|
tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
|
|
|
|
if (IS_ERR(tdma->dma_clk)) {
|
|
|
|
dev_err(&pdev->dev, "Error: Missing controller clock\n");
|
|
|
|
return PTR_ERR(tdma->dma_clk);
|
|
|
|
}
|
|
|
|
|
2013-11-06 23:35:34 +00:00
|
|
|
tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
|
|
|
|
if (IS_ERR(tdma->rst)) {
|
|
|
|
dev_err(&pdev->dev, "Error: Missing reset\n");
|
|
|
|
return PTR_ERR(tdma->rst);
|
|
|
|
}
|
|
|
|
|
2012-06-06 05:25:27 +00:00
|
|
|
spin_lock_init(&tdma->global_lock);
|
|
|
|
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
2015-11-13 16:39:38 +00:00
|
|
|
if (!pm_runtime_enabled(&pdev->dev))
|
2012-06-06 05:25:27 +00:00
|
|
|
ret = tegra_dma_runtime_resume(&pdev->dev);
|
2015-11-13 16:39:38 +00:00
|
|
|
else
|
|
|
|
ret = pm_runtime_get_sync(&pdev->dev);
|
2012-06-06 05:25:27 +00:00
|
|
|
|
2012-07-20 08:01:08 +00:00
|
|
|
if (ret < 0) {
|
2015-11-13 16:39:38 +00:00
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return ret;
|
2012-07-20 08:01:08 +00:00
|
|
|
}
|
|
|
|
|
2012-06-06 05:25:27 +00:00
|
|
|
/* Reset DMA controller */
|
2013-11-06 23:35:34 +00:00
|
|
|
reset_control_assert(tdma->rst);
|
2012-06-06 05:25:27 +00:00
|
|
|
udelay(2);
|
2013-11-06 23:35:34 +00:00
|
|
|
reset_control_deassert(tdma->rst);
|
2012-06-06 05:25:27 +00:00
|
|
|
|
|
|
|
/* Enable global DMA registers */
|
|
|
|
tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
|
|
|
|
tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
|
|
|
|
tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
|
|
|
|
|
2015-11-13 16:39:38 +00:00
|
|
|
pm_runtime_put(&pdev->dev);
|
2012-07-20 08:01:08 +00:00
|
|
|
|
2012-06-06 05:25:27 +00:00
|
|
|
INIT_LIST_HEAD(&tdma->dma_dev.channels);
|
|
|
|
for (i = 0; i < cdata->nr_channels; i++) {
|
|
|
|
struct tegra_dma_channel *tdc = &tdma->channels[i];
|
|
|
|
|
2015-08-06 13:32:31 +00:00
|
|
|
tdc->chan_addr = tdma->base_addr +
|
|
|
|
TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
|
|
|
|
(i * cdata->channel_reg_size);
|
2012-06-06 05:25:27 +00:00
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
|
|
|
|
if (!res) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
|
|
|
|
goto err_irq;
|
|
|
|
}
|
|
|
|
tdc->irq = res->start;
|
2012-10-03 17:18:07 +00:00
|
|
|
snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i);
|
2012-06-06 05:25:27 +00:00
|
|
|
ret = devm_request_irq(&pdev->dev, tdc->irq,
|
2012-10-03 17:18:07 +00:00
|
|
|
tegra_dma_isr, 0, tdc->name, tdc);
|
2012-06-06 05:25:27 +00:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"request_irq failed with err %d channel %d\n",
|
2013-05-11 16:30:52 +00:00
|
|
|
ret, i);
|
2012-06-06 05:25:27 +00:00
|
|
|
goto err_irq;
|
|
|
|
}
|
|
|
|
|
|
|
|
tdc->dma_chan.device = &tdma->dma_dev;
|
|
|
|
dma_cookie_init(&tdc->dma_chan);
|
|
|
|
list_add_tail(&tdc->dma_chan.device_node,
|
|
|
|
&tdma->dma_dev.channels);
|
|
|
|
tdc->tdma = tdma;
|
|
|
|
tdc->id = i;
|
|
|
|
|
|
|
|
tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
|
|
|
|
(unsigned long)tdc);
|
|
|
|
spin_lock_init(&tdc->lock);
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&tdc->pending_sg_req);
|
|
|
|
INIT_LIST_HEAD(&tdc->free_sg_req);
|
|
|
|
INIT_LIST_HEAD(&tdc->free_dma_desc);
|
|
|
|
INIT_LIST_HEAD(&tdc->cb_desc);
|
|
|
|
}
|
|
|
|
|
|
|
|
dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
|
|
|
|
dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
|
2012-06-22 11:42:43 +00:00
|
|
|
dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
|
|
|
|
|
2015-08-06 13:32:33 +00:00
|
|
|
tdma->global_pause_count = 0;
|
2012-06-06 05:25:27 +00:00
|
|
|
tdma->dma_dev.dev = &pdev->dev;
|
|
|
|
tdma->dma_dev.device_alloc_chan_resources =
|
|
|
|
tegra_dma_alloc_chan_resources;
|
|
|
|
tdma->dma_dev.device_free_chan_resources =
|
|
|
|
tegra_dma_free_chan_resources;
|
|
|
|
tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
|
|
|
|
tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
|
2015-01-06 06:44:56 +00:00
|
|
|
tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
|
|
|
|
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
|
|
|
|
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
|
|
|
|
BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
|
|
|
|
tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
|
|
|
|
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
|
|
|
|
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
|
|
|
|
BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
|
|
|
|
tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
|
|
|
|
/*
|
|
|
|
* XXX The hardware appears to support
|
|
|
|
* DMA_RESIDUE_GRANULARITY_BURST-level reporting, but it's
|
|
|
|
* only used by this driver during tegra_dma_terminate_all()
|
|
|
|
*/
|
|
|
|
tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
|
2014-11-17 13:42:37 +00:00
|
|
|
tdma->dma_dev.device_config = tegra_dma_slave_config;
|
|
|
|
tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
|
2012-06-06 05:25:27 +00:00
|
|
|
tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
|
|
|
|
tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
|
|
|
|
|
|
|
|
ret = dma_async_device_register(&tdma->dma_dev);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"Tegra20 APB DMA driver registration failed %d\n", ret);
|
|
|
|
goto err_irq;
|
|
|
|
}
|
|
|
|
|
2013-11-11 20:09:35 +00:00
|
|
|
ret = of_dma_controller_register(pdev->dev.of_node,
|
|
|
|
tegra_dma_of_xlate, tdma);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"Tegra20 APB DMA OF registration failed %d\n", ret);
|
|
|
|
goto err_unregister_dma_dev;
|
|
|
|
}
|
|
|
|
|
2012-06-06 05:25:27 +00:00
|
|
|
dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
|
|
|
|
cdata->nr_channels);
|
|
|
|
return 0;
|
|
|
|
|
2013-11-11 20:09:35 +00:00
|
|
|
err_unregister_dma_dev:
|
|
|
|
dma_async_device_unregister(&tdma->dma_dev);
|
2012-06-06 05:25:27 +00:00
|
|
|
err_irq:
|
|
|
|
while (--i >= 0) {
|
|
|
|
struct tegra_dma_channel *tdc = &tdma->channels[i];
|
|
|
|
tasklet_kill(&tdc->tasklet);
|
|
|
|
}
|
|
|
|
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
|
|
tegra_dma_runtime_suspend(&pdev->dev);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-12-21 23:09:59 +00:00
|
|
|
static int tegra_dma_remove(struct platform_device *pdev)
|
2012-06-06 05:25:27 +00:00
|
|
|
{
|
|
|
|
struct tegra_dma *tdma = platform_get_drvdata(pdev);
|
|
|
|
int i;
|
|
|
|
struct tegra_dma_channel *tdc;
|
|
|
|
|
|
|
|
dma_async_device_unregister(&tdma->dma_dev);
|
|
|
|
|
|
|
|
for (i = 0; i < tdma->chip_data->nr_channels; ++i) {
|
|
|
|
tdc = &tdma->channels[i];
|
|
|
|
tasklet_kill(&tdc->tasklet);
|
|
|
|
}
|
|
|
|
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
|
|
tegra_dma_runtime_suspend(&pdev->dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_dma_runtime_suspend(struct device *dev)
|
|
|
|
{
|
2015-11-13 16:39:39 +00:00
|
|
|
struct tegra_dma *tdma = dev_get_drvdata(dev);
|
2012-06-06 05:25:27 +00:00
|
|
|
|
2012-06-25 06:31:31 +00:00
|
|
|
clk_disable_unprepare(tdma->dma_clk);
|
2012-06-06 05:25:27 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_dma_runtime_resume(struct device *dev)
|
|
|
|
{
|
2015-11-13 16:39:39 +00:00
|
|
|
struct tegra_dma *tdma = dev_get_drvdata(dev);
|
2012-06-06 05:25:27 +00:00
|
|
|
int ret;
|
|
|
|
|
2012-06-25 06:31:31 +00:00
|
|
|
ret = clk_prepare_enable(tdma->dma_clk);
|
2012-06-06 05:25:27 +00:00
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(dev, "clk_enable failed: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-04-24 09:54:27 +00:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
|
|
static int tegra_dma_pm_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct tegra_dma *tdma = dev_get_drvdata(dev);
|
|
|
|
int i;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Enable clock before accessing register */
|
2015-11-13 16:39:38 +00:00
|
|
|
ret = pm_runtime_get_sync(dev);
|
2013-04-24 09:54:27 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
|
|
|
|
for (i = 0; i < tdma->chip_data->nr_channels; i++) {
|
|
|
|
struct tegra_dma_channel *tdc = &tdma->channels[i];
|
|
|
|
struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
|
|
|
|
|
|
|
|
ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
|
|
|
|
ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
|
|
|
|
ch_reg->apb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBPTR);
|
|
|
|
ch_reg->ahb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBSEQ);
|
|
|
|
ch_reg->apb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBSEQ);
|
2015-11-13 16:39:40 +00:00
|
|
|
if (tdma->chip_data->support_separate_wcount_reg)
|
|
|
|
ch_reg->wcount = tdc_read(tdc,
|
|
|
|
TEGRA_APBDMA_CHAN_WCOUNT);
|
2013-04-24 09:54:27 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Disable clock */
|
2015-11-13 16:39:38 +00:00
|
|
|
pm_runtime_put(dev);
|
2013-04-24 09:54:27 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_dma_pm_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct tegra_dma *tdma = dev_get_drvdata(dev);
|
|
|
|
int i;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Enable clock before accessing register */
|
2015-11-13 16:39:38 +00:00
|
|
|
ret = pm_runtime_get_sync(dev);
|
2013-04-24 09:54:27 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);
|
|
|
|
tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
|
|
|
|
tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
|
|
|
|
|
|
|
|
for (i = 0; i < tdma->chip_data->nr_channels; i++) {
|
|
|
|
struct tegra_dma_channel *tdc = &tdma->channels[i];
|
|
|
|
struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
|
|
|
|
|
2015-11-13 16:39:40 +00:00
|
|
|
if (tdma->chip_data->support_separate_wcount_reg)
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
|
|
|
|
ch_reg->wcount);
|
2013-04-24 09:54:27 +00:00
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq);
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr);
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq);
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr);
|
|
|
|
tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
|
|
|
|
(ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Disable clock */
|
2015-11-13 16:39:38 +00:00
|
|
|
pm_runtime_put(dev);
|
2013-04-24 09:54:27 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-12-21 23:09:59 +00:00
|
|
|
static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
|
2015-11-13 16:39:38 +00:00
|
|
|
SET_RUNTIME_PM_OPS(tegra_dma_runtime_suspend, tegra_dma_runtime_resume,
|
|
|
|
NULL)
|
2013-04-24 09:54:27 +00:00
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
|
2012-06-06 05:25:27 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_driver tegra_dmac_driver = {
|
|
|
|
.driver = {
|
2012-07-02 08:22:08 +00:00
|
|
|
.name = "tegra-apbdma",
|
2012-06-06 05:25:27 +00:00
|
|
|
.pm = &tegra_dma_dev_pm_ops,
|
2013-03-11 22:30:26 +00:00
|
|
|
.of_match_table = tegra_dma_of_match,
|
2012-06-06 05:25:27 +00:00
|
|
|
},
|
|
|
|
.probe = tegra_dma_probe,
|
2012-11-19 18:20:04 +00:00
|
|
|
.remove = tegra_dma_remove,
|
2012-06-06 05:25:27 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(tegra_dmac_driver);
|
|
|
|
|
|
|
|
MODULE_ALIAS("platform:tegra20-apbdma");
|
|
|
|
MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
|
|
|
|
MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
|
|
|
|
MODULE_LICENSE("GPL v2");
|