2019-05-29 23:57:35 +00:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2016-09-12 18:54:20 +00:00
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/*
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* Copyright (C) 2016, Semihalf
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* Author: Tomasz Nowicki <tn@semihalf.com>
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*/
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#ifndef __ACPI_IORT_H__
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#define __ACPI_IORT_H__
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#include <linux/acpi.h>
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2016-09-12 18:32:21 +00:00
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#include <linux/fwnode.h>
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#include <linux/irqdomain.h>
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2016-09-12 18:54:20 +00:00
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2016-11-21 10:01:45 +00:00
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#define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL)
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#define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL)
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2019-03-26 15:17:50 +00:00
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/*
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* PMCG model identifiers for use in smmu pmu driver. Please note
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* that this is purely for the use of software and has nothing to
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* do with hardware or with IORT specification.
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*/
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#define IORT_SMMU_V3_PMCG_GENERIC 0x00000000 /* Generic SMMUv3 PMCG */
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2019-03-26 15:17:53 +00:00
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#define IORT_SMMU_V3_PMCG_HISI_HIP08 0x00000001 /* HiSilicon HIP08 PMCG */
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2023-08-14 12:40:12 +00:00
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#define IORT_SMMU_V3_PMCG_HISI_HIP09 0x00000002 /* HiSilicon HIP09 PMCG */
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2019-03-26 15:17:50 +00:00
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2018-02-13 15:20:50 +00:00
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int iort_register_domain_token(int trans_id, phys_addr_t base,
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struct fwnode_handle *fw_node);
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2016-09-12 18:32:21 +00:00
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void iort_deregister_domain_token(int trans_id);
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struct fwnode_handle *iort_find_domain_token(int trans_id);
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2023-05-16 20:05:08 +00:00
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int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id);
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2016-09-12 18:54:20 +00:00
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#ifdef CONFIG_ACPI_IORT
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2020-06-19 08:20:04 +00:00
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u32 iort_msi_map_id(struct device *dev, u32 id);
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2020-06-19 08:20:03 +00:00
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struct irq_domain *iort_get_device_domain(struct device *dev, u32 id,
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enum irq_domain_bus_token bus_token);
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2017-03-07 12:40:06 +00:00
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void acpi_configure_pmsi_domain(struct device *dev);
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2022-06-15 10:10:40 +00:00
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void iort_get_rmr_sids(struct fwnode_handle *iommu_fwnode,
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struct list_head *head);
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void iort_put_rmr_sids(struct fwnode_handle *iommu_fwnode,
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struct list_head *head);
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2016-11-21 10:01:48 +00:00
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/* IOMMU interface */
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2021-06-18 15:20:56 +00:00
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int iort_dma_get_ranges(struct device *dev, u64 *size);
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2021-06-18 15:20:57 +00:00
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int iort_iommu_configure_id(struct device *dev, const u32 *id_in);
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2022-06-15 10:10:38 +00:00
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void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head);
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arm64: mm: Set ZONE_DMA size based on early IORT scan
We recently introduced a 1 GB sized ZONE_DMA to cater for platforms
incorporating masters that can address less than 32 bits of DMA, in
particular the Raspberry Pi 4, which has 4 or 8 GB of DRAM, but has
peripherals that can only address up to 1 GB (and its PCIe host
bridge can only access the bottom 3 GB)
Instructing the DMA layer about these limitations is straight-forward,
even though we had to fix some issues regarding memory limits set in
the IORT for named components, and regarding the handling of ACPI _DMA
methods. However, the DMA layer also needs to be able to allocate
memory that is guaranteed to meet those DMA constraints, for bounce
buffering as well as allocating the backing for consistent mappings.
This is why the 1 GB ZONE_DMA was introduced recently. Unfortunately,
it turns out the having a 1 GB ZONE_DMA as well as a ZONE_DMA32 causes
problems with kdump, and potentially in other places where allocations
cannot cross zone boundaries. Therefore, we should avoid having two
separate DMA zones when possible.
So let's do an early scan of the IORT, and only create the ZONE_DMA
if we encounter any devices that need it. This puts the burden on
the firmware to describe such limitations in the IORT, which may be
redundant (and less precise) if _DMA methods are also being provided.
However, it should be noted that this situation is highly unusual for
arm64 ACPI machines. Also, the DMA subsystem still gives precedence to
the _DMA method if implemented, and so we will not lose the ability to
perform streaming DMA outside the ZONE_DMA if the _DMA method permits
it.
[nsaenz: unified implementation with DT's counterpart]
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Hanjun Guo <guohanjun@huawei.com>
Cc: Jeremy Linton <jeremy.linton@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Hanjun Guo <guohanjun@huawei.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/20201119175400.9995-7-nsaenzjulienne@suse.de
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-11-19 17:53:58 +00:00
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phys_addr_t acpi_iort_dma_get_max_cpu_address(void);
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2016-09-12 18:54:20 +00:00
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#else
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2020-06-19 08:20:04 +00:00
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static inline u32 iort_msi_map_id(struct device *dev, u32 id)
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{ return id; }
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2020-06-19 08:20:03 +00:00
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static inline struct irq_domain *iort_get_device_domain(
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struct device *dev, u32 id, enum irq_domain_bus_token bus_token)
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2016-09-12 18:32:21 +00:00
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{ return NULL; }
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2017-03-07 12:40:06 +00:00
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static inline void acpi_configure_pmsi_domain(struct device *dev) { }
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2022-06-15 10:10:40 +00:00
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static inline
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void iort_get_rmr_sids(struct fwnode_handle *iommu_fwnode, struct list_head *head) { }
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static inline
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void iort_put_rmr_sids(struct fwnode_handle *iommu_fwnode, struct list_head *head) { }
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2016-11-21 10:01:48 +00:00
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/* IOMMU interface */
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2021-06-18 15:20:56 +00:00
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static inline int iort_dma_get_ranges(struct device *dev, u64 *size)
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{ return -ENODEV; }
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2021-06-18 15:20:57 +00:00
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static inline int iort_iommu_configure_id(struct device *dev, const u32 *id_in)
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{ return -ENODEV; }
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2018-02-13 15:20:50 +00:00
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static inline
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2022-06-15 10:10:38 +00:00
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void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head)
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2022-06-15 10:10:37 +00:00
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{ }
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arm64: mm: Set ZONE_DMA size based on early IORT scan
We recently introduced a 1 GB sized ZONE_DMA to cater for platforms
incorporating masters that can address less than 32 bits of DMA, in
particular the Raspberry Pi 4, which has 4 or 8 GB of DRAM, but has
peripherals that can only address up to 1 GB (and its PCIe host
bridge can only access the bottom 3 GB)
Instructing the DMA layer about these limitations is straight-forward,
even though we had to fix some issues regarding memory limits set in
the IORT for named components, and regarding the handling of ACPI _DMA
methods. However, the DMA layer also needs to be able to allocate
memory that is guaranteed to meet those DMA constraints, for bounce
buffering as well as allocating the backing for consistent mappings.
This is why the 1 GB ZONE_DMA was introduced recently. Unfortunately,
it turns out the having a 1 GB ZONE_DMA as well as a ZONE_DMA32 causes
problems with kdump, and potentially in other places where allocations
cannot cross zone boundaries. Therefore, we should avoid having two
separate DMA zones when possible.
So let's do an early scan of the IORT, and only create the ZONE_DMA
if we encounter any devices that need it. This puts the burden on
the firmware to describe such limitations in the IORT, which may be
redundant (and less precise) if _DMA methods are also being provided.
However, it should be noted that this situation is highly unusual for
arm64 ACPI machines. Also, the DMA subsystem still gives precedence to
the _DMA method if implemented, and so we will not lose the ability to
perform streaming DMA outside the ZONE_DMA if the _DMA method permits
it.
[nsaenz: unified implementation with DT's counterpart]
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Hanjun Guo <guohanjun@huawei.com>
Cc: Jeremy Linton <jeremy.linton@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Hanjun Guo <guohanjun@huawei.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/20201119175400.9995-7-nsaenzjulienne@suse.de
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-11-19 17:53:58 +00:00
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static inline phys_addr_t acpi_iort_dma_get_max_cpu_address(void)
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{ return PHYS_ADDR_MAX; }
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2016-09-12 18:54:20 +00:00
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#endif
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#endif /* __ACPI_IORT_H__ */
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