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0242737dc4
Some HiSilicon SMMU PMCG suffers the erratum 162001900 that the PMU disable control sometimes fail to disable the counters. This will lead to error or inaccurate data since before we enable the counters the counter's still counting for the event used in last perf session. This patch tries to fix this by hardening the global disable process. Before disable the PMU, writing an invalid event type (0xffff) to focibly stop the counters. Correspondingly restore each events on pmu::pmu_enable(). Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Link: https://lore.kernel.org/r/20230814124012.58013-1-yangyicong@huawei.com Signed-off-by: Will Deacon <will@kernel.org>
70 lines
2.6 KiB
C
70 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2016, Semihalf
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* Author: Tomasz Nowicki <tn@semihalf.com>
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*/
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#ifndef __ACPI_IORT_H__
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#define __ACPI_IORT_H__
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#include <linux/acpi.h>
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#include <linux/fwnode.h>
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#include <linux/irqdomain.h>
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#define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL)
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#define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL)
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/*
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* PMCG model identifiers for use in smmu pmu driver. Please note
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* that this is purely for the use of software and has nothing to
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* do with hardware or with IORT specification.
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*/
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#define IORT_SMMU_V3_PMCG_GENERIC 0x00000000 /* Generic SMMUv3 PMCG */
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#define IORT_SMMU_V3_PMCG_HISI_HIP08 0x00000001 /* HiSilicon HIP08 PMCG */
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#define IORT_SMMU_V3_PMCG_HISI_HIP09 0x00000002 /* HiSilicon HIP09 PMCG */
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int iort_register_domain_token(int trans_id, phys_addr_t base,
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struct fwnode_handle *fw_node);
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void iort_deregister_domain_token(int trans_id);
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struct fwnode_handle *iort_find_domain_token(int trans_id);
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int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id);
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#ifdef CONFIG_ACPI_IORT
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u32 iort_msi_map_id(struct device *dev, u32 id);
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struct irq_domain *iort_get_device_domain(struct device *dev, u32 id,
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enum irq_domain_bus_token bus_token);
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void acpi_configure_pmsi_domain(struct device *dev);
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void iort_get_rmr_sids(struct fwnode_handle *iommu_fwnode,
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struct list_head *head);
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void iort_put_rmr_sids(struct fwnode_handle *iommu_fwnode,
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struct list_head *head);
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/* IOMMU interface */
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int iort_dma_get_ranges(struct device *dev, u64 *size);
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int iort_iommu_configure_id(struct device *dev, const u32 *id_in);
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void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head);
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phys_addr_t acpi_iort_dma_get_max_cpu_address(void);
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#else
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static inline u32 iort_msi_map_id(struct device *dev, u32 id)
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{ return id; }
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static inline struct irq_domain *iort_get_device_domain(
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struct device *dev, u32 id, enum irq_domain_bus_token bus_token)
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{ return NULL; }
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static inline void acpi_configure_pmsi_domain(struct device *dev) { }
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static inline
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void iort_get_rmr_sids(struct fwnode_handle *iommu_fwnode, struct list_head *head) { }
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static inline
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void iort_put_rmr_sids(struct fwnode_handle *iommu_fwnode, struct list_head *head) { }
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/* IOMMU interface */
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static inline int iort_dma_get_ranges(struct device *dev, u64 *size)
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{ return -ENODEV; }
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static inline int iort_iommu_configure_id(struct device *dev, const u32 *id_in)
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{ return -ENODEV; }
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static inline
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void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head)
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{ }
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static inline phys_addr_t acpi_iort_dma_get_max_cpu_address(void)
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{ return PHYS_ADDR_MAX; }
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#endif
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#endif /* __ACPI_IORT_H__ */
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