2012-05-11 20:56:09 +00:00
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/* linux/drivers/iommu/exynos_iommu.c
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifdef CONFIG_EXYNOS_IOMMU_DEBUG
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#define DEBUG
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#endif
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/mm.h>
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#include <linux/iommu.h>
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#include <linux/errno.h>
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#include <linux/list.h>
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#include <linux/memblock.h>
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#include <linux/export.h>
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#include <asm/cacheflush.h>
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#include <asm/pgtable.h>
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/* We does not consider super section mapping (16MB) */
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#define SECT_ORDER 20
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#define LPAGE_ORDER 16
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#define SPAGE_ORDER 12
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#define SECT_SIZE (1 << SECT_ORDER)
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#define LPAGE_SIZE (1 << LPAGE_ORDER)
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#define SPAGE_SIZE (1 << SPAGE_ORDER)
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#define SECT_MASK (~(SECT_SIZE - 1))
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#define LPAGE_MASK (~(LPAGE_SIZE - 1))
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#define SPAGE_MASK (~(SPAGE_SIZE - 1))
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#define lv1ent_fault(sent) (((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
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#define lv1ent_page(sent) ((*(sent) & 3) == 1)
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#define lv1ent_section(sent) ((*(sent) & 3) == 2)
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#define lv2ent_fault(pent) ((*(pent) & 3) == 0)
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#define lv2ent_small(pent) ((*(pent) & 2) == 2)
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#define lv2ent_large(pent) ((*(pent) & 3) == 1)
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#define section_phys(sent) (*(sent) & SECT_MASK)
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#define section_offs(iova) ((iova) & 0xFFFFF)
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#define lpage_phys(pent) (*(pent) & LPAGE_MASK)
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#define lpage_offs(iova) ((iova) & 0xFFFF)
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#define spage_phys(pent) (*(pent) & SPAGE_MASK)
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#define spage_offs(iova) ((iova) & 0xFFF)
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#define lv1ent_offset(iova) ((iova) >> SECT_ORDER)
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#define lv2ent_offset(iova) (((iova) & 0xFF000) >> SPAGE_ORDER)
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#define NUM_LV1ENTRIES 4096
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#define NUM_LV2ENTRIES 256
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#define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
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#define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
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#define lv2table_base(sent) (*(sent) & 0xFFFFFC00)
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#define mk_lv1ent_sect(pa) ((pa) | 2)
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#define mk_lv1ent_page(pa) ((pa) | 1)
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#define mk_lv2ent_lpage(pa) ((pa) | 1)
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#define mk_lv2ent_spage(pa) ((pa) | 2)
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#define CTRL_ENABLE 0x5
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#define CTRL_BLOCK 0x7
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#define CTRL_DISABLE 0x0
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#define REG_MMU_CTRL 0x000
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#define REG_MMU_CFG 0x004
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#define REG_MMU_STATUS 0x008
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#define REG_MMU_FLUSH 0x00C
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#define REG_MMU_FLUSH_ENTRY 0x010
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#define REG_PT_BASE_ADDR 0x014
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#define REG_INT_STATUS 0x018
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#define REG_INT_CLEAR 0x01C
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#define REG_PAGE_FAULT_ADDR 0x024
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#define REG_AW_FAULT_ADDR 0x028
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#define REG_AR_FAULT_ADDR 0x02C
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#define REG_DEFAULT_SLAVE_ADDR 0x030
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#define REG_MMU_VERSION 0x034
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#define REG_PB0_SADDR 0x04C
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#define REG_PB0_EADDR 0x050
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#define REG_PB1_SADDR 0x054
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#define REG_PB1_EADDR 0x058
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2014-05-12 06:14:48 +00:00
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static struct kmem_cache *lv2table_kmem_cache;
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2012-05-11 20:56:09 +00:00
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static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
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{
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return pgtable + lv1ent_offset(iova);
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}
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static unsigned long *page_entry(unsigned long *sent, unsigned long iova)
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{
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2014-05-12 06:14:46 +00:00
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return (unsigned long *)phys_to_virt(
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lv2table_base(sent)) + lv2ent_offset(iova);
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2012-05-11 20:56:09 +00:00
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}
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enum exynos_sysmmu_inttype {
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SYSMMU_PAGEFAULT,
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SYSMMU_AR_MULTIHIT,
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SYSMMU_AW_MULTIHIT,
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SYSMMU_BUSERROR,
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SYSMMU_AR_SECURITY,
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SYSMMU_AR_ACCESS,
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SYSMMU_AW_SECURITY,
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SYSMMU_AW_PROTECTION, /* 7 */
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SYSMMU_FAULT_UNKNOWN,
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SYSMMU_FAULTS_NUM
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};
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/*
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* @itype: type of fault.
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* @pgtable_base: the physical address of page table base. This is 0 if @itype
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* is SYSMMU_BUSERROR.
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* @fault_addr: the device (virtual) address that the System MMU tried to
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* translated. This is 0 if @itype is SYSMMU_BUSERROR.
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*/
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typedef int (*sysmmu_fault_handler_t)(enum exynos_sysmmu_inttype itype,
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2014-05-12 06:14:46 +00:00
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phys_addr_t pgtable_base, unsigned long fault_addr);
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2012-05-11 20:56:09 +00:00
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static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
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REG_PAGE_FAULT_ADDR,
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REG_AR_FAULT_ADDR,
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REG_AW_FAULT_ADDR,
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REG_DEFAULT_SLAVE_ADDR,
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REG_AR_FAULT_ADDR,
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REG_AR_FAULT_ADDR,
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REG_AW_FAULT_ADDR,
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REG_AW_FAULT_ADDR
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};
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static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
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"PAGE FAULT",
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"AR MULTI-HIT FAULT",
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"AW MULTI-HIT FAULT",
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"BUS ERROR",
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"AR SECURITY PROTECTION FAULT",
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"AR ACCESS PROTECTION FAULT",
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"AW SECURITY PROTECTION FAULT",
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"AW ACCESS PROTECTION FAULT",
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"UNKNOWN FAULT"
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};
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struct exynos_iommu_domain {
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struct list_head clients; /* list of sysmmu_drvdata.node */
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unsigned long *pgtable; /* lv1 page table, 16KB */
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short *lv2entcnt; /* free lv2 entry counter for each section */
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spinlock_t lock; /* lock for this structure */
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spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
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};
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struct sysmmu_drvdata {
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struct list_head node; /* entry of exynos_iommu_domain.clients */
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struct device *sysmmu; /* System MMU's device descriptor */
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struct device *dev; /* Owner of system MMU */
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2014-05-12 06:14:46 +00:00
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void __iomem *sfrbase;
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struct clk *clk;
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2014-05-12 06:14:55 +00:00
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struct clk *clk_master;
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2012-05-11 20:56:09 +00:00
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int activations;
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rwlock_t lock;
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struct iommu_domain *domain;
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sysmmu_fault_handler_t fault_handler;
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2014-05-12 06:14:46 +00:00
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phys_addr_t pgtable;
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2012-05-11 20:56:09 +00:00
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};
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static bool set_sysmmu_active(struct sysmmu_drvdata *data)
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{
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/* return true if the System MMU was not active previously
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and it needs to be initialized */
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return ++data->activations == 1;
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}
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static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
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{
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/* return true if the System MMU is needed to be disabled */
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BUG_ON(data->activations < 1);
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return --data->activations == 0;
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}
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static bool is_sysmmu_active(struct sysmmu_drvdata *data)
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{
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return data->activations > 0;
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}
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static void sysmmu_unblock(void __iomem *sfrbase)
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{
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__raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL);
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}
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static bool sysmmu_block(void __iomem *sfrbase)
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{
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int i = 120;
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__raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL);
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while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1))
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--i;
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if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) {
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sysmmu_unblock(sfrbase);
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return false;
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}
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return true;
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}
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static void __sysmmu_tlb_invalidate(void __iomem *sfrbase)
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{
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__raw_writel(0x1, sfrbase + REG_MMU_FLUSH);
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}
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static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase,
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2014-05-12 06:14:49 +00:00
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unsigned long iova, unsigned int num_inv)
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2012-05-11 20:56:09 +00:00
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{
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2014-05-12 06:14:49 +00:00
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unsigned int i;
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for (i = 0; i < num_inv; i++) {
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__raw_writel((iova & SPAGE_MASK) | 1,
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sfrbase + REG_MMU_FLUSH_ENTRY);
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iova += SPAGE_SIZE;
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}
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2012-05-11 20:56:09 +00:00
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}
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static void __sysmmu_set_ptbase(void __iomem *sfrbase,
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unsigned long pgd)
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{
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__raw_writel(0x1, sfrbase + REG_MMU_CFG); /* 16KB LV1, LRU */
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__raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR);
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__sysmmu_tlb_invalidate(sfrbase);
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}
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static void __set_fault_handler(struct sysmmu_drvdata *data,
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sysmmu_fault_handler_t handler)
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{
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unsigned long flags;
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write_lock_irqsave(&data->lock, flags);
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data->fault_handler = handler;
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write_unlock_irqrestore(&data->lock, flags);
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}
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void exynos_sysmmu_set_fault_handler(struct device *dev,
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sysmmu_fault_handler_t handler)
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{
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struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
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__set_fault_handler(data, handler);
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}
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static int default_fault_handler(enum exynos_sysmmu_inttype itype,
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2014-05-12 06:14:46 +00:00
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phys_addr_t pgtable_base, unsigned long fault_addr)
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2012-05-11 20:56:09 +00:00
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{
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unsigned long *ent;
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if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
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itype = SYSMMU_FAULT_UNKNOWN;
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2014-05-12 06:14:46 +00:00
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pr_err("%s occurred at 0x%lx(Page table base: %pa)\n",
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sysmmu_fault_name[itype], fault_addr, &pgtable_base);
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2012-05-11 20:56:09 +00:00
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2014-05-12 06:14:46 +00:00
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ent = section_entry(phys_to_virt(pgtable_base), fault_addr);
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2012-05-11 20:56:09 +00:00
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pr_err("\tLv1 entry: 0x%lx\n", *ent);
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if (lv1ent_page(ent)) {
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ent = page_entry(ent, fault_addr);
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pr_err("\t Lv2 entry: 0x%lx\n", *ent);
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}
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pr_err("Generating Kernel OOPS... because it is unrecoverable.\n");
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BUG();
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return 0;
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}
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static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
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{
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/* SYSMMU is in blocked when interrupt occurred. */
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struct sysmmu_drvdata *data = dev_id;
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enum exynos_sysmmu_inttype itype;
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unsigned long addr = -1;
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2014-05-12 06:14:46 +00:00
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int ret = -ENOSYS;
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2012-05-11 20:56:09 +00:00
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read_lock(&data->lock);
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WARN_ON(!is_sysmmu_active(data));
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2014-05-12 06:14:55 +00:00
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if (!IS_ERR(data->clk_master))
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clk_enable(data->clk_master);
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2014-05-12 06:14:46 +00:00
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itype = (enum exynos_sysmmu_inttype)
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__ffs(__raw_readl(data->sfrbase + REG_INT_STATUS));
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if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
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2012-05-11 20:56:09 +00:00
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itype = SYSMMU_FAULT_UNKNOWN;
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2014-05-12 06:14:46 +00:00
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else
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addr = __raw_readl(data->sfrbase + fault_reg_offset[itype]);
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2012-05-11 20:56:09 +00:00
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if (data->domain)
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2014-05-12 06:14:46 +00:00
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ret = report_iommu_fault(data->domain, data->dev, addr, itype);
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2012-05-11 20:56:09 +00:00
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if ((ret == -ENOSYS) && data->fault_handler) {
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unsigned long base = data->pgtable;
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if (itype != SYSMMU_FAULT_UNKNOWN)
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2014-05-12 06:14:46 +00:00
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base = __raw_readl(data->sfrbase + REG_PT_BASE_ADDR);
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2012-05-11 20:56:09 +00:00
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ret = data->fault_handler(itype, base, addr);
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}
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if (!ret && (itype != SYSMMU_FAULT_UNKNOWN))
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2014-05-12 06:14:46 +00:00
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__raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR);
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2012-05-11 20:56:09 +00:00
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else
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2014-05-12 06:14:53 +00:00
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dev_dbg(data->sysmmu, "%s is not handled.\n",
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sysmmu_fault_name[itype]);
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2012-05-11 20:56:09 +00:00
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if (itype != SYSMMU_FAULT_UNKNOWN)
|
2014-05-12 06:14:46 +00:00
|
|
|
sysmmu_unblock(data->sfrbase);
|
2012-05-11 20:56:09 +00:00
|
|
|
|
2014-05-12 06:14:55 +00:00
|
|
|
if (!IS_ERR(data->clk_master))
|
|
|
|
clk_disable(data->clk_master);
|
|
|
|
|
2012-05-11 20:56:09 +00:00
|
|
|
read_unlock(&data->lock);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool __exynos_sysmmu_disable(struct sysmmu_drvdata *data)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
bool disabled = false;
|
|
|
|
|
|
|
|
write_lock_irqsave(&data->lock, flags);
|
|
|
|
|
|
|
|
if (!set_sysmmu_inactive(data))
|
|
|
|
goto finish;
|
|
|
|
|
2014-05-12 06:14:55 +00:00
|
|
|
if (!IS_ERR(data->clk_master))
|
|
|
|
clk_enable(data->clk_master);
|
|
|
|
|
2014-05-12 06:14:46 +00:00
|
|
|
__raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
|
2012-05-11 20:56:09 +00:00
|
|
|
|
2014-05-12 06:14:54 +00:00
|
|
|
clk_disable(data->clk);
|
2014-05-12 06:14:55 +00:00
|
|
|
if (!IS_ERR(data->clk_master))
|
|
|
|
clk_disable(data->clk_master);
|
2012-05-11 20:56:09 +00:00
|
|
|
|
|
|
|
disabled = true;
|
|
|
|
data->pgtable = 0;
|
|
|
|
data->domain = NULL;
|
|
|
|
finish:
|
|
|
|
write_unlock_irqrestore(&data->lock, flags);
|
|
|
|
|
|
|
|
if (disabled)
|
2014-05-12 06:14:53 +00:00
|
|
|
dev_dbg(data->sysmmu, "Disabled\n");
|
2012-05-11 20:56:09 +00:00
|
|
|
else
|
2014-05-12 06:14:53 +00:00
|
|
|
dev_dbg(data->sysmmu, "%d times left to be disabled\n",
|
|
|
|
data->activations);
|
2012-05-11 20:56:09 +00:00
|
|
|
|
|
|
|
return disabled;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* __exynos_sysmmu_enable: Enables System MMU
|
|
|
|
*
|
|
|
|
* returns -error if an error occurred and System MMU is not enabled,
|
|
|
|
* 0 if the System MMU has been just enabled and 1 if System MMU was already
|
|
|
|
* enabled before.
|
|
|
|
*/
|
|
|
|
static int __exynos_sysmmu_enable(struct sysmmu_drvdata *data,
|
|
|
|
unsigned long pgtable, struct iommu_domain *domain)
|
|
|
|
{
|
2014-05-12 06:14:46 +00:00
|
|
|
int ret = 0;
|
2012-05-11 20:56:09 +00:00
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
write_lock_irqsave(&data->lock, flags);
|
|
|
|
|
|
|
|
if (!set_sysmmu_active(data)) {
|
|
|
|
if (WARN_ON(pgtable != data->pgtable)) {
|
|
|
|
ret = -EBUSY;
|
|
|
|
set_sysmmu_inactive(data);
|
|
|
|
} else {
|
|
|
|
ret = 1;
|
|
|
|
}
|
|
|
|
|
2014-05-12 06:14:53 +00:00
|
|
|
dev_dbg(data->sysmmu, "Already enabled\n");
|
2012-05-11 20:56:09 +00:00
|
|
|
goto finish;
|
|
|
|
}
|
|
|
|
|
|
|
|
data->pgtable = pgtable;
|
|
|
|
|
2014-05-12 06:14:55 +00:00
|
|
|
if (!IS_ERR(data->clk_master))
|
|
|
|
clk_enable(data->clk_master);
|
|
|
|
clk_enable(data->clk);
|
|
|
|
|
2014-05-12 06:14:46 +00:00
|
|
|
__sysmmu_set_ptbase(data->sfrbase, pgtable);
|
2012-05-11 20:56:09 +00:00
|
|
|
|
2014-05-12 06:14:46 +00:00
|
|
|
__raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
|
|
|
|
|
2014-05-12 06:14:55 +00:00
|
|
|
if (!IS_ERR(data->clk_master))
|
|
|
|
clk_disable(data->clk_master);
|
|
|
|
|
2012-05-11 20:56:09 +00:00
|
|
|
data->domain = domain;
|
|
|
|
|
2014-05-12 06:14:53 +00:00
|
|
|
dev_dbg(data->sysmmu, "Enabled\n");
|
2012-05-11 20:56:09 +00:00
|
|
|
finish:
|
|
|
|
write_unlock_irqrestore(&data->lock, flags);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int exynos_sysmmu_enable(struct device *dev, unsigned long pgtable)
|
|
|
|
{
|
|
|
|
struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
BUG_ON(!memblock_is_memory(pgtable));
|
|
|
|
|
|
|
|
ret = pm_runtime_get_sync(data->sysmmu);
|
|
|
|
if (ret < 0) {
|
2014-05-12 06:14:53 +00:00
|
|
|
dev_dbg(data->sysmmu, "Failed to enable\n");
|
2012-05-11 20:56:09 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = __exynos_sysmmu_enable(data, pgtable, NULL);
|
|
|
|
if (WARN_ON(ret < 0)) {
|
|
|
|
pm_runtime_put(data->sysmmu);
|
2014-05-12 06:14:53 +00:00
|
|
|
dev_err(data->sysmmu, "Already enabled with page table %#x\n",
|
|
|
|
data->pgtable);
|
2012-05-11 20:56:09 +00:00
|
|
|
} else {
|
|
|
|
data->dev = dev;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-02-06 08:25:17 +00:00
|
|
|
static bool exynos_sysmmu_disable(struct device *dev)
|
2012-05-11 20:56:09 +00:00
|
|
|
{
|
|
|
|
struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
|
|
|
|
bool disabled;
|
|
|
|
|
|
|
|
disabled = __exynos_sysmmu_disable(data);
|
|
|
|
pm_runtime_put(data->sysmmu);
|
|
|
|
|
|
|
|
return disabled;
|
|
|
|
}
|
|
|
|
|
2014-05-12 06:14:49 +00:00
|
|
|
static void sysmmu_tlb_invalidate_entry(struct device *dev, unsigned long iova,
|
|
|
|
size_t size)
|
2012-05-11 20:56:09 +00:00
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
|
|
|
|
|
|
|
|
read_lock_irqsave(&data->lock, flags);
|
|
|
|
|
|
|
|
if (is_sysmmu_active(data)) {
|
2014-05-12 06:14:49 +00:00
|
|
|
unsigned int maj;
|
|
|
|
unsigned int num_inv = 1;
|
2014-05-12 06:14:55 +00:00
|
|
|
|
|
|
|
if (!IS_ERR(data->clk_master))
|
|
|
|
clk_enable(data->clk_master);
|
|
|
|
|
2014-05-12 06:14:49 +00:00
|
|
|
maj = __raw_readl(data->sfrbase + REG_MMU_VERSION);
|
|
|
|
/*
|
|
|
|
* L2TLB invalidation required
|
|
|
|
* 4KB page: 1 invalidation
|
|
|
|
* 64KB page: 16 invalidation
|
|
|
|
* 1MB page: 64 invalidation
|
|
|
|
* because it is set-associative TLB
|
|
|
|
* with 8-way and 64 sets.
|
|
|
|
* 1MB page can be cached in one of all sets.
|
|
|
|
* 64KB page can be one of 16 consecutive sets.
|
|
|
|
*/
|
|
|
|
if ((maj >> 28) == 2) /* major version number */
|
|
|
|
num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
|
|
|
|
|
2014-05-12 06:14:46 +00:00
|
|
|
if (sysmmu_block(data->sfrbase)) {
|
|
|
|
__sysmmu_tlb_invalidate_entry(
|
2014-05-12 06:14:49 +00:00
|
|
|
data->sfrbase, iova, num_inv);
|
2014-05-12 06:14:46 +00:00
|
|
|
sysmmu_unblock(data->sfrbase);
|
2012-05-11 20:56:09 +00:00
|
|
|
}
|
2014-05-12 06:14:55 +00:00
|
|
|
if (!IS_ERR(data->clk_master))
|
|
|
|
clk_disable(data->clk_master);
|
2012-05-11 20:56:09 +00:00
|
|
|
} else {
|
2014-05-12 06:14:53 +00:00
|
|
|
dev_dbg(data->sysmmu, "Disabled. Skipping invalidating TLB.\n");
|
2012-05-11 20:56:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
read_unlock_irqrestore(&data->lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
void exynos_sysmmu_tlb_invalidate(struct device *dev)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
|
|
|
|
|
|
|
|
read_lock_irqsave(&data->lock, flags);
|
|
|
|
|
|
|
|
if (is_sysmmu_active(data)) {
|
2014-05-12 06:14:55 +00:00
|
|
|
if (!IS_ERR(data->clk_master))
|
|
|
|
clk_enable(data->clk_master);
|
2014-05-12 06:14:46 +00:00
|
|
|
if (sysmmu_block(data->sfrbase)) {
|
|
|
|
__sysmmu_tlb_invalidate(data->sfrbase);
|
|
|
|
sysmmu_unblock(data->sfrbase);
|
2012-05-11 20:56:09 +00:00
|
|
|
}
|
2014-05-12 06:14:55 +00:00
|
|
|
if (!IS_ERR(data->clk_master))
|
|
|
|
clk_disable(data->clk_master);
|
2012-05-11 20:56:09 +00:00
|
|
|
} else {
|
2014-05-12 06:14:53 +00:00
|
|
|
dev_dbg(data->sysmmu, "Disabled. Skipping invalidating TLB.\n");
|
2012-05-11 20:56:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
read_unlock_irqrestore(&data->lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int exynos_sysmmu_probe(struct platform_device *pdev)
|
|
|
|
{
|
2014-05-12 06:14:54 +00:00
|
|
|
int irq, ret;
|
2014-05-12 06:14:46 +00:00
|
|
|
struct device *dev = &pdev->dev;
|
2012-05-11 20:56:09 +00:00
|
|
|
struct sysmmu_drvdata *data;
|
2014-05-12 06:14:46 +00:00
|
|
|
struct resource *res;
|
2012-05-11 20:56:09 +00:00
|
|
|
|
2014-05-12 06:14:54 +00:00
|
|
|
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
|
|
|
if (!data)
|
|
|
|
return -ENOMEM;
|
2012-05-11 20:56:09 +00:00
|
|
|
|
2014-05-12 06:14:46 +00:00
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2014-05-12 06:14:54 +00:00
|
|
|
data->sfrbase = devm_ioremap_resource(dev, res);
|
|
|
|
if (IS_ERR(data->sfrbase))
|
|
|
|
return PTR_ERR(data->sfrbase);
|
2012-05-11 20:56:09 +00:00
|
|
|
|
2014-05-12 06:14:54 +00:00
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq <= 0) {
|
2014-05-12 06:14:46 +00:00
|
|
|
dev_dbg(dev, "Unable to find IRQ resource\n");
|
2014-05-12 06:14:54 +00:00
|
|
|
return irq;
|
2012-05-11 20:56:09 +00:00
|
|
|
}
|
|
|
|
|
2014-05-12 06:14:54 +00:00
|
|
|
ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
|
2014-05-12 06:14:46 +00:00
|
|
|
dev_name(dev), data);
|
|
|
|
if (ret) {
|
2014-05-12 06:14:54 +00:00
|
|
|
dev_err(dev, "Unabled to register handler of irq %d\n", irq);
|
|
|
|
return ret;
|
2012-05-11 20:56:09 +00:00
|
|
|
}
|
|
|
|
|
2014-05-12 06:14:54 +00:00
|
|
|
data->clk = devm_clk_get(dev, "sysmmu");
|
|
|
|
if (IS_ERR(data->clk)) {
|
|
|
|
dev_err(dev, "Failed to get clock!\n");
|
|
|
|
return PTR_ERR(data->clk);
|
|
|
|
} else {
|
|
|
|
ret = clk_prepare(data->clk);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to prepare clk\n");
|
|
|
|
return ret;
|
|
|
|
}
|
2012-05-11 20:56:09 +00:00
|
|
|
}
|
|
|
|
|
2014-05-12 06:14:55 +00:00
|
|
|
data->clk_master = devm_clk_get(dev, "master");
|
|
|
|
if (!IS_ERR(data->clk_master)) {
|
|
|
|
ret = clk_prepare(data->clk_master);
|
|
|
|
if (ret) {
|
|
|
|
clk_unprepare(data->clk);
|
|
|
|
dev_err(dev, "Failed to prepare master's clk\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-05-11 20:56:09 +00:00
|
|
|
data->sysmmu = dev;
|
|
|
|
rwlock_init(&data->lock);
|
|
|
|
INIT_LIST_HEAD(&data->node);
|
|
|
|
|
|
|
|
__set_fault_handler(data, &default_fault_handler);
|
|
|
|
|
2014-05-12 06:14:46 +00:00
|
|
|
platform_set_drvdata(pdev, data);
|
|
|
|
|
2014-05-12 06:14:52 +00:00
|
|
|
pm_runtime_enable(dev);
|
2012-05-11 20:56:09 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver exynos_sysmmu_driver = {
|
|
|
|
.probe = exynos_sysmmu_probe,
|
|
|
|
.driver = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.name = "exynos-sysmmu",
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static inline void pgtable_flush(void *vastart, void *vaend)
|
|
|
|
{
|
|
|
|
dmac_flush_range(vastart, vaend);
|
|
|
|
outer_flush_range(virt_to_phys(vastart),
|
|
|
|
virt_to_phys(vaend));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int exynos_iommu_domain_init(struct iommu_domain *domain)
|
|
|
|
{
|
|
|
|
struct exynos_iommu_domain *priv;
|
|
|
|
|
|
|
|
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
|
|
|
if (!priv)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
priv->pgtable = (unsigned long *)__get_free_pages(
|
|
|
|
GFP_KERNEL | __GFP_ZERO, 2);
|
|
|
|
if (!priv->pgtable)
|
|
|
|
goto err_pgtable;
|
|
|
|
|
|
|
|
priv->lv2entcnt = (short *)__get_free_pages(
|
|
|
|
GFP_KERNEL | __GFP_ZERO, 1);
|
|
|
|
if (!priv->lv2entcnt)
|
|
|
|
goto err_counter;
|
|
|
|
|
|
|
|
pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
|
|
|
|
|
|
|
|
spin_lock_init(&priv->lock);
|
|
|
|
spin_lock_init(&priv->pgtablelock);
|
|
|
|
INIT_LIST_HEAD(&priv->clients);
|
|
|
|
|
2012-08-01 09:05:17 +00:00
|
|
|
domain->geometry.aperture_start = 0;
|
|
|
|
domain->geometry.aperture_end = ~0UL;
|
|
|
|
domain->geometry.force_aperture = true;
|
2012-07-11 10:41:10 +00:00
|
|
|
|
2012-05-11 20:56:09 +00:00
|
|
|
domain->priv = priv;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_counter:
|
|
|
|
free_pages((unsigned long)priv->pgtable, 2);
|
|
|
|
err_pgtable:
|
|
|
|
kfree(priv);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void exynos_iommu_domain_destroy(struct iommu_domain *domain)
|
|
|
|
{
|
|
|
|
struct exynos_iommu_domain *priv = domain->priv;
|
|
|
|
struct sysmmu_drvdata *data;
|
|
|
|
unsigned long flags;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
WARN_ON(!list_empty(&priv->clients));
|
|
|
|
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
|
|
|
|
list_for_each_entry(data, &priv->clients, node) {
|
|
|
|
while (!exynos_sysmmu_disable(data->dev))
|
|
|
|
; /* until System MMU is actually disabled */
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
|
|
|
|
for (i = 0; i < NUM_LV1ENTRIES; i++)
|
|
|
|
if (lv1ent_page(priv->pgtable + i))
|
2014-05-12 06:14:48 +00:00
|
|
|
kmem_cache_free(lv2table_kmem_cache,
|
|
|
|
phys_to_virt(lv2table_base(priv->pgtable + i)));
|
2012-05-11 20:56:09 +00:00
|
|
|
|
|
|
|
free_pages((unsigned long)priv->pgtable, 2);
|
|
|
|
free_pages((unsigned long)priv->lv2entcnt, 1);
|
|
|
|
kfree(domain->priv);
|
|
|
|
domain->priv = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int exynos_iommu_attach_device(struct iommu_domain *domain,
|
|
|
|
struct device *dev)
|
|
|
|
{
|
|
|
|
struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
|
|
|
|
struct exynos_iommu_domain *priv = domain->priv;
|
2014-05-12 06:14:46 +00:00
|
|
|
phys_addr_t pagetable = virt_to_phys(priv->pgtable);
|
2012-05-11 20:56:09 +00:00
|
|
|
unsigned long flags;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = pm_runtime_get_sync(data->sysmmu);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = 0;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
|
2014-05-12 06:14:46 +00:00
|
|
|
ret = __exynos_sysmmu_enable(data, pagetable, domain);
|
2012-05-11 20:56:09 +00:00
|
|
|
|
|
|
|
if (ret == 0) {
|
|
|
|
/* 'data->node' must not be appeared in priv->clients */
|
|
|
|
BUG_ON(!list_empty(&data->node));
|
|
|
|
data->dev = dev;
|
|
|
|
list_add_tail(&data->node, &priv->clients);
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
|
|
|
|
if (ret < 0) {
|
2014-05-12 06:14:46 +00:00
|
|
|
dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n",
|
|
|
|
__func__, &pagetable);
|
2012-05-11 20:56:09 +00:00
|
|
|
pm_runtime_put(data->sysmmu);
|
2014-05-12 06:14:46 +00:00
|
|
|
return ret;
|
2012-05-11 20:56:09 +00:00
|
|
|
}
|
|
|
|
|
2014-05-12 06:14:46 +00:00
|
|
|
dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n",
|
|
|
|
__func__, &pagetable, (ret == 0) ? "" : ", again");
|
|
|
|
|
2012-05-11 20:56:09 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void exynos_iommu_detach_device(struct iommu_domain *domain,
|
|
|
|
struct device *dev)
|
|
|
|
{
|
|
|
|
struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
|
|
|
|
struct exynos_iommu_domain *priv = domain->priv;
|
|
|
|
struct list_head *pos;
|
2014-05-12 06:14:46 +00:00
|
|
|
phys_addr_t pagetable = virt_to_phys(priv->pgtable);
|
2012-05-11 20:56:09 +00:00
|
|
|
unsigned long flags;
|
|
|
|
bool found = false;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
|
|
|
|
list_for_each(pos, &priv->clients) {
|
|
|
|
if (list_entry(pos, struct sysmmu_drvdata, node) == data) {
|
|
|
|
found = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!found)
|
|
|
|
goto finish;
|
|
|
|
|
|
|
|
if (__exynos_sysmmu_disable(data)) {
|
2014-05-12 06:14:46 +00:00
|
|
|
dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n",
|
|
|
|
__func__, &pagetable);
|
2012-09-06 04:34:09 +00:00
|
|
|
list_del_init(&data->node);
|
2012-05-11 20:56:09 +00:00
|
|
|
|
|
|
|
} else {
|
2014-05-12 06:14:46 +00:00
|
|
|
dev_dbg(dev, "%s: Detaching IOMMU with pgtable %pa delayed",
|
|
|
|
__func__, &pagetable);
|
2012-05-11 20:56:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
finish:
|
|
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
|
|
|
|
if (found)
|
|
|
|
pm_runtime_put(data->sysmmu);
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova,
|
|
|
|
short *pgcounter)
|
|
|
|
{
|
2014-05-12 06:14:47 +00:00
|
|
|
if (lv1ent_section(sent)) {
|
|
|
|
WARN(1, "Trying mapping on %#08lx mapped with 1MiB page", iova);
|
|
|
|
return ERR_PTR(-EADDRINUSE);
|
|
|
|
}
|
|
|
|
|
2012-05-11 20:56:09 +00:00
|
|
|
if (lv1ent_fault(sent)) {
|
|
|
|
unsigned long *pent;
|
|
|
|
|
2014-05-12 06:14:48 +00:00
|
|
|
pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
|
2012-05-11 20:56:09 +00:00
|
|
|
BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
|
|
|
|
if (!pent)
|
2014-05-12 06:14:47 +00:00
|
|
|
return ERR_PTR(-ENOMEM);
|
2012-05-11 20:56:09 +00:00
|
|
|
|
2014-05-12 06:14:46 +00:00
|
|
|
*sent = mk_lv1ent_page(virt_to_phys(pent));
|
2012-05-11 20:56:09 +00:00
|
|
|
*pgcounter = NUM_LV2ENTRIES;
|
|
|
|
pgtable_flush(pent, pent + NUM_LV2ENTRIES);
|
|
|
|
pgtable_flush(sent, sent + 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
return page_entry(sent, iova);
|
|
|
|
}
|
|
|
|
|
2014-05-12 06:14:47 +00:00
|
|
|
static int lv1set_section(unsigned long *sent, unsigned long iova,
|
|
|
|
phys_addr_t paddr, short *pgcnt)
|
2012-05-11 20:56:09 +00:00
|
|
|
{
|
2014-05-12 06:14:47 +00:00
|
|
|
if (lv1ent_section(sent)) {
|
|
|
|
WARN(1, "Trying mapping on 1MiB@%#08lx that is mapped",
|
|
|
|
iova);
|
2012-05-11 20:56:09 +00:00
|
|
|
return -EADDRINUSE;
|
2014-05-12 06:14:47 +00:00
|
|
|
}
|
2012-05-11 20:56:09 +00:00
|
|
|
|
|
|
|
if (lv1ent_page(sent)) {
|
2014-05-12 06:14:47 +00:00
|
|
|
if (*pgcnt != NUM_LV2ENTRIES) {
|
|
|
|
WARN(1, "Trying mapping on 1MiB@%#08lx that is mapped",
|
|
|
|
iova);
|
2012-05-11 20:56:09 +00:00
|
|
|
return -EADDRINUSE;
|
2014-05-12 06:14:47 +00:00
|
|
|
}
|
2012-05-11 20:56:09 +00:00
|
|
|
|
2014-05-12 06:14:48 +00:00
|
|
|
kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
|
2012-05-11 20:56:09 +00:00
|
|
|
*pgcnt = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
*sent = mk_lv1ent_sect(paddr);
|
|
|
|
|
|
|
|
pgtable_flush(sent, sent + 1);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int lv2set_page(unsigned long *pent, phys_addr_t paddr, size_t size,
|
|
|
|
short *pgcnt)
|
|
|
|
{
|
|
|
|
if (size == SPAGE_SIZE) {
|
2014-05-12 06:14:47 +00:00
|
|
|
if (!lv2ent_fault(pent)) {
|
|
|
|
WARN(1, "Trying mapping on 4KiB where mapping exists");
|
2012-05-11 20:56:09 +00:00
|
|
|
return -EADDRINUSE;
|
2014-05-12 06:14:47 +00:00
|
|
|
}
|
2012-05-11 20:56:09 +00:00
|
|
|
|
|
|
|
*pent = mk_lv2ent_spage(paddr);
|
|
|
|
pgtable_flush(pent, pent + 1);
|
|
|
|
*pgcnt -= 1;
|
|
|
|
} else { /* size == LPAGE_SIZE */
|
|
|
|
int i;
|
|
|
|
for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
|
|
|
|
if (!lv2ent_fault(pent)) {
|
2014-05-12 06:14:47 +00:00
|
|
|
WARN(1,
|
|
|
|
"Trying mapping on 64KiB where mapping exists");
|
|
|
|
if (i > 0)
|
|
|
|
memset(pent - i, 0, sizeof(*pent) * i);
|
2012-05-11 20:56:09 +00:00
|
|
|
return -EADDRINUSE;
|
|
|
|
}
|
|
|
|
|
|
|
|
*pent = mk_lv2ent_lpage(paddr);
|
|
|
|
}
|
|
|
|
pgtable_flush(pent - SPAGES_PER_LPAGE, pent);
|
|
|
|
*pgcnt -= SPAGES_PER_LPAGE;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int exynos_iommu_map(struct iommu_domain *domain, unsigned long iova,
|
|
|
|
phys_addr_t paddr, size_t size, int prot)
|
|
|
|
{
|
|
|
|
struct exynos_iommu_domain *priv = domain->priv;
|
|
|
|
unsigned long *entry;
|
|
|
|
unsigned long flags;
|
|
|
|
int ret = -ENOMEM;
|
|
|
|
|
|
|
|
BUG_ON(priv->pgtable == NULL);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&priv->pgtablelock, flags);
|
|
|
|
|
|
|
|
entry = section_entry(priv->pgtable, iova);
|
|
|
|
|
|
|
|
if (size == SECT_SIZE) {
|
2014-05-12 06:14:47 +00:00
|
|
|
ret = lv1set_section(entry, iova, paddr,
|
2012-05-11 20:56:09 +00:00
|
|
|
&priv->lv2entcnt[lv1ent_offset(iova)]);
|
|
|
|
} else {
|
|
|
|
unsigned long *pent;
|
|
|
|
|
|
|
|
pent = alloc_lv2entry(entry, iova,
|
|
|
|
&priv->lv2entcnt[lv1ent_offset(iova)]);
|
|
|
|
|
2014-05-12 06:14:47 +00:00
|
|
|
if (IS_ERR(pent))
|
|
|
|
ret = PTR_ERR(pent);
|
2012-05-11 20:56:09 +00:00
|
|
|
else
|
|
|
|
ret = lv2set_page(pent, paddr, size,
|
|
|
|
&priv->lv2entcnt[lv1ent_offset(iova)]);
|
|
|
|
}
|
|
|
|
|
2014-05-12 06:14:47 +00:00
|
|
|
if (ret)
|
2012-05-11 20:56:09 +00:00
|
|
|
pr_debug("%s: Failed to map iova 0x%lx/0x%x bytes\n",
|
|
|
|
__func__, iova, size);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&priv->pgtablelock, flags);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static size_t exynos_iommu_unmap(struct iommu_domain *domain,
|
|
|
|
unsigned long iova, size_t size)
|
|
|
|
{
|
|
|
|
struct exynos_iommu_domain *priv = domain->priv;
|
|
|
|
struct sysmmu_drvdata *data;
|
|
|
|
unsigned long flags;
|
|
|
|
unsigned long *ent;
|
2014-05-12 06:14:47 +00:00
|
|
|
size_t err_pgsize;
|
2012-05-11 20:56:09 +00:00
|
|
|
|
|
|
|
BUG_ON(priv->pgtable == NULL);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&priv->pgtablelock, flags);
|
|
|
|
|
|
|
|
ent = section_entry(priv->pgtable, iova);
|
|
|
|
|
|
|
|
if (lv1ent_section(ent)) {
|
2014-05-12 06:14:47 +00:00
|
|
|
if (size < SECT_SIZE) {
|
|
|
|
err_pgsize = SECT_SIZE;
|
|
|
|
goto err;
|
|
|
|
}
|
2012-05-11 20:56:09 +00:00
|
|
|
|
|
|
|
*ent = 0;
|
|
|
|
pgtable_flush(ent, ent + 1);
|
|
|
|
size = SECT_SIZE;
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (unlikely(lv1ent_fault(ent))) {
|
|
|
|
if (size > SECT_SIZE)
|
|
|
|
size = SECT_SIZE;
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* lv1ent_page(sent) == true here */
|
|
|
|
|
|
|
|
ent = page_entry(ent, iova);
|
|
|
|
|
|
|
|
if (unlikely(lv2ent_fault(ent))) {
|
|
|
|
size = SPAGE_SIZE;
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (lv2ent_small(ent)) {
|
|
|
|
*ent = 0;
|
|
|
|
size = SPAGE_SIZE;
|
2014-05-12 06:14:51 +00:00
|
|
|
pgtable_flush(ent, ent + 1);
|
2012-05-11 20:56:09 +00:00
|
|
|
priv->lv2entcnt[lv1ent_offset(iova)] += 1;
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* lv1ent_large(ent) == true here */
|
2014-05-12 06:14:47 +00:00
|
|
|
if (size < LPAGE_SIZE) {
|
|
|
|
err_pgsize = LPAGE_SIZE;
|
|
|
|
goto err;
|
|
|
|
}
|
2012-05-11 20:56:09 +00:00
|
|
|
|
|
|
|
memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
|
2014-05-12 06:14:51 +00:00
|
|
|
pgtable_flush(ent, ent + SPAGES_PER_LPAGE);
|
2012-05-11 20:56:09 +00:00
|
|
|
|
|
|
|
size = LPAGE_SIZE;
|
|
|
|
priv->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
|
|
|
|
done:
|
|
|
|
spin_unlock_irqrestore(&priv->pgtablelock, flags);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
list_for_each_entry(data, &priv->clients, node)
|
2014-05-12 06:14:49 +00:00
|
|
|
sysmmu_tlb_invalidate_entry(data->dev, iova, size);
|
2012-05-11 20:56:09 +00:00
|
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
|
|
|
|
return size;
|
2014-05-12 06:14:47 +00:00
|
|
|
err:
|
|
|
|
spin_unlock_irqrestore(&priv->pgtablelock, flags);
|
|
|
|
|
|
|
|
WARN(1,
|
|
|
|
"%s: Failed due to size(%#x) @ %#08lx is smaller than page size %#x\n",
|
|
|
|
__func__, size, iova, err_pgsize);
|
|
|
|
|
|
|
|
return 0;
|
2012-05-11 20:56:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain,
|
2013-03-28 19:53:58 +00:00
|
|
|
dma_addr_t iova)
|
2012-05-11 20:56:09 +00:00
|
|
|
{
|
|
|
|
struct exynos_iommu_domain *priv = domain->priv;
|
|
|
|
unsigned long *entry;
|
|
|
|
unsigned long flags;
|
|
|
|
phys_addr_t phys = 0;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&priv->pgtablelock, flags);
|
|
|
|
|
|
|
|
entry = section_entry(priv->pgtable, iova);
|
|
|
|
|
|
|
|
if (lv1ent_section(entry)) {
|
|
|
|
phys = section_phys(entry) + section_offs(iova);
|
|
|
|
} else if (lv1ent_page(entry)) {
|
|
|
|
entry = page_entry(entry, iova);
|
|
|
|
|
|
|
|
if (lv2ent_large(entry))
|
|
|
|
phys = lpage_phys(entry) + lpage_offs(iova);
|
|
|
|
else if (lv2ent_small(entry))
|
|
|
|
phys = spage_phys(entry) + spage_offs(iova);
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&priv->pgtablelock, flags);
|
|
|
|
|
|
|
|
return phys;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct iommu_ops exynos_iommu_ops = {
|
|
|
|
.domain_init = &exynos_iommu_domain_init,
|
|
|
|
.domain_destroy = &exynos_iommu_domain_destroy,
|
|
|
|
.attach_dev = &exynos_iommu_attach_device,
|
|
|
|
.detach_dev = &exynos_iommu_detach_device,
|
|
|
|
.map = &exynos_iommu_map,
|
|
|
|
.unmap = &exynos_iommu_unmap,
|
|
|
|
.iova_to_phys = &exynos_iommu_iova_to_phys,
|
|
|
|
.pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init exynos_iommu_init(void)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2014-05-12 06:14:48 +00:00
|
|
|
lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
|
|
|
|
LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
|
|
|
|
if (!lv2table_kmem_cache) {
|
|
|
|
pr_err("%s: Failed to create kmem cache\n", __func__);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2012-05-11 20:56:09 +00:00
|
|
|
ret = platform_driver_register(&exynos_sysmmu_driver);
|
2014-05-12 06:14:48 +00:00
|
|
|
if (ret) {
|
|
|
|
pr_err("%s: Failed to register driver\n", __func__);
|
|
|
|
goto err_reg_driver;
|
|
|
|
}
|
2012-05-11 20:56:09 +00:00
|
|
|
|
2014-05-12 06:14:48 +00:00
|
|
|
ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
|
|
|
|
if (ret) {
|
|
|
|
pr_err("%s: Failed to register exynos-iommu driver.\n",
|
|
|
|
__func__);
|
|
|
|
goto err_set_iommu;
|
|
|
|
}
|
2012-05-11 20:56:09 +00:00
|
|
|
|
2014-05-12 06:14:48 +00:00
|
|
|
return 0;
|
|
|
|
err_set_iommu:
|
|
|
|
platform_driver_unregister(&exynos_sysmmu_driver);
|
|
|
|
err_reg_driver:
|
|
|
|
kmem_cache_destroy(lv2table_kmem_cache);
|
2012-05-11 20:56:09 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
subsys_initcall(exynos_iommu_init);
|