2019-05-19 13:51:43 +00:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2016-11-10 14:29:37 +00:00
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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2014 Endless Mobile
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*
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* Written by:
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* Jasper St. Pierre <jstpierre@mecheye.net>
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*/
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2017-04-04 12:15:23 +00:00
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#include <linux/component.h>
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2019-07-16 06:42:02 +00:00
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#include <linux/module.h>
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2016-11-10 14:29:37 +00:00
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#include <linux/of_graph.h>
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2020-04-28 09:21:47 +00:00
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#include <linux/sys_soc.h>
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2019-07-16 06:42:02 +00:00
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#include <linux/platform_device.h>
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#include <linux/soc/amlogic/meson-canvas.h>
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2016-11-10 14:29:37 +00:00
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2021-04-12 13:10:42 +00:00
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#include <drm/drm_aperture.h>
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2016-11-10 14:29:37 +00:00
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#include <drm/drm_atomic_helper.h>
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2019-07-16 06:42:02 +00:00
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#include <drm/drm_drv.h>
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2023-03-13 15:51:24 +00:00
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#include <drm/drm_fbdev_dma.h>
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2022-08-02 00:04:03 +00:00
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#include <drm/drm_gem_dma_helper.h>
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2017-09-24 12:26:19 +00:00
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#include <drm/drm_gem_framebuffer_helper.h>
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2019-07-16 06:42:02 +00:00
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#include <drm/drm_modeset_helper_vtables.h>
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2021-12-17 00:37:27 +00:00
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#include <drm/drm_module.h>
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2019-01-17 21:03:34 +00:00
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#include <drm/drm_probe_helper.h>
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2019-07-16 06:42:02 +00:00
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#include <drm/drm_vblank.h>
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2016-11-10 14:29:37 +00:00
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2019-07-16 06:42:02 +00:00
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#include "meson_crtc.h"
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2016-11-10 14:29:37 +00:00
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#include "meson_drv.h"
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2018-11-06 09:40:00 +00:00
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#include "meson_overlay.h"
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2019-07-16 06:42:02 +00:00
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#include "meson_plane.h"
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drm/meson: Add AFBCD module driver
This adds the driver for the ARM Framebuffer Compression decoders found
in the Amlogic GXM and G12A SoCs.
The Amlogic GXM and G12A AFBC decoder are totally different, the GXM only
handling only the AFBC v1.0 modes and the G12A decoder handling the
AFBC v1.2 modes.
The G12A AFBC decoder is an external IP integrated in the video pipeline,
and the GXM AFBC decoder seems to the an Amlogic custom decoder more
tighly integrated in the video pipeline.
The GXM AFBC decoder can handle only one AFBC plane for 2 available
OSD planes available in HW, and the G12A AFBC decoder can handle up
to 4 AFBC planes for up to 3 OSD planes available in HW.
The Amlogic GXM supports 16x16 SPARSE and 16x16 SPLIT AFBC buffers up
to 4k.
On the other side, for G12A SPLIT is mandatory in 16x16 block mode, but
for 4k modes 32x8+SPLIT AFBC buffers is manadatory for performances reasons.
The RDMA is used here to reset and program the AFBC decoder unit
on each vsync without involving the interrupt handler that can
be masked for a long period of time, producing display glitches.
For this we use the meson_rdma_writel_sync() which adds the register
write tuple (VPU register offset and register value) to the RDMA buffer
and write the value to the HW.
When enabled, the RDMA is enabled to rewrite the same sequence at the
next VSYNC event, until a new buffer is committed to the OSD plane.
Then the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder
doesn't need a reset/reprogram at each vsync, but needs to keep the
vsync interrupt enabled to trigger the RDMA module.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
[narmstrong: fixed typo in commit log]
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-6-narmstrong@baylibre.com
2019-10-21 09:15:05 +00:00
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#include "meson_osd_afbcd.h"
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2019-07-16 06:42:02 +00:00
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#include "meson_registers.h"
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2021-10-20 12:39:46 +00:00
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#include "meson_encoder_cvbs.h"
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2021-10-20 12:39:44 +00:00
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#include "meson_encoder_hdmi.h"
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2023-05-30 07:38:12 +00:00
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#include "meson_encoder_dsi.h"
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2016-11-10 14:29:37 +00:00
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#include "meson_viu.h"
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2019-07-16 06:42:02 +00:00
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#include "meson_vpp.h"
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drm/meson: Add AFBCD module driver
This adds the driver for the ARM Framebuffer Compression decoders found
in the Amlogic GXM and G12A SoCs.
The Amlogic GXM and G12A AFBC decoder are totally different, the GXM only
handling only the AFBC v1.0 modes and the G12A decoder handling the
AFBC v1.2 modes.
The G12A AFBC decoder is an external IP integrated in the video pipeline,
and the GXM AFBC decoder seems to the an Amlogic custom decoder more
tighly integrated in the video pipeline.
The GXM AFBC decoder can handle only one AFBC plane for 2 available
OSD planes available in HW, and the G12A AFBC decoder can handle up
to 4 AFBC planes for up to 3 OSD planes available in HW.
The Amlogic GXM supports 16x16 SPARSE and 16x16 SPLIT AFBC buffers up
to 4k.
On the other side, for G12A SPLIT is mandatory in 16x16 block mode, but
for 4k modes 32x8+SPLIT AFBC buffers is manadatory for performances reasons.
The RDMA is used here to reset and program the AFBC decoder unit
on each vsync without involving the interrupt handler that can
be masked for a long period of time, producing display glitches.
For this we use the meson_rdma_writel_sync() which adds the register
write tuple (VPU register offset and register value) to the RDMA buffer
and write the value to the HW.
When enabled, the RDMA is enabled to rewrite the same sequence at the
next VSYNC event, until a new buffer is committed to the OSD plane.
Then the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder
doesn't need a reset/reprogram at each vsync, but needs to keep the
vsync interrupt enabled to trigger the RDMA module.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
[narmstrong: fixed typo in commit log]
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-6-narmstrong@baylibre.com
2019-10-21 09:15:05 +00:00
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#include "meson_rdma.h"
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2016-11-10 14:29:37 +00:00
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#define DRIVER_NAME "meson"
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#define DRIVER_DESC "Amlogic Meson DRM driver"
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2017-04-04 12:15:29 +00:00
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/**
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* DOC: Video Processing Unit
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2016-11-10 14:29:37 +00:00
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*
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* VPU Handles the Global Video Processing, it includes management of the
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* clocks gates, blocks reset lines and power domains.
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*
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* What is missing :
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2017-04-04 12:15:29 +00:00
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*
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2016-11-10 14:29:37 +00:00
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* - Full reset of entire video processing HW blocks
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* - Scaling and setup of the VPU clock
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* - Bus clock gates
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* - Powering up video processing HW blocks
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* - Powering Up HDMI controller and PHY
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*/
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static const struct drm_mode_config_funcs meson_mode_config_funcs = {
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.atomic_check = drm_atomic_helper_check,
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.atomic_commit = drm_atomic_helper_commit,
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2017-09-24 12:26:19 +00:00
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.fb_create = drm_gem_fb_create,
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2016-11-10 14:29:37 +00:00
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};
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2019-01-14 15:31:18 +00:00
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static const struct drm_mode_config_helper_funcs meson_mode_config_helpers = {
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.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
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};
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2016-11-10 14:29:37 +00:00
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static irqreturn_t meson_irq(int irq, void *arg)
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{
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struct drm_device *dev = arg;
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struct meson_drm *priv = dev->dev_private;
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(void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG));
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meson_crtc_irq(priv);
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return IRQ_HANDLED;
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}
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2019-04-08 09:01:37 +00:00
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static int meson_dumb_create(struct drm_file *file, struct drm_device *dev,
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struct drm_mode_create_dumb *args)
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{
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/*
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* We need 64bytes aligned stride, and PAGE aligned size
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*/
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args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), SZ_64);
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args->size = PAGE_ALIGN(args->pitch * args->height);
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2022-08-02 00:04:03 +00:00
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return drm_gem_dma_dumb_create_internal(file, dev, args);
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2019-04-08 09:01:37 +00:00
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}
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2022-08-02 00:04:03 +00:00
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DEFINE_DRM_GEM_DMA_FOPS(fops);
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2016-11-10 14:29:37 +00:00
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2020-11-04 10:04:24 +00:00
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static const struct drm_driver meson_driver = {
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2019-06-17 15:39:24 +00:00
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.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
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2016-11-10 14:29:37 +00:00
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2022-08-02 00:04:03 +00:00
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/* DMA Ops */
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DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(meson_dumb_create),
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2016-11-10 14:29:37 +00:00
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/* Misc */
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.fops = &fops,
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.name = DRIVER_NAME,
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.desc = DRIVER_DESC,
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.date = "20161109",
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.major = 1,
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.minor = 0,
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};
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static bool meson_vpu_has_available_connectors(struct device *dev)
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{
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struct device_node *ep, *remote;
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/* Parses each endpoint and check if remote exists */
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for_each_endpoint_of_node(dev->of_node, ep) {
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/* If the endpoint node exists, consider it enabled */
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remote = of_graph_get_remote_port(ep);
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2022-07-26 01:07:22 +00:00
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if (remote) {
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of_node_put(remote);
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of_node_put(ep);
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2016-11-10 14:29:37 +00:00
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return true;
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2022-07-26 01:07:22 +00:00
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}
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2016-11-10 14:29:37 +00:00
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}
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return false;
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}
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static struct regmap_config meson_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = 0x1000,
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};
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2017-12-06 11:54:28 +00:00
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static void meson_vpu_init(struct meson_drm *priv)
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{
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2019-06-24 14:48:27 +00:00
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u32 value;
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/*
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* Slave dc0 and dc5 connected to master port 1.
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* By default other slaves are connected to master port 0.
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*/
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value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) |
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VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1);
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writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
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/* Slave dc0 connected to master port 1 */
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value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1);
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writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
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/* Slave dc4 and dc7 connected to master port 1 */
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value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) |
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VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1);
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writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
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/* Slave dc1 connected to master port 1 */
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value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1);
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writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
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2017-12-06 11:54:28 +00:00
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}
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2020-04-28 09:21:47 +00:00
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struct meson_drm_soc_attr {
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struct meson_drm_soc_limits limits;
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const struct soc_device_attribute *attrs;
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};
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static const struct meson_drm_soc_attr meson_drm_soc_attrs[] = {
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/* S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz */
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{
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.limits = {
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.max_hdmi_phy_freq = 1650000,
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},
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.attrs = (const struct soc_device_attribute []) {
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{ .soc_id = "GXL (S805*)", },
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2022-03-03 12:44:56 +00:00
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{ /* sentinel */ }
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2020-04-28 09:21:47 +00:00
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}
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},
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};
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2017-05-29 14:15:52 +00:00
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static int meson_drv_bind_master(struct device *dev, bool has_components)
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2016-11-10 14:29:37 +00:00
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{
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2017-04-04 12:15:23 +00:00
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struct platform_device *pdev = to_platform_device(dev);
|
drm/meson: Add AFBCD module driver
This adds the driver for the ARM Framebuffer Compression decoders found
in the Amlogic GXM and G12A SoCs.
The Amlogic GXM and G12A AFBC decoder are totally different, the GXM only
handling only the AFBC v1.0 modes and the G12A decoder handling the
AFBC v1.2 modes.
The G12A AFBC decoder is an external IP integrated in the video pipeline,
and the GXM AFBC decoder seems to the an Amlogic custom decoder more
tighly integrated in the video pipeline.
The GXM AFBC decoder can handle only one AFBC plane for 2 available
OSD planes available in HW, and the G12A AFBC decoder can handle up
to 4 AFBC planes for up to 3 OSD planes available in HW.
The Amlogic GXM supports 16x16 SPARSE and 16x16 SPLIT AFBC buffers up
to 4k.
On the other side, for G12A SPLIT is mandatory in 16x16 block mode, but
for 4k modes 32x8+SPLIT AFBC buffers is manadatory for performances reasons.
The RDMA is used here to reset and program the AFBC decoder unit
on each vsync without involving the interrupt handler that can
be masked for a long period of time, producing display glitches.
For this we use the meson_rdma_writel_sync() which adds the register
write tuple (VPU register offset and register value) to the RDMA buffer
and write the value to the HW.
When enabled, the RDMA is enabled to rewrite the same sequence at the
next VSYNC event, until a new buffer is committed to the OSD plane.
Then the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder
doesn't need a reset/reprogram at each vsync, but needs to keep the
vsync interrupt enabled to trigger the RDMA module.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
[narmstrong: fixed typo in commit log]
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-6-narmstrong@baylibre.com
2019-10-21 09:15:05 +00:00
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const struct meson_drm_match_data *match;
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2016-11-10 14:29:37 +00:00
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struct meson_drm *priv;
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struct drm_device *drm;
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struct resource *res;
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void __iomem *regs;
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2020-04-28 09:21:47 +00:00
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int ret, i;
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2016-11-10 14:29:37 +00:00
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/* Checks if an output connector is available */
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if (!meson_vpu_has_available_connectors(dev)) {
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dev_err(dev, "No output connector available\n");
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return -ENODEV;
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}
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drm/meson: Add AFBCD module driver
This adds the driver for the ARM Framebuffer Compression decoders found
in the Amlogic GXM and G12A SoCs.
The Amlogic GXM and G12A AFBC decoder are totally different, the GXM only
handling only the AFBC v1.0 modes and the G12A decoder handling the
AFBC v1.2 modes.
The G12A AFBC decoder is an external IP integrated in the video pipeline,
and the GXM AFBC decoder seems to the an Amlogic custom decoder more
tighly integrated in the video pipeline.
The GXM AFBC decoder can handle only one AFBC plane for 2 available
OSD planes available in HW, and the G12A AFBC decoder can handle up
to 4 AFBC planes for up to 3 OSD planes available in HW.
The Amlogic GXM supports 16x16 SPARSE and 16x16 SPLIT AFBC buffers up
to 4k.
On the other side, for G12A SPLIT is mandatory in 16x16 block mode, but
for 4k modes 32x8+SPLIT AFBC buffers is manadatory for performances reasons.
The RDMA is used here to reset and program the AFBC decoder unit
on each vsync without involving the interrupt handler that can
be masked for a long period of time, producing display glitches.
For this we use the meson_rdma_writel_sync() which adds the register
write tuple (VPU register offset and register value) to the RDMA buffer
and write the value to the HW.
When enabled, the RDMA is enabled to rewrite the same sequence at the
next VSYNC event, until a new buffer is committed to the OSD plane.
Then the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder
doesn't need a reset/reprogram at each vsync, but needs to keep the
vsync interrupt enabled to trigger the RDMA module.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
[narmstrong: fixed typo in commit log]
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-6-narmstrong@baylibre.com
2019-10-21 09:15:05 +00:00
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match = of_device_get_match_data(dev);
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if (!match)
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return -ENODEV;
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2016-11-10 14:29:37 +00:00
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drm = drm_dev_alloc(&meson_driver, dev);
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if (IS_ERR(drm))
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return PTR_ERR(drm);
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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ret = -ENOMEM;
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goto free_drm;
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}
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drm->dev_private = priv;
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priv->drm = drm;
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priv->dev = dev;
|
drm/meson: Add AFBCD module driver
This adds the driver for the ARM Framebuffer Compression decoders found
in the Amlogic GXM and G12A SoCs.
The Amlogic GXM and G12A AFBC decoder are totally different, the GXM only
handling only the AFBC v1.0 modes and the G12A decoder handling the
AFBC v1.2 modes.
The G12A AFBC decoder is an external IP integrated in the video pipeline,
and the GXM AFBC decoder seems to the an Amlogic custom decoder more
tighly integrated in the video pipeline.
The GXM AFBC decoder can handle only one AFBC plane for 2 available
OSD planes available in HW, and the G12A AFBC decoder can handle up
to 4 AFBC planes for up to 3 OSD planes available in HW.
The Amlogic GXM supports 16x16 SPARSE and 16x16 SPLIT AFBC buffers up
to 4k.
On the other side, for G12A SPLIT is mandatory in 16x16 block mode, but
for 4k modes 32x8+SPLIT AFBC buffers is manadatory for performances reasons.
The RDMA is used here to reset and program the AFBC decoder unit
on each vsync without involving the interrupt handler that can
be masked for a long period of time, producing display glitches.
For this we use the meson_rdma_writel_sync() which adds the register
write tuple (VPU register offset and register value) to the RDMA buffer
and write the value to the HW.
When enabled, the RDMA is enabled to rewrite the same sequence at the
next VSYNC event, until a new buffer is committed to the OSD plane.
Then the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder
doesn't need a reset/reprogram at each vsync, but needs to keep the
vsync interrupt enabled to trigger the RDMA module.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
[narmstrong: fixed typo in commit log]
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-6-narmstrong@baylibre.com
2019-10-21 09:15:05 +00:00
|
|
|
priv->compat = match->compat;
|
|
|
|
priv->afbcd.ops = match->afbcd_ops;
|
2019-08-22 14:43:41 +00:00
|
|
|
|
2021-08-31 13:56:43 +00:00
|
|
|
regs = devm_platform_ioremap_resource_byname(pdev, "vpu");
|
2018-03-12 20:15:10 +00:00
|
|
|
if (IS_ERR(regs)) {
|
|
|
|
ret = PTR_ERR(regs);
|
|
|
|
goto free_drm;
|
|
|
|
}
|
2016-11-10 14:29:37 +00:00
|
|
|
|
|
|
|
priv->io_base = regs;
|
|
|
|
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi");
|
2018-06-11 16:53:35 +00:00
|
|
|
if (!res) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto free_drm;
|
|
|
|
}
|
2016-11-10 14:29:37 +00:00
|
|
|
/* Simply ioremap since it may be a shared register zone */
|
|
|
|
regs = devm_ioremap(dev, res->start, resource_size(res));
|
2018-03-12 20:15:10 +00:00
|
|
|
if (!regs) {
|
|
|
|
ret = -EADDRNOTAVAIL;
|
|
|
|
goto free_drm;
|
|
|
|
}
|
2016-11-10 14:29:37 +00:00
|
|
|
|
|
|
|
priv->hhi = devm_regmap_init_mmio(dev, regs,
|
|
|
|
&meson_regmap_config);
|
|
|
|
if (IS_ERR(priv->hhi)) {
|
|
|
|
dev_err(&pdev->dev, "Couldn't create the HHI regmap\n");
|
2018-03-12 20:15:10 +00:00
|
|
|
ret = PTR_ERR(priv->hhi);
|
|
|
|
goto free_drm;
|
2016-11-10 14:29:37 +00:00
|
|
|
}
|
|
|
|
|
2018-11-05 10:45:08 +00:00
|
|
|
priv->canvas = meson_canvas_get(dev);
|
2019-03-11 10:51:44 +00:00
|
|
|
if (IS_ERR(priv->canvas)) {
|
|
|
|
ret = PTR_ERR(priv->canvas);
|
|
|
|
goto free_drm;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1);
|
|
|
|
if (ret)
|
|
|
|
goto free_drm;
|
|
|
|
ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0);
|
|
|
|
if (ret) {
|
|
|
|
meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
|
|
|
|
goto free_drm;
|
|
|
|
}
|
|
|
|
ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1);
|
|
|
|
if (ret) {
|
|
|
|
meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
|
|
|
|
meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
|
|
|
|
goto free_drm;
|
|
|
|
}
|
|
|
|
ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2);
|
|
|
|
if (ret) {
|
|
|
|
meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
|
|
|
|
meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
|
|
|
|
meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
|
|
|
|
goto free_drm;
|
2016-11-10 14:29:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
priv->vsync_irq = platform_get_irq(pdev, 0);
|
|
|
|
|
2018-03-12 20:15:08 +00:00
|
|
|
ret = drm_vblank_init(drm, 1);
|
|
|
|
if (ret)
|
|
|
|
goto free_drm;
|
|
|
|
|
2020-04-28 09:21:47 +00:00
|
|
|
/* Assign limits per soc revision/package */
|
|
|
|
for (i = 0 ; i < ARRAY_SIZE(meson_drm_soc_attrs) ; ++i) {
|
|
|
|
if (soc_device_match(meson_drm_soc_attrs[i].attrs)) {
|
|
|
|
priv->limits = &meson_drm_soc_attrs[i].limits;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-04-12 13:10:42 +00:00
|
|
|
/*
|
|
|
|
* Remove early framebuffers (ie. simplefb). The framebuffer can be
|
|
|
|
* located anywhere in RAM
|
|
|
|
*/
|
2023-04-06 13:21:03 +00:00
|
|
|
ret = drm_aperture_remove_framebuffers(&meson_driver);
|
2021-04-12 13:10:42 +00:00
|
|
|
if (ret)
|
|
|
|
goto free_drm;
|
2018-12-10 09:28:53 +00:00
|
|
|
|
2020-03-23 14:49:33 +00:00
|
|
|
ret = drmm_mode_config_init(drm);
|
|
|
|
if (ret)
|
|
|
|
goto free_drm;
|
2017-04-04 12:15:23 +00:00
|
|
|
drm->mode_config.max_width = 3840;
|
|
|
|
drm->mode_config.max_height = 2160;
|
|
|
|
drm->mode_config.funcs = &meson_mode_config_funcs;
|
2019-01-14 15:31:18 +00:00
|
|
|
drm->mode_config.helper_private = &meson_mode_config_helpers;
|
2017-04-04 12:15:23 +00:00
|
|
|
|
|
|
|
/* Hardware Initialization */
|
|
|
|
|
2017-12-06 11:54:28 +00:00
|
|
|
meson_vpu_init(priv);
|
2017-04-04 12:15:23 +00:00
|
|
|
meson_venc_init(priv);
|
|
|
|
meson_vpp_init(priv);
|
|
|
|
meson_viu_init(priv);
|
drm/meson: Add AFBCD module driver
This adds the driver for the ARM Framebuffer Compression decoders found
in the Amlogic GXM and G12A SoCs.
The Amlogic GXM and G12A AFBC decoder are totally different, the GXM only
handling only the AFBC v1.0 modes and the G12A decoder handling the
AFBC v1.2 modes.
The G12A AFBC decoder is an external IP integrated in the video pipeline,
and the GXM AFBC decoder seems to the an Amlogic custom decoder more
tighly integrated in the video pipeline.
The GXM AFBC decoder can handle only one AFBC plane for 2 available
OSD planes available in HW, and the G12A AFBC decoder can handle up
to 4 AFBC planes for up to 3 OSD planes available in HW.
The Amlogic GXM supports 16x16 SPARSE and 16x16 SPLIT AFBC buffers up
to 4k.
On the other side, for G12A SPLIT is mandatory in 16x16 block mode, but
for 4k modes 32x8+SPLIT AFBC buffers is manadatory for performances reasons.
The RDMA is used here to reset and program the AFBC decoder unit
on each vsync without involving the interrupt handler that can
be masked for a long period of time, producing display glitches.
For this we use the meson_rdma_writel_sync() which adds the register
write tuple (VPU register offset and register value) to the RDMA buffer
and write the value to the HW.
When enabled, the RDMA is enabled to rewrite the same sequence at the
next VSYNC event, until a new buffer is committed to the OSD plane.
Then the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder
doesn't need a reset/reprogram at each vsync, but needs to keep the
vsync interrupt enabled to trigger the RDMA module.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
[narmstrong: fixed typo in commit log]
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-6-narmstrong@baylibre.com
2019-10-21 09:15:05 +00:00
|
|
|
if (priv->afbcd.ops) {
|
|
|
|
ret = priv->afbcd.ops->init(priv);
|
|
|
|
if (ret)
|
2021-12-30 23:55:15 +00:00
|
|
|
goto free_drm;
|
drm/meson: Add AFBCD module driver
This adds the driver for the ARM Framebuffer Compression decoders found
in the Amlogic GXM and G12A SoCs.
The Amlogic GXM and G12A AFBC decoder are totally different, the GXM only
handling only the AFBC v1.0 modes and the G12A decoder handling the
AFBC v1.2 modes.
The G12A AFBC decoder is an external IP integrated in the video pipeline,
and the GXM AFBC decoder seems to the an Amlogic custom decoder more
tighly integrated in the video pipeline.
The GXM AFBC decoder can handle only one AFBC plane for 2 available
OSD planes available in HW, and the G12A AFBC decoder can handle up
to 4 AFBC planes for up to 3 OSD planes available in HW.
The Amlogic GXM supports 16x16 SPARSE and 16x16 SPLIT AFBC buffers up
to 4k.
On the other side, for G12A SPLIT is mandatory in 16x16 block mode, but
for 4k modes 32x8+SPLIT AFBC buffers is manadatory for performances reasons.
The RDMA is used here to reset and program the AFBC decoder unit
on each vsync without involving the interrupt handler that can
be masked for a long period of time, producing display glitches.
For this we use the meson_rdma_writel_sync() which adds the register
write tuple (VPU register offset and register value) to the RDMA buffer
and write the value to the HW.
When enabled, the RDMA is enabled to rewrite the same sequence at the
next VSYNC event, until a new buffer is committed to the OSD plane.
Then the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder
doesn't need a reset/reprogram at each vsync, but needs to keep the
vsync interrupt enabled to trigger the RDMA module.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
[narmstrong: fixed typo in commit log]
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-6-narmstrong@baylibre.com
2019-10-21 09:15:05 +00:00
|
|
|
}
|
2016-11-10 14:29:37 +00:00
|
|
|
|
|
|
|
/* Encoder Initialization */
|
|
|
|
|
2024-02-18 17:50:35 +00:00
|
|
|
ret = meson_encoder_cvbs_probe(priv);
|
2016-11-10 14:29:37 +00:00
|
|
|
if (ret)
|
2021-12-30 23:55:15 +00:00
|
|
|
goto exit_afbcd;
|
2016-11-10 14:29:37 +00:00
|
|
|
|
2017-05-29 14:15:52 +00:00
|
|
|
if (has_components) {
|
2023-05-30 07:38:09 +00:00
|
|
|
ret = component_bind_all(dev, drm);
|
2017-05-29 14:15:52 +00:00
|
|
|
if (ret) {
|
|
|
|
dev_err(drm->dev, "Couldn't bind all components\n");
|
2023-05-30 07:38:09 +00:00
|
|
|
/* Do not try to unbind */
|
|
|
|
has_components = false;
|
2021-12-30 23:55:15 +00:00
|
|
|
goto exit_afbcd;
|
2017-05-29 14:15:52 +00:00
|
|
|
}
|
2017-04-04 12:15:23 +00:00
|
|
|
}
|
2016-11-10 14:29:37 +00:00
|
|
|
|
2024-02-18 17:50:35 +00:00
|
|
|
ret = meson_encoder_hdmi_probe(priv);
|
2021-10-20 12:39:44 +00:00
|
|
|
if (ret)
|
2023-05-30 07:38:09 +00:00
|
|
|
goto exit_afbcd;
|
2021-10-20 12:39:44 +00:00
|
|
|
|
2023-05-30 07:38:12 +00:00
|
|
|
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
|
2024-02-18 17:50:35 +00:00
|
|
|
ret = meson_encoder_dsi_probe(priv);
|
2023-05-30 07:38:12 +00:00
|
|
|
if (ret)
|
|
|
|
goto exit_afbcd;
|
|
|
|
}
|
|
|
|
|
2016-11-10 14:29:37 +00:00
|
|
|
ret = meson_plane_create(priv);
|
|
|
|
if (ret)
|
2023-05-30 07:38:09 +00:00
|
|
|
goto exit_afbcd;
|
2016-11-10 14:29:37 +00:00
|
|
|
|
2018-11-06 09:40:00 +00:00
|
|
|
ret = meson_overlay_create(priv);
|
|
|
|
if (ret)
|
2023-05-30 07:38:09 +00:00
|
|
|
goto exit_afbcd;
|
2018-11-06 09:40:00 +00:00
|
|
|
|
2016-11-10 14:29:37 +00:00
|
|
|
ret = meson_crtc_create(priv);
|
|
|
|
if (ret)
|
2023-05-30 07:38:09 +00:00
|
|
|
goto exit_afbcd;
|
2016-11-10 14:29:37 +00:00
|
|
|
|
2021-07-06 07:45:45 +00:00
|
|
|
ret = request_irq(priv->vsync_irq, meson_irq, 0, drm->driver->name, drm);
|
2016-11-10 14:29:37 +00:00
|
|
|
if (ret)
|
2023-05-30 07:38:09 +00:00
|
|
|
goto exit_afbcd;
|
2016-11-10 14:29:37 +00:00
|
|
|
|
|
|
|
drm_mode_config_reset(drm);
|
|
|
|
|
|
|
|
drm_kms_helper_poll_init(drm);
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
|
|
|
|
ret = drm_dev_register(drm, 0);
|
|
|
|
if (ret)
|
2019-03-22 15:26:57 +00:00
|
|
|
goto uninstall_irq;
|
2016-11-10 14:29:37 +00:00
|
|
|
|
2023-03-13 15:51:24 +00:00
|
|
|
drm_fbdev_dma_setup(drm, 32);
|
2018-09-08 13:46:33 +00:00
|
|
|
|
2016-11-10 14:29:37 +00:00
|
|
|
return 0;
|
|
|
|
|
2019-03-22 15:26:57 +00:00
|
|
|
uninstall_irq:
|
2021-07-06 07:45:45 +00:00
|
|
|
free_irq(priv->vsync_irq, drm);
|
2021-12-30 23:55:15 +00:00
|
|
|
exit_afbcd:
|
|
|
|
if (priv->afbcd.ops)
|
|
|
|
priv->afbcd.ops->exit(priv);
|
2016-11-10 14:29:37 +00:00
|
|
|
free_drm:
|
2018-03-12 20:15:09 +00:00
|
|
|
drm_dev_put(drm);
|
2016-11-10 14:29:37 +00:00
|
|
|
|
2023-05-30 07:38:12 +00:00
|
|
|
meson_encoder_dsi_remove(priv);
|
2023-05-30 07:38:09 +00:00
|
|
|
meson_encoder_hdmi_remove(priv);
|
|
|
|
meson_encoder_cvbs_remove(priv);
|
|
|
|
|
|
|
|
if (has_components)
|
|
|
|
component_unbind_all(dev, drm);
|
|
|
|
|
2016-11-10 14:29:37 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-05-29 14:15:52 +00:00
|
|
|
static int meson_drv_bind(struct device *dev)
|
|
|
|
{
|
|
|
|
return meson_drv_bind_master(dev, true);
|
|
|
|
}
|
|
|
|
|
2017-04-04 12:15:23 +00:00
|
|
|
static void meson_drv_unbind(struct device *dev)
|
2016-11-10 14:29:37 +00:00
|
|
|
{
|
2019-03-22 15:26:56 +00:00
|
|
|
struct meson_drm *priv = dev_get_drvdata(dev);
|
|
|
|
struct drm_device *drm = priv->drm;
|
2018-11-05 10:45:08 +00:00
|
|
|
|
2018-11-06 09:40:00 +00:00
|
|
|
if (priv->canvas) {
|
2018-11-05 10:45:08 +00:00
|
|
|
meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
|
2018-11-06 09:40:00 +00:00
|
|
|
meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
|
|
|
|
meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
|
|
|
|
meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2);
|
|
|
|
}
|
2016-11-10 14:29:37 +00:00
|
|
|
|
|
|
|
drm_dev_unregister(drm);
|
|
|
|
drm_kms_helper_poll_fini(drm);
|
2020-11-16 20:07:42 +00:00
|
|
|
drm_atomic_helper_shutdown(drm);
|
2021-07-06 07:45:45 +00:00
|
|
|
free_irq(priv->vsync_irq, drm);
|
2018-03-12 20:15:09 +00:00
|
|
|
drm_dev_put(drm);
|
2022-09-20 22:28:42 +00:00
|
|
|
|
2023-05-30 07:38:12 +00:00
|
|
|
meson_encoder_dsi_remove(priv);
|
2022-09-20 22:28:42 +00:00
|
|
|
meson_encoder_hdmi_remove(priv);
|
|
|
|
meson_encoder_cvbs_remove(priv);
|
|
|
|
|
drm/meson: reorder driver deinit sequence to fix use-after-free bug
Unloading the driver triggers the following KASAN warning:
[ +0.006275] =============================================================
[ +0.000029] BUG: KASAN: use-after-free in __list_del_entry_valid+0xe0/0x1a0
[ +0.000026] Read of size 8 at addr ffff000020c395e0 by task rmmod/2695
[ +0.000019] CPU: 5 PID: 2695 Comm: rmmod Tainted: G C O 5.19.0-rc6-lrmbkasan+ #1
[ +0.000013] Hardware name: Hardkernel ODROID-N2Plus (DT)
[ +0.000008] Call trace:
[ +0.000007] dump_backtrace+0x1ec/0x280
[ +0.000013] show_stack+0x24/0x80
[ +0.000008] dump_stack_lvl+0x98/0xd4
[ +0.000011] print_address_description.constprop.0+0x80/0x520
[ +0.000011] print_report+0x128/0x260
[ +0.000007] kasan_report+0xb8/0xfc
[ +0.000008] __asan_report_load8_noabort+0x3c/0x50
[ +0.000010] __list_del_entry_valid+0xe0/0x1a0
[ +0.000009] drm_atomic_private_obj_fini+0x30/0x200 [drm]
[ +0.000172] drm_bridge_detach+0x94/0x260 [drm]
[ +0.000145] drm_encoder_cleanup+0xa4/0x290 [drm]
[ +0.000144] drm_mode_config_cleanup+0x118/0x740 [drm]
[ +0.000143] drm_mode_config_init_release+0x1c/0x2c [drm]
[ +0.000144] drm_managed_release+0x170/0x414 [drm]
[ +0.000142] drm_dev_put.part.0+0xc0/0x124 [drm]
[ +0.000143] drm_dev_put+0x20/0x30 [drm]
[ +0.000142] meson_drv_unbind+0x1d8/0x2ac [meson_drm]
[ +0.000028] take_down_aggregate_device+0xb0/0x160
[ +0.000016] component_del+0x18c/0x360
[ +0.000009] meson_dw_hdmi_remove+0x28/0x40 [meson_dw_hdmi]
[ +0.000015] platform_remove+0x64/0xb0
[ +0.000009] device_remove+0xb8/0x154
[ +0.000009] device_release_driver_internal+0x398/0x5b0
[ +0.000009] driver_detach+0xac/0x1b0
[ +0.000009] bus_remove_driver+0x158/0x29c
[ +0.000009] driver_unregister+0x70/0xb0
[ +0.000008] platform_driver_unregister+0x20/0x2c
[ +0.000008] meson_dw_hdmi_platform_driver_exit+0x1c/0x30 [meson_dw_hdmi]
[ +0.000012] __do_sys_delete_module+0x288/0x400
[ +0.000011] __arm64_sys_delete_module+0x5c/0x80
[ +0.000009] invoke_syscall+0x74/0x260
[ +0.000009] el0_svc_common.constprop.0+0xcc/0x260
[ +0.000009] do_el0_svc+0x50/0x70
[ +0.000007] el0_svc+0x68/0x1a0
[ +0.000012] el0t_64_sync_handler+0x11c/0x150
[ +0.000008] el0t_64_sync+0x18c/0x190
[ +0.000018] Allocated by task 0:
[ +0.000007] (stack is not available)
[ +0.000011] Freed by task 2695:
[ +0.000008] kasan_save_stack+0x2c/0x5c
[ +0.000011] kasan_set_track+0x2c/0x40
[ +0.000008] kasan_set_free_info+0x28/0x50
[ +0.000009] ____kasan_slab_free+0x128/0x1d4
[ +0.000008] __kasan_slab_free+0x18/0x24
[ +0.000007] slab_free_freelist_hook+0x108/0x230
[ +0.000011] kfree+0x110/0x35c
[ +0.000008] release_nodes+0xf0/0x16c
[ +0.000009] devres_release_group+0x180/0x270
[ +0.000008] component_unbind+0x128/0x1e0
[ +0.000010] component_unbind_all+0x1b8/0x264
[ +0.000009] meson_drv_unbind+0x1a0/0x2ac [meson_drm]
[ +0.000025] take_down_aggregate_device+0xb0/0x160
[ +0.000009] component_del+0x18c/0x360
[ +0.000009] meson_dw_hdmi_remove+0x28/0x40 [meson_dw_hdmi]
[ +0.000012] platform_remove+0x64/0xb0
[ +0.000008] device_remove+0xb8/0x154
[ +0.000009] device_release_driver_internal+0x398/0x5b0
[ +0.000009] driver_detach+0xac/0x1b0
[ +0.000009] bus_remove_driver+0x158/0x29c
[ +0.000008] driver_unregister+0x70/0xb0
[ +0.000008] platform_driver_unregister+0x20/0x2c
[ +0.000008] meson_dw_hdmi_platform_driver_exit+0x1c/0x30 [meson_dw_hdmi]
[ +0.000011] __do_sys_delete_module+0x288/0x400
[ +0.000010] __arm64_sys_delete_module+0x5c/0x80
[ +0.000008] invoke_syscall+0x74/0x260
[ +0.000008] el0_svc_common.constprop.0+0xcc/0x260
[ +0.000008] do_el0_svc+0x50/0x70
[ +0.000007] el0_svc+0x68/0x1a0
[ +0.000009] el0t_64_sync_handler+0x11c/0x150
[ +0.000009] el0t_64_sync+0x18c/0x190
[ +0.000014] The buggy address belongs to the object at ffff000020c39000
which belongs to the cache kmalloc-4k of size 4096
[ +0.000008] The buggy address is located 1504 bytes inside of
4096-byte region [ffff000020c39000, ffff000020c3a000)
[ +0.000016] The buggy address belongs to the physical page:
[ +0.000009] page:fffffc0000830e00 refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0x20c38
[ +0.000013] head:fffffc0000830e00 order:3 compound_mapcount:0 compound_pincount:0
[ +0.000008] flags: 0xffff00000010200(slab|head|node=0|zone=0|lastcpupid=0xffff)
[ +0.000019] raw: 0ffff00000010200 fffffc0000fd4808 fffffc0000126208 ffff000000002e80
[ +0.000009] raw: 0000000000000000 0000000000020002 00000001ffffffff 0000000000000000
[ +0.000008] page dumped because: kasan: bad access detected
[ +0.000011] Memory state around the buggy address:
[ +0.000008] ffff000020c39480: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
[ +0.000007] ffff000020c39500: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
[ +0.000007] >ffff000020c39580: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
[ +0.000007] ^
[ +0.000007] ffff000020c39600: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
[ +0.000007] ffff000020c39680: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
[ +0.000006] ==================================================================
The reason this is happening is unloading meson-dw-hdmi will cause the
component API to take down the aggregate device, which in turn will cause
all devres-managed memory to be freed, including the struct dw_hdmi
allocated in dw_hdmi_probe. This struct embeds a struct drm_bridge that is
added at the end of the function, and which is later on picked up in
meson_encoder_hdmi_init.
However, when attaching the bridge to the encoder created in
meson_encoder_hdmi_init, it's linked to the encoder's bridge chain, from
where it never leaves, even after devres_release_group is called when the
driver's components are unbound and the embedding structure freed.
Then, when calling drm_dev_put in the aggregate driver's unbind function,
drm_bridge_detach is called for every single bridge linked to the encoder,
including the one whose memory had already been deallocated.
Fix by calling component_unbind_all after drm_dev_put.
Signed-off-by: Adrián Larumbe <adrian.larumbe@collabora.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220919010940.419893-2-adrian.larumbe@collabora.com
2022-09-19 01:09:38 +00:00
|
|
|
component_unbind_all(dev, drm);
|
2020-11-16 20:07:41 +00:00
|
|
|
|
2021-12-30 23:55:14 +00:00
|
|
|
if (priv->afbcd.ops)
|
|
|
|
priv->afbcd.ops->exit(priv);
|
2016-11-10 14:29:37 +00:00
|
|
|
}
|
|
|
|
|
2017-04-04 12:15:23 +00:00
|
|
|
static const struct component_master_ops meson_drv_master_ops = {
|
|
|
|
.bind = meson_drv_bind,
|
|
|
|
.unbind = meson_drv_unbind,
|
|
|
|
};
|
|
|
|
|
2019-08-27 09:58:25 +00:00
|
|
|
static int __maybe_unused meson_drv_pm_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct meson_drm *priv = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
if (!priv)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return drm_mode_config_helper_suspend(priv->drm);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __maybe_unused meson_drv_pm_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct meson_drm *priv = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
if (!priv)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
meson_vpu_init(priv);
|
|
|
|
meson_venc_init(priv);
|
|
|
|
meson_vpp_init(priv);
|
|
|
|
meson_viu_init(priv);
|
drm/meson: Add AFBCD module driver
This adds the driver for the ARM Framebuffer Compression decoders found
in the Amlogic GXM and G12A SoCs.
The Amlogic GXM and G12A AFBC decoder are totally different, the GXM only
handling only the AFBC v1.0 modes and the G12A decoder handling the
AFBC v1.2 modes.
The G12A AFBC decoder is an external IP integrated in the video pipeline,
and the GXM AFBC decoder seems to the an Amlogic custom decoder more
tighly integrated in the video pipeline.
The GXM AFBC decoder can handle only one AFBC plane for 2 available
OSD planes available in HW, and the G12A AFBC decoder can handle up
to 4 AFBC planes for up to 3 OSD planes available in HW.
The Amlogic GXM supports 16x16 SPARSE and 16x16 SPLIT AFBC buffers up
to 4k.
On the other side, for G12A SPLIT is mandatory in 16x16 block mode, but
for 4k modes 32x8+SPLIT AFBC buffers is manadatory for performances reasons.
The RDMA is used here to reset and program the AFBC decoder unit
on each vsync without involving the interrupt handler that can
be masked for a long period of time, producing display glitches.
For this we use the meson_rdma_writel_sync() which adds the register
write tuple (VPU register offset and register value) to the RDMA buffer
and write the value to the HW.
When enabled, the RDMA is enabled to rewrite the same sequence at the
next VSYNC event, until a new buffer is committed to the OSD plane.
Then the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder
doesn't need a reset/reprogram at each vsync, but needs to keep the
vsync interrupt enabled to trigger the RDMA module.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
[narmstrong: fixed typo in commit log]
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-6-narmstrong@baylibre.com
2019-10-21 09:15:05 +00:00
|
|
|
if (priv->afbcd.ops)
|
|
|
|
priv->afbcd.ops->init(priv);
|
2019-08-27 09:58:25 +00:00
|
|
|
|
2020-04-28 13:17:47 +00:00
|
|
|
return drm_mode_config_helper_resume(priv->drm);
|
2019-08-27 09:58:25 +00:00
|
|
|
}
|
|
|
|
|
2021-03-02 04:22:02 +00:00
|
|
|
static void meson_drv_shutdown(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct meson_drm *priv = dev_get_drvdata(&pdev->dev);
|
|
|
|
|
2021-04-30 08:27:44 +00:00
|
|
|
if (!priv)
|
|
|
|
return;
|
|
|
|
|
|
|
|
drm_kms_helper_poll_fini(priv->drm);
|
|
|
|
drm_atomic_helper_shutdown(priv->drm);
|
2021-03-02 04:22:02 +00:00
|
|
|
}
|
|
|
|
|
2023-05-30 07:38:10 +00:00
|
|
|
/*
|
|
|
|
* Only devices to use as components
|
|
|
|
* TOFIX: get rid of components when we can finally
|
|
|
|
* get meson_dx_hdmi to stop using the meson_drm
|
|
|
|
* private structure for HHI registers.
|
|
|
|
*/
|
|
|
|
static const struct of_device_id components_dev_match[] = {
|
|
|
|
{ .compatible = "amlogic,meson-gxbb-dw-hdmi" },
|
|
|
|
{ .compatible = "amlogic,meson-gxl-dw-hdmi" },
|
|
|
|
{ .compatible = "amlogic,meson-gxm-dw-hdmi" },
|
|
|
|
{ .compatible = "amlogic,meson-g12a-dw-hdmi" },
|
2021-10-20 12:39:43 +00:00
|
|
|
{}
|
|
|
|
};
|
|
|
|
|
2017-04-04 12:15:23 +00:00
|
|
|
static int meson_drv_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct component_match *match = NULL;
|
|
|
|
struct device_node *np = pdev->dev.of_node;
|
|
|
|
struct device_node *ep, *remote;
|
|
|
|
int count = 0;
|
|
|
|
|
|
|
|
for_each_endpoint_of_node(np, ep) {
|
|
|
|
remote = of_graph_get_remote_port_parent(ep);
|
2019-01-13 09:44:51 +00:00
|
|
|
if (!remote || !of_device_is_available(remote)) {
|
|
|
|
of_node_put(remote);
|
2017-04-04 12:15:23 +00:00
|
|
|
continue;
|
2019-01-13 09:44:51 +00:00
|
|
|
}
|
2017-04-04 12:15:23 +00:00
|
|
|
|
2023-05-30 07:38:10 +00:00
|
|
|
if (of_match_node(components_dev_match, remote)) {
|
|
|
|
component_match_add(&pdev->dev, &match, component_compare_of, remote);
|
2021-10-20 12:39:43 +00:00
|
|
|
|
2023-05-30 07:38:10 +00:00
|
|
|
dev_dbg(&pdev->dev, "parent %pOF remote match add %pOF parent %s\n",
|
|
|
|
np, remote, dev_name(&pdev->dev));
|
|
|
|
}
|
2021-10-20 12:39:43 +00:00
|
|
|
|
2019-01-13 09:44:51 +00:00
|
|
|
of_node_put(remote);
|
2021-10-20 12:39:43 +00:00
|
|
|
|
|
|
|
++count;
|
2017-04-04 12:15:23 +00:00
|
|
|
}
|
|
|
|
|
2017-05-29 14:15:52 +00:00
|
|
|
if (count && !match)
|
|
|
|
return meson_drv_bind_master(&pdev->dev, false);
|
|
|
|
|
2017-04-04 12:15:23 +00:00
|
|
|
/* If some endpoints were found, initialize the nodes */
|
|
|
|
if (count) {
|
|
|
|
dev_info(&pdev->dev, "Queued %d outputs on vpu\n", count);
|
|
|
|
|
|
|
|
return component_master_add_with_match(&pdev->dev,
|
|
|
|
&meson_drv_master_ops,
|
|
|
|
match);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If no output endpoints were available, simply bail out */
|
|
|
|
return 0;
|
|
|
|
};
|
|
|
|
|
2023-05-07 16:25:53 +00:00
|
|
|
static void meson_drv_remove(struct platform_device *pdev)
|
2022-09-19 01:09:39 +00:00
|
|
|
{
|
|
|
|
component_master_del(&pdev->dev, &meson_drv_master_ops);
|
|
|
|
}
|
|
|
|
|
drm/meson: Add AFBCD module driver
This adds the driver for the ARM Framebuffer Compression decoders found
in the Amlogic GXM and G12A SoCs.
The Amlogic GXM and G12A AFBC decoder are totally different, the GXM only
handling only the AFBC v1.0 modes and the G12A decoder handling the
AFBC v1.2 modes.
The G12A AFBC decoder is an external IP integrated in the video pipeline,
and the GXM AFBC decoder seems to the an Amlogic custom decoder more
tighly integrated in the video pipeline.
The GXM AFBC decoder can handle only one AFBC plane for 2 available
OSD planes available in HW, and the G12A AFBC decoder can handle up
to 4 AFBC planes for up to 3 OSD planes available in HW.
The Amlogic GXM supports 16x16 SPARSE and 16x16 SPLIT AFBC buffers up
to 4k.
On the other side, for G12A SPLIT is mandatory in 16x16 block mode, but
for 4k modes 32x8+SPLIT AFBC buffers is manadatory for performances reasons.
The RDMA is used here to reset and program the AFBC decoder unit
on each vsync without involving the interrupt handler that can
be masked for a long period of time, producing display glitches.
For this we use the meson_rdma_writel_sync() which adds the register
write tuple (VPU register offset and register value) to the RDMA buffer
and write the value to the HW.
When enabled, the RDMA is enabled to rewrite the same sequence at the
next VSYNC event, until a new buffer is committed to the OSD plane.
Then the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder
doesn't need a reset/reprogram at each vsync, but needs to keep the
vsync interrupt enabled to trigger the RDMA module.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
[narmstrong: fixed typo in commit log]
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-6-narmstrong@baylibre.com
2019-10-21 09:15:05 +00:00
|
|
|
static struct meson_drm_match_data meson_drm_gxbb_data = {
|
|
|
|
.compat = VPU_COMPATIBLE_GXBB,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct meson_drm_match_data meson_drm_gxl_data = {
|
|
|
|
.compat = VPU_COMPATIBLE_GXL,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct meson_drm_match_data meson_drm_gxm_data = {
|
|
|
|
.compat = VPU_COMPATIBLE_GXM,
|
|
|
|
.afbcd_ops = &meson_afbcd_gxm_ops,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct meson_drm_match_data meson_drm_g12a_data = {
|
|
|
|
.compat = VPU_COMPATIBLE_G12A,
|
|
|
|
.afbcd_ops = &meson_afbcd_g12a_ops,
|
|
|
|
};
|
|
|
|
|
2016-11-10 14:29:37 +00:00
|
|
|
static const struct of_device_id dt_match[] = {
|
2019-08-22 14:43:41 +00:00
|
|
|
{ .compatible = "amlogic,meson-gxbb-vpu",
|
drm/meson: Add AFBCD module driver
This adds the driver for the ARM Framebuffer Compression decoders found
in the Amlogic GXM and G12A SoCs.
The Amlogic GXM and G12A AFBC decoder are totally different, the GXM only
handling only the AFBC v1.0 modes and the G12A decoder handling the
AFBC v1.2 modes.
The G12A AFBC decoder is an external IP integrated in the video pipeline,
and the GXM AFBC decoder seems to the an Amlogic custom decoder more
tighly integrated in the video pipeline.
The GXM AFBC decoder can handle only one AFBC plane for 2 available
OSD planes available in HW, and the G12A AFBC decoder can handle up
to 4 AFBC planes for up to 3 OSD planes available in HW.
The Amlogic GXM supports 16x16 SPARSE and 16x16 SPLIT AFBC buffers up
to 4k.
On the other side, for G12A SPLIT is mandatory in 16x16 block mode, but
for 4k modes 32x8+SPLIT AFBC buffers is manadatory for performances reasons.
The RDMA is used here to reset and program the AFBC decoder unit
on each vsync without involving the interrupt handler that can
be masked for a long period of time, producing display glitches.
For this we use the meson_rdma_writel_sync() which adds the register
write tuple (VPU register offset and register value) to the RDMA buffer
and write the value to the HW.
When enabled, the RDMA is enabled to rewrite the same sequence at the
next VSYNC event, until a new buffer is committed to the OSD plane.
Then the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder
doesn't need a reset/reprogram at each vsync, but needs to keep the
vsync interrupt enabled to trigger the RDMA module.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
[narmstrong: fixed typo in commit log]
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-6-narmstrong@baylibre.com
2019-10-21 09:15:05 +00:00
|
|
|
.data = (void *)&meson_drm_gxbb_data },
|
2019-08-22 14:43:41 +00:00
|
|
|
{ .compatible = "amlogic,meson-gxl-vpu",
|
drm/meson: Add AFBCD module driver
This adds the driver for the ARM Framebuffer Compression decoders found
in the Amlogic GXM and G12A SoCs.
The Amlogic GXM and G12A AFBC decoder are totally different, the GXM only
handling only the AFBC v1.0 modes and the G12A decoder handling the
AFBC v1.2 modes.
The G12A AFBC decoder is an external IP integrated in the video pipeline,
and the GXM AFBC decoder seems to the an Amlogic custom decoder more
tighly integrated in the video pipeline.
The GXM AFBC decoder can handle only one AFBC plane for 2 available
OSD planes available in HW, and the G12A AFBC decoder can handle up
to 4 AFBC planes for up to 3 OSD planes available in HW.
The Amlogic GXM supports 16x16 SPARSE and 16x16 SPLIT AFBC buffers up
to 4k.
On the other side, for G12A SPLIT is mandatory in 16x16 block mode, but
for 4k modes 32x8+SPLIT AFBC buffers is manadatory for performances reasons.
The RDMA is used here to reset and program the AFBC decoder unit
on each vsync without involving the interrupt handler that can
be masked for a long period of time, producing display glitches.
For this we use the meson_rdma_writel_sync() which adds the register
write tuple (VPU register offset and register value) to the RDMA buffer
and write the value to the HW.
When enabled, the RDMA is enabled to rewrite the same sequence at the
next VSYNC event, until a new buffer is committed to the OSD plane.
Then the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder
doesn't need a reset/reprogram at each vsync, but needs to keep the
vsync interrupt enabled to trigger the RDMA module.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
[narmstrong: fixed typo in commit log]
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-6-narmstrong@baylibre.com
2019-10-21 09:15:05 +00:00
|
|
|
.data = (void *)&meson_drm_gxl_data },
|
2019-08-22 14:43:41 +00:00
|
|
|
{ .compatible = "amlogic,meson-gxm-vpu",
|
drm/meson: Add AFBCD module driver
This adds the driver for the ARM Framebuffer Compression decoders found
in the Amlogic GXM and G12A SoCs.
The Amlogic GXM and G12A AFBC decoder are totally different, the GXM only
handling only the AFBC v1.0 modes and the G12A decoder handling the
AFBC v1.2 modes.
The G12A AFBC decoder is an external IP integrated in the video pipeline,
and the GXM AFBC decoder seems to the an Amlogic custom decoder more
tighly integrated in the video pipeline.
The GXM AFBC decoder can handle only one AFBC plane for 2 available
OSD planes available in HW, and the G12A AFBC decoder can handle up
to 4 AFBC planes for up to 3 OSD planes available in HW.
The Amlogic GXM supports 16x16 SPARSE and 16x16 SPLIT AFBC buffers up
to 4k.
On the other side, for G12A SPLIT is mandatory in 16x16 block mode, but
for 4k modes 32x8+SPLIT AFBC buffers is manadatory for performances reasons.
The RDMA is used here to reset and program the AFBC decoder unit
on each vsync without involving the interrupt handler that can
be masked for a long period of time, producing display glitches.
For this we use the meson_rdma_writel_sync() which adds the register
write tuple (VPU register offset and register value) to the RDMA buffer
and write the value to the HW.
When enabled, the RDMA is enabled to rewrite the same sequence at the
next VSYNC event, until a new buffer is committed to the OSD plane.
Then the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder
doesn't need a reset/reprogram at each vsync, but needs to keep the
vsync interrupt enabled to trigger the RDMA module.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
[narmstrong: fixed typo in commit log]
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-6-narmstrong@baylibre.com
2019-10-21 09:15:05 +00:00
|
|
|
.data = (void *)&meson_drm_gxm_data },
|
2019-08-22 14:43:41 +00:00
|
|
|
{ .compatible = "amlogic,meson-g12a-vpu",
|
drm/meson: Add AFBCD module driver
This adds the driver for the ARM Framebuffer Compression decoders found
in the Amlogic GXM and G12A SoCs.
The Amlogic GXM and G12A AFBC decoder are totally different, the GXM only
handling only the AFBC v1.0 modes and the G12A decoder handling the
AFBC v1.2 modes.
The G12A AFBC decoder is an external IP integrated in the video pipeline,
and the GXM AFBC decoder seems to the an Amlogic custom decoder more
tighly integrated in the video pipeline.
The GXM AFBC decoder can handle only one AFBC plane for 2 available
OSD planes available in HW, and the G12A AFBC decoder can handle up
to 4 AFBC planes for up to 3 OSD planes available in HW.
The Amlogic GXM supports 16x16 SPARSE and 16x16 SPLIT AFBC buffers up
to 4k.
On the other side, for G12A SPLIT is mandatory in 16x16 block mode, but
for 4k modes 32x8+SPLIT AFBC buffers is manadatory for performances reasons.
The RDMA is used here to reset and program the AFBC decoder unit
on each vsync without involving the interrupt handler that can
be masked for a long period of time, producing display glitches.
For this we use the meson_rdma_writel_sync() which adds the register
write tuple (VPU register offset and register value) to the RDMA buffer
and write the value to the HW.
When enabled, the RDMA is enabled to rewrite the same sequence at the
next VSYNC event, until a new buffer is committed to the OSD plane.
Then the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder
doesn't need a reset/reprogram at each vsync, but needs to keep the
vsync interrupt enabled to trigger the RDMA module.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
[narmstrong: fixed typo in commit log]
Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-6-narmstrong@baylibre.com
2019-10-21 09:15:05 +00:00
|
|
|
.data = (void *)&meson_drm_g12a_data },
|
2016-11-10 14:29:37 +00:00
|
|
|
{}
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, dt_match);
|
|
|
|
|
2019-08-27 09:58:25 +00:00
|
|
|
static const struct dev_pm_ops meson_drv_pm_ops = {
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(meson_drv_pm_suspend, meson_drv_pm_resume)
|
|
|
|
};
|
|
|
|
|
2016-11-10 14:29:37 +00:00
|
|
|
static struct platform_driver meson_drm_platform_driver = {
|
|
|
|
.probe = meson_drv_probe,
|
2023-05-07 16:25:53 +00:00
|
|
|
.remove_new = meson_drv_remove,
|
2021-03-02 04:22:02 +00:00
|
|
|
.shutdown = meson_drv_shutdown,
|
2016-11-10 14:29:37 +00:00
|
|
|
.driver = {
|
2017-02-02 09:47:44 +00:00
|
|
|
.name = "meson-drm",
|
2016-11-10 14:29:37 +00:00
|
|
|
.of_match_table = dt_match,
|
2019-08-27 09:58:25 +00:00
|
|
|
.pm = &meson_drv_pm_ops,
|
2016-11-10 14:29:37 +00:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2021-12-17 00:37:27 +00:00
|
|
|
drm_module_platform_driver(meson_drm_platform_driver);
|
2016-11-10 14:29:37 +00:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Jasper St. Pierre <jstpierre@mecheye.net>");
|
|
|
|
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
|
|
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
|
|
MODULE_LICENSE("GPL");
|