2020-02-25 17:35:34 +00:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2021-01-30 13:08:40 +00:00
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#include <linux/context_tracking.h>
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2020-02-25 17:35:34 +00:00
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#include <linux/err.h>
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2021-02-08 15:10:29 +00:00
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#include <linux/compat.h>
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2021-06-22 12:16:28 +00:00
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#include <linux/sched/debug.h> /* for show_regs */
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2021-02-08 15:10:29 +00:00
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2020-02-25 17:35:34 +00:00
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#include <asm/asm-prototypes.h>
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2020-11-19 12:43:53 +00:00
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#include <asm/kup.h>
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2020-02-25 17:35:34 +00:00
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#include <asm/cputime.h>
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#include <asm/hw_irq.h>
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2021-01-30 13:08:38 +00:00
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#include <asm/interrupt.h>
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2020-02-25 17:35:34 +00:00
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#include <asm/kprobes.h>
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#include <asm/paca.h>
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#include <asm/ptrace.h>
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#include <asm/reg.h>
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#include <asm/signal.h>
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#include <asm/switch_to.h>
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#include <asm/syscall.h>
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#include <asm/time.h>
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powerpc/64s: system call scv tabort fix for corrupt irq soft-mask state
If a system call is made with a transaction active, the kernel
immediately aborts it and returns. scv system calls disable irqs even
earlier in their interrupt handler, and tabort_syscall does not fix this
up.
This can result in irq soft-mask state being messed up on the next
kernel entry, and crashing at BUG_ON(arch_irq_disabled_regs(regs)) in
the kernel exit handlers, or possibly worse.
This can't easily be fixed in asm because at this point an async irq may
have hit, which is soft-masked and marked pending. The pending interrupt
has to be replayed before returning to userspace. The fix is to move the
tabort_syscall code to C in the main syscall handler, and just skip the
system call but otherwise return as usual, which will take care of the
pending irqs. This also does a bunch of other things including possible
signal delivery to the process, but the doomed transaction should still
be aborted when it is eventually returned to.
The sc system call path is changed to use the new C function as well to
reduce code and path differences. This slows down how quickly system
calls are aborted when called while a transaction is active, which could
potentially impact TM performance. But making any system call is already
bad for performance, and TM is on the way out, so go with simpler over
faster.
Fixes: 7fa95f9adaee7 ("powerpc/64s: system call support for scv/rfscv instructions")
Reported-by: Eirik Fuller <efuller@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[mpe: Use #ifdef rather than IS_ENABLED() to fix build error on 32-bit]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210903125707.1601269-1-npiggin@gmail.com
2021-09-03 12:57:06 +00:00
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#include <asm/tm.h>
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2020-02-25 17:35:34 +00:00
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#include <asm/unistd.h>
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2021-03-12 12:50:34 +00:00
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#if defined(CONFIG_PPC_ADV_DEBUG_REGS) && defined(CONFIG_PPC32)
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unsigned long global_dbcr0[NR_CPUS];
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#endif
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2020-02-25 17:35:34 +00:00
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typedef long (*syscall_fn)(long, long, long, long, long, long);
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2021-06-17 15:51:11 +00:00
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#ifdef CONFIG_PPC_BOOK3S_64
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DEFINE_STATIC_KEY_FALSE(interrupt_exit_not_reentrant);
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static inline bool exit_must_hard_disable(void)
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{
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return static_branch_unlikely(&interrupt_exit_not_reentrant);
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}
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2021-06-25 14:31:46 +00:00
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#else
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2021-06-17 15:51:11 +00:00
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static inline bool exit_must_hard_disable(void)
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{
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2021-06-30 07:46:15 +00:00
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return true;
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2021-06-17 15:51:11 +00:00
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}
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#endif
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/*
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* local irqs must be disabled. Returns false if the caller must re-enable
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* them, check for new work, and try again.
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*
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* This should be called with local irqs disabled, but if they were previously
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* enabled when the interrupt handler returns (indicating a process-context /
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* synchronous interrupt) then irqs_enabled should be true.
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2021-06-17 15:51:14 +00:00
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*
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* restartable is true then EE/RI can be left on because interrupts are handled
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* with a restart sequence.
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2021-06-17 15:51:11 +00:00
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*/
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2021-06-17 15:51:15 +00:00
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static notrace __always_inline bool prep_irq_for_enabled_exit(bool restartable)
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2021-06-17 15:51:11 +00:00
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{
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/* This must be done with RI=1 because tracing may touch vmaps */
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trace_hardirqs_on();
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2021-06-17 15:51:14 +00:00
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if (exit_must_hard_disable() || !restartable)
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2021-06-17 15:51:11 +00:00
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__hard_EE_RI_disable();
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2021-06-25 14:31:46 +00:00
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#ifdef CONFIG_PPC64
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2021-06-17 15:51:11 +00:00
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/* This pattern matches prep_irq_for_idle */
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if (unlikely(lazy_irq_pending_nocheck())) {
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2021-06-17 15:51:14 +00:00
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if (exit_must_hard_disable() || !restartable) {
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2021-06-17 15:51:11 +00:00
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local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
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__hard_RI_enable();
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}
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trace_hardirqs_off();
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return false;
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}
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#endif
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return true;
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}
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2020-02-25 17:35:39 +00:00
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/* Has to run notrace because it is entered not completely "reconciled" */
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notrace long system_call_exception(long r3, long r4, long r5,
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long r6, long r7, long r8,
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unsigned long r0, struct pt_regs *regs)
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2020-02-25 17:35:34 +00:00
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{
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syscall_fn f;
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2021-03-12 12:50:47 +00:00
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kuep_lock();
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2021-02-08 15:10:30 +00:00
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regs->orig_gpr3 = r3;
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2020-02-25 17:35:39 +00:00
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if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG))
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BUG_ON(irq_soft_mask_return() != IRQS_ALL_DISABLED);
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2021-03-16 10:41:55 +00:00
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trace_hardirqs_off(); /* finish reconciling */
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2021-01-30 13:08:40 +00:00
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CT_WARN_ON(ct_state() == CONTEXT_KERNEL);
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user_exit_irqoff();
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2021-08-23 08:24:21 +00:00
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BUG_ON(regs_is_unrecoverable(regs));
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2020-02-25 17:35:34 +00:00
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BUG_ON(!(regs->msr & MSR_PR));
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2021-02-08 15:10:28 +00:00
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BUG_ON(arch_irq_disabled_regs(regs));
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2020-02-25 17:35:34 +00:00
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2020-11-27 04:44:12 +00:00
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#ifdef CONFIG_PPC_PKEY
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if (mmu_has_feature(MMU_FTR_PKEY)) {
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unsigned long amr, iamr;
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2020-11-27 04:44:24 +00:00
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bool flush_needed = false;
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2020-11-27 04:44:12 +00:00
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/*
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* When entering from userspace we mostly have the AMR/IAMR
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* different from kernel default values. Hence don't compare.
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*/
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amr = mfspr(SPRN_AMR);
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iamr = mfspr(SPRN_IAMR);
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regs->amr = amr;
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regs->iamr = iamr;
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2020-11-27 04:44:24 +00:00
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if (mmu_has_feature(MMU_FTR_BOOK3S_KUAP)) {
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2020-11-27 04:44:12 +00:00
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mtspr(SPRN_AMR, AMR_KUAP_BLOCKED);
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2020-11-27 04:44:24 +00:00
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flush_needed = true;
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}
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if (mmu_has_feature(MMU_FTR_BOOK3S_KUEP)) {
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2020-11-27 04:44:12 +00:00
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mtspr(SPRN_IAMR, AMR_KUEP_BLOCKED);
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2020-11-27 04:44:24 +00:00
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flush_needed = true;
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}
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if (flush_needed)
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isync();
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2020-11-27 04:44:12 +00:00
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} else
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#endif
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2021-03-12 12:50:48 +00:00
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kuap_assert_locked();
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2020-04-29 06:56:49 +00:00
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2021-02-09 19:29:28 +00:00
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booke_restore_dbcr0();
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2020-02-25 17:35:34 +00:00
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account_cpu_user_entry();
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2021-01-30 13:08:47 +00:00
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account_stolen_time();
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2020-02-25 17:35:34 +00:00
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/*
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* This is not required for the syscall exit path, but makes the
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* stack frame look nicer. If this was initialised in the first stack
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* frame, or if the unwinder was taught the first stack frame always
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* returns to user with IRQS_ENABLED, this store could be avoided!
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*/
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2021-02-08 15:10:28 +00:00
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irq_soft_mask_regs_set_state(regs, IRQS_ENABLED);
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2020-02-25 17:35:34 +00:00
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2021-09-08 10:17:17 +00:00
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/*
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* If system call is called with TM active, set _TIF_RESTOREALL to
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* prevent RFSCV being used to return to userspace, because POWER9
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* TM implementation has problems with this instruction returning to
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* transactional state. Final register values are not relevant because
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* the transaction will be aborted upon return anyway. Or in the case
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* of unsupported_scv SIGILL fault, the return state does not much
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* matter because it's an edge case.
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*/
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if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) &&
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unlikely(MSR_TM_TRANSACTIONAL(regs->msr)))
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2021-11-29 13:06:51 +00:00
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set_bits(_TIF_RESTOREALL, ¤t_thread_info()->flags);
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2021-09-08 10:17:17 +00:00
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powerpc/64s: system call scv tabort fix for corrupt irq soft-mask state
If a system call is made with a transaction active, the kernel
immediately aborts it and returns. scv system calls disable irqs even
earlier in their interrupt handler, and tabort_syscall does not fix this
up.
This can result in irq soft-mask state being messed up on the next
kernel entry, and crashing at BUG_ON(arch_irq_disabled_regs(regs)) in
the kernel exit handlers, or possibly worse.
This can't easily be fixed in asm because at this point an async irq may
have hit, which is soft-masked and marked pending. The pending interrupt
has to be replayed before returning to userspace. The fix is to move the
tabort_syscall code to C in the main syscall handler, and just skip the
system call but otherwise return as usual, which will take care of the
pending irqs. This also does a bunch of other things including possible
signal delivery to the process, but the doomed transaction should still
be aborted when it is eventually returned to.
The sc system call path is changed to use the new C function as well to
reduce code and path differences. This slows down how quickly system
calls are aborted when called while a transaction is active, which could
potentially impact TM performance. But making any system call is already
bad for performance, and TM is on the way out, so go with simpler over
faster.
Fixes: 7fa95f9adaee7 ("powerpc/64s: system call support for scv/rfscv instructions")
Reported-by: Eirik Fuller <efuller@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[mpe: Use #ifdef rather than IS_ENABLED() to fix build error on 32-bit]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210903125707.1601269-1-npiggin@gmail.com
2021-09-03 12:57:06 +00:00
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/*
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* If the system call was made with a transaction active, doom it and
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* return without performing the system call. Unless it was an
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* unsupported scv vector, in which case it's treated like an illegal
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* instruction.
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*/
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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if (unlikely(MSR_TM_TRANSACTIONAL(regs->msr)) &&
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!trap_is_unsupported_scv(regs)) {
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/* Enable TM in the kernel, and disable EE (for scv) */
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hard_irq_disable();
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mtmsr(mfmsr() | MSR_TM);
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/* tabort, this dooms the transaction, nothing else */
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asm volatile(".long 0x7c00071d | ((%0) << 16)"
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:: "r"(TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT));
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/*
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* Userspace will never see the return value. Execution will
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* resume after the tbegin. of the aborted transaction with the
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* checkpointed register state. A context switch could occur
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* or signal delivered to the process before resuming the
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* doomed transaction context, but that should all be handled
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* as expected.
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*/
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return -ENOSYS;
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}
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#endif // CONFIG_PPC_TRANSACTIONAL_MEM
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2020-02-25 17:35:39 +00:00
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local_irq_enable();
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2020-02-25 17:35:34 +00:00
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2021-11-29 13:06:52 +00:00
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if (unlikely(read_thread_flags() & _TIF_SYSCALL_DOTRACE)) {
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2021-02-09 19:29:27 +00:00
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if (unlikely(trap_is_unsupported_scv(regs))) {
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2020-06-11 08:12:03 +00:00
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/* Unsupported scv vector */
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_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
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return regs->gpr[3];
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}
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2020-02-25 17:35:34 +00:00
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/*
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* We use the return value of do_syscall_trace_enter() as the
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* syscall number. If the syscall was rejected for any reason
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* do_syscall_trace_enter() returns an invalid syscall number
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* and the test against NR_syscalls will fail and the return
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* value to be used is in regs->gpr[3].
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*/
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r0 = do_syscall_trace_enter(regs);
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if (unlikely(r0 >= NR_syscalls))
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return regs->gpr[3];
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r3 = regs->gpr[3];
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r4 = regs->gpr[4];
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r5 = regs->gpr[5];
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r6 = regs->gpr[6];
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r7 = regs->gpr[7];
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r8 = regs->gpr[8];
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} else if (unlikely(r0 >= NR_syscalls)) {
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2021-02-09 19:29:27 +00:00
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if (unlikely(trap_is_unsupported_scv(regs))) {
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2020-06-11 08:12:03 +00:00
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/* Unsupported scv vector */
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_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
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return regs->gpr[3];
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}
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2020-02-25 17:35:34 +00:00
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return -ENOSYS;
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}
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/* May be faster to do array_index_nospec? */
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barrier_nospec();
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2021-02-08 15:10:29 +00:00
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if (unlikely(is_compat_task())) {
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2020-02-25 17:35:34 +00:00
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f = (void *)compat_sys_call_table[r0];
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r3 &= 0x00000000ffffffffULL;
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r4 &= 0x00000000ffffffffULL;
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r5 &= 0x00000000ffffffffULL;
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r6 &= 0x00000000ffffffffULL;
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r7 &= 0x00000000ffffffffULL;
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r8 &= 0x00000000ffffffffULL;
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} else {
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f = (void *)sys_call_table[r0];
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}
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return f(r3, r4, r5, r6, r7, r8);
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}
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2021-02-09 19:29:28 +00:00
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static notrace void booke_load_dbcr0(void)
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{
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#ifdef CONFIG_PPC_ADV_DEBUG_REGS
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unsigned long dbcr0 = current->thread.debug.dbcr0;
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|
|
|
|
|
|
if (likely(!(dbcr0 & DBCR0_IDM)))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Check to see if the dbcr0 register is set up to debug.
|
|
|
|
|
* Use the internal debug mode bit to do this.
|
|
|
|
|
*/
|
|
|
|
|
mtmsr(mfmsr() & ~MSR_DE);
|
|
|
|
|
if (IS_ENABLED(CONFIG_PPC32)) {
|
|
|
|
|
isync();
|
|
|
|
|
global_dbcr0[smp_processor_id()] = mfspr(SPRN_DBCR0);
|
|
|
|
|
}
|
|
|
|
|
mtspr(SPRN_DBCR0, dbcr0);
|
|
|
|
|
mtspr(SPRN_DBSR, -1);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
2021-06-22 12:16:28 +00:00
|
|
|
static void check_return_regs_valid(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
|
|
|
|
unsigned long trap, srr0, srr1;
|
|
|
|
|
static bool warned;
|
|
|
|
|
u8 *validp;
|
|
|
|
|
char *h;
|
|
|
|
|
|
2021-06-25 14:49:09 +00:00
|
|
|
if (trap_is_scv(regs))
|
2021-06-22 12:16:28 +00:00
|
|
|
return;
|
|
|
|
|
|
2021-10-26 12:25:31 +00:00
|
|
|
trap = TRAP(regs);
|
2021-06-22 12:16:28 +00:00
|
|
|
// EE in HV mode sets HSRRs like 0xea0
|
2021-06-25 14:49:09 +00:00
|
|
|
if (cpu_has_feature(CPU_FTR_HVMODE) && trap == INTERRUPT_EXTERNAL)
|
2021-06-22 12:16:28 +00:00
|
|
|
trap = 0xea0;
|
|
|
|
|
|
|
|
|
|
switch (trap) {
|
|
|
|
|
case 0x980:
|
|
|
|
|
case INTERRUPT_H_DATA_STORAGE:
|
|
|
|
|
case 0xe20:
|
|
|
|
|
case 0xe40:
|
|
|
|
|
case INTERRUPT_HMI:
|
|
|
|
|
case 0xe80:
|
|
|
|
|
case 0xea0:
|
|
|
|
|
case INTERRUPT_H_FAC_UNAVAIL:
|
|
|
|
|
case 0x1200:
|
|
|
|
|
case 0x1500:
|
|
|
|
|
case 0x1600:
|
|
|
|
|
case 0x1800:
|
|
|
|
|
validp = &local_paca->hsrr_valid;
|
|
|
|
|
if (!*validp)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
srr0 = mfspr(SPRN_HSRR0);
|
|
|
|
|
srr1 = mfspr(SPRN_HSRR1);
|
|
|
|
|
h = "H";
|
|
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
validp = &local_paca->srr_valid;
|
|
|
|
|
if (!*validp)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
srr0 = mfspr(SPRN_SRR0);
|
|
|
|
|
srr1 = mfspr(SPRN_SRR1);
|
|
|
|
|
h = "";
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (srr0 == regs->nip && srr1 == regs->msr)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* A NMI / soft-NMI interrupt may have come in after we found
|
|
|
|
|
* srr_valid and before the SRRs are loaded. The interrupt then
|
|
|
|
|
* comes in and clobbers SRRs and clears srr_valid. Then we load
|
|
|
|
|
* the SRRs here and test them above and find they don't match.
|
|
|
|
|
*
|
|
|
|
|
* Test validity again after that, to catch such false positives.
|
|
|
|
|
*
|
|
|
|
|
* This test in general will have some window for false negatives
|
|
|
|
|
* and may not catch and fix all such cases if an NMI comes in
|
|
|
|
|
* later and clobbers SRRs without clearing srr_valid, but hopefully
|
|
|
|
|
* such things will get caught most of the time, statistically
|
|
|
|
|
* enough to be able to get a warning out.
|
|
|
|
|
*/
|
|
|
|
|
barrier();
|
|
|
|
|
|
|
|
|
|
if (!*validp)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
if (!warned) {
|
|
|
|
|
warned = true;
|
|
|
|
|
printk("%sSRR0 was: %lx should be: %lx\n", h, srr0, regs->nip);
|
|
|
|
|
printk("%sSRR1 was: %lx should be: %lx\n", h, srr1, regs->msr);
|
|
|
|
|
show_regs(regs);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
*validp = 0; /* fixup */
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
2021-06-17 15:51:12 +00:00
|
|
|
static notrace unsigned long
|
|
|
|
|
interrupt_exit_user_prepare_main(unsigned long ret, struct pt_regs *regs)
|
2020-02-25 17:35:34 +00:00
|
|
|
{
|
|
|
|
|
unsigned long ti_flags;
|
2021-01-30 13:08:11 +00:00
|
|
|
|
2021-01-30 13:08:45 +00:00
|
|
|
again:
|
2021-11-29 13:06:52 +00:00
|
|
|
ti_flags = read_thread_flags();
|
2020-02-25 17:35:34 +00:00
|
|
|
while (unlikely(ti_flags & (_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM))) {
|
|
|
|
|
local_irq_enable();
|
|
|
|
|
if (ti_flags & _TIF_NEED_RESCHED) {
|
|
|
|
|
schedule();
|
|
|
|
|
} else {
|
|
|
|
|
/*
|
|
|
|
|
* SIGPENDING must restore signal handler function
|
|
|
|
|
* argument GPRs, and some non-volatiles (e.g., r1).
|
|
|
|
|
* Restore all for now. This could be made lighter.
|
|
|
|
|
*/
|
|
|
|
|
if (ti_flags & _TIF_SIGPENDING)
|
|
|
|
|
ret |= _TIF_RESTOREALL;
|
|
|
|
|
do_notify_resume(regs, ti_flags);
|
|
|
|
|
}
|
|
|
|
|
local_irq_disable();
|
2021-11-29 13:06:52 +00:00
|
|
|
ti_flags = read_thread_flags();
|
2020-02-25 17:35:34 +00:00
|
|
|
}
|
|
|
|
|
|
2021-06-17 15:51:00 +00:00
|
|
|
if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && IS_ENABLED(CONFIG_PPC_FPU)) {
|
2020-02-25 17:35:34 +00:00
|
|
|
if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) &&
|
|
|
|
|
unlikely((ti_flags & _TIF_RESTORE_TM))) {
|
|
|
|
|
restore_tm_state(regs);
|
|
|
|
|
} else {
|
|
|
|
|
unsigned long mathflags = MSR_FP;
|
|
|
|
|
|
|
|
|
|
if (cpu_has_feature(CPU_FTR_VSX))
|
|
|
|
|
mathflags |= MSR_VEC | MSR_VSX;
|
|
|
|
|
else if (cpu_has_feature(CPU_FTR_ALTIVEC))
|
|
|
|
|
mathflags |= MSR_VEC;
|
|
|
|
|
|
powerpc/64s: Fix restore_math unnecessarily changing MSR
Before returning to user, if there are missing FP/VEC/VSX bits from the
user MSR then those registers had been saved and must be restored again
before use. restore_math will decide whether to restore immediately, or
skip the restore and let fp/vec/vsx unavailable faults demand load the
registers.
Each time restore_math restores one of the FP/VSX or VEC register sets
is loaded, an 8-bit counter is incremented (load_fp and load_vec). When
these wrap to zero, restore_math no longer restores that register set
until after they are next demand faulted.
It's quite usual for those counters to have different values, so if one
wraps to zero and restore_math no longer restores its registers or user
MSR bit but the other is not zero yet does not need to be restored
(because the kernel is not frequently using the FPU), then restore_math
will be called and it will also not return in the early exit check.
This causes msr_check_and_set to test and set the MSR at every kernel
exit despite having no work to do.
This can cause workloads (e.g., a NULL syscall microbenchmark) to run
fast for a time while both counters are non-zero, then slow down when
one of the counters reaches zero, then speed up again after the second
counter reaches zero. The cost is significant, about 10% slowdown on a
NULL syscall benchmark, and the jittery behaviour is very undesirable.
Fix this by having restore_math test all conditions first, and only
update MSR if we will be loading registers.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200623234139.2262227-2-npiggin@gmail.com
2020-06-23 23:41:38 +00:00
|
|
|
/*
|
|
|
|
|
* If userspace MSR has all available FP bits set,
|
|
|
|
|
* then they are live and no need to restore. If not,
|
|
|
|
|
* it means the regs were given up and restore_math
|
|
|
|
|
* may decide to restore them (to avoid taking an FP
|
|
|
|
|
* fault).
|
|
|
|
|
*/
|
2020-02-25 17:35:34 +00:00
|
|
|
if ((regs->msr & mathflags) != mathflags)
|
|
|
|
|
restore_math(regs);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2021-06-22 12:16:28 +00:00
|
|
|
check_return_regs_valid(regs);
|
|
|
|
|
|
2021-06-17 15:51:16 +00:00
|
|
|
user_enter_irqoff();
|
|
|
|
|
if (!prep_irq_for_enabled_exit(true)) {
|
|
|
|
|
user_exit_irqoff();
|
2021-01-30 13:08:40 +00:00
|
|
|
local_irq_enable();
|
2021-01-30 13:08:45 +00:00
|
|
|
local_irq_disable();
|
2020-02-25 17:35:34 +00:00
|
|
|
goto again;
|
2021-01-30 13:08:40 +00:00
|
|
|
}
|
2020-02-25 17:35:34 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
|
|
|
|
local_paca->tm_scratch = regs->msr;
|
|
|
|
|
#endif
|
|
|
|
|
|
2021-02-09 19:29:28 +00:00
|
|
|
booke_load_dbcr0();
|
|
|
|
|
|
2020-02-25 17:35:34 +00:00
|
|
|
account_cpu_user_exit();
|
|
|
|
|
|
2021-03-16 10:41:57 +00:00
|
|
|
/* Restore user access locks last */
|
2020-11-27 04:44:12 +00:00
|
|
|
kuap_user_restore(regs);
|
2021-03-12 12:50:47 +00:00
|
|
|
kuep_unlock();
|
|
|
|
|
|
2020-02-25 17:35:34 +00:00
|
|
|
return ret;
|
|
|
|
|
}
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
|
2021-06-17 15:51:11 +00:00
|
|
|
/*
|
|
|
|
|
* This should be called after a syscall returns, with r3 the return value
|
|
|
|
|
* from the syscall. If this function returns non-zero, the system call
|
|
|
|
|
* exit assembly should additionally load all GPR registers and CTR and XER
|
|
|
|
|
* from the interrupt frame.
|
|
|
|
|
*
|
|
|
|
|
* The function graph tracer can not trace the return side of this function,
|
|
|
|
|
* because RI=0 and soft mask state is "unreconciled", so it is marked notrace.
|
|
|
|
|
*/
|
|
|
|
|
notrace unsigned long syscall_exit_prepare(unsigned long r3,
|
|
|
|
|
struct pt_regs *regs,
|
|
|
|
|
long scv)
|
|
|
|
|
{
|
|
|
|
|
unsigned long ti_flags;
|
|
|
|
|
unsigned long ret = 0;
|
|
|
|
|
bool is_not_scv = !IS_ENABLED(CONFIG_PPC_BOOK3S_64) || !scv;
|
|
|
|
|
|
|
|
|
|
CT_WARN_ON(ct_state() == CONTEXT_USER);
|
|
|
|
|
|
|
|
|
|
kuap_assert_locked();
|
|
|
|
|
|
|
|
|
|
regs->result = r3;
|
|
|
|
|
|
|
|
|
|
/* Check whether the syscall is issued inside a restartable sequence */
|
|
|
|
|
rseq_syscall(regs);
|
|
|
|
|
|
2021-11-29 13:06:52 +00:00
|
|
|
ti_flags = read_thread_flags();
|
2021-06-17 15:51:11 +00:00
|
|
|
|
|
|
|
|
if (unlikely(r3 >= (unsigned long)-MAX_ERRNO) && is_not_scv) {
|
|
|
|
|
if (likely(!(ti_flags & (_TIF_NOERROR | _TIF_RESTOREALL)))) {
|
|
|
|
|
r3 = -r3;
|
|
|
|
|
regs->ccr |= 0x10000000; /* Set SO bit in CR */
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (unlikely(ti_flags & _TIF_PERSYSCALL_MASK)) {
|
|
|
|
|
if (ti_flags & _TIF_RESTOREALL)
|
|
|
|
|
ret = _TIF_RESTOREALL;
|
|
|
|
|
else
|
|
|
|
|
regs->gpr[3] = r3;
|
|
|
|
|
clear_bits(_TIF_PERSYSCALL_MASK, ¤t_thread_info()->flags);
|
|
|
|
|
} else {
|
|
|
|
|
regs->gpr[3] = r3;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (unlikely(ti_flags & _TIF_SYSCALL_DOTRACE)) {
|
|
|
|
|
do_syscall_trace_leave(regs);
|
|
|
|
|
ret |= _TIF_RESTOREALL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
local_irq_disable();
|
2021-06-17 15:51:12 +00:00
|
|
|
ret = interrupt_exit_user_prepare_main(ret, regs);
|
2021-06-17 15:51:11 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
regs->exit_result = ret;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
notrace unsigned long syscall_exit_restart(unsigned long r3, struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
/*
|
|
|
|
|
* This is called when detecting a soft-pending interrupt as well as
|
|
|
|
|
* an alternate-return interrupt. So we can't just have the alternate
|
|
|
|
|
* return path clear SRR1[MSR] and set PACA_IRQ_HARD_DIS (unless
|
|
|
|
|
* the soft-pending case were to fix things up as well). RI might be
|
|
|
|
|
* disabled, in which case it gets re-enabled by __hard_irq_disable().
|
|
|
|
|
*/
|
|
|
|
|
__hard_irq_disable();
|
|
|
|
|
local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
|
|
|
|
set_kuap(AMR_KUAP_BLOCKED);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
trace_hardirqs_off();
|
|
|
|
|
user_exit_irqoff();
|
|
|
|
|
account_cpu_user_entry();
|
|
|
|
|
|
|
|
|
|
BUG_ON(!user_mode(regs));
|
|
|
|
|
|
2021-06-17 15:51:12 +00:00
|
|
|
regs->exit_result = interrupt_exit_user_prepare_main(regs->exit_result, regs);
|
2021-06-17 15:51:11 +00:00
|
|
|
|
|
|
|
|
return regs->exit_result;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2021-06-17 15:51:01 +00:00
|
|
|
notrace unsigned long interrupt_exit_user_prepare(struct pt_regs *regs)
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
{
|
2021-06-17 15:51:13 +00:00
|
|
|
unsigned long ret;
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
|
2021-08-23 08:24:21 +00:00
|
|
|
BUG_ON(regs_is_unrecoverable(regs));
|
2021-02-08 15:10:28 +00:00
|
|
|
BUG_ON(arch_irq_disabled_regs(regs));
|
2021-01-30 13:08:45 +00:00
|
|
|
CT_WARN_ON(ct_state() == CONTEXT_USER);
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
|
2020-04-29 06:56:51 +00:00
|
|
|
/*
|
|
|
|
|
* We don't need to restore AMR on the way back to userspace for KUAP.
|
|
|
|
|
* AMR can only have been unlocked if we interrupted the kernel.
|
|
|
|
|
*/
|
2021-03-12 12:50:48 +00:00
|
|
|
kuap_assert_locked();
|
2020-04-29 06:56:49 +00:00
|
|
|
|
2021-06-17 15:51:13 +00:00
|
|
|
local_irq_disable();
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
|
2021-06-17 15:51:13 +00:00
|
|
|
ret = interrupt_exit_user_prepare_main(0, regs);
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
|
2021-06-17 15:51:11 +00:00
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
regs->exit_result = ret;
|
|
|
|
|
#endif
|
|
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void preempt_schedule_irq(void);
|
|
|
|
|
|
2021-06-17 15:51:01 +00:00
|
|
|
notrace unsigned long interrupt_exit_kernel_prepare(struct pt_regs *regs)
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
{
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
unsigned long ret = 0;
|
2021-03-12 12:50:48 +00:00
|
|
|
unsigned long kuap;
|
2021-11-29 13:06:52 +00:00
|
|
|
bool stack_store = read_thread_flags() & _TIF_EMULATE_STACK_STORE;
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
|
2021-08-23 08:24:21 +00:00
|
|
|
if (regs_is_unrecoverable(regs))
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
unrecoverable_exception(regs);
|
2021-01-30 13:08:45 +00:00
|
|
|
/*
|
|
|
|
|
* CT_WARN_ON comes here via program_check_exception,
|
|
|
|
|
* so avoid recursion.
|
|
|
|
|
*/
|
2021-04-14 11:00:33 +00:00
|
|
|
if (TRAP(regs) != INTERRUPT_PROGRAM)
|
2021-01-30 13:08:45 +00:00
|
|
|
CT_WARN_ON(ct_state() == CONTEXT_USER);
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
|
2021-03-12 12:50:48 +00:00
|
|
|
kuap = kuap_get_and_assert_locked();
|
2020-04-29 06:56:49 +00:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
local_irq_save(flags);
|
|
|
|
|
|
2021-02-08 15:10:28 +00:00
|
|
|
if (!arch_irq_disabled_regs(regs)) {
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
/* Returning to a kernel context with local irqs enabled. */
|
|
|
|
|
WARN_ON_ONCE(!(regs->msr & MSR_EE));
|
|
|
|
|
again:
|
|
|
|
|
if (IS_ENABLED(CONFIG_PREEMPT)) {
|
|
|
|
|
/* Return to preemptible kernel context */
|
2021-11-29 13:06:52 +00:00
|
|
|
if (unlikely(read_thread_flags() & _TIF_NEED_RESCHED)) {
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
if (preempt_count() == 0)
|
|
|
|
|
preempt_schedule_irq();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2021-06-22 12:16:28 +00:00
|
|
|
check_return_regs_valid(regs);
|
|
|
|
|
|
2021-06-17 15:51:11 +00:00
|
|
|
/*
|
|
|
|
|
* Stack store exit can't be restarted because the interrupt
|
|
|
|
|
* stack frame might have been clobbered.
|
|
|
|
|
*/
|
2021-06-17 15:51:15 +00:00
|
|
|
if (!prep_irq_for_enabled_exit(unlikely(stack_store))) {
|
2021-06-17 15:51:11 +00:00
|
|
|
/*
|
|
|
|
|
* Replay pending soft-masked interrupts now. Don't
|
|
|
|
|
* just local_irq_enabe(); local_irq_disable(); because
|
|
|
|
|
* if we are returning from an asynchronous interrupt
|
|
|
|
|
* here, another one might hit after irqs are enabled,
|
|
|
|
|
* and it would exit via this same path allowing
|
|
|
|
|
* another to fire, and so on unbounded.
|
|
|
|
|
*/
|
|
|
|
|
hard_irq_disable();
|
|
|
|
|
replay_soft_interrupts();
|
|
|
|
|
/* Took an interrupt, may have more exit work to do. */
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
goto again;
|
2021-06-17 15:51:11 +00:00
|
|
|
}
|
2021-02-08 15:10:28 +00:00
|
|
|
#ifdef CONFIG_PPC64
|
2021-06-17 15:51:11 +00:00
|
|
|
/*
|
|
|
|
|
* An interrupt may clear MSR[EE] and set this concurrently,
|
|
|
|
|
* but it will be marked pending and the exit will be retried.
|
|
|
|
|
* This leaves a racy window where MSR[EE]=0 and HARD_DIS is
|
|
|
|
|
* clear, until interrupt_exit_kernel_restart() calls
|
|
|
|
|
* hard_irq_disable(), which will set HARD_DIS again.
|
|
|
|
|
*/
|
|
|
|
|
local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS;
|
|
|
|
|
|
|
|
|
|
} else {
|
2021-06-22 12:16:28 +00:00
|
|
|
check_return_regs_valid(regs);
|
|
|
|
|
|
2021-06-17 15:51:11 +00:00
|
|
|
if (unlikely(stack_store))
|
|
|
|
|
__hard_EE_RI_disable();
|
|
|
|
|
/*
|
|
|
|
|
* Returning to a kernel context with local irqs disabled.
|
|
|
|
|
* Here, if EE was enabled in the interrupted context, enable
|
|
|
|
|
* it on return as well. A problem exists here where a soft
|
|
|
|
|
* masked interrupt may have cleared MSR[EE] and set HARD_DIS
|
|
|
|
|
* here, and it will still exist on return to the caller. This
|
|
|
|
|
* will be resolved by the masked interrupt firing again.
|
|
|
|
|
*/
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
if (regs->msr & MSR_EE)
|
|
|
|
|
local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS;
|
2021-06-17 15:51:11 +00:00
|
|
|
#endif /* CONFIG_PPC64 */
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
}
|
|
|
|
|
|
2021-06-17 15:51:11 +00:00
|
|
|
if (unlikely(stack_store)) {
|
|
|
|
|
clear_bits(_TIF_EMULATE_STACK_STORE, ¤t_thread_info()->flags);
|
|
|
|
|
ret = 1;
|
|
|
|
|
}
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
|
|
|
|
local_paca->tm_scratch = regs->msr;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/*
|
2021-03-16 10:41:57 +00:00
|
|
|
* 64s does not want to mfspr(SPRN_AMR) here, because this comes after
|
|
|
|
|
* mtmsr, which would cause Read-After-Write stalls. Hence, take the
|
|
|
|
|
* AMR value from the check above.
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
*/
|
2021-03-12 12:50:48 +00:00
|
|
|
kuap_kernel_restore(regs, kuap);
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-25 17:35:37 +00:00
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
2021-06-17 15:51:11 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
notrace unsigned long interrupt_exit_user_restart(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
__hard_irq_disable();
|
|
|
|
|
local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
|
|
|
|
set_kuap(AMR_KUAP_BLOCKED);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
trace_hardirqs_off();
|
|
|
|
|
user_exit_irqoff();
|
|
|
|
|
account_cpu_user_entry();
|
|
|
|
|
|
|
|
|
|
BUG_ON(!user_mode(regs));
|
|
|
|
|
|
|
|
|
|
regs->exit_result |= interrupt_exit_user_prepare(regs);
|
|
|
|
|
|
|
|
|
|
return regs->exit_result;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* No real need to return a value here because the stack store case does not
|
|
|
|
|
* get restarted.
|
|
|
|
|
*/
|
|
|
|
|
notrace unsigned long interrupt_exit_kernel_restart(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
__hard_irq_disable();
|
|
|
|
|
local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
|
|
|
|
set_kuap(AMR_KUAP_BLOCKED);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
if (regs->softe == IRQS_ENABLED)
|
|
|
|
|
trace_hardirqs_off();
|
|
|
|
|
|
|
|
|
|
BUG_ON(user_mode(regs));
|
|
|
|
|
|
|
|
|
|
return interrupt_exit_kernel_prepare(regs);
|
|
|
|
|
}
|
|
|
|
|
#endif
|