2013-11-15 15:06:05 +00:00
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/*
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* Copyright (C) 2013 NVIDIA Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of_gpio.h>
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2016-06-29 09:17:55 +00:00
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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2017-10-12 15:32:52 +00:00
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#include <linux/pm_runtime.h>
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2013-11-15 15:06:05 +00:00
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/regulator/consumer.h>
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2014-04-25 14:42:32 +00:00
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#include <linux/workqueue.h>
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2013-11-15 15:06:05 +00:00
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_panel.h>
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#include "dpaux.h"
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#include "drm.h"
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2017-08-15 13:41:13 +00:00
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#include "trace.h"
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2013-11-15 15:06:05 +00:00
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static DEFINE_MUTEX(dpaux_lock);
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static LIST_HEAD(dpaux_list);
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struct tegra_dpaux {
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struct drm_dp_aux aux;
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struct device *dev;
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void __iomem *regs;
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int irq;
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struct tegra_output *output;
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struct reset_control *rst;
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struct clk *clk_parent;
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struct clk *clk;
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struct regulator *vdd;
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struct completion complete;
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2014-04-25 14:42:32 +00:00
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struct work_struct work;
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2013-11-15 15:06:05 +00:00
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struct list_head list;
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2016-06-29 09:17:55 +00:00
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#ifdef CONFIG_GENERIC_PINCONF
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struct pinctrl_dev *pinctrl;
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struct pinctrl_desc desc;
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#endif
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2013-11-15 15:06:05 +00:00
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};
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static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
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{
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return container_of(aux, struct tegra_dpaux, aux);
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}
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2014-04-25 14:42:32 +00:00
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static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
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{
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return container_of(work, struct tegra_dpaux, work);
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}
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2015-06-02 11:13:01 +00:00
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static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
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2017-08-15 13:41:06 +00:00
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unsigned int offset)
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2013-11-15 15:06:05 +00:00
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{
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2017-08-15 13:41:13 +00:00
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u32 value = readl(dpaux->regs + (offset << 2));
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trace_dpaux_readl(dpaux->dev, offset, value);
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return value;
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2013-11-15 15:06:05 +00:00
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}
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static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
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2017-08-15 13:41:06 +00:00
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u32 value, unsigned int offset)
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2013-11-15 15:06:05 +00:00
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{
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2017-08-15 13:41:13 +00:00
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trace_dpaux_writel(dpaux->dev, offset, value);
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2013-11-15 15:06:05 +00:00
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writel(value, dpaux->regs + (offset << 2));
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}
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static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
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size_t size)
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{
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size_t i, j;
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2015-06-11 16:33:48 +00:00
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for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
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size_t num = min_t(size_t, size - i * 4, 4);
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2015-06-02 11:13:01 +00:00
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u32 value = 0;
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2013-11-15 15:06:05 +00:00
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for (j = 0; j < num; j++)
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2015-06-11 16:33:48 +00:00
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value |= buffer[i * 4 + j] << (j * 8);
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2013-11-15 15:06:05 +00:00
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2015-06-11 16:33:48 +00:00
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tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
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2013-11-15 15:06:05 +00:00
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}
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}
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static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
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size_t size)
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{
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size_t i, j;
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2015-06-11 16:33:48 +00:00
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for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
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size_t num = min_t(size_t, size - i * 4, 4);
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2015-06-02 11:13:01 +00:00
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u32 value;
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2013-11-15 15:06:05 +00:00
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2015-06-11 16:33:48 +00:00
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value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
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2013-11-15 15:06:05 +00:00
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for (j = 0; j < num; j++)
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2015-06-11 16:33:48 +00:00
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buffer[i * 4 + j] = value >> (j * 8);
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2013-11-15 15:06:05 +00:00
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}
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}
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static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
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struct drm_dp_aux_msg *msg)
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{
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unsigned long timeout = msecs_to_jiffies(250);
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struct tegra_dpaux *dpaux = to_dpaux(aux);
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unsigned long status;
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ssize_t ret = 0;
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2014-04-07 08:37:44 +00:00
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u32 value;
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2013-11-15 15:06:05 +00:00
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2014-04-07 08:37:44 +00:00
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/* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
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if (msg->size > 16)
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2013-11-15 15:06:05 +00:00
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return -EINVAL;
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2014-04-07 08:37:44 +00:00
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/*
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* Allow zero-sized messages only for I2C, in which case they specify
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* address-only transactions.
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*/
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if (msg->size < 1) {
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switch (msg->request & ~DP_AUX_I2C_MOT) {
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2015-08-27 14:23:29 +00:00
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case DP_AUX_I2C_WRITE_STATUS_UPDATE:
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2014-04-07 08:37:44 +00:00
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case DP_AUX_I2C_WRITE:
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case DP_AUX_I2C_READ:
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value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
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break;
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default:
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return -EINVAL;
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}
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} else {
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/* For non-zero-sized messages, set the CMDLEN field. */
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value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
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}
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2013-11-15 15:06:05 +00:00
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switch (msg->request & ~DP_AUX_I2C_MOT) {
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case DP_AUX_I2C_WRITE:
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if (msg->request & DP_AUX_I2C_MOT)
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2014-04-07 08:37:44 +00:00
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value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
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2013-11-15 15:06:05 +00:00
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else
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2014-04-07 08:37:44 +00:00
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value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
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2013-11-15 15:06:05 +00:00
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break;
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case DP_AUX_I2C_READ:
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if (msg->request & DP_AUX_I2C_MOT)
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2014-04-07 08:37:44 +00:00
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value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
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2013-11-15 15:06:05 +00:00
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else
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2014-04-07 08:37:44 +00:00
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value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
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2013-11-15 15:06:05 +00:00
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break;
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2015-08-27 14:23:26 +00:00
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case DP_AUX_I2C_WRITE_STATUS_UPDATE:
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2013-11-15 15:06:05 +00:00
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if (msg->request & DP_AUX_I2C_MOT)
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2014-04-07 08:37:44 +00:00
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value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
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2013-11-15 15:06:05 +00:00
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else
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2014-04-07 08:37:44 +00:00
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value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
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2013-11-15 15:06:05 +00:00
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break;
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case DP_AUX_NATIVE_WRITE:
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2014-04-07 08:37:44 +00:00
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value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
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2013-11-15 15:06:05 +00:00
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break;
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case DP_AUX_NATIVE_READ:
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2014-04-07 08:37:44 +00:00
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value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
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2013-11-15 15:06:05 +00:00
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break;
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default:
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return -EINVAL;
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}
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2014-04-07 08:37:44 +00:00
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tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
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2013-11-15 15:06:05 +00:00
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tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
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if ((msg->request & DP_AUX_I2C_READ) == 0) {
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tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
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ret = msg->size;
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}
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/* start transaction */
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value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
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value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
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tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
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status = wait_for_completion_timeout(&dpaux->complete, timeout);
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if (!status)
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return -ETIMEDOUT;
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/* read status and clear errors */
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value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
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tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
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if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
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return -ETIMEDOUT;
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if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
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(value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
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(value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
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return -EIO;
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switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
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case 0x00:
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msg->reply = DP_AUX_NATIVE_REPLY_ACK;
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break;
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case 0x01:
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msg->reply = DP_AUX_NATIVE_REPLY_NACK;
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break;
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case 0x02:
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msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
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break;
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case 0x04:
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msg->reply = DP_AUX_I2C_REPLY_NACK;
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break;
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case 0x08:
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msg->reply = DP_AUX_I2C_REPLY_DEFER;
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break;
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}
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2014-04-07 08:37:44 +00:00
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if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
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2013-11-15 15:06:05 +00:00
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if (msg->request & DP_AUX_I2C_READ) {
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size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
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if (WARN_ON(count != msg->size))
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count = min_t(size_t, count, msg->size);
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tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
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ret = count;
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}
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}
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return ret;
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}
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2014-04-25 14:42:32 +00:00
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static void tegra_dpaux_hotplug(struct work_struct *work)
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{
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struct tegra_dpaux *dpaux = work_to_dpaux(work);
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if (dpaux->output)
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drm_helper_hpd_irq_event(dpaux->output->connector.dev);
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}
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2013-11-15 15:06:05 +00:00
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static irqreturn_t tegra_dpaux_irq(int irq, void *data)
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{
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struct tegra_dpaux *dpaux = data;
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irqreturn_t ret = IRQ_HANDLED;
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2015-06-02 11:13:01 +00:00
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u32 value;
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2013-11-15 15:06:05 +00:00
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/* clear interrupts */
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value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
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tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
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2014-04-25 14:42:32 +00:00
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if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
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schedule_work(&dpaux->work);
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2013-11-15 15:06:05 +00:00
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if (value & DPAUX_INTR_IRQ_EVENT) {
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/* TODO: handle this */
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}
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if (value & DPAUX_INTR_AUX_DONE)
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complete(&dpaux->complete);
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return ret;
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}
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2016-06-29 09:17:55 +00:00
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enum tegra_dpaux_functions {
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DPAUX_PADCTL_FUNC_AUX,
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DPAUX_PADCTL_FUNC_I2C,
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DPAUX_PADCTL_FUNC_OFF,
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};
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2016-06-29 09:17:49 +00:00
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static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
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{
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u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
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value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
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tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
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}
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static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)
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{
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u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
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value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
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tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
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}
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static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
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{
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u32 value;
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switch (function) {
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2016-06-29 09:17:55 +00:00
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case DPAUX_PADCTL_FUNC_AUX:
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2016-06-29 09:17:49 +00:00
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value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
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DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
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DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
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|
|
DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
|
|
|
|
DPAUX_HYBRID_PADCTL_MODE_AUX;
|
|
|
|
break;
|
|
|
|
|
2016-06-29 09:17:55 +00:00
|
|
|
case DPAUX_PADCTL_FUNC_I2C:
|
2016-06-29 09:17:49 +00:00
|
|
|
value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
|
|
|
|
DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
|
2017-12-14 12:25:37 +00:00
|
|
|
DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
|
|
|
|
DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
|
|
|
|
DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
|
2016-06-29 09:17:49 +00:00
|
|
|
DPAUX_HYBRID_PADCTL_MODE_I2C;
|
|
|
|
break;
|
|
|
|
|
2016-06-29 09:17:55 +00:00
|
|
|
case DPAUX_PADCTL_FUNC_OFF:
|
|
|
|
tegra_dpaux_pad_power_down(dpaux);
|
|
|
|
return 0;
|
|
|
|
|
2016-06-29 09:17:49 +00:00
|
|
|
default:
|
|
|
|
return -ENOTSUPP;
|
|
|
|
}
|
|
|
|
|
|
|
|
tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
|
|
|
|
tegra_dpaux_pad_power_up(dpaux);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-06-29 09:17:55 +00:00
|
|
|
#ifdef CONFIG_GENERIC_PINCONF
|
|
|
|
static const struct pinctrl_pin_desc tegra_dpaux_pins[] = {
|
|
|
|
PINCTRL_PIN(0, "DP_AUX_CHx_P"),
|
|
|
|
PINCTRL_PIN(1, "DP_AUX_CHx_N"),
|
|
|
|
};
|
|
|
|
|
|
|
|
static const unsigned tegra_dpaux_pin_numbers[] = { 0, 1 };
|
|
|
|
|
|
|
|
static const char * const tegra_dpaux_groups[] = {
|
|
|
|
"dpaux-io",
|
|
|
|
};
|
|
|
|
|
|
|
|
static const char * const tegra_dpaux_functions[] = {
|
|
|
|
"aux",
|
|
|
|
"i2c",
|
|
|
|
"off",
|
|
|
|
};
|
|
|
|
|
|
|
|
static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl)
|
|
|
|
{
|
|
|
|
return ARRAY_SIZE(tegra_dpaux_groups);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl,
|
|
|
|
unsigned int group)
|
|
|
|
{
|
|
|
|
return tegra_dpaux_groups[group];
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl,
|
|
|
|
unsigned group, const unsigned **pins,
|
|
|
|
unsigned *num_pins)
|
|
|
|
{
|
|
|
|
*pins = tegra_dpaux_pin_numbers;
|
|
|
|
*num_pins = ARRAY_SIZE(tegra_dpaux_pin_numbers);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = {
|
|
|
|
.get_groups_count = tegra_dpaux_get_groups_count,
|
|
|
|
.get_group_name = tegra_dpaux_get_group_name,
|
|
|
|
.get_group_pins = tegra_dpaux_get_group_pins,
|
|
|
|
.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
|
|
|
|
.dt_free_map = pinconf_generic_dt_free_map,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl)
|
|
|
|
{
|
|
|
|
return ARRAY_SIZE(tegra_dpaux_functions);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl,
|
|
|
|
unsigned int function)
|
|
|
|
{
|
|
|
|
return tegra_dpaux_functions[function];
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl,
|
|
|
|
unsigned int function,
|
|
|
|
const char * const **groups,
|
|
|
|
unsigned * const num_groups)
|
|
|
|
{
|
|
|
|
*num_groups = ARRAY_SIZE(tegra_dpaux_groups);
|
|
|
|
*groups = tegra_dpaux_groups;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl,
|
|
|
|
unsigned int function, unsigned int group)
|
|
|
|
{
|
|
|
|
struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);
|
|
|
|
|
|
|
|
return tegra_dpaux_pad_config(dpaux, function);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct pinmux_ops tegra_dpaux_pinmux_ops = {
|
|
|
|
.get_functions_count = tegra_dpaux_get_functions_count,
|
|
|
|
.get_function_name = tegra_dpaux_get_function_name,
|
|
|
|
.get_function_groups = tegra_dpaux_get_function_groups,
|
|
|
|
.set_mux = tegra_dpaux_set_mux,
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2013-11-15 15:06:05 +00:00
|
|
|
static int tegra_dpaux_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct tegra_dpaux *dpaux;
|
|
|
|
struct resource *regs;
|
2015-06-02 11:13:01 +00:00
|
|
|
u32 value;
|
2013-11-15 15:06:05 +00:00
|
|
|
int err;
|
|
|
|
|
|
|
|
dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
|
|
|
|
if (!dpaux)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2014-04-25 14:42:32 +00:00
|
|
|
INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
|
2013-11-15 15:06:05 +00:00
|
|
|
init_completion(&dpaux->complete);
|
|
|
|
INIT_LIST_HEAD(&dpaux->list);
|
|
|
|
dpaux->dev = &pdev->dev;
|
|
|
|
|
|
|
|
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
|
|
|
|
if (IS_ERR(dpaux->regs))
|
|
|
|
return PTR_ERR(dpaux->regs);
|
|
|
|
|
|
|
|
dpaux->irq = platform_get_irq(pdev, 0);
|
|
|
|
if (dpaux->irq < 0) {
|
|
|
|
dev_err(&pdev->dev, "failed to get IRQ\n");
|
|
|
|
return -ENXIO;
|
|
|
|
}
|
|
|
|
|
2016-06-29 09:17:51 +00:00
|
|
|
if (!pdev->dev.pm_domain) {
|
|
|
|
dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
|
|
|
|
if (IS_ERR(dpaux->rst)) {
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"failed to get reset control: %ld\n",
|
|
|
|
PTR_ERR(dpaux->rst));
|
|
|
|
return PTR_ERR(dpaux->rst);
|
|
|
|
}
|
2015-04-27 12:50:30 +00:00
|
|
|
}
|
2013-11-15 15:06:05 +00:00
|
|
|
|
|
|
|
dpaux->clk = devm_clk_get(&pdev->dev, NULL);
|
2015-04-27 12:50:30 +00:00
|
|
|
if (IS_ERR(dpaux->clk)) {
|
|
|
|
dev_err(&pdev->dev, "failed to get module clock: %ld\n",
|
|
|
|
PTR_ERR(dpaux->clk));
|
2013-11-15 15:06:05 +00:00
|
|
|
return PTR_ERR(dpaux->clk);
|
2015-04-27 12:50:30 +00:00
|
|
|
}
|
2013-11-15 15:06:05 +00:00
|
|
|
|
|
|
|
dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
|
2015-04-27 12:50:30 +00:00
|
|
|
if (IS_ERR(dpaux->clk_parent)) {
|
|
|
|
dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
|
|
|
|
PTR_ERR(dpaux->clk_parent));
|
2017-10-12 15:32:52 +00:00
|
|
|
return PTR_ERR(dpaux->clk_parent);
|
2015-04-27 12:50:30 +00:00
|
|
|
}
|
2013-11-15 15:06:05 +00:00
|
|
|
|
|
|
|
err = clk_set_rate(dpaux->clk_parent, 270000000);
|
|
|
|
if (err < 0) {
|
|
|
|
dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
|
|
|
|
err);
|
2017-10-12 15:32:52 +00:00
|
|
|
return err;
|
2013-11-15 15:06:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
|
2015-04-27 12:50:30 +00:00
|
|
|
if (IS_ERR(dpaux->vdd)) {
|
|
|
|
dev_err(&pdev->dev, "failed to get VDD supply: %ld\n",
|
|
|
|
PTR_ERR(dpaux->vdd));
|
2017-10-12 15:32:52 +00:00
|
|
|
return PTR_ERR(dpaux->vdd);
|
2015-04-27 12:50:30 +00:00
|
|
|
}
|
2013-11-15 15:06:05 +00:00
|
|
|
|
2017-10-12 15:32:52 +00:00
|
|
|
platform_set_drvdata(pdev, dpaux);
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
|
|
|
2013-11-15 15:06:05 +00:00
|
|
|
err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
|
|
|
|
dev_name(dpaux->dev), dpaux);
|
|
|
|
if (err < 0) {
|
|
|
|
dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
|
|
|
|
dpaux->irq, err);
|
2017-10-12 15:32:52 +00:00
|
|
|
return err;
|
2013-11-15 15:06:05 +00:00
|
|
|
}
|
|
|
|
|
2015-07-03 12:56:46 +00:00
|
|
|
disable_irq(dpaux->irq);
|
|
|
|
|
2013-11-15 15:06:05 +00:00
|
|
|
dpaux->aux.transfer = tegra_dpaux_transfer;
|
|
|
|
dpaux->aux.dev = &pdev->dev;
|
|
|
|
|
2014-06-04 06:02:28 +00:00
|
|
|
err = drm_dp_aux_register(&dpaux->aux);
|
2013-11-15 15:06:05 +00:00
|
|
|
if (err < 0)
|
2017-10-12 15:32:52 +00:00
|
|
|
return err;
|
2013-11-15 15:06:05 +00:00
|
|
|
|
2015-04-27 13:16:26 +00:00
|
|
|
/*
|
|
|
|
* Assume that by default the DPAUX/I2C pads will be used for HDMI,
|
|
|
|
* so power them up and configure them in I2C mode.
|
|
|
|
*
|
|
|
|
* The DPAUX code paths reconfigure the pads in AUX mode, but there
|
|
|
|
* is no possibility to perform the I2C mode configuration in the
|
|
|
|
* HDMI path.
|
|
|
|
*/
|
2018-09-21 11:42:41 +00:00
|
|
|
err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C);
|
2016-06-29 09:17:49 +00:00
|
|
|
if (err < 0)
|
|
|
|
return err;
|
2015-04-27 13:16:26 +00:00
|
|
|
|
2016-06-29 09:17:55 +00:00
|
|
|
#ifdef CONFIG_GENERIC_PINCONF
|
|
|
|
dpaux->desc.name = dev_name(&pdev->dev);
|
|
|
|
dpaux->desc.pins = tegra_dpaux_pins;
|
|
|
|
dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins);
|
|
|
|
dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops;
|
|
|
|
dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops;
|
|
|
|
dpaux->desc.owner = THIS_MODULE;
|
|
|
|
|
|
|
|
dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);
|
2016-10-28 09:09:45 +00:00
|
|
|
if (IS_ERR(dpaux->pinctrl)) {
|
2016-06-29 09:17:55 +00:00
|
|
|
dev_err(&pdev->dev, "failed to register pincontrol\n");
|
2016-10-28 09:09:45 +00:00
|
|
|
return PTR_ERR(dpaux->pinctrl);
|
2016-06-29 09:17:55 +00:00
|
|
|
}
|
|
|
|
#endif
|
2013-11-15 15:06:05 +00:00
|
|
|
/* enable and clear all interrupts */
|
|
|
|
value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
|
|
|
|
DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
|
|
|
|
tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
|
|
|
|
tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
|
|
|
|
|
|
|
|
mutex_lock(&dpaux_lock);
|
|
|
|
list_add_tail(&dpaux->list, &dpaux_list);
|
|
|
|
mutex_unlock(&dpaux_lock);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_dpaux_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
|
2015-04-27 13:16:26 +00:00
|
|
|
|
2017-10-12 15:32:52 +00:00
|
|
|
cancel_work_sync(&dpaux->work);
|
|
|
|
|
2015-04-27 13:16:26 +00:00
|
|
|
/* make sure pads are powered down when not in use */
|
2016-06-29 09:17:49 +00:00
|
|
|
tegra_dpaux_pad_power_down(dpaux);
|
2013-11-15 15:06:05 +00:00
|
|
|
|
2017-10-12 15:32:52 +00:00
|
|
|
pm_runtime_put(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
|
2014-06-04 06:02:28 +00:00
|
|
|
drm_dp_aux_unregister(&dpaux->aux);
|
2013-11-15 15:06:05 +00:00
|
|
|
|
|
|
|
mutex_lock(&dpaux_lock);
|
|
|
|
list_del(&dpaux->list);
|
|
|
|
mutex_unlock(&dpaux_lock);
|
|
|
|
|
2017-10-12 15:32:52 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2014-04-25 14:42:32 +00:00
|
|
|
|
2017-10-12 15:32:52 +00:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int tegra_dpaux_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
|
|
|
|
int err = 0;
|
|
|
|
|
|
|
|
if (dpaux->rst) {
|
|
|
|
err = reset_control_assert(dpaux->rst);
|
|
|
|
if (err < 0) {
|
|
|
|
dev_err(dev, "failed to assert reset: %d\n", err);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
}
|
2016-06-29 09:17:51 +00:00
|
|
|
|
2017-10-12 15:32:52 +00:00
|
|
|
usleep_range(1000, 2000);
|
2016-06-29 09:17:51 +00:00
|
|
|
|
2017-10-12 15:32:52 +00:00
|
|
|
clk_disable_unprepare(dpaux->clk_parent);
|
2013-11-15 15:06:05 +00:00
|
|
|
clk_disable_unprepare(dpaux->clk);
|
|
|
|
|
2017-10-12 15:32:52 +00:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_dpaux_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = clk_prepare_enable(dpaux->clk);
|
|
|
|
if (err < 0) {
|
|
|
|
dev_err(dev, "failed to enable clock: %d\n", err);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = clk_prepare_enable(dpaux->clk_parent);
|
|
|
|
if (err < 0) {
|
|
|
|
dev_err(dev, "failed to enable parent clock: %d\n", err);
|
|
|
|
goto disable_clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
usleep_range(1000, 2000);
|
|
|
|
|
|
|
|
if (dpaux->rst) {
|
|
|
|
err = reset_control_deassert(dpaux->rst);
|
|
|
|
if (err < 0) {
|
|
|
|
dev_err(dev, "failed to deassert reset: %d\n", err);
|
|
|
|
goto disable_parent;
|
|
|
|
}
|
|
|
|
|
|
|
|
usleep_range(1000, 2000);
|
|
|
|
}
|
|
|
|
|
2013-11-15 15:06:05 +00:00
|
|
|
return 0;
|
2017-10-12 15:32:52 +00:00
|
|
|
|
|
|
|
disable_parent:
|
|
|
|
clk_disable_unprepare(dpaux->clk_parent);
|
|
|
|
disable_clk:
|
|
|
|
clk_disable_unprepare(dpaux->clk);
|
|
|
|
return err;
|
2013-11-15 15:06:05 +00:00
|
|
|
}
|
2017-10-12 15:32:52 +00:00
|
|
|
#endif
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static const struct dev_pm_ops tegra_dpaux_pm_ops = {
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SET_RUNTIME_PM_OPS(tegra_dpaux_suspend, tegra_dpaux_resume, NULL)
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};
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2013-11-15 15:06:05 +00:00
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static const struct of_device_id tegra_dpaux_of_match[] = {
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2018-09-21 10:27:45 +00:00
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{ .compatible = "nvidia,tegra194-dpaux", },
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2017-10-12 15:34:11 +00:00
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{ .compatible = "nvidia,tegra186-dpaux", },
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2015-04-27 13:16:26 +00:00
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{ .compatible = "nvidia,tegra210-dpaux", },
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2013-11-15 15:06:05 +00:00
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{ .compatible = "nvidia,tegra124-dpaux", },
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{ },
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};
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2014-06-18 22:21:55 +00:00
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MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
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2013-11-15 15:06:05 +00:00
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struct platform_driver tegra_dpaux_driver = {
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.driver = {
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.name = "tegra-dpaux",
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.of_match_table = tegra_dpaux_of_match,
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2017-10-12 15:32:52 +00:00
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.pm = &tegra_dpaux_pm_ops,
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2013-11-15 15:06:05 +00:00
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},
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.probe = tegra_dpaux_probe,
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.remove = tegra_dpaux_remove,
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};
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2015-07-08 11:39:09 +00:00
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struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np)
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2013-11-15 15:06:05 +00:00
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{
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struct tegra_dpaux *dpaux;
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mutex_lock(&dpaux_lock);
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list_for_each_entry(dpaux, &dpaux_list, list)
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if (np == dpaux->dev->of_node) {
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mutex_unlock(&dpaux_lock);
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2015-07-08 11:39:09 +00:00
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return &dpaux->aux;
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2013-11-15 15:06:05 +00:00
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}
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mutex_unlock(&dpaux_lock);
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return NULL;
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}
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2015-07-08 11:39:09 +00:00
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int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output)
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2013-11-15 15:06:05 +00:00
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{
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2015-07-08 11:39:09 +00:00
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struct tegra_dpaux *dpaux = to_dpaux(aux);
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2013-11-15 15:06:05 +00:00
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unsigned long timeout;
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int err;
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2014-04-25 14:44:48 +00:00
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output->connector.polled = DRM_CONNECTOR_POLL_HPD;
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2013-11-15 15:06:05 +00:00
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dpaux->output = output;
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err = regulator_enable(dpaux->vdd);
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if (err < 0)
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return err;
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timeout = jiffies + msecs_to_jiffies(250);
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while (time_before(jiffies, timeout)) {
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enum drm_connector_status status;
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2015-07-08 11:39:09 +00:00
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status = drm_dp_aux_detect(aux);
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2015-07-03 12:56:46 +00:00
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if (status == connector_status_connected) {
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enable_irq(dpaux->irq);
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2013-11-15 15:06:05 +00:00
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return 0;
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2015-07-03 12:56:46 +00:00
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}
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2013-11-15 15:06:05 +00:00
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usleep_range(1000, 2000);
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}
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return -ETIMEDOUT;
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}
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2015-07-08 11:39:09 +00:00
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int drm_dp_aux_detach(struct drm_dp_aux *aux)
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2013-11-15 15:06:05 +00:00
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{
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2015-07-08 11:39:09 +00:00
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struct tegra_dpaux *dpaux = to_dpaux(aux);
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2013-11-15 15:06:05 +00:00
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unsigned long timeout;
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int err;
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2015-07-03 12:56:46 +00:00
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disable_irq(dpaux->irq);
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2013-11-15 15:06:05 +00:00
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err = regulator_disable(dpaux->vdd);
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if (err < 0)
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return err;
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timeout = jiffies + msecs_to_jiffies(250);
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while (time_before(jiffies, timeout)) {
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enum drm_connector_status status;
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2015-07-08 11:39:09 +00:00
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status = drm_dp_aux_detect(aux);
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2013-11-15 15:06:05 +00:00
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if (status == connector_status_disconnected) {
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dpaux->output = NULL;
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return 0;
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}
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usleep_range(1000, 2000);
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}
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return -ETIMEDOUT;
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}
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|
2015-07-08 11:39:09 +00:00
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enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux)
|
2013-11-15 15:06:05 +00:00
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{
|
2015-07-08 11:39:09 +00:00
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struct tegra_dpaux *dpaux = to_dpaux(aux);
|
2015-06-02 11:13:01 +00:00
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u32 value;
|
2013-11-15 15:06:05 +00:00
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value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
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if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
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return connector_status_connected;
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return connector_status_disconnected;
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}
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|
2015-07-08 11:39:09 +00:00
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int drm_dp_aux_enable(struct drm_dp_aux *aux)
|
2013-11-15 15:06:05 +00:00
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{
|
2015-07-08 11:39:09 +00:00
|
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struct tegra_dpaux *dpaux = to_dpaux(aux);
|
2013-11-15 15:06:05 +00:00
|
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|
2016-06-29 09:17:55 +00:00
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return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX);
|
2013-11-15 15:06:05 +00:00
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}
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|
2015-07-08 11:39:09 +00:00
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int drm_dp_aux_disable(struct drm_dp_aux *aux)
|
2013-11-15 15:06:05 +00:00
|
|
|
{
|
2015-07-08 11:39:09 +00:00
|
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struct tegra_dpaux *dpaux = to_dpaux(aux);
|
2013-11-15 15:06:05 +00:00
|
|
|
|
2016-06-29 09:17:49 +00:00
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|
|
tegra_dpaux_pad_power_down(dpaux);
|
2013-11-15 15:06:05 +00:00
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|
return 0;
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|
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}
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|
|
|
|
2015-07-08 11:39:09 +00:00
|
|
|
int drm_dp_aux_prepare(struct drm_dp_aux *aux, u8 encoding)
|
2013-11-15 15:06:05 +00:00
|
|
|
{
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|
|
|
int err;
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|
|
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|
2015-07-08 11:39:09 +00:00
|
|
|
err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
|
2013-11-15 15:06:05 +00:00
|
|
|
encoding);
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|
|
|
if (err < 0)
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|
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|
return err;
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|
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|
return 0;
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|
|
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}
|
|
|
|
|
2015-07-08 11:39:09 +00:00
|
|
|
int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link,
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|
u8 pattern)
|
2013-11-15 15:06:05 +00:00
|
|
|
{
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|
|
|
u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
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|
|
|
u8 status[DP_LINK_STATUS_SIZE], values[4];
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|
|
|
unsigned int i;
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|
|
|
int err;
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|
|
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|
2015-07-08 11:39:09 +00:00
|
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|
err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, pattern);
|
2013-11-15 15:06:05 +00:00
|
|
|
if (err < 0)
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|
|
|
return err;
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|
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|
|
if (tp == DP_TRAINING_PATTERN_DISABLE)
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|
return 0;
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|
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|
for (i = 0; i < link->num_lanes; i++)
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|
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|
values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
|
2014-08-08 10:53:45 +00:00
|
|
|
DP_TRAIN_PRE_EMPH_LEVEL_0 |
|
2013-11-15 15:06:05 +00:00
|
|
|
DP_TRAIN_MAX_SWING_REACHED |
|
2014-08-08 10:53:45 +00:00
|
|
|
DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
|
2013-11-15 15:06:05 +00:00
|
|
|
|
2015-07-08 11:39:09 +00:00
|
|
|
err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values,
|
2013-11-15 15:06:05 +00:00
|
|
|
link->num_lanes);
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|
|
|
if (err < 0)
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|
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|
return err;
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|
|
|
|
|
|
|
usleep_range(500, 1000);
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|
|
|
|
2015-07-08 11:39:09 +00:00
|
|
|
err = drm_dp_dpcd_read_link_status(aux, status);
|
2013-11-15 15:06:05 +00:00
|
|
|
if (err < 0)
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|
return err;
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|
|
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|
|
switch (tp) {
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|
|
|
case DP_TRAINING_PATTERN_1:
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|
|
|
if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
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|
|
|
return -EAGAIN;
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|
|
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|
|
|
|
break;
|
|
|
|
|
|
|
|
case DP_TRAINING_PATTERN_2:
|
|
|
|
if (!drm_dp_channel_eq_ok(status, link->num_lanes))
|
|
|
|
return -EAGAIN;
|
|
|
|
|
|
|
|
break;
|
|
|
|
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|
default:
|
2015-07-08 11:39:09 +00:00
|
|
|
dev_err(aux->dev, "unsupported training pattern %u\n", tp);
|
2013-11-15 15:06:05 +00:00
|
|
|
return -EINVAL;
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|
|
|
}
|
|
|
|
|
2015-07-08 11:39:09 +00:00
|
|
|
err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, 0);
|
2013-11-15 15:06:05 +00:00
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|