2013-06-21 07:24:54 +00:00
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/*
|
2017-09-01 21:35:50 +00:00
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* Synopsys DesignWare PCIe host controller driver
|
2013-06-21 07:24:54 +00:00
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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PCI: designware: Add generic dw_pcie_wait_for_link()
Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and
spear13xx) had similar loops waiting for the link to come up.
Add a generic dw_pcie_wait_for_link() for use by all these drivers so the
waiting is done consistently, e.g., always using usleep_range() rather than
mdelay() and using similar timeouts and retry counts.
Note that this changes the Keystone link training/wait for link strategy,
so we initiate link training, then wait longer for the link to come up
before re-initiating link training.
[bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c]
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
2016-03-10 20:44:35 +00:00
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#include <linux/delay.h>
|
2017-02-15 13:18:17 +00:00
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#include <linux/of.h>
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#include <linux/types.h>
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2013-06-21 07:24:54 +00:00
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2013-07-31 08:14:10 +00:00
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#include "pcie-designware.h"
|
2013-06-21 07:24:54 +00:00
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|
|
2016-03-10 20:44:44 +00:00
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/* PCIe Port Logic registers */
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#define PLR_OFFSET 0x700
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#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
|
2016-08-17 20:57:37 +00:00
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#define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4)
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#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
|
2016-03-10 20:44:44 +00:00
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|
2017-02-15 13:18:12 +00:00
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int dw_pcie_read(void __iomem *addr, int size, u32 *val)
|
2013-06-21 07:24:54 +00:00
|
|
|
{
|
2015-10-08 19:27:53 +00:00
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if ((uintptr_t)addr & (size - 1)) {
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*val = 0;
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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|
2017-02-15 13:18:16 +00:00
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if (size == 4) {
|
2015-10-08 19:27:43 +00:00
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*val = readl(addr);
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2017-02-15 13:18:16 +00:00
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} else if (size == 2) {
|
2015-10-08 19:27:48 +00:00
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*val = readw(addr);
|
2017-02-15 13:18:16 +00:00
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} else if (size == 1) {
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2015-10-08 19:27:48 +00:00
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*val = readb(addr);
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2017-02-15 13:18:16 +00:00
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} else {
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2015-10-08 19:27:43 +00:00
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*val = 0;
|
2013-06-21 07:24:54 +00:00
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return PCIBIOS_BAD_REGISTER_NUMBER;
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2015-10-08 19:27:43 +00:00
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}
|
2013-06-21 07:24:54 +00:00
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return PCIBIOS_SUCCESSFUL;
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}
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|
2017-02-15 13:18:12 +00:00
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int dw_pcie_write(void __iomem *addr, int size, u32 val)
|
2013-06-21 07:24:54 +00:00
|
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{
|
2015-10-08 19:27:53 +00:00
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if ((uintptr_t)addr & (size - 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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|
2013-06-21 07:24:54 +00:00
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if (size == 4)
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writel(val, addr);
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else if (size == 2)
|
2015-10-08 19:27:48 +00:00
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writew(val, addr);
|
2013-06-21 07:24:54 +00:00
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else if (size == 1)
|
2015-10-08 19:27:48 +00:00
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writeb(val, addr);
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2013-06-21 07:24:54 +00:00
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else
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return PCIBIOS_BAD_REGISTER_NUMBER;
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return PCIBIOS_SUCCESSFUL;
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}
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|
2017-03-13 13:43:26 +00:00
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u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
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size_t size)
|
2013-06-21 07:24:54 +00:00
|
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{
|
2017-03-13 13:43:26 +00:00
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int ret;
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u32 val;
|
2016-08-17 19:17:58 +00:00
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2017-03-13 13:43:26 +00:00
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if (pci->ops->read_dbi)
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return pci->ops->read_dbi(pci, base, reg, size);
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ret = dw_pcie_read(base + reg, size, &val);
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if (ret)
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dev_err(pci->dev, "read DBI address failed\n");
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return val;
|
2013-06-21 07:24:54 +00:00
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}
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|
2017-03-13 13:43:26 +00:00
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void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
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size_t size, u32 val)
|
2013-06-21 07:24:54 +00:00
|
|
|
{
|
2017-03-13 13:43:26 +00:00
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int ret;
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if (pci->ops->write_dbi) {
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pci->ops->write_dbi(pci, base, reg, size, val);
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|
return;
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|
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|
}
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ret = dw_pcie_write(base + reg, size, val);
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if (ret)
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dev_err(pci->dev, "write DBI address failed\n");
|
2013-06-21 07:24:54 +00:00
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|
}
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|
2017-03-13 13:43:27 +00:00
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static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
|
2016-08-10 10:02:39 +00:00
|
|
|
{
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|
|
|
u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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|
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|
2017-02-15 13:18:14 +00:00
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return dw_pcie_readl_dbi(pci, offset + reg);
|
2016-08-10 10:02:39 +00:00
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|
|
}
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|
2017-03-13 13:43:27 +00:00
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static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
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|
|
u32 val)
|
2016-08-10 10:02:39 +00:00
|
|
|
{
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|
|
|
u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
|
|
|
|
|
2017-02-15 13:18:14 +00:00
|
|
|
dw_pcie_writel_dbi(pci, offset + reg, val);
|
2016-08-10 10:02:39 +00:00
|
|
|
}
|
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|
|
2017-07-17 13:13:34 +00:00
|
|
|
static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
|
|
|
|
int type, u64 cpu_addr,
|
|
|
|
u64 pci_addr, u32 size)
|
2017-03-13 13:43:27 +00:00
|
|
|
{
|
|
|
|
u32 retries, val;
|
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|
|
|
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|
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
|
|
|
|
lower_32_bits(cpu_addr));
|
|
|
|
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
|
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|
|
upper_32_bits(cpu_addr));
|
|
|
|
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
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|
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lower_32_bits(cpu_addr + size - 1));
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|
|
|
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
|
|
|
|
lower_32_bits(pci_addr));
|
|
|
|
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
|
|
|
|
upper_32_bits(pci_addr));
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|
|
|
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
|
|
|
|
type);
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|
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|
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
|
|
|
|
PCIE_ATU_ENABLE);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Make sure ATU enable takes effect before any subsequent config
|
|
|
|
* and I/O accesses.
|
|
|
|
*/
|
|
|
|
for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
|
|
|
|
val = dw_pcie_readl_ob_unroll(pci, index,
|
|
|
|
PCIE_ATU_UNR_REGION_CTRL2);
|
|
|
|
if (val & PCIE_ATU_ENABLE)
|
|
|
|
return;
|
|
|
|
|
|
|
|
usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
|
|
|
|
}
|
|
|
|
dev_err(pci->dev, "outbound iATU is not being enabled\n");
|
|
|
|
}
|
|
|
|
|
2017-02-15 13:18:17 +00:00
|
|
|
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
|
|
|
|
u64 cpu_addr, u64 pci_addr, u32 size)
|
2015-04-30 08:22:28 +00:00
|
|
|
{
|
2016-08-17 18:26:07 +00:00
|
|
|
u32 retries, val;
|
2015-12-18 12:38:55 +00:00
|
|
|
|
2017-03-13 13:43:22 +00:00
|
|
|
if (pci->ops->cpu_addr_fixup)
|
|
|
|
cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr);
|
|
|
|
|
2017-02-15 13:18:14 +00:00
|
|
|
if (pci->iatu_unroll_enabled) {
|
2017-03-13 13:43:27 +00:00
|
|
|
dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr,
|
|
|
|
pci_addr, size);
|
|
|
|
return;
|
2016-08-10 10:02:39 +00:00
|
|
|
}
|
2015-12-18 12:38:55 +00:00
|
|
|
|
2017-03-13 13:43:27 +00:00
|
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
|
|
|
|
PCIE_ATU_REGION_OUTBOUND | index);
|
|
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
|
|
|
|
lower_32_bits(cpu_addr));
|
|
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
|
|
|
|
upper_32_bits(cpu_addr));
|
|
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
|
|
|
|
lower_32_bits(cpu_addr + size - 1));
|
|
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
|
|
|
|
lower_32_bits(pci_addr));
|
|
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
|
|
|
|
upper_32_bits(pci_addr));
|
|
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
|
|
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
|
|
|
|
|
2015-12-18 12:38:55 +00:00
|
|
|
/*
|
|
|
|
* Make sure ATU enable takes effect before any subsequent config
|
|
|
|
* and I/O accesses.
|
|
|
|
*/
|
2016-08-17 18:26:07 +00:00
|
|
|
for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
|
2017-03-13 13:43:27 +00:00
|
|
|
val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
|
2017-07-18 06:48:21 +00:00
|
|
|
if (val & PCIE_ATU_ENABLE)
|
2016-08-17 18:26:07 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
|
|
|
|
}
|
2017-03-13 13:43:27 +00:00
|
|
|
dev_err(pci->dev, "outbound iATU is not being enabled\n");
|
2015-04-30 08:22:28 +00:00
|
|
|
}
|
|
|
|
|
2017-03-27 09:45:05 +00:00
|
|
|
static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
|
|
|
|
{
|
|
|
|
u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
|
|
|
|
|
|
|
|
return dw_pcie_readl_dbi(pci, offset + reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
|
|
|
|
u32 val)
|
|
|
|
{
|
|
|
|
u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
|
|
|
|
|
|
|
|
dw_pcie_writel_dbi(pci, offset + reg, val);
|
|
|
|
}
|
|
|
|
|
2017-07-17 13:13:34 +00:00
|
|
|
static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index,
|
|
|
|
int bar, u64 cpu_addr,
|
|
|
|
enum dw_pcie_as_type as_type)
|
2017-03-27 09:45:05 +00:00
|
|
|
{
|
|
|
|
int type;
|
|
|
|
u32 retries, val;
|
|
|
|
|
|
|
|
dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
|
|
|
|
lower_32_bits(cpu_addr));
|
|
|
|
dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
|
|
|
|
upper_32_bits(cpu_addr));
|
|
|
|
|
|
|
|
switch (as_type) {
|
|
|
|
case DW_PCIE_AS_MEM:
|
|
|
|
type = PCIE_ATU_TYPE_MEM;
|
|
|
|
break;
|
|
|
|
case DW_PCIE_AS_IO:
|
|
|
|
type = PCIE_ATU_TYPE_IO;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type);
|
|
|
|
dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
|
|
|
|
PCIE_ATU_ENABLE |
|
|
|
|
PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Make sure ATU enable takes effect before any subsequent config
|
|
|
|
* and I/O accesses.
|
|
|
|
*/
|
|
|
|
for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
|
|
|
|
val = dw_pcie_readl_ib_unroll(pci, index,
|
|
|
|
PCIE_ATU_UNR_REGION_CTRL2);
|
|
|
|
if (val & PCIE_ATU_ENABLE)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
|
|
|
|
}
|
|
|
|
dev_err(pci->dev, "inbound iATU is not being enabled\n");
|
|
|
|
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
|
|
|
|
u64 cpu_addr, enum dw_pcie_as_type as_type)
|
|
|
|
{
|
|
|
|
int type;
|
|
|
|
u32 retries, val;
|
|
|
|
|
|
|
|
if (pci->iatu_unroll_enabled)
|
|
|
|
return dw_pcie_prog_inbound_atu_unroll(pci, index, bar,
|
|
|
|
cpu_addr, as_type);
|
|
|
|
|
|
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND |
|
|
|
|
index);
|
|
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr));
|
|
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr));
|
|
|
|
|
|
|
|
switch (as_type) {
|
|
|
|
case DW_PCIE_AS_MEM:
|
|
|
|
type = PCIE_ATU_TYPE_MEM;
|
|
|
|
break;
|
|
|
|
case DW_PCIE_AS_IO:
|
|
|
|
type = PCIE_ATU_TYPE_IO;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
|
|
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE
|
|
|
|
| PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Make sure ATU enable takes effect before any subsequent config
|
|
|
|
* and I/O accesses.
|
|
|
|
*/
|
|
|
|
for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
|
|
|
|
val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
|
|
|
|
if (val & PCIE_ATU_ENABLE)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
|
|
|
|
}
|
|
|
|
dev_err(pci->dev, "inbound iATU is not being enabled\n");
|
|
|
|
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
|
|
|
|
enum dw_pcie_region_type type)
|
|
|
|
{
|
|
|
|
int region;
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case DW_PCIE_REGION_INBOUND:
|
|
|
|
region = PCIE_ATU_REGION_INBOUND;
|
|
|
|
break;
|
|
|
|
case DW_PCIE_REGION_OUTBOUND:
|
|
|
|
region = PCIE_ATU_REGION_OUTBOUND;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
|
|
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~PCIE_ATU_ENABLE);
|
|
|
|
}
|
|
|
|
|
2017-02-15 13:18:14 +00:00
|
|
|
int dw_pcie_wait_for_link(struct dw_pcie *pci)
|
PCI: designware: Add generic dw_pcie_wait_for_link()
Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and
spear13xx) had similar loops waiting for the link to come up.
Add a generic dw_pcie_wait_for_link() for use by all these drivers so the
waiting is done consistently, e.g., always using usleep_range() rather than
mdelay() and using similar timeouts and retry counts.
Note that this changes the Keystone link training/wait for link strategy,
so we initiate link training, then wait longer for the link to come up
before re-initiating link training.
[bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c]
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
2016-03-10 20:44:35 +00:00
|
|
|
{
|
|
|
|
int retries;
|
|
|
|
|
|
|
|
/* check if the link is up or not */
|
|
|
|
for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
|
2017-02-15 13:18:14 +00:00
|
|
|
if (dw_pcie_link_up(pci)) {
|
|
|
|
dev_info(pci->dev, "link up\n");
|
PCI: designware: Add generic dw_pcie_wait_for_link()
Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and
spear13xx) had similar loops waiting for the link to come up.
Add a generic dw_pcie_wait_for_link() for use by all these drivers so the
waiting is done consistently, e.g., always using usleep_range() rather than
mdelay() and using similar timeouts and retry counts.
Note that this changes the Keystone link training/wait for link strategy,
so we initiate link training, then wait longer for the link to come up
before re-initiating link training.
[bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c]
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
2016-03-10 20:44:35 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
|
|
|
|
}
|
|
|
|
|
2017-02-15 13:18:14 +00:00
|
|
|
dev_err(pci->dev, "phy link never came up\n");
|
PCI: designware: Add generic dw_pcie_wait_for_link()
Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and
spear13xx) had similar loops waiting for the link to come up.
Add a generic dw_pcie_wait_for_link() for use by all these drivers so the
waiting is done consistently, e.g., always using usleep_range() rather than
mdelay() and using similar timeouts and retry counts.
Note that this changes the Keystone link training/wait for link strategy,
so we initiate link training, then wait longer for the link to come up
before re-initiating link training.
[bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c]
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
2016-03-10 20:44:35 +00:00
|
|
|
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
2017-02-15 13:18:14 +00:00
|
|
|
int dw_pcie_link_up(struct dw_pcie *pci)
|
2013-07-31 08:14:10 +00:00
|
|
|
{
|
2016-03-10 20:44:44 +00:00
|
|
|
u32 val;
|
|
|
|
|
2017-02-15 13:18:14 +00:00
|
|
|
if (pci->ops->link_up)
|
|
|
|
return pci->ops->link_up(pci);
|
2016-01-05 21:48:11 +00:00
|
|
|
|
2017-02-15 13:18:14 +00:00
|
|
|
val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1);
|
2016-08-17 20:57:37 +00:00
|
|
|
return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
|
|
|
|
(!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
|
2013-07-31 08:14:10 +00:00
|
|
|
}
|
|
|
|
|
2017-02-15 13:18:17 +00:00
|
|
|
void dw_pcie_setup(struct dw_pcie *pci)
|
2013-06-21 07:24:54 +00:00
|
|
|
{
|
2017-02-15 13:18:15 +00:00
|
|
|
int ret;
|
2013-06-21 07:24:54 +00:00
|
|
|
u32 val;
|
2017-02-15 13:18:17 +00:00
|
|
|
u32 lanes;
|
2017-02-15 13:18:15 +00:00
|
|
|
struct device *dev = pci->dev;
|
|
|
|
struct device_node *np = dev->of_node;
|
|
|
|
|
|
|
|
ret = of_property_read_u32(np, "num-lanes", &lanes);
|
|
|
|
if (ret)
|
|
|
|
lanes = 0;
|
2013-06-21 07:24:54 +00:00
|
|
|
|
2014-04-14 20:22:54 +00:00
|
|
|
/* set the number of lanes */
|
2017-02-15 13:18:14 +00:00
|
|
|
val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
|
2013-06-21 07:24:54 +00:00
|
|
|
val &= ~PORT_LINK_MODE_MASK;
|
2017-02-15 13:18:15 +00:00
|
|
|
switch (lanes) {
|
2013-07-31 08:14:10 +00:00
|
|
|
case 1:
|
|
|
|
val |= PORT_LINK_MODE_1_LANES;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
val |= PORT_LINK_MODE_2_LANES;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
val |= PORT_LINK_MODE_4_LANES;
|
|
|
|
break;
|
2015-05-13 06:44:34 +00:00
|
|
|
case 8:
|
|
|
|
val |= PORT_LINK_MODE_8_LANES;
|
|
|
|
break;
|
2015-09-28 16:03:10 +00:00
|
|
|
default:
|
2017-02-15 13:18:15 +00:00
|
|
|
dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
|
2015-09-28 16:03:10 +00:00
|
|
|
return;
|
2013-07-31 08:14:10 +00:00
|
|
|
}
|
2017-02-15 13:18:14 +00:00
|
|
|
dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
|
2013-06-21 07:24:54 +00:00
|
|
|
|
|
|
|
/* set link width speed control register */
|
2017-02-15 13:18:14 +00:00
|
|
|
val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
|
2013-06-21 07:24:54 +00:00
|
|
|
val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
|
2017-02-15 13:18:15 +00:00
|
|
|
switch (lanes) {
|
2013-07-31 08:14:10 +00:00
|
|
|
case 1:
|
|
|
|
val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
|
|
|
|
break;
|
2015-05-13 06:44:34 +00:00
|
|
|
case 8:
|
|
|
|
val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
|
|
|
|
break;
|
2013-07-31 08:14:10 +00:00
|
|
|
}
|
2017-02-15 13:18:14 +00:00
|
|
|
dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
|
2013-06-21 07:24:54 +00:00
|
|
|
}
|