License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2015-04-22 08:17:06 +00:00
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/*
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* FPU data structures:
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*/
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#ifndef _ASM_X86_FPU_H
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#define _ASM_X86_FPU_H
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2015-04-22 07:57:24 +00:00
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2023-12-15 22:08:47 +00:00
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#include <asm/page_types.h>
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2015-05-02 08:22:45 +00:00
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/*
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* The legacy x87 FPU state format, as saved by FSAVE and
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* restored by the FRSTOR instructions:
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*/
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2015-04-30 15:15:32 +00:00
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struct fregs_state {
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2015-04-22 07:57:24 +00:00
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u32 cwd; /* FPU Control Word */
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u32 swd; /* FPU Status Word */
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u32 twd; /* FPU Tag Word */
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u32 fip; /* FPU IP Offset */
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u32 fcs; /* FPU IP Selector */
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u32 foo; /* FPU Operand Pointer Offset */
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u32 fos; /* FPU Operand Pointer Selector */
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/* 8*10 bytes for each FP-reg = 80 bytes: */
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u32 st_space[20];
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2015-05-02 08:22:45 +00:00
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/* Software status information [not touched by FSAVE]: */
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2015-04-22 07:57:24 +00:00
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u32 status;
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};
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2015-05-02 08:22:45 +00:00
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/*
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* The legacy fx SSE/MMX FPU state format, as saved by FXSAVE and
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* restored by the FXRSTOR instructions. It's similar to the FSAVE
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* format, but differs in some areas, plus has extensions at
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* the end for the XMM registers.
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*/
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2015-04-30 15:15:32 +00:00
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struct fxregs_state {
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2015-04-22 07:57:24 +00:00
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u16 cwd; /* Control Word */
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u16 swd; /* Status Word */
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u16 twd; /* Tag Word */
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u16 fop; /* Last Instruction Opcode */
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union {
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struct {
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u64 rip; /* Instruction Pointer */
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u64 rdp; /* Data Pointer */
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};
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struct {
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u32 fip; /* FPU IP Offset */
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u32 fcs; /* FPU IP Selector */
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u32 foo; /* FPU Operand Offset */
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u32 fos; /* FPU Operand Selector */
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};
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};
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u32 mxcsr; /* MXCSR Register State */
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u32 mxcsr_mask; /* MXCSR Mask */
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/* 8*16 bytes for each FP-reg = 128 bytes: */
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u32 st_space[32];
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/* 16*16 bytes for each XMM-reg = 256 bytes: */
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u32 xmm_space[64];
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u32 padding[12];
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union {
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u32 padding1[12];
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u32 sw_reserved[12];
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};
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} __attribute__((aligned(16)));
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2015-05-05 13:56:33 +00:00
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/* Default value for fxregs_state.mxcsr: */
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#define MXCSR_DEFAULT 0x1f80
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2017-09-23 13:00:04 +00:00
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/* Copy both mxcsr & mxcsr_flags with a single u64 memcpy: */
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#define MXCSR_AND_FLAGS_SIZE sizeof(u64)
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2015-04-22 08:17:06 +00:00
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/*
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2015-05-02 08:22:45 +00:00
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* Software based FPU emulation state. This is arbitrary really,
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* it matches the x87 format to make it easier to understand:
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2015-04-22 08:17:06 +00:00
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*/
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2015-04-30 15:15:32 +00:00
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struct swregs_state {
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2015-04-22 07:57:24 +00:00
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u32 cwd;
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u32 swd;
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u32 twd;
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u32 fip;
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u32 fcs;
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u32 foo;
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u32 fos;
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/* 8*10 bytes for each FP-reg = 80 bytes: */
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u32 st_space[20];
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u8 ftop;
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u8 changed;
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u8 lookahead;
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u8 no_update;
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u8 rm;
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u8 alimit;
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struct math_emu_info *info;
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u32 entry_eip;
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};
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2015-04-28 07:46:04 +00:00
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/*
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* List of XSAVE features Linux knows about:
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*/
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2015-09-02 23:31:26 +00:00
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enum xfeature {
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XFEATURE_FP,
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XFEATURE_SSE,
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/*
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* Values above here are "legacy states".
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* Those below are "extended states".
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*/
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XFEATURE_YMM,
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XFEATURE_BNDREGS,
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XFEATURE_BNDCSR,
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XFEATURE_OPMASK,
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XFEATURE_ZMM_Hi256,
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XFEATURE_Hi16_ZMM,
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2016-02-12 21:01:58 +00:00
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XFEATURE_PT_UNIMPLEMENTED_SO_FAR,
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2016-02-12 21:02:04 +00:00
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XFEATURE_PKRU,
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2020-09-15 16:30:09 +00:00
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XFEATURE_PASID,
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x86/fpu/xstate: Introduce CET MSR and XSAVES supervisor states
Shadow stack register state can be managed with XSAVE. The registers
can logically be separated into two groups:
* Registers controlling user-mode operation
* Registers controlling kernel-mode operation
The architecture has two new XSAVE state components: one for each group
of those groups of registers. This lets an OS manage them separately if
it chooses. Future patches for host userspace and KVM guests will only
utilize the user-mode registers, so only configure XSAVE to save
user-mode registers. This state will add 16 bytes to the xsave buffer
size.
Future patches will use the user-mode XSAVE area to save guest user-mode
CET state. However, VMCS includes new fields for guest CET supervisor
states. KVM can use these to save and restore guest supervisor state, so
host supervisor XSAVE support is not required.
Adding this exacerbates the already unwieldy if statement in
check_xstate_against_struct() that handles warning about unimplemented
xfeatures. So refactor these check's by having XCHECK_SZ() set a bool when
it actually check's the xfeature. This ends up exceeding 80 chars, but was
better on balance than other options explored. Pass the bool as pointer to
make it clear that XCHECK_SZ() can change the variable.
While configuring user-mode XSAVE, clarify kernel-mode registers are not
managed by XSAVE by defining the xfeature in
XFEATURE_MASK_SUPERVISOR_UNSUPPORTED, like is done for XFEATURE_MASK_PT.
This serves more of a documentation as code purpose, and functionally,
only enables a few safety checks.
Both XSAVE state components are supervisor states, even the state
controlling user-mode operation. This is a departure from earlier features
like protection keys where the PKRU state is a normal user
(non-supervisor) state. Having the user state be supervisor-managed
ensures there is no direct, unprivileged access to it, making it harder
for an attacker to subvert CET.
To facilitate this privileged access, define the two user-mode CET MSRs,
and the bits defined in those MSRs relevant to future shadow stack
enablement patches.
Co-developed-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Signed-off-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Kees Cook <keescook@chromium.org>
Acked-by: Mike Rapoport (IBM) <rppt@kernel.org>
Tested-by: Pengfei Xu <pengfei.xu@intel.com>
Tested-by: John Allen <john.allen@amd.com>
Tested-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/all/20230613001108.3040476-25-rick.p.edgecombe%40intel.com
2023-06-13 00:10:50 +00:00
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XFEATURE_CET_USER,
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XFEATURE_CET_KERNEL_UNUSED,
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x86/fpu/xstate: Support dynamic supervisor feature for LBR
Last Branch Records (LBR) registers are used to log taken branches and
other control flows. In perf with call stack mode, LBR information is
used to reconstruct a call stack. To get the complete call stack, perf
has to save/restore all LBR registers during a context switch. Due to
the large number of the LBR registers, e.g., the current platform has
96 LBR registers, this process causes a high CPU overhead. To reduce
the CPU overhead during a context switch, an LBR state component that
contains all the LBR related registers is introduced in hardware. All
LBR registers can be saved/restored together using one XSAVES/XRSTORS
instruction.
However, the kernel should not save/restore the LBR state component at
each context switch, like other state components, because of the
following unique features of LBR:
- The LBR state component only contains valuable information when LBR
is enabled in the perf subsystem, but for most of the time, LBR is
disabled.
- The size of the LBR state component is huge. For the current
platform, it's 808 bytes.
If the kernel saves/restores the LBR state at each context switch, for
most of the time, it is just a waste of space and cycles.
To efficiently support the LBR state component, it is desired to have:
- only context-switch the LBR when the LBR feature is enabled in perf.
- only allocate an LBR-specific XSAVE buffer on demand.
(Besides the LBR state, a legacy region and an XSAVE header have to be
included in the buffer as well. There is a total of (808+576) byte
overhead for the LBR-specific XSAVE buffer. The overhead only happens
when the perf is actively using LBRs. There is still a space-saving,
on average, when it replaces the constant 808 bytes of overhead for
every task, all the time on the systems that support architectural
LBR.)
- be able to use XSAVES/XRSTORS for accessing LBR at run time.
However, the IA32_XSS should not be adjusted at run time.
(The XCR0 | IA32_XSS are used to determine the requested-feature
bitmap (RFBM) of XSAVES.)
A solution, called dynamic supervisor feature, is introduced to address
this issue, which
- does not allocate a buffer in each task->fpu;
- does not save/restore a state component at each context switch;
- sets the bit corresponding to the dynamic supervisor feature in
IA32_XSS at boot time, and avoids setting it at run time.
- dynamically allocates a specific buffer for a state component
on demand, e.g. only allocates LBR-specific XSAVE buffer when LBR is
enabled in perf. (Note: The buffer has to include the LBR state
component, a legacy region and a XSAVE header space.)
(Implemented in a later patch)
- saves/restores a state component on demand, e.g. manually invokes
the XSAVES/XRSTORS instruction to save/restore the LBR state
to/from the buffer when perf is active and a call stack is required.
(Implemented in a later patch)
A new mask XFEATURE_MASK_DYNAMIC and a helper xfeatures_mask_dynamic()
are introduced to indicate the dynamic supervisor feature. For the
systems which support the Architecture LBR, LBR is the only dynamic
supervisor feature for now. For the previous systems, there is no
dynamic supervisor feature available.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Dave Hansen <dave.hansen@intel.com>
Link: https://lkml.kernel.org/r/1593780569-62993-21-git-send-email-kan.liang@linux.intel.com
2020-07-03 12:49:26 +00:00
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XFEATURE_RSRVD_COMP_13,
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XFEATURE_RSRVD_COMP_14,
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XFEATURE_LBR,
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2021-10-21 22:55:24 +00:00
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XFEATURE_RSRVD_COMP_16,
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XFEATURE_XTILE_CFG,
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XFEATURE_XTILE_DATA,
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2015-04-28 07:46:04 +00:00
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2015-09-02 23:31:27 +00:00
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XFEATURE_MAX,
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2015-04-28 07:46:04 +00:00
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};
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2015-09-02 23:31:26 +00:00
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#define XFEATURE_MASK_FP (1 << XFEATURE_FP)
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#define XFEATURE_MASK_SSE (1 << XFEATURE_SSE)
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#define XFEATURE_MASK_YMM (1 << XFEATURE_YMM)
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#define XFEATURE_MASK_BNDREGS (1 << XFEATURE_BNDREGS)
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#define XFEATURE_MASK_BNDCSR (1 << XFEATURE_BNDCSR)
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#define XFEATURE_MASK_OPMASK (1 << XFEATURE_OPMASK)
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#define XFEATURE_MASK_ZMM_Hi256 (1 << XFEATURE_ZMM_Hi256)
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#define XFEATURE_MASK_Hi16_ZMM (1 << XFEATURE_Hi16_ZMM)
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2016-06-17 20:07:16 +00:00
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#define XFEATURE_MASK_PT (1 << XFEATURE_PT_UNIMPLEMENTED_SO_FAR)
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2016-02-12 21:02:04 +00:00
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#define XFEATURE_MASK_PKRU (1 << XFEATURE_PKRU)
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2020-09-15 16:30:09 +00:00
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#define XFEATURE_MASK_PASID (1 << XFEATURE_PASID)
|
x86/fpu/xstate: Introduce CET MSR and XSAVES supervisor states
Shadow stack register state can be managed with XSAVE. The registers
can logically be separated into two groups:
* Registers controlling user-mode operation
* Registers controlling kernel-mode operation
The architecture has two new XSAVE state components: one for each group
of those groups of registers. This lets an OS manage them separately if
it chooses. Future patches for host userspace and KVM guests will only
utilize the user-mode registers, so only configure XSAVE to save
user-mode registers. This state will add 16 bytes to the xsave buffer
size.
Future patches will use the user-mode XSAVE area to save guest user-mode
CET state. However, VMCS includes new fields for guest CET supervisor
states. KVM can use these to save and restore guest supervisor state, so
host supervisor XSAVE support is not required.
Adding this exacerbates the already unwieldy if statement in
check_xstate_against_struct() that handles warning about unimplemented
xfeatures. So refactor these check's by having XCHECK_SZ() set a bool when
it actually check's the xfeature. This ends up exceeding 80 chars, but was
better on balance than other options explored. Pass the bool as pointer to
make it clear that XCHECK_SZ() can change the variable.
While configuring user-mode XSAVE, clarify kernel-mode registers are not
managed by XSAVE by defining the xfeature in
XFEATURE_MASK_SUPERVISOR_UNSUPPORTED, like is done for XFEATURE_MASK_PT.
This serves more of a documentation as code purpose, and functionally,
only enables a few safety checks.
Both XSAVE state components are supervisor states, even the state
controlling user-mode operation. This is a departure from earlier features
like protection keys where the PKRU state is a normal user
(non-supervisor) state. Having the user state be supervisor-managed
ensures there is no direct, unprivileged access to it, making it harder
for an attacker to subvert CET.
To facilitate this privileged access, define the two user-mode CET MSRs,
and the bits defined in those MSRs relevant to future shadow stack
enablement patches.
Co-developed-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Signed-off-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Kees Cook <keescook@chromium.org>
Acked-by: Mike Rapoport (IBM) <rppt@kernel.org>
Tested-by: Pengfei Xu <pengfei.xu@intel.com>
Tested-by: John Allen <john.allen@amd.com>
Tested-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/all/20230613001108.3040476-25-rick.p.edgecombe%40intel.com
2023-06-13 00:10:50 +00:00
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#define XFEATURE_MASK_CET_USER (1 << XFEATURE_CET_USER)
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|
|
#define XFEATURE_MASK_CET_KERNEL (1 << XFEATURE_CET_KERNEL_UNUSED)
|
x86/fpu/xstate: Support dynamic supervisor feature for LBR
Last Branch Records (LBR) registers are used to log taken branches and
other control flows. In perf with call stack mode, LBR information is
used to reconstruct a call stack. To get the complete call stack, perf
has to save/restore all LBR registers during a context switch. Due to
the large number of the LBR registers, e.g., the current platform has
96 LBR registers, this process causes a high CPU overhead. To reduce
the CPU overhead during a context switch, an LBR state component that
contains all the LBR related registers is introduced in hardware. All
LBR registers can be saved/restored together using one XSAVES/XRSTORS
instruction.
However, the kernel should not save/restore the LBR state component at
each context switch, like other state components, because of the
following unique features of LBR:
- The LBR state component only contains valuable information when LBR
is enabled in the perf subsystem, but for most of the time, LBR is
disabled.
- The size of the LBR state component is huge. For the current
platform, it's 808 bytes.
If the kernel saves/restores the LBR state at each context switch, for
most of the time, it is just a waste of space and cycles.
To efficiently support the LBR state component, it is desired to have:
- only context-switch the LBR when the LBR feature is enabled in perf.
- only allocate an LBR-specific XSAVE buffer on demand.
(Besides the LBR state, a legacy region and an XSAVE header have to be
included in the buffer as well. There is a total of (808+576) byte
overhead for the LBR-specific XSAVE buffer. The overhead only happens
when the perf is actively using LBRs. There is still a space-saving,
on average, when it replaces the constant 808 bytes of overhead for
every task, all the time on the systems that support architectural
LBR.)
- be able to use XSAVES/XRSTORS for accessing LBR at run time.
However, the IA32_XSS should not be adjusted at run time.
(The XCR0 | IA32_XSS are used to determine the requested-feature
bitmap (RFBM) of XSAVES.)
A solution, called dynamic supervisor feature, is introduced to address
this issue, which
- does not allocate a buffer in each task->fpu;
- does not save/restore a state component at each context switch;
- sets the bit corresponding to the dynamic supervisor feature in
IA32_XSS at boot time, and avoids setting it at run time.
- dynamically allocates a specific buffer for a state component
on demand, e.g. only allocates LBR-specific XSAVE buffer when LBR is
enabled in perf. (Note: The buffer has to include the LBR state
component, a legacy region and a XSAVE header space.)
(Implemented in a later patch)
- saves/restores a state component on demand, e.g. manually invokes
the XSAVES/XRSTORS instruction to save/restore the LBR state
to/from the buffer when perf is active and a call stack is required.
(Implemented in a later patch)
A new mask XFEATURE_MASK_DYNAMIC and a helper xfeatures_mask_dynamic()
are introduced to indicate the dynamic supervisor feature. For the
systems which support the Architecture LBR, LBR is the only dynamic
supervisor feature for now. For the previous systems, there is no
dynamic supervisor feature available.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Dave Hansen <dave.hansen@intel.com>
Link: https://lkml.kernel.org/r/1593780569-62993-21-git-send-email-kan.liang@linux.intel.com
2020-07-03 12:49:26 +00:00
|
|
|
#define XFEATURE_MASK_LBR (1 << XFEATURE_LBR)
|
2021-10-21 22:55:24 +00:00
|
|
|
#define XFEATURE_MASK_XTILE_CFG (1 << XFEATURE_XTILE_CFG)
|
|
|
|
#define XFEATURE_MASK_XTILE_DATA (1 << XFEATURE_XTILE_DATA)
|
2015-09-02 23:31:26 +00:00
|
|
|
|
|
|
|
#define XFEATURE_MASK_FPSSE (XFEATURE_MASK_FP | XFEATURE_MASK_SSE)
|
|
|
|
#define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK \
|
|
|
|
| XFEATURE_MASK_ZMM_Hi256 \
|
|
|
|
| XFEATURE_MASK_Hi16_ZMM)
|
2015-04-28 07:46:04 +00:00
|
|
|
|
2021-10-21 22:55:24 +00:00
|
|
|
#ifdef CONFIG_X86_64
|
|
|
|
# define XFEATURE_MASK_XTILE (XFEATURE_MASK_XTILE_DATA \
|
|
|
|
| XFEATURE_MASK_XTILE_CFG)
|
|
|
|
#else
|
|
|
|
# define XFEATURE_MASK_XTILE (0)
|
|
|
|
#endif
|
|
|
|
|
2015-09-02 23:31:28 +00:00
|
|
|
#define FIRST_EXTENDED_XFEATURE XFEATURE_YMM
|
|
|
|
|
2015-09-02 23:31:29 +00:00
|
|
|
struct reg_128_bit {
|
|
|
|
u8 regbytes[128/8];
|
|
|
|
};
|
2015-09-02 23:31:29 +00:00
|
|
|
struct reg_256_bit {
|
|
|
|
u8 regbytes[256/8];
|
|
|
|
};
|
|
|
|
struct reg_512_bit {
|
|
|
|
u8 regbytes[512/8];
|
|
|
|
};
|
2021-10-21 22:55:24 +00:00
|
|
|
struct reg_1024_byte {
|
|
|
|
u8 regbytes[1024];
|
|
|
|
};
|
2015-09-02 23:31:29 +00:00
|
|
|
|
2015-04-24 09:43:47 +00:00
|
|
|
/*
|
2015-09-02 23:31:29 +00:00
|
|
|
* State component 2:
|
|
|
|
*
|
2015-04-24 09:43:47 +00:00
|
|
|
* There are 16x 256-bit AVX registers named YMM0-YMM15.
|
|
|
|
* The low 128 bits are aliased to the 16 SSE registers (XMM0-XMM15)
|
2015-09-02 23:31:29 +00:00
|
|
|
* and are stored in 'struct fxregs_state::xmm_space[]' in the
|
|
|
|
* "legacy" area.
|
2015-04-24 09:43:47 +00:00
|
|
|
*
|
2015-09-02 23:31:29 +00:00
|
|
|
* The high 128 bits are stored here.
|
2015-04-24 09:43:47 +00:00
|
|
|
*/
|
2015-04-22 07:57:24 +00:00
|
|
|
struct ymmh_struct {
|
2015-09-02 23:31:29 +00:00
|
|
|
struct reg_128_bit hi_ymm[16];
|
|
|
|
} __packed;
|
2015-04-22 07:57:24 +00:00
|
|
|
|
2015-04-22 08:17:06 +00:00
|
|
|
/* Intel MPX support: */
|
2015-09-02 23:31:29 +00:00
|
|
|
|
|
|
|
struct mpx_bndreg {
|
2015-04-22 08:17:06 +00:00
|
|
|
u64 lower_bound;
|
|
|
|
u64 upper_bound;
|
2015-04-22 07:57:24 +00:00
|
|
|
} __packed;
|
2015-09-02 23:31:29 +00:00
|
|
|
/*
|
|
|
|
* State component 3 is used for the 4 128-bit bounds registers
|
|
|
|
*/
|
|
|
|
struct mpx_bndreg_state {
|
|
|
|
struct mpx_bndreg bndreg[4];
|
|
|
|
} __packed;
|
2015-04-22 07:57:24 +00:00
|
|
|
|
2015-09-02 23:31:29 +00:00
|
|
|
/*
|
|
|
|
* State component 4 is used for the 64-bit user-mode MPX
|
|
|
|
* configuration register BNDCFGU and the 64-bit MPX status
|
|
|
|
* register BNDSTATUS. We call the pair "BNDCSR".
|
|
|
|
*/
|
|
|
|
struct mpx_bndcsr {
|
2015-04-22 08:17:06 +00:00
|
|
|
u64 bndcfgu;
|
|
|
|
u64 bndstatus;
|
2015-04-22 07:57:24 +00:00
|
|
|
} __packed;
|
|
|
|
|
2015-09-02 23:31:29 +00:00
|
|
|
/*
|
|
|
|
* The BNDCSR state is padded out to be 64-bytes in size.
|
|
|
|
*/
|
|
|
|
struct mpx_bndcsr_state {
|
|
|
|
union {
|
|
|
|
struct mpx_bndcsr bndcsr;
|
|
|
|
u8 pad_to_64_bytes[64];
|
|
|
|
};
|
|
|
|
} __packed;
|
2015-05-04 07:04:56 +00:00
|
|
|
|
2015-09-02 23:31:29 +00:00
|
|
|
/* AVX-512 Components: */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* State component 5 is used for the 8 64-bit opmask registers
|
|
|
|
* k0-k7 (opmask state).
|
|
|
|
*/
|
|
|
|
struct avx_512_opmask_state {
|
|
|
|
u64 opmask_reg[8];
|
|
|
|
} __packed;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* State component 6 is used for the upper 256 bits of the
|
|
|
|
* registers ZMM0-ZMM15. These 16 256-bit values are denoted
|
|
|
|
* ZMM0_H-ZMM15_H (ZMM_Hi256 state).
|
|
|
|
*/
|
|
|
|
struct avx_512_zmm_uppers_state {
|
|
|
|
struct reg_256_bit zmm_upper[16];
|
|
|
|
} __packed;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* State component 7 is used for the 16 512-bit registers
|
|
|
|
* ZMM16-ZMM31 (Hi16_ZMM state).
|
|
|
|
*/
|
|
|
|
struct avx_512_hi16_state {
|
|
|
|
struct reg_512_bit hi16_zmm[16];
|
|
|
|
} __packed;
|
|
|
|
|
2016-02-12 21:02:04 +00:00
|
|
|
/*
|
|
|
|
* State component 9: 32-bit PKRU register. The state is
|
|
|
|
* 8 bytes long but only 4 bytes is used currently.
|
|
|
|
*/
|
|
|
|
struct pkru_state {
|
|
|
|
u32 pkru;
|
|
|
|
u32 pad;
|
|
|
|
} __packed;
|
|
|
|
|
x86/fpu/xstate: Introduce CET MSR and XSAVES supervisor states
Shadow stack register state can be managed with XSAVE. The registers
can logically be separated into two groups:
* Registers controlling user-mode operation
* Registers controlling kernel-mode operation
The architecture has two new XSAVE state components: one for each group
of those groups of registers. This lets an OS manage them separately if
it chooses. Future patches for host userspace and KVM guests will only
utilize the user-mode registers, so only configure XSAVE to save
user-mode registers. This state will add 16 bytes to the xsave buffer
size.
Future patches will use the user-mode XSAVE area to save guest user-mode
CET state. However, VMCS includes new fields for guest CET supervisor
states. KVM can use these to save and restore guest supervisor state, so
host supervisor XSAVE support is not required.
Adding this exacerbates the already unwieldy if statement in
check_xstate_against_struct() that handles warning about unimplemented
xfeatures. So refactor these check's by having XCHECK_SZ() set a bool when
it actually check's the xfeature. This ends up exceeding 80 chars, but was
better on balance than other options explored. Pass the bool as pointer to
make it clear that XCHECK_SZ() can change the variable.
While configuring user-mode XSAVE, clarify kernel-mode registers are not
managed by XSAVE by defining the xfeature in
XFEATURE_MASK_SUPERVISOR_UNSUPPORTED, like is done for XFEATURE_MASK_PT.
This serves more of a documentation as code purpose, and functionally,
only enables a few safety checks.
Both XSAVE state components are supervisor states, even the state
controlling user-mode operation. This is a departure from earlier features
like protection keys where the PKRU state is a normal user
(non-supervisor) state. Having the user state be supervisor-managed
ensures there is no direct, unprivileged access to it, making it harder
for an attacker to subvert CET.
To facilitate this privileged access, define the two user-mode CET MSRs,
and the bits defined in those MSRs relevant to future shadow stack
enablement patches.
Co-developed-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Signed-off-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Kees Cook <keescook@chromium.org>
Acked-by: Mike Rapoport (IBM) <rppt@kernel.org>
Tested-by: Pengfei Xu <pengfei.xu@intel.com>
Tested-by: John Allen <john.allen@amd.com>
Tested-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/all/20230613001108.3040476-25-rick.p.edgecombe%40intel.com
2023-06-13 00:10:50 +00:00
|
|
|
/*
|
|
|
|
* State component 11 is Control-flow Enforcement user states
|
|
|
|
*/
|
|
|
|
struct cet_user_state {
|
|
|
|
/* user control-flow settings */
|
|
|
|
u64 user_cet;
|
|
|
|
/* user shadow stack pointer */
|
|
|
|
u64 user_ssp;
|
|
|
|
};
|
|
|
|
|
perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switch
In the LBR call stack mode, LBR information is used to reconstruct a
call stack. To get the complete call stack, perf has to save/restore
all LBR registers during a context switch. Due to a large number of the
LBR registers, this process causes a high CPU overhead. To reduce the
CPU overhead during a context switch, use the XSAVES/XRSTORS
instructions.
Every XSAVE area must follow a canonical format: the legacy region, an
XSAVE header and the extended region. Although the LBR information is
only kept in the extended region, a space for the legacy region and
XSAVE header is still required. Add a new dedicated structure for LBR
XSAVES support.
Before enabling XSAVES support, the size of the LBR state has to be
sanity checked, because:
- the size of the software structure is calculated from the max number
of the LBR depth, which is enumerated by the CPUID leaf for Arch LBR.
The size of the LBR state is enumerated by the CPUID leaf for XSAVE
support of Arch LBR. If the values from the two CPUID leaves are not
consistent, it may trigger a buffer overflow. For example, a hypervisor
may unconsciously set inconsistent values for the two emulated CPUID.
- unlike other state components, the size of an LBR state depends on the
max number of LBRs, which may vary from generation to generation.
Expose the function xfeature_size() for the sanity check.
The LBR XSAVES support will be disabled if the size of the LBR state
enumerated by CPUID doesn't match with the size of the software
structure.
The XSAVE instruction requires 64-byte alignment for state buffers. A
new macro is added to reflect the alignment requirement. A 64-byte
aligned kmem_cache is created for architecture LBR.
Currently, the structure for each state component is maintained in
fpu/types.h. The structure for the new LBR state component should be
maintained in the same place. Move structure lbr_entry to fpu/types.h as
well for broader sharing.
Add dedicated lbr_save/lbr_restore functions for LBR XSAVES support,
which invokes the corresponding xstate helpers to XSAVES/XRSTORS LBR
information at the context switch when the call stack mode is enabled.
Since the XSAVES/XRSTORS instructions will be eventually invoked, the
dedicated functions is named with '_xsaves'/'_xrstors' postfix.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Dave Hansen <dave.hansen@intel.com>
Link: https://lkml.kernel.org/r/1593780569-62993-23-git-send-email-kan.liang@linux.intel.com
2020-07-03 12:49:28 +00:00
|
|
|
/*
|
|
|
|
* State component 15: Architectural LBR configuration state.
|
|
|
|
* The size of Arch LBR state depends on the number of LBRs (lbr_depth).
|
|
|
|
*/
|
|
|
|
|
|
|
|
struct lbr_entry {
|
|
|
|
u64 from;
|
|
|
|
u64 to;
|
|
|
|
u64 info;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct arch_lbr_state {
|
|
|
|
u64 lbr_ctl;
|
|
|
|
u64 lbr_depth;
|
|
|
|
u64 ler_from;
|
|
|
|
u64 ler_to;
|
|
|
|
u64 ler_info;
|
|
|
|
struct lbr_entry entries[];
|
2021-10-21 22:55:24 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* State component 17: 64-byte tile configuration register.
|
|
|
|
*/
|
|
|
|
struct xtile_cfg {
|
|
|
|
u64 tcfg[8];
|
|
|
|
} __packed;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* State component 18: 1KB tile data register.
|
|
|
|
* Each register represents 16 64-byte rows of the matrix
|
|
|
|
* data. But the number of registers depends on the actual
|
|
|
|
* implementation.
|
|
|
|
*/
|
|
|
|
struct xtile_data {
|
|
|
|
struct reg_1024_byte tmm;
|
perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switch
In the LBR call stack mode, LBR information is used to reconstruct a
call stack. To get the complete call stack, perf has to save/restore
all LBR registers during a context switch. Due to a large number of the
LBR registers, this process causes a high CPU overhead. To reduce the
CPU overhead during a context switch, use the XSAVES/XRSTORS
instructions.
Every XSAVE area must follow a canonical format: the legacy region, an
XSAVE header and the extended region. Although the LBR information is
only kept in the extended region, a space for the legacy region and
XSAVE header is still required. Add a new dedicated structure for LBR
XSAVES support.
Before enabling XSAVES support, the size of the LBR state has to be
sanity checked, because:
- the size of the software structure is calculated from the max number
of the LBR depth, which is enumerated by the CPUID leaf for Arch LBR.
The size of the LBR state is enumerated by the CPUID leaf for XSAVE
support of Arch LBR. If the values from the two CPUID leaves are not
consistent, it may trigger a buffer overflow. For example, a hypervisor
may unconsciously set inconsistent values for the two emulated CPUID.
- unlike other state components, the size of an LBR state depends on the
max number of LBRs, which may vary from generation to generation.
Expose the function xfeature_size() for the sanity check.
The LBR XSAVES support will be disabled if the size of the LBR state
enumerated by CPUID doesn't match with the size of the software
structure.
The XSAVE instruction requires 64-byte alignment for state buffers. A
new macro is added to reflect the alignment requirement. A 64-byte
aligned kmem_cache is created for architecture LBR.
Currently, the structure for each state component is maintained in
fpu/types.h. The structure for the new LBR state component should be
maintained in the same place. Move structure lbr_entry to fpu/types.h as
well for broader sharing.
Add dedicated lbr_save/lbr_restore functions for LBR XSAVES support,
which invokes the corresponding xstate helpers to XSAVES/XRSTORS LBR
information at the context switch when the call stack mode is enabled.
Since the XSAVES/XRSTORS instructions will be eventually invoked, the
dedicated functions is named with '_xsaves'/'_xrstors' postfix.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Dave Hansen <dave.hansen@intel.com>
Link: https://lkml.kernel.org/r/1593780569-62993-23-git-send-email-kan.liang@linux.intel.com
2020-07-03 12:49:28 +00:00
|
|
|
} __packed;
|
|
|
|
|
2020-09-15 16:30:09 +00:00
|
|
|
/*
|
|
|
|
* State component 10 is supervisor state used for context-switching the
|
|
|
|
* PASID state.
|
|
|
|
*/
|
|
|
|
struct ia32_pasid_state {
|
|
|
|
u64 pasid;
|
|
|
|
} __packed;
|
|
|
|
|
2015-04-24 08:14:36 +00:00
|
|
|
struct xstate_header {
|
2015-04-24 08:19:47 +00:00
|
|
|
u64 xfeatures;
|
2015-04-22 08:17:06 +00:00
|
|
|
u64 xcomp_bv;
|
|
|
|
u64 reserved[6];
|
2015-04-22 07:57:24 +00:00
|
|
|
} __attribute__((packed));
|
|
|
|
|
2016-07-11 16:18:56 +00:00
|
|
|
/*
|
|
|
|
* xstate_header.xcomp_bv[63] indicates that the extended_state_area
|
|
|
|
* is in compacted format.
|
|
|
|
*/
|
|
|
|
#define XCOMP_BV_COMPACTED_FORMAT ((u64)1 << 63)
|
|
|
|
|
2015-05-02 08:22:45 +00:00
|
|
|
/*
|
|
|
|
* This is our most modern FPU state format, as saved by the XSAVE
|
|
|
|
* and restored by the XRSTOR instructions.
|
|
|
|
*
|
|
|
|
* It consists of a legacy fxregs portion, an xstate header and
|
2015-09-02 23:31:25 +00:00
|
|
|
* subsequent areas as defined by the xstate header. Not all CPUs
|
|
|
|
* support all the extensions, so the size of the extended area
|
|
|
|
* can vary quite a bit between CPUs.
|
2015-05-02 08:22:45 +00:00
|
|
|
*/
|
2015-04-30 15:15:32 +00:00
|
|
|
struct xregs_state {
|
|
|
|
struct fxregs_state i387;
|
2015-04-24 08:14:36 +00:00
|
|
|
struct xstate_header header;
|
2023-01-10 01:40:38 +00:00
|
|
|
u8 extended_state_area[];
|
2015-04-22 07:57:24 +00:00
|
|
|
} __attribute__ ((packed, aligned (64)));
|
|
|
|
|
2015-05-02 08:22:45 +00:00
|
|
|
/*
|
|
|
|
* This is a union of all the possible FPU state formats
|
|
|
|
* put together, so that we can pick the right one runtime.
|
|
|
|
*
|
|
|
|
* The size of the structure is determined by the largest
|
2015-09-02 23:31:25 +00:00
|
|
|
* member - which is the xsave area. The padding is there
|
|
|
|
* to ensure that statically-allocated task_structs (just
|
|
|
|
* the init_task today) have enough space.
|
2015-05-02 08:22:45 +00:00
|
|
|
*/
|
2015-04-30 15:15:32 +00:00
|
|
|
union fpregs_state {
|
|
|
|
struct fregs_state fsave;
|
|
|
|
struct fxregs_state fxsave;
|
|
|
|
struct swregs_state soft;
|
|
|
|
struct xregs_state xsave;
|
2015-07-17 10:28:11 +00:00
|
|
|
u8 __padding[PAGE_SIZE];
|
2015-04-22 07:57:24 +00:00
|
|
|
};
|
|
|
|
|
2021-10-13 14:55:27 +00:00
|
|
|
struct fpstate {
|
2021-10-13 14:55:46 +00:00
|
|
|
/* @kernel_size: The size of the kernel register image */
|
|
|
|
unsigned int size;
|
|
|
|
|
|
|
|
/* @user_size: The size in non-compacted UABI format */
|
|
|
|
unsigned int user_size;
|
|
|
|
|
|
|
|
/* @xfeatures: xfeatures for which the storage is sized */
|
|
|
|
u64 xfeatures;
|
|
|
|
|
|
|
|
/* @user_xfeatures: xfeatures valid in UABI buffers */
|
|
|
|
u64 user_xfeatures;
|
|
|
|
|
2021-10-21 22:55:18 +00:00
|
|
|
/* @xfd: xfeatures disabled to trap userspace use. */
|
|
|
|
u64 xfd;
|
|
|
|
|
2021-10-22 18:55:49 +00:00
|
|
|
/* @is_valloc: Indicator for dynamically allocated state */
|
|
|
|
unsigned int is_valloc : 1;
|
|
|
|
|
|
|
|
/* @is_guest: Indicator for guest state (KVM) */
|
|
|
|
unsigned int is_guest : 1;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* @is_confidential: Indicator for KVM confidential mode.
|
|
|
|
* The FPU registers are restored by the
|
|
|
|
* vmentry firmware from encrypted guest
|
|
|
|
* memory. On vmexit the FPU registers are
|
|
|
|
* saved by firmware to encrypted guest memory
|
|
|
|
* and the registers are scrubbed before
|
|
|
|
* returning to the host. So there is no
|
|
|
|
* content which is worth saving and restoring.
|
|
|
|
* The fpstate has to be there so that
|
|
|
|
* preemption and softirq FPU usage works
|
|
|
|
* without special casing.
|
|
|
|
*/
|
|
|
|
unsigned int is_confidential : 1;
|
|
|
|
|
|
|
|
/* @in_use: State is in use */
|
|
|
|
unsigned int in_use : 1;
|
|
|
|
|
2021-10-13 14:55:27 +00:00
|
|
|
/* @regs: The register state union for all supported formats */
|
2021-10-22 18:55:49 +00:00
|
|
|
union fpregs_state regs;
|
2021-10-13 14:55:27 +00:00
|
|
|
|
|
|
|
/* @regs is dynamically sized! Don't add anything after @regs! */
|
|
|
|
} __aligned(64);
|
|
|
|
|
2022-01-05 12:35:12 +00:00
|
|
|
#define FPU_GUEST_PERM_LOCKED BIT_ULL(63)
|
|
|
|
|
2021-10-21 22:55:08 +00:00
|
|
|
struct fpu_state_perm {
|
|
|
|
/*
|
|
|
|
* @__state_perm:
|
|
|
|
*
|
|
|
|
* This bitmap indicates the permission for state components, which
|
|
|
|
* are available to a thread group. The permission prctl() sets the
|
|
|
|
* enabled state bits in thread_group_leader()->thread.fpu.
|
|
|
|
*
|
|
|
|
* All run time operations use the per thread information in the
|
|
|
|
* currently active fpu.fpstate which contains the xfeature masks
|
|
|
|
* and sizes for kernel and user space.
|
|
|
|
*
|
|
|
|
* This master permission field is only to be used when
|
|
|
|
* task.fpu.fpstate based checks fail to validate whether the task
|
|
|
|
* is allowed to expand it's xfeatures set which requires to
|
|
|
|
* allocate a larger sized fpstate buffer.
|
|
|
|
*
|
|
|
|
* Do not access this field directly. Use the provided helper
|
|
|
|
* function. Unlocked access is possible for quick checks.
|
|
|
|
*/
|
|
|
|
u64 __state_perm;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* @__state_size:
|
|
|
|
*
|
|
|
|
* The size required for @__state_perm. Only valid to access
|
|
|
|
* with sighand locked.
|
|
|
|
*/
|
|
|
|
unsigned int __state_size;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* @__user_state_size:
|
|
|
|
*
|
|
|
|
* The size required for @__state_perm user part. Only valid to
|
|
|
|
* access with sighand locked.
|
|
|
|
*/
|
|
|
|
unsigned int __user_state_size;
|
|
|
|
};
|
|
|
|
|
2015-05-02 08:22:45 +00:00
|
|
|
/*
|
|
|
|
* Highest level per task FPU state data structure that
|
|
|
|
* contains the FPU register state plus various FPU
|
|
|
|
* state fields:
|
|
|
|
*/
|
2015-04-22 07:57:24 +00:00
|
|
|
struct fpu {
|
2015-05-01 07:59:04 +00:00
|
|
|
/*
|
|
|
|
* @last_cpu:
|
|
|
|
*
|
2015-04-23 15:08:41 +00:00
|
|
|
* Records the last CPU on which this context was loaded into
|
2015-05-01 07:59:04 +00:00
|
|
|
* FPU registers. (In the lazy-restore case we might be
|
2015-04-23 15:08:41 +00:00
|
|
|
* able to reuse FPU registers across multiple context switches
|
|
|
|
* this way, if no intermediate task used the FPU.)
|
|
|
|
*
|
|
|
|
* A value of -1 is used to indicate that the FPU state in context
|
|
|
|
* memory is newer than the FPU state in registers, and that the
|
|
|
|
* FPU state should be reloaded next time the task is run.
|
|
|
|
*/
|
2015-04-22 08:17:06 +00:00
|
|
|
unsigned int last_cpu;
|
2015-04-23 15:08:41 +00:00
|
|
|
|
2019-01-17 18:38:20 +00:00
|
|
|
/*
|
|
|
|
* @avx512_timestamp:
|
|
|
|
*
|
|
|
|
* Records the timestamp of AVX512 use during last context switch.
|
|
|
|
*/
|
|
|
|
unsigned long avx512_timestamp;
|
|
|
|
|
2021-10-13 14:55:27 +00:00
|
|
|
/*
|
|
|
|
* @fpstate:
|
|
|
|
*
|
|
|
|
* Pointer to the active struct fpstate. Initialized to
|
|
|
|
* point at @__fpstate below.
|
|
|
|
*/
|
|
|
|
struct fpstate *fpstate;
|
|
|
|
|
2021-10-22 18:55:49 +00:00
|
|
|
/*
|
|
|
|
* @__task_fpstate:
|
|
|
|
*
|
|
|
|
* Pointer to an inactive struct fpstate. Initialized to NULL. Is
|
|
|
|
* used only for KVM support to swap out the regular task fpstate.
|
|
|
|
*/
|
|
|
|
struct fpstate *__task_fpstate;
|
|
|
|
|
2021-10-21 22:55:08 +00:00
|
|
|
/*
|
|
|
|
* @perm:
|
|
|
|
*
|
|
|
|
* Permission related information
|
|
|
|
*/
|
|
|
|
struct fpu_state_perm perm;
|
|
|
|
|
2022-01-05 12:35:12 +00:00
|
|
|
/*
|
|
|
|
* @guest_perm:
|
|
|
|
*
|
|
|
|
* Permission related information for guest pseudo FPUs
|
|
|
|
*/
|
|
|
|
struct fpu_state_perm guest_perm;
|
|
|
|
|
2015-07-17 10:28:11 +00:00
|
|
|
/*
|
2021-10-13 14:55:42 +00:00
|
|
|
* @__fpstate:
|
2015-07-17 10:28:11 +00:00
|
|
|
*
|
2021-10-13 14:55:42 +00:00
|
|
|
* Initial in-memory storage for FPU registers which are saved in
|
|
|
|
* context switch and when the kernel uses the FPU. The registers
|
|
|
|
* are restored from this storage on return to user space if they
|
|
|
|
* are not longer containing the tasks FPU register state.
|
2015-07-17 10:28:11 +00:00
|
|
|
*/
|
2021-10-13 14:55:42 +00:00
|
|
|
struct fpstate __fpstate;
|
2015-07-17 10:28:11 +00:00
|
|
|
/*
|
2021-10-13 14:55:42 +00:00
|
|
|
* WARNING: '__fpstate' is dynamically-sized. Do not put
|
2015-07-17 10:28:11 +00:00
|
|
|
* anything after it here.
|
|
|
|
*/
|
2015-04-22 07:57:24 +00:00
|
|
|
};
|
|
|
|
|
2021-10-22 18:55:49 +00:00
|
|
|
/*
|
|
|
|
* Guest pseudo FPU container
|
|
|
|
*/
|
|
|
|
struct fpu_guest {
|
2022-01-05 12:35:13 +00:00
|
|
|
/*
|
|
|
|
* @xfeatures: xfeature bitmap of features which are
|
|
|
|
* currently enabled for the guest vCPU.
|
|
|
|
*/
|
|
|
|
u64 xfeatures;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* @perm: xfeature bitmap of features which are
|
|
|
|
* permitted to be enabled for the guest
|
|
|
|
* vCPU.
|
|
|
|
*/
|
|
|
|
u64 perm;
|
|
|
|
|
2022-01-05 12:35:22 +00:00
|
|
|
/*
|
|
|
|
* @xfd_err: Save the guest value.
|
|
|
|
*/
|
|
|
|
u64 xfd_err;
|
|
|
|
|
2022-01-05 12:35:28 +00:00
|
|
|
/*
|
|
|
|
* @uabi_size: Size required for save/restore
|
|
|
|
*/
|
|
|
|
unsigned int uabi_size;
|
|
|
|
|
2021-10-22 18:55:49 +00:00
|
|
|
/*
|
|
|
|
* @fpstate: Pointer to the allocated guest fpstate
|
|
|
|
*/
|
|
|
|
struct fpstate *fpstate;
|
|
|
|
};
|
|
|
|
|
2021-10-14 23:09:29 +00:00
|
|
|
/*
|
|
|
|
* FPU state configuration data. Initialized at boot time. Read only after init.
|
|
|
|
*/
|
|
|
|
struct fpu_state_config {
|
|
|
|
/*
|
|
|
|
* @max_size:
|
|
|
|
*
|
|
|
|
* The maximum size of the register state buffer. Includes all
|
|
|
|
* supported features except independent managed features.
|
|
|
|
*/
|
|
|
|
unsigned int max_size;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* @default_size:
|
|
|
|
*
|
|
|
|
* The default size of the register state buffer. Includes all
|
|
|
|
* supported features except independent managed features and
|
|
|
|
* features which have to be requested by user space before usage.
|
|
|
|
*/
|
|
|
|
unsigned int default_size;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* @max_features:
|
|
|
|
*
|
|
|
|
* The maximum supported features bitmap. Does not include
|
|
|
|
* independent managed features.
|
|
|
|
*/
|
|
|
|
u64 max_features;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* @default_features:
|
|
|
|
*
|
|
|
|
* The default supported features bitmap. Does not include
|
|
|
|
* independent managed features and features which have to
|
|
|
|
* be requested by user space before usage.
|
|
|
|
*/
|
|
|
|
u64 default_features;
|
2021-10-21 22:55:09 +00:00
|
|
|
/*
|
|
|
|
* @legacy_features:
|
|
|
|
*
|
|
|
|
* Features which can be reported back to user space
|
|
|
|
* even without XSAVE support, i.e. legacy features FP + SSE
|
|
|
|
*/
|
|
|
|
u64 legacy_features;
|
2021-10-14 23:09:29 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/* FPU state configuration information */
|
|
|
|
extern struct fpu_state_config fpu_kernel_cfg, fpu_user_cfg;
|
|
|
|
|
2015-04-22 08:17:06 +00:00
|
|
|
#endif /* _ASM_X86_FPU_H */
|