2005-09-07 16:20:27 +00:00
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/*
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2008-08-05 15:14:15 +00:00
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* arch/arm/plat-omap/include/mach/dmtimer.h
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2005-09-07 16:20:27 +00:00
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*
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* OMAP Dual-Mode Timers
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*
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2011-02-23 07:14:04 +00:00
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* Tarun Kanti DebBarma <tarun.kanti@ti.com>
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* Thara Gopinath <thara@ti.com>
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*
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* Platform device conversion and hwmod support.
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*
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2005-09-07 16:20:27 +00:00
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* Copyright (C) 2005 Nokia Corporation
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* Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
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2006-06-26 23:16:12 +00:00
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* PWM and clock framwork support by Timo Teras.
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2005-09-07 16:20:27 +00:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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2006-06-26 23:16:12 +00:00
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#ifndef __ASM_ARCH_DMTIMER_H
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#define __ASM_ARCH_DMTIMER_H
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2005-09-07 16:20:27 +00:00
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2006-06-26 23:16:12 +00:00
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/* clock sources */
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#define OMAP_TIMER_SRC_SYS_CLK 0x00
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#define OMAP_TIMER_SRC_32_KHZ 0x01
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#define OMAP_TIMER_SRC_EXT_CLK 0x02
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2005-09-07 16:20:27 +00:00
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2006-06-26 23:16:12 +00:00
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/* timer interrupt enable bits */
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#define OMAP_TIMER_INT_CAPTURE (1 << 2)
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#define OMAP_TIMER_INT_OVERFLOW (1 << 1)
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#define OMAP_TIMER_INT_MATCH (1 << 0)
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2005-09-07 16:20:27 +00:00
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2006-06-26 23:16:12 +00:00
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/* trigger types */
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#define OMAP_TIMER_TRIGGER_NONE 0x00
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#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
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#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
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2005-09-07 16:20:27 +00:00
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2011-02-23 07:14:04 +00:00
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/*
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* IP revision identifier so that Highlander IP
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* in OMAP4 can be distinguished.
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*/
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#define OMAP_TIMER_IP_VERSION_1 0x1
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2006-06-26 23:16:12 +00:00
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struct omap_dm_timer;
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2010-10-08 16:56:37 +00:00
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extern struct omap_dm_timer *gptimer_wakeup;
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2006-06-26 23:16:12 +00:00
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struct clk;
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2005-09-07 16:20:27 +00:00
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2006-06-26 23:16:12 +00:00
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int omap_dm_timer_init(void);
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2005-09-07 16:20:27 +00:00
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2006-06-26 23:16:12 +00:00
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struct omap_dm_timer *omap_dm_timer_request(void);
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struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
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2005-09-07 16:20:27 +00:00
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void omap_dm_timer_free(struct omap_dm_timer *timer);
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2006-09-25 09:41:42 +00:00
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void omap_dm_timer_enable(struct omap_dm_timer *timer);
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void omap_dm_timer_disable(struct omap_dm_timer *timer);
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2005-09-07 16:20:27 +00:00
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2006-06-26 23:16:12 +00:00
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int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
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u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
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struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
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2005-09-07 16:20:27 +00:00
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void omap_dm_timer_trigger(struct omap_dm_timer *timer);
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void omap_dm_timer_start(struct omap_dm_timer *timer);
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void omap_dm_timer_stop(struct omap_dm_timer *timer);
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OMAP2/3 GPTIMER: allow system tick GPTIMER to be changed in board-*.c files
Add a function omap2_gp_clockevent_set_gptimer() for board-*.c files
to use in .init_irq functions to configure the system tick GPTIMER.
Practical choices at this point are GPTIMER1 or GPTIMER12. Both of
these timers are in the WKUP powerdomain, and so are unaffected by
chip power management. GPTIMER1 can use sys_clk as a source, for
applications where a high-resolution timer is more important than
power management. GPTIMER12 has the special property that it has the
secure 32kHz oscillator as its source clock, which may be less prone
to glitches than the off-chip 32kHz oscillator. But on HS devices, it
may not be available for Linux use.
It appears that most boards are fine with GPTIMER1, but BeagleBoard
should use GPTIMER12 when using a 32KiHz timer source, due to hardware bugs
in revisions B4 and below. Modify board-omap3beagle.c to use GPTIMER12.
This patch originally used a Kbuild config option to select the GPTIMER,
but was changed to allow this to be specified in board-*.c files, per
Tony's request.
Kalle Vallo <kalle.valo@nokia.com> found a bug in an earlier version of
this patch - thanks Kalle.
Tested on Beagle rev B4 ES2.1, with and without CONFIG_OMAP_32K_TIMER, and
3430SDP.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Cc: Kalle Valo <kalle.valo@nokia.com>
2009-04-24 03:11:10 +00:00
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int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
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2006-06-26 23:16:12 +00:00
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void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
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2008-07-03 09:24:30 +00:00
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void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
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2006-06-26 23:16:12 +00:00
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void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
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void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
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void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
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void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
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2005-09-07 16:20:27 +00:00
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unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
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void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
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unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
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2006-06-26 23:16:23 +00:00
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void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
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2005-09-07 16:20:27 +00:00
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int omap_dm_timers_active(void);
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2011-03-29 22:54:48 +00:00
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/*
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* Do not use the defines below, they are not needed. They should be only
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* used by dmtimer.c and sys_timer related code.
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*/
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/* register offsets */
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#define _OMAP_TIMER_ID_OFFSET 0x00
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#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
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#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
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#define _OMAP_TIMER_STAT_OFFSET 0x18
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#define _OMAP_TIMER_INT_EN_OFFSET 0x1c
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#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
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#define _OMAP_TIMER_CTRL_OFFSET 0x24
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#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
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#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
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#define OMAP_TIMER_CTRL_PT (1 << 12)
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#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
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#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
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#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
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#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
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#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
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#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
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#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
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#define OMAP_TIMER_CTRL_POSTED (1 << 2)
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#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
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#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
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#define _OMAP_TIMER_COUNTER_OFFSET 0x28
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#define _OMAP_TIMER_LOAD_OFFSET 0x2c
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#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
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#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
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#define WP_NONE 0 /* no write pending bit */
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#define WP_TCLR (1 << 0)
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#define WP_TCRR (1 << 1)
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#define WP_TLDR (1 << 2)
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#define WP_TTGR (1 << 3)
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#define WP_TMAR (1 << 4)
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#define WP_TPIR (1 << 5)
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#define WP_TNIR (1 << 6)
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#define WP_TCVR (1 << 7)
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#define WP_TOCR (1 << 8)
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#define WP_TOWR (1 << 9)
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#define _OMAP_TIMER_MATCH_OFFSET 0x38
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#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
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#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
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#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
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#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
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#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
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#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
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#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
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#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
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/* register offsets with the write pending bit encoded */
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#define WPSHIFT 16
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#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
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| (WP_TCLR << WPSHIFT))
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#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
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| (WP_TCRR << WPSHIFT))
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#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
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| (WP_TLDR << WPSHIFT))
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#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
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| (WP_TTGR << WPSHIFT))
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#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
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| (WP_TMAR << WPSHIFT))
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#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
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| (WP_TPIR << WPSHIFT))
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#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
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| (WP_TNIR << WPSHIFT))
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#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
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| (WP_TCVR << WPSHIFT))
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#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
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(_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
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#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
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(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
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struct omap_dm_timer {
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unsigned long phys_base;
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int irq;
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#ifdef CONFIG_ARCH_OMAP2PLUS
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struct clk *iclk, *fclk;
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#endif
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void __iomem *io_base;
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unsigned reserved:1;
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unsigned enabled:1;
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unsigned posted:1;
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};
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2006-06-26 23:16:12 +00:00
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#endif /* __ASM_ARCH_DMTIMER_H */
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