2018-08-01 07:29:12 +00:00
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// SPDX-License-Identifier: GPL-2.0
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// spi-uniphier.c - Socionext UniPhier SPI controller driver
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// Copyright 2012 Panasonic Corporation
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// Copyright 2016-2018 Socionext Inc.
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#include <linux/kernel.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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2019-09-03 05:31:01 +00:00
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#include <linux/delay.h>
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2019-12-24 00:58:27 +00:00
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#include <linux/dmaengine.h>
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2018-08-01 07:29:12 +00:00
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <asm/unaligned.h>
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#define SSI_TIMEOUT_MS 2000
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2019-09-03 05:31:01 +00:00
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#define SSI_POLL_TIMEOUT_US 200
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2018-08-01 07:29:12 +00:00
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#define SSI_MAX_CLK_DIVIDER 254
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#define SSI_MIN_CLK_DIVIDER 4
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struct uniphier_spi_priv {
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void __iomem *base;
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2019-12-24 00:58:27 +00:00
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dma_addr_t base_dma_addr;
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2018-08-01 07:29:12 +00:00
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struct clk *clk;
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struct spi_master *master;
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struct completion xfer_done;
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int error;
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unsigned int tx_bytes;
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unsigned int rx_bytes;
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const u8 *tx_buf;
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u8 *rx_buf;
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2019-12-24 00:58:27 +00:00
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atomic_t dma_busy;
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2018-08-01 07:29:12 +00:00
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bool is_save_param;
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u8 bits_per_word;
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u16 mode;
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u32 speed_hz;
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};
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#define SSI_CTL 0x00
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#define SSI_CTL_EN BIT(0)
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#define SSI_CKS 0x04
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#define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
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#define SSI_CKS_CKPHS BIT(14)
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#define SSI_CKS_CKINIT BIT(13)
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#define SSI_CKS_CKDLY BIT(12)
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#define SSI_TXWDS 0x08
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#define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
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#define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
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#define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
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#define SSI_RXWDS 0x0c
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#define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
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#define SSI_FPS 0x10
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#define SSI_FPS_FSPOL BIT(15)
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#define SSI_FPS_FSTRT BIT(14)
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#define SSI_SR 0x14
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#define SSI_SR_BUSY BIT(7)
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2018-08-01 07:29:12 +00:00
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#define SSI_SR_RNE BIT(0)
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#define SSI_IE 0x18
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2019-12-24 00:58:27 +00:00
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#define SSI_IE_TCIE BIT(4)
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2018-08-01 07:29:12 +00:00
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#define SSI_IE_RCIE BIT(3)
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2019-12-24 00:58:27 +00:00
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#define SSI_IE_TXRE BIT(2)
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#define SSI_IE_RXRE BIT(1)
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2018-08-01 07:29:12 +00:00
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#define SSI_IE_RORIE BIT(0)
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2019-12-24 00:58:27 +00:00
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#define SSI_IE_ALL_MASK GENMASK(4, 0)
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2018-08-01 07:29:12 +00:00
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#define SSI_IS 0x1c
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#define SSI_IS_RXRS BIT(9)
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#define SSI_IS_RCID BIT(3)
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#define SSI_IS_RORID BIT(0)
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#define SSI_IC 0x1c
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#define SSI_IC_TCIC BIT(4)
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#define SSI_IC_RCIC BIT(3)
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#define SSI_IC_RORIC BIT(0)
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#define SSI_FC 0x20
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#define SSI_FC_TXFFL BIT(12)
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#define SSI_FC_TXFTH_MASK GENMASK(11, 8)
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#define SSI_FC_RXFFL BIT(4)
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#define SSI_FC_RXFTH_MASK GENMASK(3, 0)
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#define SSI_TXDR 0x24
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#define SSI_RXDR 0x24
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#define SSI_FIFO_DEPTH 8U
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2019-12-24 00:58:27 +00:00
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#define SSI_FIFO_BURST_NUM 1
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#define SSI_DMA_RX_BUSY BIT(1)
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#define SSI_DMA_TX_BUSY BIT(0)
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2018-08-01 07:29:12 +00:00
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static inline unsigned int bytes_per_word(unsigned int bits)
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{
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return bits <= 8 ? 1 : (bits <= 16 ? 2 : 4);
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}
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2019-12-24 00:58:24 +00:00
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static inline void uniphier_spi_irq_enable(struct uniphier_spi_priv *priv,
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u32 mask)
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2018-08-01 07:29:12 +00:00
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{
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u32 val;
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val = readl(priv->base + SSI_IE);
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val |= mask;
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writel(val, priv->base + SSI_IE);
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}
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2019-12-24 00:58:24 +00:00
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static inline void uniphier_spi_irq_disable(struct uniphier_spi_priv *priv,
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u32 mask)
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2018-08-01 07:29:12 +00:00
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{
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u32 val;
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val = readl(priv->base + SSI_IE);
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val &= ~mask;
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writel(val, priv->base + SSI_IE);
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}
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static void uniphier_spi_set_mode(struct spi_device *spi)
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{
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struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
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u32 val1, val2;
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/*
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* clock setting
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* CKPHS capture timing. 0:rising edge, 1:falling edge
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* CKINIT clock initial level. 0:low, 1:high
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* CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT
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* (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
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*
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* frame setting
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* FSPOL frame signal porarity. 0: low, 1: high
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* FSTRT start frame timing
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* 0: rising edge of clock, 1: falling edge of clock
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*/
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2021-05-10 13:12:17 +00:00
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switch (spi->mode & SPI_MODE_X_MASK) {
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2018-08-01 07:29:12 +00:00
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case SPI_MODE_0:
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/* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
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val1 = SSI_CKS_CKPHS | SSI_CKS_CKDLY;
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val2 = 0;
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break;
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case SPI_MODE_1:
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/* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
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val1 = 0;
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val2 = SSI_FPS_FSTRT;
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break;
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case SPI_MODE_2:
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/* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
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val1 = SSI_CKS_CKINIT | SSI_CKS_CKDLY;
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val2 = SSI_FPS_FSTRT;
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break;
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case SPI_MODE_3:
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/* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
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val1 = SSI_CKS_CKPHS | SSI_CKS_CKINIT;
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val2 = 0;
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break;
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}
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if (!(spi->mode & SPI_CS_HIGH))
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val2 |= SSI_FPS_FSPOL;
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writel(val1, priv->base + SSI_CKS);
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writel(val2, priv->base + SSI_FPS);
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val1 = 0;
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if (spi->mode & SPI_LSB_FIRST)
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val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
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writel(val1, priv->base + SSI_TXWDS);
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writel(val1, priv->base + SSI_RXWDS);
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}
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static void uniphier_spi_set_transfer_size(struct spi_device *spi, int size)
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{
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struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
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u32 val;
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val = readl(priv->base + SSI_TXWDS);
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val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK);
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val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
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val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
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writel(val, priv->base + SSI_TXWDS);
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val = readl(priv->base + SSI_RXWDS);
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val &= ~SSI_RXWDS_DTLEN_MASK;
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val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
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writel(val, priv->base + SSI_RXWDS);
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}
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static void uniphier_spi_set_baudrate(struct spi_device *spi,
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unsigned int speed)
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{
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struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
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u32 val, ckdiv;
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/*
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* the supported rates are even numbers from 4 to 254. (4,6,8...254)
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* round up as we look for equal or less speed
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*/
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ckdiv = DIV_ROUND_UP(clk_get_rate(priv->clk), speed);
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ckdiv = round_up(ckdiv, 2);
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val = readl(priv->base + SSI_CKS);
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val &= ~SSI_CKS_CKRAT_MASK;
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val |= ckdiv & SSI_CKS_CKRAT_MASK;
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writel(val, priv->base + SSI_CKS);
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}
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static void uniphier_spi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
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u32 val;
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priv->error = 0;
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priv->tx_buf = t->tx_buf;
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priv->rx_buf = t->rx_buf;
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priv->tx_bytes = priv->rx_bytes = t->len;
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if (!priv->is_save_param || priv->mode != spi->mode) {
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uniphier_spi_set_mode(spi);
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priv->mode = spi->mode;
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2019-09-03 05:30:59 +00:00
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priv->is_save_param = false;
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2018-08-01 07:29:12 +00:00
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}
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if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) {
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uniphier_spi_set_transfer_size(spi, t->bits_per_word);
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priv->bits_per_word = t->bits_per_word;
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}
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if (!priv->is_save_param || priv->speed_hz != t->speed_hz) {
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uniphier_spi_set_baudrate(spi, t->speed_hz);
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priv->speed_hz = t->speed_hz;
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}
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2019-09-03 05:31:00 +00:00
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priv->is_save_param = true;
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2018-08-01 07:29:12 +00:00
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/* reset FIFOs */
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val = SSI_FC_TXFFL | SSI_FC_RXFFL;
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writel(val, priv->base + SSI_FC);
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}
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static void uniphier_spi_send(struct uniphier_spi_priv *priv)
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{
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int wsize;
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u32 val = 0;
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wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
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priv->tx_bytes -= wsize;
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if (priv->tx_buf) {
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switch (wsize) {
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case 1:
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val = *priv->tx_buf;
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break;
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case 2:
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val = get_unaligned_le16(priv->tx_buf);
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break;
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case 4:
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val = get_unaligned_le32(priv->tx_buf);
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break;
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}
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priv->tx_buf += wsize;
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}
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writel(val, priv->base + SSI_TXDR);
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}
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static void uniphier_spi_recv(struct uniphier_spi_priv *priv)
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{
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int rsize;
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u32 val;
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rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
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priv->rx_bytes -= rsize;
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val = readl(priv->base + SSI_RXDR);
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if (priv->rx_buf) {
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switch (rsize) {
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case 1:
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*priv->rx_buf = val;
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break;
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case 2:
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put_unaligned_le16(val, priv->rx_buf);
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break;
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case 4:
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put_unaligned_le32(val, priv->rx_buf);
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break;
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}
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priv->rx_buf += rsize;
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}
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}
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spi: uniphier: Fix FIFO threshold
Rx threshold means the value to inform the receiver when the number of words
in Rx FIFO is equal to or more than the value. Similarly, Tx threshold means
the value to inform the sender when the number of words in Tx FIFO is equal
to or less than the value. The controller triggers the driver to start
the transfer.
In case of Rx, the driver wants to detect that the specified number of words
N are in Rx FIFO, so the value of Rx threshold should be N. In case of Tx,
the driver wants to detect that the same number of spaces as Rx are in
Tx FIFO, so the value of Tx threshold should be (FIFO size - N).
For example, in order for the driver to receive at least 3 words from
Rx FIFO, set 3 to Rx threshold.
+-+-+-+-+-+-+-+-+
| | | | | |*|*|*|
+-+-+-+-+-+-+-+-+
In order for the driver to send at least 3 words to Tx FIFO, because
it needs at least 3 spaces, set 8(FIFO size) - 3 = 5 to Tx threshold.
+-+-+-+-+-+-+-+-+
|*|*|*|*|*| | | |
+-+-+-+-+-+-+-+-+
This adds new function uniphier_spi_set_fifo_threshold() to set
threshold value to the register.
And more, FIFO counts by 'words', so this renames 'fill_bytes' with
'fill_words', and fixes the calculation using bytes_per_words.
Fixes: 37ffab817098 ("spi: uniphier: introduce polling mode")
Cc: Keiji Hayashibara <hayashibara.keiji@socionext.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1577149107-30670-2-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-12-24 00:58:23 +00:00
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static void uniphier_spi_set_fifo_threshold(struct uniphier_spi_priv *priv,
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unsigned int threshold)
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2018-08-01 07:29:12 +00:00
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{
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u32 val;
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val = readl(priv->base + SSI_FC);
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val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
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spi: uniphier: Fix FIFO threshold
Rx threshold means the value to inform the receiver when the number of words
in Rx FIFO is equal to or more than the value. Similarly, Tx threshold means
the value to inform the sender when the number of words in Tx FIFO is equal
to or less than the value. The controller triggers the driver to start
the transfer.
In case of Rx, the driver wants to detect that the specified number of words
N are in Rx FIFO, so the value of Rx threshold should be N. In case of Tx,
the driver wants to detect that the same number of spaces as Rx are in
Tx FIFO, so the value of Tx threshold should be (FIFO size - N).
For example, in order for the driver to receive at least 3 words from
Rx FIFO, set 3 to Rx threshold.
+-+-+-+-+-+-+-+-+
| | | | | |*|*|*|
+-+-+-+-+-+-+-+-+
In order for the driver to send at least 3 words to Tx FIFO, because
it needs at least 3 spaces, set 8(FIFO size) - 3 = 5 to Tx threshold.
+-+-+-+-+-+-+-+-+
|*|*|*|*|*| | | |
+-+-+-+-+-+-+-+-+
This adds new function uniphier_spi_set_fifo_threshold() to set
threshold value to the register.
And more, FIFO counts by 'words', so this renames 'fill_bytes' with
'fill_words', and fixes the calculation using bytes_per_words.
Fixes: 37ffab817098 ("spi: uniphier: introduce polling mode")
Cc: Keiji Hayashibara <hayashibara.keiji@socionext.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1577149107-30670-2-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-12-24 00:58:23 +00:00
|
|
|
val |= FIELD_PREP(SSI_FC_TXFTH_MASK, SSI_FIFO_DEPTH - threshold);
|
|
|
|
val |= FIELD_PREP(SSI_FC_RXFTH_MASK, threshold);
|
2018-08-01 07:29:12 +00:00
|
|
|
writel(val, priv->base + SSI_FC);
|
spi: uniphier: Fix FIFO threshold
Rx threshold means the value to inform the receiver when the number of words
in Rx FIFO is equal to or more than the value. Similarly, Tx threshold means
the value to inform the sender when the number of words in Tx FIFO is equal
to or less than the value. The controller triggers the driver to start
the transfer.
In case of Rx, the driver wants to detect that the specified number of words
N are in Rx FIFO, so the value of Rx threshold should be N. In case of Tx,
the driver wants to detect that the same number of spaces as Rx are in
Tx FIFO, so the value of Tx threshold should be (FIFO size - N).
For example, in order for the driver to receive at least 3 words from
Rx FIFO, set 3 to Rx threshold.
+-+-+-+-+-+-+-+-+
| | | | | |*|*|*|
+-+-+-+-+-+-+-+-+
In order for the driver to send at least 3 words to Tx FIFO, because
it needs at least 3 spaces, set 8(FIFO size) - 3 = 5 to Tx threshold.
+-+-+-+-+-+-+-+-+
|*|*|*|*|*| | | |
+-+-+-+-+-+-+-+-+
This adds new function uniphier_spi_set_fifo_threshold() to set
threshold value to the register.
And more, FIFO counts by 'words', so this renames 'fill_bytes' with
'fill_words', and fixes the calculation using bytes_per_words.
Fixes: 37ffab817098 ("spi: uniphier: introduce polling mode")
Cc: Keiji Hayashibara <hayashibara.keiji@socionext.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1577149107-30670-2-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-12-24 00:58:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void uniphier_spi_fill_tx_fifo(struct uniphier_spi_priv *priv)
|
|
|
|
{
|
|
|
|
unsigned int fifo_threshold, fill_words;
|
|
|
|
unsigned int bpw = bytes_per_word(priv->bits_per_word);
|
|
|
|
|
|
|
|
fifo_threshold = DIV_ROUND_UP(priv->rx_bytes, bpw);
|
|
|
|
fifo_threshold = min(fifo_threshold, SSI_FIFO_DEPTH);
|
|
|
|
|
|
|
|
uniphier_spi_set_fifo_threshold(priv, fifo_threshold);
|
|
|
|
|
|
|
|
fill_words = fifo_threshold -
|
|
|
|
DIV_ROUND_UP(priv->rx_bytes - priv->tx_bytes, bpw);
|
2018-08-01 07:29:12 +00:00
|
|
|
|
spi: uniphier: Fix FIFO threshold
Rx threshold means the value to inform the receiver when the number of words
in Rx FIFO is equal to or more than the value. Similarly, Tx threshold means
the value to inform the sender when the number of words in Tx FIFO is equal
to or less than the value. The controller triggers the driver to start
the transfer.
In case of Rx, the driver wants to detect that the specified number of words
N are in Rx FIFO, so the value of Rx threshold should be N. In case of Tx,
the driver wants to detect that the same number of spaces as Rx are in
Tx FIFO, so the value of Tx threshold should be (FIFO size - N).
For example, in order for the driver to receive at least 3 words from
Rx FIFO, set 3 to Rx threshold.
+-+-+-+-+-+-+-+-+
| | | | | |*|*|*|
+-+-+-+-+-+-+-+-+
In order for the driver to send at least 3 words to Tx FIFO, because
it needs at least 3 spaces, set 8(FIFO size) - 3 = 5 to Tx threshold.
+-+-+-+-+-+-+-+-+
|*|*|*|*|*| | | |
+-+-+-+-+-+-+-+-+
This adds new function uniphier_spi_set_fifo_threshold() to set
threshold value to the register.
And more, FIFO counts by 'words', so this renames 'fill_bytes' with
'fill_words', and fixes the calculation using bytes_per_words.
Fixes: 37ffab817098 ("spi: uniphier: introduce polling mode")
Cc: Keiji Hayashibara <hayashibara.keiji@socionext.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1577149107-30670-2-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-12-24 00:58:23 +00:00
|
|
|
while (fill_words--)
|
2018-08-01 07:29:12 +00:00
|
|
|
uniphier_spi_send(priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void uniphier_spi_set_cs(struct spi_device *spi, bool enable)
|
|
|
|
{
|
|
|
|
struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master);
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
val = readl(priv->base + SSI_FPS);
|
|
|
|
|
|
|
|
if (enable)
|
|
|
|
val |= SSI_FPS_FSPOL;
|
|
|
|
else
|
|
|
|
val &= ~SSI_FPS_FSPOL;
|
|
|
|
|
|
|
|
writel(val, priv->base + SSI_FPS);
|
|
|
|
}
|
|
|
|
|
2019-12-24 00:58:27 +00:00
|
|
|
static bool uniphier_spi_can_dma(struct spi_master *master,
|
|
|
|
struct spi_device *spi,
|
|
|
|
struct spi_transfer *t)
|
|
|
|
{
|
|
|
|
struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
|
|
|
|
unsigned int bpw = bytes_per_word(priv->bits_per_word);
|
|
|
|
|
|
|
|
if ((!master->dma_tx && !master->dma_rx)
|
|
|
|
|| (!master->dma_tx && t->tx_buf)
|
|
|
|
|| (!master->dma_rx && t->rx_buf))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return DIV_ROUND_UP(t->len, bpw) > SSI_FIFO_DEPTH;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void uniphier_spi_dma_rxcb(void *data)
|
|
|
|
{
|
|
|
|
struct spi_master *master = data;
|
|
|
|
struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
|
|
|
|
int state = atomic_fetch_andnot(SSI_DMA_RX_BUSY, &priv->dma_busy);
|
|
|
|
|
|
|
|
uniphier_spi_irq_disable(priv, SSI_IE_RXRE);
|
|
|
|
|
|
|
|
if (!(state & SSI_DMA_TX_BUSY))
|
|
|
|
spi_finalize_current_transfer(master);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void uniphier_spi_dma_txcb(void *data)
|
|
|
|
{
|
|
|
|
struct spi_master *master = data;
|
|
|
|
struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
|
|
|
|
int state = atomic_fetch_andnot(SSI_DMA_TX_BUSY, &priv->dma_busy);
|
|
|
|
|
|
|
|
uniphier_spi_irq_disable(priv, SSI_IE_TXRE);
|
|
|
|
|
|
|
|
if (!(state & SSI_DMA_RX_BUSY))
|
|
|
|
spi_finalize_current_transfer(master);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int uniphier_spi_transfer_one_dma(struct spi_master *master,
|
|
|
|
struct spi_device *spi,
|
|
|
|
struct spi_transfer *t)
|
|
|
|
{
|
|
|
|
struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
|
|
|
|
struct dma_async_tx_descriptor *rxdesc = NULL, *txdesc = NULL;
|
|
|
|
int buswidth;
|
|
|
|
|
|
|
|
atomic_set(&priv->dma_busy, 0);
|
|
|
|
|
|
|
|
uniphier_spi_set_fifo_threshold(priv, SSI_FIFO_BURST_NUM);
|
|
|
|
|
|
|
|
if (priv->bits_per_word <= 8)
|
|
|
|
buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
|
|
|
|
else if (priv->bits_per_word <= 16)
|
|
|
|
buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
|
|
|
|
else
|
|
|
|
buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
|
|
|
|
|
if (priv->rx_buf) {
|
|
|
|
struct dma_slave_config rxconf = {
|
|
|
|
.direction = DMA_DEV_TO_MEM,
|
|
|
|
.src_addr = priv->base_dma_addr + SSI_RXDR,
|
|
|
|
.src_addr_width = buswidth,
|
|
|
|
.src_maxburst = SSI_FIFO_BURST_NUM,
|
|
|
|
};
|
|
|
|
|
|
|
|
dmaengine_slave_config(master->dma_rx, &rxconf);
|
|
|
|
|
|
|
|
rxdesc = dmaengine_prep_slave_sg(
|
|
|
|
master->dma_rx,
|
|
|
|
t->rx_sg.sgl, t->rx_sg.nents,
|
|
|
|
DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
|
|
if (!rxdesc)
|
|
|
|
goto out_err_prep;
|
|
|
|
|
|
|
|
rxdesc->callback = uniphier_spi_dma_rxcb;
|
|
|
|
rxdesc->callback_param = master;
|
|
|
|
|
|
|
|
uniphier_spi_irq_enable(priv, SSI_IE_RXRE);
|
|
|
|
atomic_or(SSI_DMA_RX_BUSY, &priv->dma_busy);
|
|
|
|
|
|
|
|
dmaengine_submit(rxdesc);
|
|
|
|
dma_async_issue_pending(master->dma_rx);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (priv->tx_buf) {
|
|
|
|
struct dma_slave_config txconf = {
|
|
|
|
.direction = DMA_MEM_TO_DEV,
|
|
|
|
.dst_addr = priv->base_dma_addr + SSI_TXDR,
|
|
|
|
.dst_addr_width = buswidth,
|
|
|
|
.dst_maxburst = SSI_FIFO_BURST_NUM,
|
|
|
|
};
|
|
|
|
|
|
|
|
dmaengine_slave_config(master->dma_tx, &txconf);
|
|
|
|
|
|
|
|
txdesc = dmaengine_prep_slave_sg(
|
|
|
|
master->dma_tx,
|
|
|
|
t->tx_sg.sgl, t->tx_sg.nents,
|
|
|
|
DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
|
|
if (!txdesc)
|
|
|
|
goto out_err_prep;
|
|
|
|
|
|
|
|
txdesc->callback = uniphier_spi_dma_txcb;
|
|
|
|
txdesc->callback_param = master;
|
|
|
|
|
|
|
|
uniphier_spi_irq_enable(priv, SSI_IE_TXRE);
|
|
|
|
atomic_or(SSI_DMA_TX_BUSY, &priv->dma_busy);
|
|
|
|
|
|
|
|
dmaengine_submit(txdesc);
|
|
|
|
dma_async_issue_pending(master->dma_tx);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* signal that we need to wait for completion */
|
|
|
|
return (priv->tx_buf || priv->rx_buf);
|
|
|
|
|
|
|
|
out_err_prep:
|
|
|
|
if (rxdesc)
|
|
|
|
dmaengine_terminate_sync(master->dma_rx);
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2019-09-03 05:31:01 +00:00
|
|
|
static int uniphier_spi_transfer_one_irq(struct spi_master *master,
|
|
|
|
struct spi_device *spi,
|
|
|
|
struct spi_transfer *t)
|
2018-08-01 07:29:12 +00:00
|
|
|
{
|
|
|
|
struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
|
2019-06-26 00:41:47 +00:00
|
|
|
struct device *dev = master->dev.parent;
|
|
|
|
unsigned long time_left;
|
2018-08-01 07:29:12 +00:00
|
|
|
|
|
|
|
reinit_completion(&priv->xfer_done);
|
|
|
|
|
|
|
|
uniphier_spi_fill_tx_fifo(priv);
|
|
|
|
|
2019-12-24 00:58:24 +00:00
|
|
|
uniphier_spi_irq_enable(priv, SSI_IE_RCIE | SSI_IE_RORIE);
|
2018-08-01 07:29:12 +00:00
|
|
|
|
2019-06-26 00:41:47 +00:00
|
|
|
time_left = wait_for_completion_timeout(&priv->xfer_done,
|
|
|
|
msecs_to_jiffies(SSI_TIMEOUT_MS));
|
2018-08-01 07:29:12 +00:00
|
|
|
|
2019-12-24 00:58:24 +00:00
|
|
|
uniphier_spi_irq_disable(priv, SSI_IE_RCIE | SSI_IE_RORIE);
|
2018-08-01 07:29:12 +00:00
|
|
|
|
2019-06-26 00:41:47 +00:00
|
|
|
if (!time_left) {
|
|
|
|
dev_err(dev, "transfer timeout.\n");
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
2018-08-01 07:29:12 +00:00
|
|
|
|
|
|
|
return priv->error;
|
|
|
|
}
|
|
|
|
|
2019-09-03 05:31:01 +00:00
|
|
|
static int uniphier_spi_transfer_one_poll(struct spi_master *master,
|
|
|
|
struct spi_device *spi,
|
|
|
|
struct spi_transfer *t)
|
|
|
|
{
|
|
|
|
struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
|
|
|
|
int loop = SSI_POLL_TIMEOUT_US * 10;
|
|
|
|
|
|
|
|
while (priv->tx_bytes) {
|
|
|
|
uniphier_spi_fill_tx_fifo(priv);
|
|
|
|
|
|
|
|
while ((priv->rx_bytes - priv->tx_bytes) > 0) {
|
|
|
|
while (!(readl(priv->base + SSI_SR) & SSI_SR_RNE)
|
|
|
|
&& loop--)
|
|
|
|
ndelay(100);
|
|
|
|
|
|
|
|
if (loop == -1)
|
|
|
|
goto irq_transfer;
|
|
|
|
|
|
|
|
uniphier_spi_recv(priv);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
irq_transfer:
|
|
|
|
return uniphier_spi_transfer_one_irq(master, spi, t);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int uniphier_spi_transfer_one(struct spi_master *master,
|
|
|
|
struct spi_device *spi,
|
|
|
|
struct spi_transfer *t)
|
|
|
|
{
|
|
|
|
struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
|
|
|
|
unsigned long threshold;
|
2019-12-24 00:58:27 +00:00
|
|
|
bool use_dma;
|
2019-09-03 05:31:01 +00:00
|
|
|
|
|
|
|
/* Terminate and return success for 0 byte length transfer */
|
|
|
|
if (!t->len)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
uniphier_spi_setup_transfer(spi, t);
|
|
|
|
|
2019-12-24 00:58:27 +00:00
|
|
|
use_dma = master->can_dma ? master->can_dma(master, spi, t) : false;
|
|
|
|
if (use_dma)
|
|
|
|
return uniphier_spi_transfer_one_dma(master, spi, t);
|
|
|
|
|
2019-09-03 05:31:01 +00:00
|
|
|
/*
|
|
|
|
* If the transfer operation will take longer than
|
|
|
|
* SSI_POLL_TIMEOUT_US, it should use irq.
|
|
|
|
*/
|
|
|
|
threshold = DIV_ROUND_UP(SSI_POLL_TIMEOUT_US * priv->speed_hz,
|
|
|
|
USEC_PER_SEC * BITS_PER_BYTE);
|
|
|
|
if (t->len > threshold)
|
|
|
|
return uniphier_spi_transfer_one_irq(master, spi, t);
|
|
|
|
else
|
|
|
|
return uniphier_spi_transfer_one_poll(master, spi, t);
|
|
|
|
}
|
|
|
|
|
2018-08-01 07:29:12 +00:00
|
|
|
static int uniphier_spi_prepare_transfer_hardware(struct spi_master *master)
|
|
|
|
{
|
|
|
|
struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
|
|
|
|
|
|
|
|
writel(SSI_CTL_EN, priv->base + SSI_CTL);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int uniphier_spi_unprepare_transfer_hardware(struct spi_master *master)
|
|
|
|
{
|
|
|
|
struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
|
|
|
|
|
|
|
|
writel(0, priv->base + SSI_CTL);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-12-24 00:58:25 +00:00
|
|
|
static void uniphier_spi_handle_err(struct spi_master *master,
|
|
|
|
struct spi_message *msg)
|
|
|
|
{
|
|
|
|
struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
/* stop running spi transfer */
|
|
|
|
writel(0, priv->base + SSI_CTL);
|
|
|
|
|
|
|
|
/* reset FIFOs */
|
|
|
|
val = SSI_FC_TXFFL | SSI_FC_RXFFL;
|
|
|
|
writel(val, priv->base + SSI_FC);
|
|
|
|
|
2019-12-24 00:58:27 +00:00
|
|
|
uniphier_spi_irq_disable(priv, SSI_IE_ALL_MASK);
|
|
|
|
|
|
|
|
if (atomic_read(&priv->dma_busy) & SSI_DMA_TX_BUSY) {
|
|
|
|
dmaengine_terminate_async(master->dma_tx);
|
|
|
|
atomic_andnot(SSI_DMA_TX_BUSY, &priv->dma_busy);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (atomic_read(&priv->dma_busy) & SSI_DMA_RX_BUSY) {
|
|
|
|
dmaengine_terminate_async(master->dma_rx);
|
|
|
|
atomic_andnot(SSI_DMA_RX_BUSY, &priv->dma_busy);
|
|
|
|
}
|
2019-12-24 00:58:25 +00:00
|
|
|
}
|
|
|
|
|
2018-08-01 07:29:12 +00:00
|
|
|
static irqreturn_t uniphier_spi_handler(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct uniphier_spi_priv *priv = dev_id;
|
|
|
|
u32 val, stat;
|
|
|
|
|
|
|
|
stat = readl(priv->base + SSI_IS);
|
|
|
|
val = SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC;
|
|
|
|
writel(val, priv->base + SSI_IC);
|
|
|
|
|
|
|
|
/* rx fifo overrun */
|
|
|
|
if (stat & SSI_IS_RORID) {
|
|
|
|
priv->error = -EIO;
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* rx complete */
|
|
|
|
if ((stat & SSI_IS_RCID) && (stat & SSI_IS_RXRS)) {
|
|
|
|
while ((readl(priv->base + SSI_SR) & SSI_SR_RNE) &&
|
|
|
|
(priv->rx_bytes - priv->tx_bytes) > 0)
|
|
|
|
uniphier_spi_recv(priv);
|
|
|
|
|
|
|
|
if ((readl(priv->base + SSI_SR) & SSI_SR_RNE) ||
|
|
|
|
(priv->rx_bytes != priv->tx_bytes)) {
|
|
|
|
priv->error = -EIO;
|
|
|
|
goto done;
|
|
|
|
} else if (priv->rx_bytes == 0)
|
|
|
|
goto done;
|
|
|
|
|
|
|
|
/* next tx transfer */
|
|
|
|
uniphier_spi_fill_tx_fifo(priv);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
done:
|
|
|
|
complete(&priv->xfer_done);
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int uniphier_spi_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct uniphier_spi_priv *priv;
|
|
|
|
struct spi_master *master;
|
2019-12-24 00:58:27 +00:00
|
|
|
struct resource *res;
|
|
|
|
struct dma_slave_caps caps;
|
|
|
|
u32 dma_tx_burst = 0, dma_rx_burst = 0;
|
2018-08-01 07:29:12 +00:00
|
|
|
unsigned long clk_rate;
|
|
|
|
int irq;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(*priv));
|
|
|
|
if (!master)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
|
|
|
|
priv = spi_master_get_devdata(master);
|
|
|
|
priv->master = master;
|
|
|
|
priv->is_save_param = false;
|
|
|
|
|
2020-05-11 08:25:30 +00:00
|
|
|
priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
|
2018-08-01 07:29:12 +00:00
|
|
|
if (IS_ERR(priv->base)) {
|
|
|
|
ret = PTR_ERR(priv->base);
|
|
|
|
goto out_master_put;
|
|
|
|
}
|
2019-12-24 00:58:27 +00:00
|
|
|
priv->base_dma_addr = res->start;
|
2018-08-01 07:29:12 +00:00
|
|
|
|
|
|
|
priv->clk = devm_clk_get(&pdev->dev, NULL);
|
|
|
|
if (IS_ERR(priv->clk)) {
|
|
|
|
dev_err(&pdev->dev, "failed to get clock\n");
|
|
|
|
ret = PTR_ERR(priv->clk);
|
|
|
|
goto out_master_put;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = clk_prepare_enable(priv->clk);
|
|
|
|
if (ret)
|
|
|
|
goto out_master_put;
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq < 0) {
|
|
|
|
ret = irq;
|
|
|
|
goto out_disable_clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, uniphier_spi_handler,
|
|
|
|
0, "uniphier-spi", priv);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "failed to request IRQ\n");
|
|
|
|
goto out_disable_clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
init_completion(&priv->xfer_done);
|
|
|
|
|
|
|
|
clk_rate = clk_get_rate(priv->clk);
|
|
|
|
|
|
|
|
master->max_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MIN_CLK_DIVIDER);
|
|
|
|
master->min_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MAX_CLK_DIVIDER);
|
|
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
|
|
|
|
master->dev.of_node = pdev->dev.of_node;
|
|
|
|
master->bus_num = pdev->id;
|
|
|
|
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
|
|
|
|
|
|
|
|
master->set_cs = uniphier_spi_set_cs;
|
|
|
|
master->transfer_one = uniphier_spi_transfer_one;
|
|
|
|
master->prepare_transfer_hardware
|
|
|
|
= uniphier_spi_prepare_transfer_hardware;
|
|
|
|
master->unprepare_transfer_hardware
|
|
|
|
= uniphier_spi_unprepare_transfer_hardware;
|
2019-12-24 00:58:25 +00:00
|
|
|
master->handle_err = uniphier_spi_handle_err;
|
2019-12-24 00:58:27 +00:00
|
|
|
master->can_dma = uniphier_spi_can_dma;
|
|
|
|
|
2018-08-01 07:29:12 +00:00
|
|
|
master->num_chipselect = 1;
|
2019-12-24 00:58:27 +00:00
|
|
|
master->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
|
|
|
|
|
|
|
|
master->dma_tx = dma_request_chan(&pdev->dev, "tx");
|
|
|
|
if (IS_ERR_OR_NULL(master->dma_tx)) {
|
2020-04-29 07:58:55 +00:00
|
|
|
if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) {
|
|
|
|
ret = -EPROBE_DEFER;
|
2019-12-24 00:58:27 +00:00
|
|
|
goto out_disable_clk;
|
2020-04-29 07:58:55 +00:00
|
|
|
}
|
2019-12-24 00:58:27 +00:00
|
|
|
master->dma_tx = NULL;
|
|
|
|
dma_tx_burst = INT_MAX;
|
|
|
|
} else {
|
|
|
|
ret = dma_get_slave_caps(master->dma_tx, &caps);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "failed to get TX DMA capacities: %d\n",
|
|
|
|
ret);
|
2022-01-25 10:12:15 +00:00
|
|
|
goto out_release_dma;
|
2019-12-24 00:58:27 +00:00
|
|
|
}
|
|
|
|
dma_tx_burst = caps.max_burst;
|
|
|
|
}
|
|
|
|
|
|
|
|
master->dma_rx = dma_request_chan(&pdev->dev, "rx");
|
|
|
|
if (IS_ERR_OR_NULL(master->dma_rx)) {
|
2020-04-29 07:58:55 +00:00
|
|
|
if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) {
|
|
|
|
ret = -EPROBE_DEFER;
|
2022-01-25 10:12:15 +00:00
|
|
|
goto out_release_dma;
|
2020-04-29 07:58:55 +00:00
|
|
|
}
|
2019-12-24 00:58:27 +00:00
|
|
|
master->dma_rx = NULL;
|
|
|
|
dma_rx_burst = INT_MAX;
|
|
|
|
} else {
|
|
|
|
ret = dma_get_slave_caps(master->dma_rx, &caps);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "failed to get RX DMA capacities: %d\n",
|
|
|
|
ret);
|
2022-01-25 10:12:15 +00:00
|
|
|
goto out_release_dma;
|
2019-12-24 00:58:27 +00:00
|
|
|
}
|
|
|
|
dma_rx_burst = caps.max_burst;
|
|
|
|
}
|
|
|
|
|
|
|
|
master->max_dma_len = min(dma_tx_burst, dma_rx_burst);
|
2018-08-01 07:29:12 +00:00
|
|
|
|
|
|
|
ret = devm_spi_register_master(&pdev->dev, master);
|
|
|
|
if (ret)
|
2022-01-25 10:12:15 +00:00
|
|
|
goto out_release_dma;
|
2018-08-01 07:29:12 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2022-01-25 10:12:15 +00:00
|
|
|
out_release_dma:
|
|
|
|
if (!IS_ERR_OR_NULL(master->dma_rx)) {
|
|
|
|
dma_release_channel(master->dma_rx);
|
|
|
|
master->dma_rx = NULL;
|
|
|
|
}
|
|
|
|
if (!IS_ERR_OR_NULL(master->dma_tx)) {
|
|
|
|
dma_release_channel(master->dma_tx);
|
|
|
|
master->dma_tx = NULL;
|
|
|
|
}
|
|
|
|
|
2018-08-01 07:29:12 +00:00
|
|
|
out_disable_clk:
|
|
|
|
clk_disable_unprepare(priv->clk);
|
|
|
|
|
|
|
|
out_master_put:
|
|
|
|
spi_master_put(master);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int uniphier_spi_remove(struct platform_device *pdev)
|
|
|
|
{
|
2021-12-22 04:48:12 +00:00
|
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
|
|
struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
|
2018-08-01 07:29:12 +00:00
|
|
|
|
2021-12-22 04:48:12 +00:00
|
|
|
if (master->dma_tx)
|
|
|
|
dma_release_channel(master->dma_tx);
|
|
|
|
if (master->dma_rx)
|
|
|
|
dma_release_channel(master->dma_rx);
|
2019-12-24 00:58:27 +00:00
|
|
|
|
2018-08-01 07:29:12 +00:00
|
|
|
clk_disable_unprepare(priv->clk);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id uniphier_spi_match[] = {
|
|
|
|
{ .compatible = "socionext,uniphier-scssi" },
|
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, uniphier_spi_match);
|
|
|
|
|
|
|
|
static struct platform_driver uniphier_spi_driver = {
|
|
|
|
.probe = uniphier_spi_probe,
|
|
|
|
.remove = uniphier_spi_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = "uniphier-spi",
|
|
|
|
.of_match_table = uniphier_spi_match,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
module_platform_driver(uniphier_spi_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
|
|
|
|
MODULE_AUTHOR("Keiji Hayashibara <hayashibara.keiji@socionext.com>");
|
|
|
|
MODULE_DESCRIPTION("Socionext UniPhier SPI controller driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|