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x86/intel_rdt/mba: Add primary support for Memory Bandwidth Allocation (MBA)
The MBA feature details like minimum bandwidth supported, bandwidth granularity etc are obtained via executing CPUID with EAX=10H ,ECX=3. Setup and initialize the MBA specific extensions to data structures like global list of RDT resources, RDT resource structure and RDT domain structure. [ tglx: Split out the seperate structure and the CBM related parts ] Signed-off-by: Vikas Shivappa <vikas.shivappa@linux.intel.com> Cc: ravi.v.shankar@intel.com Cc: tony.luck@intel.com Cc: fenghua.yu@intel.com Cc: vikas.shivappa@intel.com Link: http://lkml.kernel.org/r/1491611637-20417-5-git-send-email-vikas.shivappa@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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parent
ab66a33b03
commit
05b93417ce
2 changed files with 110 additions and 3 deletions
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@ -12,6 +12,7 @@
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#define IA32_L3_QOS_CFG 0xc81
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#define IA32_L3_CBM_BASE 0xc90
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#define IA32_L2_CBM_BASE 0xd10
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#define IA32_MBA_THRTL_BASE 0xd50
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#define L3_QOS_CDP_ENABLE 0x01ULL
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@ -119,6 +120,23 @@ struct rdt_cache {
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unsigned int cbm_idx_offset;
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};
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/**
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* struct rdt_membw - Memory bandwidth allocation related data
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* @max_delay: Max throttle delay. Delay is the hardware
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* representation for memory bandwidth.
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* @min_bw: Minimum memory bandwidth percentage user can request
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* @bw_gran: Granularity at which the memory bandwidth is allocated
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* @delay_linear: True if memory B/W delay is in linear scale
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* @mb_map: Mapping of memory B/W percentage to memory B/W delay
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*/
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struct rdt_membw {
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u32 max_delay;
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u32 min_bw;
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u32 bw_gran;
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u32 delay_linear;
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u32 *mb_map;
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};
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/**
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* struct rdt_resource - attributes of an RDT resource
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* @enabled: Is this feature enabled on this machine
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@ -145,7 +163,10 @@ struct rdt_resource {
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struct rdt_resource *r);
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int data_width;
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struct list_head domains;
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struct rdt_cache cache;
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union {
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struct rdt_cache cache;
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struct rdt_membw membw;
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};
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};
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extern struct mutex rdtgroup_mutex;
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@ -161,6 +182,7 @@ enum {
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RDT_RESOURCE_L3DATA,
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RDT_RESOURCE_L3CODE,
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RDT_RESOURCE_L2,
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RDT_RESOURCE_MBA,
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/* Must be the last */
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RDT_NUM_RESOURCES,
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@ -32,6 +32,9 @@
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#include <asm/intel-family.h>
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#include <asm/intel_rdt.h>
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#define MAX_MBA_BW 100u
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#define MBA_IS_LINEAR 0x4
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/* Mutex to protect rdtgroup access. */
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DEFINE_MUTEX(rdtgroup_mutex);
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@ -43,6 +46,8 @@ DEFINE_PER_CPU_READ_MOSTLY(int, cpu_closid);
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*/
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int max_name_width, max_data_width;
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static void
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mba_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r);
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static void
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cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r);
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@ -97,6 +102,13 @@ struct rdt_resource rdt_resources_all[] = {
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.cbm_idx_offset = 0,
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},
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},
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{
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.name = "MB",
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.domains = domain_init(RDT_RESOURCE_MBA),
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.msr_base = IA32_MBA_THRTL_BASE,
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.msr_update = mba_wrmsr,
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.cache_level = 3,
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},
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};
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static unsigned int cbm_idx(struct rdt_resource *r, unsigned int closid)
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@ -151,6 +163,53 @@ static inline bool cache_alloc_hsw_probe(void)
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return false;
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}
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/*
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* rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values
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* exposed to user interface and the h/w understandable delay values.
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*
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* The non-linear delay values have the granularity of power of two
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* and also the h/w does not guarantee a curve for configured delay
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* values vs. actual b/w enforced.
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* Hence we need a mapping that is pre calibrated so the user can
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* express the memory b/w as a percentage value.
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*/
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static inline bool rdt_get_mb_table(struct rdt_resource *r)
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{
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/*
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* There are no Intel SKUs as of now to support non-linear delay.
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*/
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pr_info("MBA b/w map not implemented for cpu:%d, model:%d",
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boot_cpu_data.x86, boot_cpu_data.x86_model);
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return false;
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}
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static bool rdt_get_mem_config(struct rdt_resource *r)
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{
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union cpuid_0x10_3_eax eax;
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union cpuid_0x10_x_edx edx;
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u32 ebx, ecx;
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cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full);
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r->num_closid = edx.split.cos_max + 1;
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r->membw.max_delay = eax.split.max_delay + 1;
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r->default_ctrl = MAX_MBA_BW;
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if (ecx & MBA_IS_LINEAR) {
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r->membw.delay_linear = true;
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r->membw.min_bw = MAX_MBA_BW - r->membw.max_delay;
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r->membw.bw_gran = MAX_MBA_BW - r->membw.max_delay;
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} else {
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if (!rdt_get_mb_table(r))
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return false;
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}
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r->data_width = 3;
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r->capable = true;
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r->enabled = true;
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return true;
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}
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static void rdt_get_cache_config(int idx, struct rdt_resource *r)
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{
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union cpuid_0x10_1_eax eax;
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@ -196,6 +255,30 @@ static int get_cache_id(int cpu, int level)
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return -1;
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}
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/*
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* Map the memory b/w percentage value to delay values
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* that can be written to QOS_MSRs.
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* There are currently no SKUs which support non linear delay values.
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*/
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static u32 delay_bw_map(unsigned long bw, struct rdt_resource *r)
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{
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if (r->membw.delay_linear)
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return MAX_MBA_BW - bw;
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pr_warn_once("Non Linear delay-bw map not supported but queried\n");
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return r->default_ctrl;
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}
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static void
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mba_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r)
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{
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unsigned int i;
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/* Write the delay values for mba. */
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for (i = m->low; i < m->high; i++)
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wrmsrl(r->msr_base + i, delay_bw_map(d->ctrl_val[i], r));
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}
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static void
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cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r)
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{
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@ -431,8 +514,10 @@ static __init bool get_rdt_resources(void)
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ret = true;
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}
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if (boot_cpu_has(X86_FEATURE_MBA))
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ret = true;
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if (boot_cpu_has(X86_FEATURE_MBA)) {
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if (rdt_get_mem_config(&rdt_resources_all[RDT_RESOURCE_MBA]))
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ret = true;
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}
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return ret;
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}
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