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synced 2024-08-21 16:29:59 +00:00
Merge branch 'drm-fixes-3.8' of git://people.freedesktop.org/~agd5f/linux
Alex writes: "A few more radeon fixes for 3.8. Mostly small stuff. The big change is disabling the use of the DMA ring for VM PT updates. This reverts back to the 3.7 behavior. Problem is we can get huge PT updates in certain cases that are too big for the DMA ring. I've got patches to use an IB for this so I can re-enable the use of the DMA ring for VM PT updates in 3.9. This request also includes the patches from the last pull request I sent on Monday in case you haven't pulled them yet." * 'drm-fixes-3.8' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: switch back to the CP ring for VM PT updates drm/radeon: prevent crash in the ring space allocation drm/radeon: Calling object_unrefer() when creating fb failure drm/radeon/r5xx-r7xx: wait for the MC to settle after MC blackout drm/radeon/evergreen+: wait for the MC to settle after MC blackout drm/radeon: protect against div by 0 in backend setup drm/radeon: fix backend map setup on 1 RB sumo boards drm/radeon: add quirk for RV100 board drm/radeon: add WAIT_UNTIL to the non-VM safe regs list for cayman/TN drm/radeon: fix MC blackout on evergreen+
This commit is contained in:
commit
089c71a7c3
8 changed files with 49 additions and 9 deletions
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@ -1313,14 +1313,18 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
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if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
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radeon_wait_for_vblank(rdev, i);
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tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
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WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
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}
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} else {
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tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
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if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
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radeon_wait_for_vblank(rdev, i);
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tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
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WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
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}
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}
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/* wait for the next frame */
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@ -1345,6 +1349,8 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
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blackout &= ~BLACKOUT_MODE_MASK;
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WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
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}
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/* wait for the MC to settle */
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udelay(100);
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}
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void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
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@ -1378,11 +1384,15 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
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if (ASIC_IS_DCE6(rdev)) {
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tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
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tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
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WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
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} else {
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tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
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tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
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WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
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}
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/* wait for the next frame */
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frame_count = radeon_get_vblank_counter(rdev, i);
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@ -2036,9 +2046,20 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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WREG32(HDP_ADDR_CONFIG, gb_addr_config);
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WREG32(DMA_TILING_CONFIG, gb_addr_config);
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tmp = gb_addr_config & NUM_PIPES_MASK;
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tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
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EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
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if ((rdev->config.evergreen.max_backends == 1) &&
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(rdev->flags & RADEON_IS_IGP)) {
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if ((disabled_rb_mask & 3) == 1) {
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/* RB0 disabled, RB1 enabled */
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tmp = 0x11111111;
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} else {
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/* RB1 disabled, RB0 enabled */
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tmp = 0x00000000;
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}
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} else {
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tmp = gb_addr_config & NUM_PIPES_MASK;
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tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
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EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
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}
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WREG32(GB_BACKEND_MAP, tmp);
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WREG32(CGTS_SYS_TCC_DISABLE, 0);
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@ -1462,12 +1462,15 @@ u32 r6xx_remap_render_backend(struct radeon_device *rdev,
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u32 disabled_rb_mask)
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{
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u32 rendering_pipe_num, rb_num_width, req_rb_num;
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u32 pipe_rb_ratio, pipe_rb_remain;
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u32 pipe_rb_ratio, pipe_rb_remain, tmp;
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u32 data = 0, mask = 1 << (max_rb_num - 1);
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unsigned i, j;
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/* mask out the RBs that don't exist on that asic */
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disabled_rb_mask |= (0xff << max_rb_num) & 0xff;
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tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
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/* make sure at least one RB is available */
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if ((tmp & 0xff) != 0xff)
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disabled_rb_mask = tmp;
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rendering_pipe_num = 1 << tiling_pipe_num;
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req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
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@ -1445,7 +1445,7 @@ static struct radeon_asic cayman_asic = {
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.vm = {
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.init = &cayman_vm_init,
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.fini = &cayman_vm_fini,
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.pt_ring_index = R600_RING_TYPE_DMA_INDEX,
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.pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
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.set_page = &cayman_vm_set_page,
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},
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.ring = {
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@ -1572,7 +1572,7 @@ static struct radeon_asic trinity_asic = {
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.vm = {
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.init = &cayman_vm_init,
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.fini = &cayman_vm_fini,
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.pt_ring_index = R600_RING_TYPE_DMA_INDEX,
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.pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
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.set_page = &cayman_vm_set_page,
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},
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.ring = {
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@ -1699,7 +1699,7 @@ static struct radeon_asic si_asic = {
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.vm = {
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.init = &si_vm_init,
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.fini = &si_vm_fini,
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.pt_ring_index = R600_RING_TYPE_DMA_INDEX,
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.pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
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.set_page = &si_vm_set_page,
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},
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.ring = {
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@ -2470,6 +2470,14 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
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1),
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ATOM_DEVICE_CRT1_SUPPORT);
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}
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/* RV100 board with external TDMS bit mis-set.
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* Actually uses internal TMDS, clear the bit.
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*/
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if (dev->pdev->device == 0x5159 &&
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dev->pdev->subsystem_vendor == 0x1014 &&
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dev->pdev->subsystem_device == 0x029A) {
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tmp &= ~(1 << 4);
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}
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if ((tmp >> 4) & 0x1) {
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devices |= ATOM_DEVICE_DFP2_SUPPORT;
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radeon_add_legacy_encoder(dev,
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@ -1115,8 +1115,10 @@ radeon_user_framebuffer_create(struct drm_device *dev,
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}
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radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
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if (radeon_fb == NULL)
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if (radeon_fb == NULL) {
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drm_gem_object_unreference_unlocked(obj);
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return ERR_PTR(-ENOMEM);
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}
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ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
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if (ret) {
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@ -377,6 +377,9 @@ int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsi
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{
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int r;
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/* make sure we aren't trying to allocate more space than there is on the ring */
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if (ndw > (ring->ring_size / 4))
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return -ENOMEM;
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/* Align requested size with padding so unlock_commit can
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* pad safely */
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ndw = (ndw + ring->align_mask) & ~ring->align_mask;
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@ -1,5 +1,6 @@
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cayman 0x9400
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0x0000802C GRBM_GFX_INDEX
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0x00008040 WAIT_UNTIL
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0x000084FC CP_STRMOUT_CNTL
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0x000085F0 CP_COHER_CNTL
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0x000085F4 CP_COHER_SIZE
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@ -336,6 +336,8 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
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WREG32(R600_CITF_CNTL, blackout);
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}
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}
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/* wait for the MC to settle */
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udelay(100);
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}
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void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
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