mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-08-26 19:00:25 +00:00
Code Issues Releases Wiki Activity

drm/omap: omap_display_timings: rename hfp to hfront_porch

Browse source 
In preparation to move the stack to use the generic videmode struct for
display timing information rename the hfp member to hfront_porch.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Peter Ujfalusi 2016-09-22 14:06:49 +03:00 committed by Tomi Valkeinen
parent 4dc2250d7d
commit 0a30e150f0
18 changed files with 47 additions and 45 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c
View file

@ -34,7 +34,7 @@ static const struct omap_video_timings tvc_pal_timings = {
.vactive = 574,
.pixelclock = 13500000,
.hsync_len = 64,
.hfp = 12,
.hfront_porch = 12,
.hbp = 68,
.vsw = 5,
.vfp = 5,

2
drivers/gpu/drm/omapdrm/displays/connector-dvi.c
View file

@ -25,7 +25,7 @@ static const struct omap_video_timings dvic_default_timings = {
.pixelclock = 23500000,
.hfp = 48,
.hfront_porch = 48,
.hsync_len = 32,
.hbp = 80,

2
drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
View file

@ -26,7 +26,7 @@ static const struct omap_video_timings hdmic_default_timings = {
.vactive = 480,
.pixelclock = 25175000,
.hsync_len = 96,
.hfp = 16,
.hfront_porch = 16,
.hbp = 48,
.vsw = 2,
.vfp = 11,

2
drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c
View file

@ -26,7 +26,7 @@ static struct omap_video_timings lb035q02_timings = {
.pixelclock = 6500000,
.hsync_len = 2,
.hfp = 20,
.hfront_porch = 20,
.hbp = 68,
.vsw = 2,

2
drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c
View file

@ -69,7 +69,7 @@ static const struct omap_video_timings nec_8048_panel_timings = {
.hactive = LCD_XRES,
.vactive = LCD_YRES,
.pixelclock = LCD_PIXEL_CLOCK,
.hfp = 6,
.hfront_porch = 6,
.hsync_len = 1,
.hbp = 4,
.vfp = 3,

2
drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c
View file

@ -42,7 +42,7 @@ static const struct omap_video_timings sharp_ls_timings = {
.pixelclock = 19200000,
.hsync_len = 2,
.hfp = 1,
.hfront_porch = 1,
.hbp = 28,
.vsw = 1,

2
drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c
View file

@ -96,7 +96,7 @@ static const struct omap_video_timings acx565akm_panel_timings = {
.hactive = 800,
.vactive = 480,
.pixelclock = 24000000,
.hfp = 28,
.hfront_porch = 28,
.hsync_len = 4,
.hbp = 24,
.vfp = 3,

2
drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c
View file

@ -46,7 +46,7 @@ static struct omap_video_timings td028ttec1_panel_timings = {
.hactive = 480,
.vactive = 640,
.pixelclock = 22153000,
.hfp = 24,
.hfront_porch = 24,
.hsync_len = 8,
.hbp = 8,
.vfp = 4,

2
drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c
View file

@ -79,7 +79,7 @@ static const struct omap_video_timings tpo_td043_timings = {
.pixelclock = 36000000,
.hsync_len = 1,
.hfp = 68,
.hfront_porch = 68,
.hbp = 214,
.vsw = 1,

22
drivers/gpu/drm/omapdrm/dss/dispc.c
View file

@ -2189,14 +2189,16 @@ static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
u64 val, blank;
int i;
nonactive = t->hactive + t->hfp + t->hsync_len + t->hbp - out_width;
nonactive = t->hactive + t->hfront_porch + t->hsync_len +
t->hbp - out_width;
i = 0;
if (out_height < height)
i++;
if (out_width < width)
i++;
blank = div_u64((u64)(t->hbp + t->hsync_len + t->hfp) * lclk, pclk);
blank = div_u64((u64)(t->hbp + t->hsync_len + t->hfront_porch) *
lclk, pclk);
DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
if (blank <= limits[i])
return -EINVAL;
@ -3129,9 +3131,9 @@ bool dispc_mgr_timings_ok(enum omap_channel channel,
if (timings->interlace)
return false;
if (!_dispc_lcd_timings_ok(timings->hsync_len, timings->hfp,
timings->hbp, timings->vsw, timings->vfp,
timings->vbp))
if (!_dispc_lcd_timings_ok(timings->hsync_len,
timings->hfront_porch, timings->hbp,
timings->vsw, timings->vfp, timings->vbp))
return false;
}
@ -3267,12 +3269,12 @@ void dispc_mgr_set_timings(enum omap_channel channel,
}
if (dss_mgr_is_lcd(channel)) {
_dispc_mgr_set_lcd_timings(channel, t.hsync_len, t.hfp, t.hbp,
t.vsw, t.vfp, t.vbp, t.vsync_level,
_dispc_mgr_set_lcd_timings(channel, t.hsync_len, t.hfront_porch,
t.hbp, t.vsw, t.vfp, t.vbp, t.vsync_level,
t.hsync_level, t.data_pclk_edge, t.de_level,
t.sync_pclk_edge);
xtot = t.hactive + t.hfp + t.hsync_len + t.hbp;
xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hbp;
ytot = t.vactive + t.vfp + t.vsw + t.vbp;
ht = timings->pixelclock / xtot;
@ -3280,7 +3282,7 @@ void dispc_mgr_set_timings(enum omap_channel channel,
DSSDBG("pck %u\n", timings->pixelclock);
DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
t.hsync_len, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
t.hsync_len, t.hfront_porch, t.hbp, t.vsw, t.vfp, t.vbp);
DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
t.vsync_level, t.hsync_level, t.data_pclk_edge,
t.de_level, t.sync_pclk_edge);
@ -4223,7 +4225,7 @@ static const struct dispc_errata_i734_data {
.timings = {
.hactive = 8, .vactive = 1,
.pixelclock = 16000000,
.hsync_len = 8, .hfp = 4, .hbp = 4,
.hsync_len = 8, .hfront_porch = 4, .hbp = 4,
.vsw = 1, .vfp = 1, .vbp = 1,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,

4
drivers/gpu/drm/omapdrm/dss/display.c
View file

@ -226,7 +226,7 @@ void videomode_to_omap_video_timings(const struct videomode *vm,
ovt->pixelclock = vm->pixelclock;
ovt->hactive = vm->hactive;
ovt->hbp = vm->hback_porch;
ovt->hfp = vm->hfront_porch;
ovt->hfront_porch = vm->hfront_porch;
ovt->hsync_len = vm->hsync_len;
ovt->vactive = vm->vactive;
ovt->vbp = vm->vback_porch;
@ -259,7 +259,7 @@ void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
vm->hactive = ovt->hactive;
vm->hback_porch = ovt->hbp;
vm->hfront_porch = ovt->hfp;
vm->hfront_porch = ovt->hfront_porch;
vm->hsync_len = ovt->hsync_len;
vm->vactive = ovt->vactive;
vm->vback_porch = ovt->vbp;

22
drivers/gpu/drm/omapdrm/dss/dsi.c
View file

@ -4331,7 +4331,7 @@ static void print_dsi_vm(const char *str,
wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
bl = t->hss + t->hsa + t->hse + t->hbp + t->hfront_porch;
tot = bl + pps;
#define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
@ -4340,14 +4340,14 @@ static void print_dsi_vm(const char *str,
"%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
str,
byteclk,
t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
t->hss, t->hsa, t->hse, t->hbp, pps, t->hfront_porch,
bl, pps, tot,
TO_DSI_T(t->hss),
TO_DSI_T(t->hsa),
TO_DSI_T(t->hse),
TO_DSI_T(t->hbp),
TO_DSI_T(pps),
TO_DSI_T(t->hfp),
TO_DSI_T(t->hfront_porch),
TO_DSI_T(bl),
TO_DSI_T(pps),
@ -4362,7 +4362,7 @@ static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
int hact, bl, tot;
hact = t->hactive;
bl = t->hsync_len + t->hbp + t->hfp;
bl = t->hsync_len + t->hbp + t->hfront_porch;
tot = hact + bl;
#define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
@ -4371,12 +4371,12 @@ static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
"%u/%u/%u/%u = %u + %u = %u\n",
str,
pck,
t->hsync_len, t->hbp, hact, t->hfp,
t->hsync_len, t->hbp, hact, t->hfront_porch,
bl, hact, tot,
TO_DISPC_T(t->hsync_len),
TO_DISPC_T(t->hbp),
TO_DISPC_T(hact),
TO_DISPC_T(t->hfp),
TO_DISPC_T(t->hfront_porch),
TO_DISPC_T(bl),
TO_DISPC_T(hact),
TO_DISPC_T(tot));
@ -4396,12 +4396,12 @@ static void print_dsi_dispc_vm(const char *str,
dsi_tput = (u64)byteclk * t->ndl * 8;
pck = (u32)div64_u64(dsi_tput, t->bitspp);
dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfront_porch;
vm.pixelclock = pck;
vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
vm.hfront_porch = div64_u64((u64)t->hfront_porch * pck, byteclk);
vm.hactive = t->hact;
print_dispc_vm(str, &vm);
@ -4423,7 +4423,7 @@ static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
t->pixelclock = pck;
t->hactive = ctx->config->timings->hactive;
t->vactive = ctx->config->timings->vactive;
t->hsync_len = t->hfp = t->hbp = t->vsw = 1;
t->hsync_len = t->hfront_porch = t->hbp = t->vsw = 1;
t->vfp = t->vbp = 0;
return true;
@ -4527,7 +4527,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
xres = req_vm->hactive;
panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsync_len;
panel_hbl = req_vm->hfront_porch + req_vm->hbp + req_vm->hsync_len;
panel_htot = xres + panel_hbl;
dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
@ -4685,7 +4685,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
if (hfp < 1)
return false;
dispc_vm->hfp = hfp;
dispc_vm->hfront_porch = hfp;
dispc_vm->hsync_len = hsa;
dispc_vm->hbp = hbp;

8
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
View file

@ -296,7 +296,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
/* video core */
video_cfg->data_enable_pol = 1; /* It is always 1*/
video_cfg->hblank = cfg->timings.hfp +
video_cfg->hblank = cfg->timings.hfront_porch +
cfg->timings.hbp + cfg->timings.hsync_len;
video_cfg->vblank_osc = 0;
video_cfg->vblank = cfg->timings.vsw +
@ -318,7 +318,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
if (cfg->timings.double_pixel) {
video_cfg->v_fc_config.timings.hactive *= 2;
video_cfg->hblank *= 2;
video_cfg->v_fc_config.timings.hfp *= 2;
video_cfg->v_fc_config.timings.hfront_porch *= 2;
video_cfg->v_fc_config.timings.hsync_len *= 2;
video_cfg->v_fc_config.timings.hbp *= 2;
}
@ -367,9 +367,9 @@ static void hdmi_core_video_config(struct hdmi_core_data *core,
/* set horizontal sync offset */
REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1,
cfg->v_fc_config.timings.hfp >> 8, 4, 0);
cfg->v_fc_config.timings.hfront_porch >> 8, 4, 0);
REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0,
cfg->v_fc_config.timings.hfp & 0xFF, 7, 0);
cfg->v_fc_config.timings.hfront_porch & 0xFF, 7, 0);
/* set vertical sync offset */
REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY,

6
drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
View file

@ -182,7 +182,7 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
hsync_len_offset = 0;
timing_h |= FLD_VAL(timings->hbp, 31, 20);
timing_h |= FLD_VAL(timings->hfp, 19, 8);
timing_h |= FLD_VAL(timings->hfront_porch, 19, 8);
timing_h |= FLD_VAL(timings->hsync_len - hsync_len_offset, 7, 0);
hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);
@ -202,7 +202,7 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
video_fmt->x_res = param->timings.hactive;
timings->hbp = param->timings.hbp;
timings->hfp = param->timings.hfp;
timings->hfront_porch = param->timings.hfront_porch;
timings->hsync_len = param->timings.hsync_len;
timings->vbp = param->timings.vbp;
timings->vfp = param->timings.vfp;
@ -222,7 +222,7 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
if (param->timings.double_pixel) {
video_fmt->x_res *= 2;
timings->hfp *= 2;
timings->hfront_porch *= 2;
timings->hsync_len *= 2;
timings->hbp *= 2;
}

2
drivers/gpu/drm/omapdrm/dss/omapdss.h
View file

@ -309,7 +309,7 @@ struct omap_video_timings {
/* Unit: pixel clocks */
u16 hsync_len; /* Horizontal synchronization pulse width */
/* Unit: pixel clocks */
u16 hfp; /* Horizontal front porch */
u16 hfront_porch; /* Horizontal front porch */
/* Unit: pixel clocks */
u16 hbp; /* Horizontal back porch */
/* Unit: line clocks */

2
drivers/gpu/drm/omapdrm/dss/rfbi.c
View file

@ -859,7 +859,7 @@ static void rfbi_config_lcd_manager(struct omap_dss_device *dssdev)
* omapdss_rfbi_set_size()
*/
rfbi.timings.hsync_len = 1;
rfbi.timings.hfp = 1;
rfbi.timings.hfront_porch = 1;
rfbi.timings.hbp = 1;
rfbi.timings.vsw = 1;
rfbi.timings.vfp = 0;

4
drivers/gpu/drm/omapdrm/dss/venc.c
View file

@ -267,7 +267,7 @@ const struct omap_video_timings omap_dss_pal_timings = {
.vactive = 574,
.pixelclock = 13500000,
.hsync_len = 64,
.hfp = 12,
.hfront_porch = 12,
.hbp = 68,
.vsw = 5,
.vfp = 5,
@ -288,7 +288,7 @@ const struct omap_video_timings omap_dss_ntsc_timings = {
.vactive = 482,
.pixelclock = 13500000,
.hsync_len = 64,
.hfp = 16,
.hfront_porch = 16,
.hbp = 58,
.vsw = 6,
.vfp = 6,

4
drivers/gpu/drm/omapdrm/omap_connector.c
View file

@ -48,7 +48,7 @@ void copy_timings_omap_to_drm(struct drm_display_mode *mode,
mode->clock = timings->pixelclock / 1000;
mode->hdisplay = timings->hactive;
mode->hsync_start = mode->hdisplay + timings->hfp;
mode->hsync_start = mode->hdisplay + timings->hfront_porch;
mode->hsync_end = mode->hsync_start + timings->hsync_len;
mode->htotal = mode->hsync_end + timings->hbp;
@ -82,7 +82,7 @@ void copy_timings_drm_to_omap(struct omap_video_timings *timings,
timings->pixelclock = mode->clock * 1000;
timings->hactive = mode->hdisplay;
timings->hfp = mode->hsync_start - mode->hdisplay;
timings->hfront_porch = mode->hsync_start - mode->hdisplay;
timings->hsync_len = mode->hsync_end - mode->hsync_start;
timings->hbp = mode->htotal - mode->hsync_end;