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drm/omap: omap_display_timings: rename hfp to hfront_porch
In preparation to move the stack to use the generic videmode struct for display timing information rename the hfp member to hfront_porch. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
parent
4dc2250d7d
commit
0a30e150f0
18 changed files with 47 additions and 45 deletions
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@ -34,7 +34,7 @@ static const struct omap_video_timings tvc_pal_timings = {
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.vactive = 574,
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.pixelclock = 13500000,
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.hsync_len = 64,
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.hfp = 12,
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.hfront_porch = 12,
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.hbp = 68,
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.vsw = 5,
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.vfp = 5,
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@ -25,7 +25,7 @@ static const struct omap_video_timings dvic_default_timings = {
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.pixelclock = 23500000,
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.hfp = 48,
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.hfront_porch = 48,
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.hsync_len = 32,
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.hbp = 80,
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@ -26,7 +26,7 @@ static const struct omap_video_timings hdmic_default_timings = {
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.vactive = 480,
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.pixelclock = 25175000,
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.hsync_len = 96,
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.hfp = 16,
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.hfront_porch = 16,
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.hbp = 48,
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.vsw = 2,
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.vfp = 11,
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@ -26,7 +26,7 @@ static struct omap_video_timings lb035q02_timings = {
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.pixelclock = 6500000,
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.hsync_len = 2,
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.hfp = 20,
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.hfront_porch = 20,
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.hbp = 68,
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.vsw = 2,
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@ -69,7 +69,7 @@ static const struct omap_video_timings nec_8048_panel_timings = {
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.hactive = LCD_XRES,
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.vactive = LCD_YRES,
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.pixelclock = LCD_PIXEL_CLOCK,
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.hfp = 6,
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.hfront_porch = 6,
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.hsync_len = 1,
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.hbp = 4,
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.vfp = 3,
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@ -42,7 +42,7 @@ static const struct omap_video_timings sharp_ls_timings = {
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.pixelclock = 19200000,
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.hsync_len = 2,
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.hfp = 1,
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.hfront_porch = 1,
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.hbp = 28,
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.vsw = 1,
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@ -96,7 +96,7 @@ static const struct omap_video_timings acx565akm_panel_timings = {
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.hactive = 800,
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.vactive = 480,
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.pixelclock = 24000000,
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.hfp = 28,
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.hfront_porch = 28,
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.hsync_len = 4,
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.hbp = 24,
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.vfp = 3,
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@ -46,7 +46,7 @@ static struct omap_video_timings td028ttec1_panel_timings = {
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.hactive = 480,
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.vactive = 640,
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.pixelclock = 22153000,
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.hfp = 24,
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.hfront_porch = 24,
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.hsync_len = 8,
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.hbp = 8,
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.vfp = 4,
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@ -79,7 +79,7 @@ static const struct omap_video_timings tpo_td043_timings = {
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.pixelclock = 36000000,
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.hsync_len = 1,
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.hfp = 68,
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.hfront_porch = 68,
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.hbp = 214,
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.vsw = 1,
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@ -2189,14 +2189,16 @@ static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
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u64 val, blank;
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int i;
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nonactive = t->hactive + t->hfp + t->hsync_len + t->hbp - out_width;
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nonactive = t->hactive + t->hfront_porch + t->hsync_len +
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t->hbp - out_width;
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i = 0;
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if (out_height < height)
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i++;
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if (out_width < width)
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i++;
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blank = div_u64((u64)(t->hbp + t->hsync_len + t->hfp) * lclk, pclk);
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blank = div_u64((u64)(t->hbp + t->hsync_len + t->hfront_porch) *
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lclk, pclk);
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DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
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if (blank <= limits[i])
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return -EINVAL;
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@ -3129,9 +3131,9 @@ bool dispc_mgr_timings_ok(enum omap_channel channel,
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if (timings->interlace)
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return false;
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if (!_dispc_lcd_timings_ok(timings->hsync_len, timings->hfp,
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timings->hbp, timings->vsw, timings->vfp,
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timings->vbp))
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if (!_dispc_lcd_timings_ok(timings->hsync_len,
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timings->hfront_porch, timings->hbp,
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timings->vsw, timings->vfp, timings->vbp))
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return false;
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}
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@ -3267,12 +3269,12 @@ void dispc_mgr_set_timings(enum omap_channel channel,
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}
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if (dss_mgr_is_lcd(channel)) {
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_dispc_mgr_set_lcd_timings(channel, t.hsync_len, t.hfp, t.hbp,
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t.vsw, t.vfp, t.vbp, t.vsync_level,
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_dispc_mgr_set_lcd_timings(channel, t.hsync_len, t.hfront_porch,
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t.hbp, t.vsw, t.vfp, t.vbp, t.vsync_level,
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t.hsync_level, t.data_pclk_edge, t.de_level,
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t.sync_pclk_edge);
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xtot = t.hactive + t.hfp + t.hsync_len + t.hbp;
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xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hbp;
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ytot = t.vactive + t.vfp + t.vsw + t.vbp;
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ht = timings->pixelclock / xtot;
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@ -3280,7 +3282,7 @@ void dispc_mgr_set_timings(enum omap_channel channel,
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DSSDBG("pck %u\n", timings->pixelclock);
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DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
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t.hsync_len, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
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t.hsync_len, t.hfront_porch, t.hbp, t.vsw, t.vfp, t.vbp);
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DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
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t.vsync_level, t.hsync_level, t.data_pclk_edge,
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t.de_level, t.sync_pclk_edge);
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@ -4223,7 +4225,7 @@ static const struct dispc_errata_i734_data {
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.timings = {
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.hactive = 8, .vactive = 1,
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.pixelclock = 16000000,
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.hsync_len = 8, .hfp = 4, .hbp = 4,
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.hsync_len = 8, .hfront_porch = 4, .hbp = 4,
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.vsw = 1, .vfp = 1, .vbp = 1,
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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@ -226,7 +226,7 @@ void videomode_to_omap_video_timings(const struct videomode *vm,
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ovt->pixelclock = vm->pixelclock;
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ovt->hactive = vm->hactive;
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ovt->hbp = vm->hback_porch;
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ovt->hfp = vm->hfront_porch;
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ovt->hfront_porch = vm->hfront_porch;
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ovt->hsync_len = vm->hsync_len;
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ovt->vactive = vm->vactive;
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ovt->vbp = vm->vback_porch;
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@ -259,7 +259,7 @@ void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
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vm->hactive = ovt->hactive;
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vm->hback_porch = ovt->hbp;
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vm->hfront_porch = ovt->hfp;
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vm->hfront_porch = ovt->hfront_porch;
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vm->hsync_len = ovt->hsync_len;
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vm->vactive = ovt->vactive;
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vm->vback_porch = ovt->vbp;
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@ -4331,7 +4331,7 @@ static void print_dsi_vm(const char *str,
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wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
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pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
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bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
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bl = t->hss + t->hsa + t->hse + t->hbp + t->hfront_porch;
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tot = bl + pps;
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#define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
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@ -4340,14 +4340,14 @@ static void print_dsi_vm(const char *str,
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"%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
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str,
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byteclk,
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t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
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t->hss, t->hsa, t->hse, t->hbp, pps, t->hfront_porch,
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bl, pps, tot,
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TO_DSI_T(t->hss),
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TO_DSI_T(t->hsa),
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TO_DSI_T(t->hse),
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TO_DSI_T(t->hbp),
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TO_DSI_T(pps),
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TO_DSI_T(t->hfp),
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TO_DSI_T(t->hfront_porch),
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TO_DSI_T(bl),
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TO_DSI_T(pps),
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@ -4362,7 +4362,7 @@ static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
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int hact, bl, tot;
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hact = t->hactive;
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bl = t->hsync_len + t->hbp + t->hfp;
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bl = t->hsync_len + t->hbp + t->hfront_porch;
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tot = hact + bl;
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#define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
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@ -4371,12 +4371,12 @@ static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
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"%u/%u/%u/%u = %u + %u = %u\n",
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str,
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pck,
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t->hsync_len, t->hbp, hact, t->hfp,
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t->hsync_len, t->hbp, hact, t->hfront_porch,
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bl, hact, tot,
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TO_DISPC_T(t->hsync_len),
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TO_DISPC_T(t->hbp),
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TO_DISPC_T(hact),
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TO_DISPC_T(t->hfp),
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TO_DISPC_T(t->hfront_porch),
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TO_DISPC_T(bl),
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TO_DISPC_T(hact),
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TO_DISPC_T(tot));
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@ -4396,12 +4396,12 @@ static void print_dsi_dispc_vm(const char *str,
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dsi_tput = (u64)byteclk * t->ndl * 8;
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pck = (u32)div64_u64(dsi_tput, t->bitspp);
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dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
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dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
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dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfront_porch;
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vm.pixelclock = pck;
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vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
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vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
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vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
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vm.hfront_porch = div64_u64((u64)t->hfront_porch * pck, byteclk);
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vm.hactive = t->hact;
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print_dispc_vm(str, &vm);
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@ -4423,7 +4423,7 @@ static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
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t->pixelclock = pck;
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t->hactive = ctx->config->timings->hactive;
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t->vactive = ctx->config->timings->vactive;
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t->hsync_len = t->hfp = t->hbp = t->vsw = 1;
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t->hsync_len = t->hfront_porch = t->hbp = t->vsw = 1;
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t->vfp = t->vbp = 0;
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return true;
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@ -4527,7 +4527,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
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xres = req_vm->hactive;
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panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsync_len;
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panel_hbl = req_vm->hfront_porch + req_vm->hbp + req_vm->hsync_len;
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panel_htot = xres + panel_hbl;
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dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
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@ -4685,7 +4685,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
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if (hfp < 1)
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return false;
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dispc_vm->hfp = hfp;
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dispc_vm->hfront_porch = hfp;
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dispc_vm->hsync_len = hsa;
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dispc_vm->hbp = hbp;
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@ -296,7 +296,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
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/* video core */
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video_cfg->data_enable_pol = 1; /* It is always 1*/
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video_cfg->hblank = cfg->timings.hfp +
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video_cfg->hblank = cfg->timings.hfront_porch +
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cfg->timings.hbp + cfg->timings.hsync_len;
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video_cfg->vblank_osc = 0;
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video_cfg->vblank = cfg->timings.vsw +
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@ -318,7 +318,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
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if (cfg->timings.double_pixel) {
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video_cfg->v_fc_config.timings.hactive *= 2;
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video_cfg->hblank *= 2;
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video_cfg->v_fc_config.timings.hfp *= 2;
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video_cfg->v_fc_config.timings.hfront_porch *= 2;
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video_cfg->v_fc_config.timings.hsync_len *= 2;
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video_cfg->v_fc_config.timings.hbp *= 2;
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}
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@ -367,9 +367,9 @@ static void hdmi_core_video_config(struct hdmi_core_data *core,
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/* set horizontal sync offset */
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REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1,
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cfg->v_fc_config.timings.hfp >> 8, 4, 0);
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cfg->v_fc_config.timings.hfront_porch >> 8, 4, 0);
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REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0,
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cfg->v_fc_config.timings.hfp & 0xFF, 7, 0);
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cfg->v_fc_config.timings.hfront_porch & 0xFF, 7, 0);
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/* set vertical sync offset */
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REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY,
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@ -182,7 +182,7 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
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hsync_len_offset = 0;
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timing_h |= FLD_VAL(timings->hbp, 31, 20);
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timing_h |= FLD_VAL(timings->hfp, 19, 8);
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timing_h |= FLD_VAL(timings->hfront_porch, 19, 8);
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timing_h |= FLD_VAL(timings->hsync_len - hsync_len_offset, 7, 0);
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hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);
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@ -202,7 +202,7 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
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video_fmt->x_res = param->timings.hactive;
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timings->hbp = param->timings.hbp;
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timings->hfp = param->timings.hfp;
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timings->hfront_porch = param->timings.hfront_porch;
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timings->hsync_len = param->timings.hsync_len;
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timings->vbp = param->timings.vbp;
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timings->vfp = param->timings.vfp;
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@ -222,7 +222,7 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
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if (param->timings.double_pixel) {
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video_fmt->x_res *= 2;
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timings->hfp *= 2;
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timings->hfront_porch *= 2;
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timings->hsync_len *= 2;
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timings->hbp *= 2;
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}
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@ -309,7 +309,7 @@ struct omap_video_timings {
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/* Unit: pixel clocks */
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u16 hsync_len; /* Horizontal synchronization pulse width */
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/* Unit: pixel clocks */
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u16 hfp; /* Horizontal front porch */
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u16 hfront_porch; /* Horizontal front porch */
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/* Unit: pixel clocks */
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u16 hbp; /* Horizontal back porch */
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/* Unit: line clocks */
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@ -859,7 +859,7 @@ static void rfbi_config_lcd_manager(struct omap_dss_device *dssdev)
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* omapdss_rfbi_set_size()
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*/
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rfbi.timings.hsync_len = 1;
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rfbi.timings.hfp = 1;
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rfbi.timings.hfront_porch = 1;
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rfbi.timings.hbp = 1;
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rfbi.timings.vsw = 1;
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rfbi.timings.vfp = 0;
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@ -267,7 +267,7 @@ const struct omap_video_timings omap_dss_pal_timings = {
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.vactive = 574,
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.pixelclock = 13500000,
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.hsync_len = 64,
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.hfp = 12,
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.hfront_porch = 12,
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.hbp = 68,
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.vsw = 5,
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.vfp = 5,
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@ -288,7 +288,7 @@ const struct omap_video_timings omap_dss_ntsc_timings = {
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.vactive = 482,
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.pixelclock = 13500000,
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.hsync_len = 64,
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.hfp = 16,
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.hfront_porch = 16,
|
||||
.hbp = 58,
|
||||
.vsw = 6,
|
||||
.vfp = 6,
|
||||
|
|
|
@ -48,7 +48,7 @@ void copy_timings_omap_to_drm(struct drm_display_mode *mode,
|
|||
mode->clock = timings->pixelclock / 1000;
|
||||
|
||||
mode->hdisplay = timings->hactive;
|
||||
mode->hsync_start = mode->hdisplay + timings->hfp;
|
||||
mode->hsync_start = mode->hdisplay + timings->hfront_porch;
|
||||
mode->hsync_end = mode->hsync_start + timings->hsync_len;
|
||||
mode->htotal = mode->hsync_end + timings->hbp;
|
||||
|
||||
|
@ -82,7 +82,7 @@ void copy_timings_drm_to_omap(struct omap_video_timings *timings,
|
|||
timings->pixelclock = mode->clock * 1000;
|
||||
|
||||
timings->hactive = mode->hdisplay;
|
||||
timings->hfp = mode->hsync_start - mode->hdisplay;
|
||||
timings->hfront_porch = mode->hsync_start - mode->hdisplay;
|
||||
timings->hsync_len = mode->hsync_end - mode->hsync_start;
|
||||
timings->hbp = mode->htotal - mode->hsync_end;
|
||||
|
||||
|
|
Loading…
Reference in a new issue