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drm/omap: omap_display_timings: rename hsw to hsync_len
In preparation to move the stack to use the generic videmode struct for display timing information rename the hsw member to hsync_len. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
parent
fb7f3c4399
commit
4dc2250d7d
18 changed files with 53 additions and 52 deletions
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@ -33,7 +33,7 @@ static const struct omap_video_timings tvc_pal_timings = {
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.hactive = 720,
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.vactive = 574,
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.pixelclock = 13500000,
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.hsw = 64,
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.hsync_len = 64,
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.hfp = 12,
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.hbp = 68,
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.vsw = 5,
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@ -26,7 +26,7 @@ static const struct omap_video_timings dvic_default_timings = {
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.pixelclock = 23500000,
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.hfp = 48,
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.hsw = 32,
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.hsync_len = 32,
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.hbp = 80,
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.vfp = 3,
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@ -25,7 +25,7 @@ static const struct omap_video_timings hdmic_default_timings = {
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.hactive = 640,
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.vactive = 480,
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.pixelclock = 25175000,
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.hsw = 96,
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.hsync_len = 96,
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.hfp = 16,
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.hbp = 48,
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.vsw = 2,
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@ -25,7 +25,7 @@ static struct omap_video_timings lb035q02_timings = {
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.pixelclock = 6500000,
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.hsw = 2,
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.hsync_len = 2,
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.hfp = 20,
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.hbp = 68,
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@ -70,7 +70,7 @@ static const struct omap_video_timings nec_8048_panel_timings = {
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.vactive = LCD_YRES,
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.pixelclock = LCD_PIXEL_CLOCK,
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.hfp = 6,
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.hsw = 1,
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.hsync_len = 1,
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.hbp = 4,
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.vfp = 3,
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.vsw = 1,
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@ -41,7 +41,7 @@ static const struct omap_video_timings sharp_ls_timings = {
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.pixelclock = 19200000,
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.hsw = 2,
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.hsync_len = 2,
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.hfp = 1,
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.hbp = 28,
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@ -97,7 +97,7 @@ static const struct omap_video_timings acx565akm_panel_timings = {
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.vactive = 480,
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.pixelclock = 24000000,
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.hfp = 28,
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.hsw = 4,
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.hsync_len = 4,
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.hbp = 24,
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.vfp = 3,
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.vsw = 3,
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@ -47,7 +47,7 @@ static struct omap_video_timings td028ttec1_panel_timings = {
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.vactive = 640,
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.pixelclock = 22153000,
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.hfp = 24,
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.hsw = 8,
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.hsync_len = 8,
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.hbp = 8,
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.vfp = 4,
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.vsw = 2,
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@ -78,7 +78,7 @@ static const struct omap_video_timings tpo_td043_timings = {
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.pixelclock = 36000000,
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.hsw = 1,
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.hsync_len = 1,
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.hfp = 68,
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.hbp = 214,
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@ -2189,14 +2189,14 @@ static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
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u64 val, blank;
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int i;
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nonactive = t->hactive + t->hfp + t->hsw + t->hbp - out_width;
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nonactive = t->hactive + t->hfp + t->hsync_len + t->hbp - out_width;
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i = 0;
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if (out_height < height)
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i++;
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if (out_width < width)
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i++;
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blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
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blank = div_u64((u64)(t->hbp + t->hsync_len + t->hfp) * lclk, pclk);
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DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
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if (blank <= limits[i])
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return -EINVAL;
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@ -3093,10 +3093,10 @@ static bool _dispc_mgr_size_ok(u16 width, u16 height)
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height <= dispc.feat->mgr_height_max;
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}
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static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
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static bool _dispc_lcd_timings_ok(int hsync_len, int hfp, int hbp,
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int vsw, int vfp, int vbp)
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{
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if (hsw < 1 || hsw > dispc.feat->sw_max ||
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if (hsync_len < 1 || hsync_len > dispc.feat->sw_max ||
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hfp < 1 || hfp > dispc.feat->hp_max ||
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hbp < 1 || hbp > dispc.feat->hp_max ||
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vsw < 1 || vsw > dispc.feat->sw_max ||
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@ -3129,7 +3129,7 @@ bool dispc_mgr_timings_ok(enum omap_channel channel,
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if (timings->interlace)
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return false;
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if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
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if (!_dispc_lcd_timings_ok(timings->hsync_len, timings->hfp,
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timings->hbp, timings->vsw, timings->vfp,
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timings->vbp))
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return false;
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@ -3138,7 +3138,7 @@ bool dispc_mgr_timings_ok(enum omap_channel channel,
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return true;
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}
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static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
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static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsync_len,
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int hfp, int hbp, int vsw, int vfp, int vbp,
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enum omap_dss_signal_level vsync_level,
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enum omap_dss_signal_level hsync_level,
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@ -3150,7 +3150,7 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
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u32 timing_h, timing_v, l;
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bool onoff, rf, ipc, vs, hs, de;
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timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
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timing_h = FLD_VAL(hsync_len-1, dispc.feat->sw_start, 0) |
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FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
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FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
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timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
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@ -3267,19 +3267,20 @@ void dispc_mgr_set_timings(enum omap_channel channel,
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}
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if (dss_mgr_is_lcd(channel)) {
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_dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
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t.vfp, t.vbp, t.vsync_level, t.hsync_level,
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t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
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_dispc_mgr_set_lcd_timings(channel, t.hsync_len, t.hfp, t.hbp,
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t.vsw, t.vfp, t.vbp, t.vsync_level,
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t.hsync_level, t.data_pclk_edge, t.de_level,
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t.sync_pclk_edge);
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xtot = t.hactive + t.hfp + t.hsw + t.hbp;
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xtot = t.hactive + t.hfp + t.hsync_len + t.hbp;
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ytot = t.vactive + t.vfp + t.vsw + t.vbp;
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ht = timings->pixelclock / xtot;
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vt = timings->pixelclock / xtot / ytot;
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DSSDBG("pck %u\n", timings->pixelclock);
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DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
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t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
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DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
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t.hsync_len, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
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DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
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t.vsync_level, t.hsync_level, t.data_pclk_edge,
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t.de_level, t.sync_pclk_edge);
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@ -4222,7 +4223,7 @@ static const struct dispc_errata_i734_data {
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.timings = {
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.hactive = 8, .vactive = 1,
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.pixelclock = 16000000,
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.hsw = 8, .hfp = 4, .hbp = 4,
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.hsync_len = 8, .hfp = 4, .hbp = 4,
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.vsw = 1, .vfp = 1, .vbp = 1,
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.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
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@ -227,7 +227,7 @@ void videomode_to_omap_video_timings(const struct videomode *vm,
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ovt->hactive = vm->hactive;
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ovt->hbp = vm->hback_porch;
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ovt->hfp = vm->hfront_porch;
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ovt->hsw = vm->hsync_len;
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ovt->hsync_len = vm->hsync_len;
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ovt->vactive = vm->vactive;
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ovt->vbp = vm->vback_porch;
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ovt->vfp = vm->vfront_porch;
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@ -260,7 +260,7 @@ void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
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vm->hactive = ovt->hactive;
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vm->hback_porch = ovt->hbp;
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vm->hfront_porch = ovt->hfp;
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vm->hsync_len = ovt->hsw;
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vm->hsync_len = ovt->hsync_len;
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vm->vactive = ovt->vactive;
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vm->vback_porch = ovt->vbp;
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vm->vfront_porch = ovt->vfp;
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@ -4362,7 +4362,7 @@ static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
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int hact, bl, tot;
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hact = t->hactive;
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bl = t->hsw + t->hbp + t->hfp;
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bl = t->hsync_len + t->hbp + t->hfp;
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tot = hact + bl;
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#define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
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@ -4371,9 +4371,9 @@ static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
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"%u/%u/%u/%u = %u + %u = %u\n",
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str,
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pck,
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t->hsw, t->hbp, hact, t->hfp,
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t->hsync_len, t->hbp, hact, t->hfp,
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bl, hact, tot,
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TO_DISPC_T(t->hsw),
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TO_DISPC_T(t->hsync_len),
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TO_DISPC_T(t->hbp),
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TO_DISPC_T(hact),
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TO_DISPC_T(t->hfp),
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@ -4399,7 +4399,7 @@ static void print_dsi_dispc_vm(const char *str,
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dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
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vm.pixelclock = pck;
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vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
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vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
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vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
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vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
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vm.hactive = t->hact;
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@ -4423,7 +4423,7 @@ static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
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t->pixelclock = pck;
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t->hactive = ctx->config->timings->hactive;
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t->vactive = ctx->config->timings->vactive;
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t->hsw = t->hfp = t->hbp = t->vsw = 1;
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t->hsync_len = t->hfp = t->hbp = t->vsw = 1;
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t->vfp = t->vbp = 0;
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return true;
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@ -4527,7 +4527,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
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xres = req_vm->hactive;
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panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw;
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panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsync_len;
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panel_htot = xres + panel_hbl;
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dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
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@ -4557,7 +4557,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
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hss = DIV_ROUND_UP(4, ndl);
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if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
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if (ndl == 3 && req_vm->hsw == 0)
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if (ndl == 3 && req_vm->hsync_len == 0)
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hse = 1;
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else
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hse = DIV_ROUND_UP(4, ndl);
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@ -4596,10 +4596,10 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
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if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
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hsa = 0;
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} else if (ndl == 3 && req_vm->hsw == 0) {
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} else if (ndl == 3 && req_vm->hsync_len == 0) {
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hsa = 0;
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} else {
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hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom);
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hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom);
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hsa = max(hsa - hse, 1);
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}
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@ -4655,7 +4655,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
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dispc_vm->pixelclock = dispc_pck;
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if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
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hsa = div64_u64((u64)req_vm->hsw * dispc_pck,
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hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck,
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req_pck_nom);
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hsa = max(hsa, 1);
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} else {
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@ -4686,7 +4686,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
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return false;
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dispc_vm->hfp = hfp;
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dispc_vm->hsw = hsa;
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dispc_vm->hsync_len = hsa;
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dispc_vm->hbp = hbp;
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return true;
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@ -297,7 +297,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
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/* video core */
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video_cfg->data_enable_pol = 1; /* It is always 1*/
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video_cfg->hblank = cfg->timings.hfp +
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cfg->timings.hbp + cfg->timings.hsw;
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cfg->timings.hbp + cfg->timings.hsync_len;
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video_cfg->vblank_osc = 0;
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video_cfg->vblank = cfg->timings.vsw +
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cfg->timings.vfp + cfg->timings.vbp;
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@ -319,7 +319,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
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video_cfg->v_fc_config.timings.hactive *= 2;
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video_cfg->hblank *= 2;
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video_cfg->v_fc_config.timings.hfp *= 2;
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video_cfg->v_fc_config.timings.hsw *= 2;
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video_cfg->v_fc_config.timings.hsync_len *= 2;
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video_cfg->v_fc_config.timings.hbp *= 2;
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}
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}
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@ -377,9 +377,9 @@ static void hdmi_core_video_config(struct hdmi_core_data *core,
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/* set horizontal sync pulse width */
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REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1,
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(cfg->v_fc_config.timings.hsw >> 8), 1, 0);
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(cfg->v_fc_config.timings.hsync_len >> 8), 1, 0);
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REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0,
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cfg->v_fc_config.timings.hsw & 0xFF, 7, 0);
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cfg->v_fc_config.timings.hsync_len & 0xFF, 7, 0);
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/* set vertical sync pulse width */
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REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH,
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@ -166,24 +166,24 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
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{
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u32 timing_h = 0;
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u32 timing_v = 0;
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unsigned hsw_offset = 1;
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unsigned hsync_len_offset = 1;
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DSSDBG("Enter hdmi_wp_video_config_timing\n");
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/*
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* On OMAP4 and OMAP5 ES1 the HSW field is programmed as is. On OMAP5
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* ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsw-1.
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* ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsync_len-1.
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* However, we don't support OMAP5 ES1 at all, so we can just check for
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* OMAP4 here.
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*/
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if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 ||
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omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 ||
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omapdss_get_version() == OMAPDSS_VER_OMAP4)
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hsw_offset = 0;
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hsync_len_offset = 0;
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timing_h |= FLD_VAL(timings->hbp, 31, 20);
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timing_h |= FLD_VAL(timings->hfp, 19, 8);
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timing_h |= FLD_VAL(timings->hsw - hsw_offset, 7, 0);
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timing_h |= FLD_VAL(timings->hsync_len - hsync_len_offset, 7, 0);
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hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);
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timing_v |= FLD_VAL(timings->vbp, 31, 20);
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@ -203,7 +203,7 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
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timings->hbp = param->timings.hbp;
|
||||
timings->hfp = param->timings.hfp;
|
||||
timings->hsw = param->timings.hsw;
|
||||
timings->hsync_len = param->timings.hsync_len;
|
||||
timings->vbp = param->timings.vbp;
|
||||
timings->vfp = param->timings.vfp;
|
||||
timings->vsw = param->timings.vsw;
|
||||
|
@ -223,7 +223,7 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
|
|||
if (param->timings.double_pixel) {
|
||||
video_fmt->x_res *= 2;
|
||||
timings->hfp *= 2;
|
||||
timings->hsw *= 2;
|
||||
timings->hsync_len *= 2;
|
||||
timings->hbp *= 2;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -307,7 +307,7 @@ struct omap_video_timings {
|
|||
/* Unit: Hz */
|
||||
u32 pixelclock;
|
||||
/* Unit: pixel clocks */
|
||||
u16 hsw; /* Horizontal synchronization pulse width */
|
||||
u16 hsync_len; /* Horizontal synchronization pulse width */
|
||||
/* Unit: pixel clocks */
|
||||
u16 hfp; /* Horizontal front porch */
|
||||
/* Unit: pixel clocks */
|
||||
|
|
|
@ -858,7 +858,7 @@ static void rfbi_config_lcd_manager(struct omap_dss_device *dssdev)
|
|||
* are expected to be already configured by the panel driver via
|
||||
* omapdss_rfbi_set_size()
|
||||
*/
|
||||
rfbi.timings.hsw = 1;
|
||||
rfbi.timings.hsync_len = 1;
|
||||
rfbi.timings.hfp = 1;
|
||||
rfbi.timings.hbp = 1;
|
||||
rfbi.timings.vsw = 1;
|
||||
|
|
|
@ -266,7 +266,7 @@ const struct omap_video_timings omap_dss_pal_timings = {
|
|||
.hactive = 720,
|
||||
.vactive = 574,
|
||||
.pixelclock = 13500000,
|
||||
.hsw = 64,
|
||||
.hsync_len = 64,
|
||||
.hfp = 12,
|
||||
.hbp = 68,
|
||||
.vsw = 5,
|
||||
|
@ -287,7 +287,7 @@ const struct omap_video_timings omap_dss_ntsc_timings = {
|
|||
.hactive = 720,
|
||||
.vactive = 482,
|
||||
.pixelclock = 13500000,
|
||||
.hsw = 64,
|
||||
.hsync_len = 64,
|
||||
.hfp = 16,
|
||||
.hbp = 58,
|
||||
.vsw = 6,
|
||||
|
|
|
@ -49,7 +49,7 @@ void copy_timings_omap_to_drm(struct drm_display_mode *mode,
|
|||
|
||||
mode->hdisplay = timings->hactive;
|
||||
mode->hsync_start = mode->hdisplay + timings->hfp;
|
||||
mode->hsync_end = mode->hsync_start + timings->hsw;
|
||||
mode->hsync_end = mode->hsync_start + timings->hsync_len;
|
||||
mode->htotal = mode->hsync_end + timings->hbp;
|
||||
|
||||
mode->vdisplay = timings->vactive;
|
||||
|
@ -83,7 +83,7 @@ void copy_timings_drm_to_omap(struct omap_video_timings *timings,
|
|||
|
||||
timings->hactive = mode->hdisplay;
|
||||
timings->hfp = mode->hsync_start - mode->hdisplay;
|
||||
timings->hsw = mode->hsync_end - mode->hsync_start;
|
||||
timings->hsync_len = mode->hsync_end - mode->hsync_start;
|
||||
timings->hbp = mode->htotal - mode->hsync_end;
|
||||
|
||||
timings->vactive = mode->vdisplay;
|
||||
|
|
Loading…
Reference in a new issue