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Merge branch 'remotes/lorenzo/pci/qcom'
- Save pointer to device match data instead of copying it (Dmitry Baryshkov) - Add ddrss_sf_tbu flag to device match data instead of checking OF compatible string (Dmitry Baryshkov) - Add SM8450 SoC PCIe DT bindings (Dmitry Baryshkov) - Add SM8450 PCIe support (Dmitry Baryshkov) * remotes/lorenzo/pci/qcom: PCI: qcom: Add SM8450 PCIe support PCI: qcom: Add ddrss_sf_tbu flag PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg dt-bindings: pci: qcom: Document PCIe bindings for SM8450
This commit is contained in:
Bjorn Helgaas
commit
0c634fcb98
2 changed files with 83 additions and 32 deletions
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@ -15,6 +15,8 @@
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- "qcom,pcie-sc8180x" for sc8180x
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- "qcom,pcie-sdm845" for sdm845
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- "qcom,pcie-sm8250" for sm8250
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- "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450
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- "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450
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- "qcom,pcie-ipq6018" for ipq6018
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- reg:
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@ -169,6 +171,24 @@
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- "ddrss_sf_tbu" PCIe SF TBU clock
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- "pipe" PIPE clock
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- clock-names:
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Usage: required for sm8450-pcie0 and sm8450-pcie1
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "aux" Auxiliary clock
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- "cfg" Configuration clock
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- "bus_master" Master AXI clock
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- "bus_slave" Slave AXI clock
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- "slave_q2a" Slave Q2A clock
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- "tbu" PCIe TBU clock
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- "ddrss_sf_tbu" PCIe SF TBU clock
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- "pipe" PIPE clock
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- "pipe_mux" PIPE MUX
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- "phy_pipe" PIPE output clock
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- "ref" REFERENCE clock
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- "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0
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- "aggre1" Aggre NoC PCIe1 AXI clock
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- resets:
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Usage: required
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Value type: <prop-encoded-array>
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@ -246,7 +266,7 @@
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- "ahb" AHB reset
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- reset-names:
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Usage: required for sc8180x, sdm845 and sm8250
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Usage: required for sc8180x, sdm845, sm8250 and sm8450
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "pci" PCIe core reset
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@ -161,7 +161,7 @@ struct qcom_pcie_resources_2_3_3 {
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/* 6 clocks typically, 7 for sm8250 */
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struct qcom_pcie_resources_2_7_0 {
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struct clk_bulk_data clks[7];
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struct clk_bulk_data clks[9];
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int num_clks;
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struct regulator_bulk_data supplies[2];
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struct reset_control *pci_reset;
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@ -195,6 +195,10 @@ struct qcom_pcie_ops {
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struct qcom_pcie_cfg {
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const struct qcom_pcie_ops *ops;
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unsigned int pipe_clk_need_muxing:1;
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unsigned int has_tbu_clk:1;
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unsigned int has_ddrss_sf_tbu_clk:1;
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unsigned int has_aggre0_clk:1;
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unsigned int has_aggre1_clk:1;
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};
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struct qcom_pcie {
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@ -204,8 +208,7 @@ struct qcom_pcie {
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union qcom_pcie_resources res;
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struct phy *phy;
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struct gpio_desc *reset;
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const struct qcom_pcie_ops *ops;
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unsigned int pipe_clk_need_muxing:1;
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const struct qcom_pcie_cfg *cfg;
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};
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#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
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@ -229,8 +232,8 @@ static int qcom_pcie_start_link(struct dw_pcie *pci)
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struct qcom_pcie *pcie = to_qcom_pcie(pci);
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/* Enable Link Training state machine */
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if (pcie->ops->ltssm_enable)
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pcie->ops->ltssm_enable(pcie);
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if (pcie->cfg->ops->ltssm_enable)
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pcie->cfg->ops->ltssm_enable(pcie);
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return 0;
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}
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@ -1146,6 +1149,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
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struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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unsigned int idx;
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int ret;
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res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
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@ -1159,24 +1163,28 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
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if (ret)
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return ret;
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res->clks[0].id = "aux";
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res->clks[1].id = "cfg";
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res->clks[2].id = "bus_master";
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res->clks[3].id = "bus_slave";
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res->clks[4].id = "slave_q2a";
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res->clks[5].id = "tbu";
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if (of_device_is_compatible(dev->of_node, "qcom,pcie-sm8250")) {
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res->clks[6].id = "ddrss_sf_tbu";
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res->num_clks = 7;
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} else {
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res->num_clks = 6;
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}
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idx = 0;
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res->clks[idx++].id = "aux";
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res->clks[idx++].id = "cfg";
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res->clks[idx++].id = "bus_master";
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res->clks[idx++].id = "bus_slave";
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res->clks[idx++].id = "slave_q2a";
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if (pcie->cfg->has_tbu_clk)
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res->clks[idx++].id = "tbu";
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if (pcie->cfg->has_ddrss_sf_tbu_clk)
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res->clks[idx++].id = "ddrss_sf_tbu";
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if (pcie->cfg->has_aggre0_clk)
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res->clks[idx++].id = "aggre0";
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if (pcie->cfg->has_aggre1_clk)
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res->clks[idx++].id = "aggre1";
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res->num_clks = idx;
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ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
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if (ret < 0)
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return ret;
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if (pcie->pipe_clk_need_muxing) {
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if (pcie->cfg->pipe_clk_need_muxing) {
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res->pipe_clk_src = devm_clk_get(dev, "pipe_mux");
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if (IS_ERR(res->pipe_clk_src))
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return PTR_ERR(res->pipe_clk_src);
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@ -1209,7 +1217,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
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}
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/* Set TCXO as clock source for pcie_pipe_clk_src */
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if (pcie->pipe_clk_need_muxing)
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if (pcie->cfg->pipe_clk_need_muxing)
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clk_set_parent(res->pipe_clk_src, res->ref_clk_src);
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ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
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@ -1236,6 +1244,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
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goto err_disable_clocks;
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}
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/* Wait for reset to complete, required on SM8450 */
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usleep_range(1000, 1500);
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/* configure PCIe to RC mode */
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writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
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@ -1284,7 +1295,7 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
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struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
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/* Set pipe clock as clock source for pcie_pipe_clk_src */
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if (pcie->pipe_clk_need_muxing)
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if (pcie->cfg->pipe_clk_need_muxing)
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clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk);
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return clk_prepare_enable(res->pipe_clk);
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@ -1384,7 +1395,7 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
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qcom_ep_reset_assert(pcie);
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ret = pcie->ops->init(pcie);
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ret = pcie->cfg->ops->init(pcie);
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if (ret)
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return ret;
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@ -1392,16 +1403,16 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
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if (ret)
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goto err_deinit;
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if (pcie->ops->post_init) {
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ret = pcie->ops->post_init(pcie);
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if (pcie->cfg->ops->post_init) {
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ret = pcie->cfg->ops->post_init(pcie);
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if (ret)
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goto err_disable_phy;
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}
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qcom_ep_reset_deassert(pcie);
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if (pcie->ops->config_sid) {
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ret = pcie->ops->config_sid(pcie);
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if (pcie->cfg->ops->config_sid) {
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ret = pcie->cfg->ops->config_sid(pcie);
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if (ret)
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goto err;
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}
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@ -1410,12 +1421,12 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
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err:
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qcom_ep_reset_assert(pcie);
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if (pcie->ops->post_deinit)
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pcie->ops->post_deinit(pcie);
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if (pcie->cfg->ops->post_deinit)
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pcie->cfg->ops->post_deinit(pcie);
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err_disable_phy:
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phy_power_off(pcie->phy);
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err_deinit:
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pcie->ops->deinit(pcie);
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pcie->cfg->ops->deinit(pcie);
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return ret;
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}
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@ -1509,14 +1520,33 @@ static const struct qcom_pcie_cfg ipq4019_cfg = {
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static const struct qcom_pcie_cfg sdm845_cfg = {
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.ops = &ops_2_7_0,
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.has_tbu_clk = true,
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};
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static const struct qcom_pcie_cfg sm8250_cfg = {
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.ops = &ops_1_9_0,
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.has_tbu_clk = true,
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.has_ddrss_sf_tbu_clk = true,
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};
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static const struct qcom_pcie_cfg sm8450_pcie0_cfg = {
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.ops = &ops_1_9_0,
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.has_ddrss_sf_tbu_clk = true,
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.pipe_clk_need_muxing = true,
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.has_aggre0_clk = true,
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.has_aggre1_clk = true,
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};
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static const struct qcom_pcie_cfg sm8450_pcie1_cfg = {
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.ops = &ops_1_9_0,
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.has_ddrss_sf_tbu_clk = true,
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.pipe_clk_need_muxing = true,
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.has_aggre1_clk = true,
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};
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static const struct qcom_pcie_cfg sc7280_cfg = {
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.ops = &ops_1_9_0,
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.has_tbu_clk = true,
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.pipe_clk_need_muxing = true,
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};
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@ -1559,8 +1589,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
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pcie->pci = pci;
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pcie->ops = pcie_cfg->ops;
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pcie->pipe_clk_need_muxing = pcie_cfg->pipe_clk_need_muxing;
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pcie->cfg = pcie_cfg;
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pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
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if (IS_ERR(pcie->reset)) {
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@ -1586,7 +1615,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
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goto err_pm_runtime_put;
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}
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ret = pcie->ops->get_resources(pcie);
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ret = pcie->cfg->ops->get_resources(pcie);
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if (ret)
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goto err_pm_runtime_put;
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@ -1628,6 +1657,8 @@ static const struct of_device_id qcom_pcie_match[] = {
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{ .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
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{ .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
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{ .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg },
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{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg },
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{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg },
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{ .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
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{ }
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};
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