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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-21 08:19:28 +00:00
- Fix the memory organization structure of a Macronix SPI-NAND chip.
- Fix a build dependency wrongly described. - Fix the sunxi NAND driver for A23/A33 SoCs by 1/ reverting the faulty commit introducing broken DMA support and 2/ applying another commit bringing working DMA support. -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEE9HuaYnbmDhq/XIDIJWrqGEe9VoQFAl0fv4EACgkQJWrqGEe9 VoQpzwgAoh+L1QH9KKBm/g7/4k8D+O1TmSEE50e5xmg8y0cQsqOwwa/Z+Jaeo4vm CsCRTsbOe7aivUX1EBbnL2Ye4nksZJGiujnIE12dhRy94oGE6NERsfMs8a2/Ksic F4is5CwR1lWAVq3mvj5WhofW+Fxh/0+NK38g/iCY87H0e2mIuateuaGhnfpfrD8y uJJHjpQHRkWaehXoL1GnytBVRLiX/vKhZyICiev1qQb6Kk5JTw/xuoFqkXT1wNOj pr/IKpS76+j+WfN7gwPvAMdkr7/LrWxhz0XdH0+/r77JY5udo6ht+KxMoLgeGYoc 8VDa9Y2q+7NQcRAJ1StMgsMJG4vcCA== =U0/M -----END PGP SIGNATURE----- Merge tag 'mtd/fixes-for-5.2-final' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull mtf fixes from Miquel Raynal: - Fix the memory organization structure of a Macronix SPI-NAND chip. - Fix a build dependency wrongly described. - Fix the sunxi NAND driver for A23/A33 SoCs by (a) reverting the faulty commit introducing broken DMA support and (b) applying another commit bringing working DMA support. * tag 'mtd/fixes-for-5.2-final' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: mtd: rawnand: sunxi: Add A23/A33 DMA support with extra MBUS configuration Revert "mtd: rawnand: sunxi: Add A23/A33 DMA support" mtd: rawnand: ingenic: Fix ingenic_ecc dependency mtd: spinand: Fix max_bad_eraseblocks_per_lun info in memorg
This commit is contained in:
commit
0e63665a1b
7 changed files with 22 additions and 39 deletions
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@ -16,7 +16,7 @@ config MTD_NAND_JZ4780
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if MTD_NAND_JZ4780
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config MTD_NAND_INGENIC_ECC
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tristate
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bool
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config MTD_NAND_JZ4740_ECC
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tristate "Hardware BCH support for JZ4740 SoC"
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@ -2,7 +2,9 @@
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obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
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obj-$(CONFIG_MTD_NAND_JZ4780) += ingenic_nand.o
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obj-$(CONFIG_MTD_NAND_INGENIC_ECC) += ingenic_ecc.o
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ingenic_nand-y += ingenic_nand_drv.o
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ingenic_nand-$(CONFIG_MTD_NAND_INGENIC_ECC) += ingenic_ecc.o
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obj-$(CONFIG_MTD_NAND_JZ4740_ECC) += jz4740_ecc.o
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obj-$(CONFIG_MTD_NAND_JZ4725B_BCH) += jz4725b_bch.o
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obj-$(CONFIG_MTD_NAND_JZ4780_BCH) += jz4780_bch.o
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@ -30,7 +30,6 @@ int ingenic_ecc_calculate(struct ingenic_ecc *ecc,
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{
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return ecc->ops->calculate(ecc, params, buf, ecc_code);
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}
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EXPORT_SYMBOL(ingenic_ecc_calculate);
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/**
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* ingenic_ecc_correct() - detect and correct bit errors
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@ -51,7 +50,6 @@ int ingenic_ecc_correct(struct ingenic_ecc *ecc,
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{
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return ecc->ops->correct(ecc, params, buf, ecc_code);
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}
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EXPORT_SYMBOL(ingenic_ecc_correct);
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/**
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* ingenic_ecc_get() - get the ECC controller device
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@ -111,7 +109,6 @@ struct ingenic_ecc *of_ingenic_ecc_get(struct device_node *of_node)
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}
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return ecc;
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}
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EXPORT_SYMBOL(of_ingenic_ecc_get);
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/**
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* ingenic_ecc_release() - release the ECC controller device
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@ -122,7 +119,6 @@ void ingenic_ecc_release(struct ingenic_ecc *ecc)
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clk_disable_unprepare(ecc->clk);
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put_device(ecc->dev);
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}
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EXPORT_SYMBOL(ingenic_ecc_release);
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int ingenic_ecc_probe(struct platform_device *pdev)
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{
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@ -159,8 +155,3 @@ int ingenic_ecc_probe(struct platform_device *pdev)
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return 0;
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}
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EXPORT_SYMBOL(ingenic_ecc_probe);
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MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
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MODULE_AUTHOR("Harvey Hunt <harveyhuntnexus@gmail.com>");
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MODULE_DESCRIPTION("Ingenic ECC common driver");
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MODULE_LICENSE("GPL v2");
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@ -51,6 +51,7 @@
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#define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4))
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#define NFC_REG_SPARE_AREA 0x00A0
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#define NFC_REG_PAT_ID 0x00A4
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#define NFC_REG_MDMA_CNT 0x00C4
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#define NFC_RAM0_BASE 0x0400
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#define NFC_RAM1_BASE 0x0800
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@ -69,6 +70,7 @@
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#define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
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#define NFC_SAM BIT(12)
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#define NFC_RAM_METHOD BIT(14)
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#define NFC_DMA_TYPE_NORMAL BIT(15)
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#define NFC_DEBUG_CTL BIT(31)
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/* define bit use in NFC_ST */
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@ -205,14 +207,13 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
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* NAND Controller capabilities structure: stores NAND controller capabilities
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* for distinction between compatible strings.
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*
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* @sram_through_ahb: On A23, we choose to access the internal RAM through AHB
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* instead of MBUS (less configuration). A10, A10s, A13 and
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* A20 use the MBUS but no extra configuration is needed.
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* @extra_mbus_conf: Contrary to A10, A10s and A13, accessing internal RAM
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* through MBUS on A23/A33 needs extra configuration.
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* @reg_io_data: I/O data register
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* @dma_maxburst: DMA maxburst
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*/
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struct sunxi_nfc_caps {
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bool sram_through_ahb;
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bool extra_mbus_conf;
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unsigned int reg_io_data;
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unsigned int dma_maxburst;
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};
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@ -368,28 +369,12 @@ static int sunxi_nfc_dma_op_prepare(struct sunxi_nfc *nfc, const void *buf,
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goto err_unmap_buf;
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}
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/*
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* On A23, we suppose the "internal RAM" (p.12 of the NFC user manual)
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* refers to the NAND controller's internal SRAM. This memory is mapped
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* and so is accessible from the AHB. It seems that it can also be
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* accessed by the MBUS. MBUS accesses are mandatory when using the
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* internal DMA instead of the external DMA engine.
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*
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* During DMA I/O operation, either we access this memory from the AHB
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* by clearing the NFC_RAM_METHOD bit, or we set the bit and use the
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* MBUS. In this case, we should also configure the MBUS DMA length
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* NFC_REG_MDMA_CNT(0xC4) to be chunksize * nchunks. NAND I/O over MBUS
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* are also limited to 32kiB pages.
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*/
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if (nfc->caps->sram_through_ahb)
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writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
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nfc->regs + NFC_REG_CTL);
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else
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writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD,
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nfc->regs + NFC_REG_CTL);
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writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD,
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nfc->regs + NFC_REG_CTL);
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writel(nchunks, nfc->regs + NFC_REG_SECTOR_NUM);
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writel(chunksize, nfc->regs + NFC_REG_CNT);
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if (nfc->caps->extra_mbus_conf)
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writel(chunksize * nchunks, nfc->regs + NFC_REG_MDMA_CNT);
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dmat = dmaengine_submit(dmad);
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@ -2151,6 +2136,11 @@ static int sunxi_nfc_probe(struct platform_device *pdev)
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dmac_cfg.src_maxburst = nfc->caps->dma_maxburst;
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dmac_cfg.dst_maxburst = nfc->caps->dma_maxburst;
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dmaengine_slave_config(nfc->dmac, &dmac_cfg);
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if (nfc->caps->extra_mbus_conf)
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writel(readl(nfc->regs + NFC_REG_CTL) |
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NFC_DMA_TYPE_NORMAL, nfc->regs + NFC_REG_CTL);
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} else {
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dev_warn(dev, "failed to request rxtx DMA channel\n");
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}
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@ -2200,7 +2190,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = {
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};
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static const struct sunxi_nfc_caps sunxi_nfc_a23_caps = {
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.sram_through_ahb = true,
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.extra_mbus_conf = true,
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.reg_io_data = NFC_REG_A23_IO_DATA,
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.dma_maxburst = 8,
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};
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@ -180,7 +180,7 @@ static const struct spinand_info gigadevice_spinand_table[] = {
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SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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gd5fxgq4xa_ecc_get_status)),
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SPINAND_INFO("GD5F4GQ4xA", 0xF4,
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NAND_MEMORG(1, 2048, 64, 64, 4096, 40, 1, 1, 1),
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NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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@ -100,7 +100,7 @@ static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand,
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static const struct spinand_info macronix_spinand_table[] = {
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SPINAND_INFO("MX35LF1GE4AB", 0x12,
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NAND_MEMORG(1, 2048, 64, 64, 1024, 40, 1, 1, 1),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(4, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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@ -109,7 +109,7 @@ static const struct spinand_info macronix_spinand_table[] = {
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SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
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mx35lf1ge4ab_ecc_get_status)),
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SPINAND_INFO("MX35LF2GE4AB", 0x22,
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NAND_MEMORG(1, 2048, 64, 64, 2048, 20, 2, 1, 1),
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NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
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NAND_ECCREQ(4, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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