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mtd: rawnand: sunxi: Add A23/A33 DMA support with extra MBUS configuration
Allwinner NAND controllers can make use of DMA to enhance the I/O
throughput thanks to ECC pipelining. DMA handling with A23/A33 NAND IP
is a bit different than with the older SoCs, hence the introduction of
a new compatible to handle:
* the differences between register offsets,
* the burst length change from 4 to minimum 8,
* manage SRAM accesses through MBUS with extra configuration.
Fixes: c49836f05a
("mtd: rawnand: sunxi: Add A23/A33 DMA support")
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
parent
4f032640bf
commit
c7a87ceb17
1 changed files with 24 additions and 0 deletions
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@ -43,6 +43,7 @@
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#define NFC_REG_RCMD_SET 0x0028
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#define NFC_REG_WCMD_SET 0x002C
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#define NFC_REG_A10_IO_DATA 0x0030
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#define NFC_REG_A23_IO_DATA 0x0300
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#define NFC_REG_ECC_CTL 0x0034
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#define NFC_REG_ECC_ST 0x0038
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#define NFC_REG_DEBUG 0x003C
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@ -50,6 +51,7 @@
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#define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4))
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#define NFC_REG_SPARE_AREA 0x00A0
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#define NFC_REG_PAT_ID 0x00A4
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#define NFC_REG_MDMA_CNT 0x00C4
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#define NFC_RAM0_BASE 0x0400
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#define NFC_RAM1_BASE 0x0800
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@ -68,6 +70,7 @@
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#define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
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#define NFC_SAM BIT(12)
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#define NFC_RAM_METHOD BIT(14)
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#define NFC_DMA_TYPE_NORMAL BIT(15)
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#define NFC_DEBUG_CTL BIT(31)
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/* define bit use in NFC_ST */
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@ -204,10 +207,13 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
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* NAND Controller capabilities structure: stores NAND controller capabilities
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* for distinction between compatible strings.
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*
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* @extra_mbus_conf: Contrary to A10, A10s and A13, accessing internal RAM
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* through MBUS on A23/A33 needs extra configuration.
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* @reg_io_data: I/O data register
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* @dma_maxburst: DMA maxburst
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*/
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struct sunxi_nfc_caps {
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bool extra_mbus_conf;
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unsigned int reg_io_data;
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unsigned int dma_maxburst;
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};
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@ -367,6 +373,9 @@ static int sunxi_nfc_dma_op_prepare(struct sunxi_nfc *nfc, const void *buf,
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nfc->regs + NFC_REG_CTL);
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writel(nchunks, nfc->regs + NFC_REG_SECTOR_NUM);
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writel(chunksize, nfc->regs + NFC_REG_CNT);
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if (nfc->caps->extra_mbus_conf)
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writel(chunksize * nchunks, nfc->regs + NFC_REG_MDMA_CNT);
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dmat = dmaengine_submit(dmad);
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ret = dma_submit_error(dmat);
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@ -2127,6 +2136,11 @@ static int sunxi_nfc_probe(struct platform_device *pdev)
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dmac_cfg.src_maxburst = nfc->caps->dma_maxburst;
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dmac_cfg.dst_maxburst = nfc->caps->dma_maxburst;
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dmaengine_slave_config(nfc->dmac, &dmac_cfg);
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if (nfc->caps->extra_mbus_conf)
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writel(readl(nfc->regs + NFC_REG_CTL) |
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NFC_DMA_TYPE_NORMAL, nfc->regs + NFC_REG_CTL);
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} else {
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dev_warn(dev, "failed to request rxtx DMA channel\n");
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}
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@ -2175,11 +2189,21 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = {
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.dma_maxburst = 4,
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};
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static const struct sunxi_nfc_caps sunxi_nfc_a23_caps = {
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.extra_mbus_conf = true,
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.reg_io_data = NFC_REG_A23_IO_DATA,
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.dma_maxburst = 8,
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};
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static const struct of_device_id sunxi_nfc_ids[] = {
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{
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.compatible = "allwinner,sun4i-a10-nand",
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.data = &sunxi_nfc_a10_caps,
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},
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{
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.compatible = "allwinner,sun8i-a23-nand-controller",
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.data = &sunxi_nfc_a23_caps,
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},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
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