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drm/amdgpu: implement vce3 check/post_soft_reset
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
fc0b3b90b7
commit
115933a577
2 changed files with 109 additions and 7 deletions
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@ -1716,6 +1716,7 @@ struct amdgpu_vce {
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struct amdgpu_irq_src irq;
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unsigned harvest_config;
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struct amd_sched_entity entity;
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uint32_t srbm_soft_reset;
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};
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/*
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@ -37,6 +37,9 @@
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#include "gca/gfx_8_0_d.h"
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#include "smu/smu_7_1_2_d.h"
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#include "smu/smu_7_1_2_sh_mask.h"
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#include "gca/gfx_8_0_d.h"
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#include "gca/gfx_8_0_sh_mask.h"
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#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04
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#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10
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@ -601,20 +604,115 @@ static int vce_v3_0_wait_for_idle(void *handle)
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return -ETIMEDOUT;
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}
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#define AMDGPU_VCE_STATUS_BUSY_MASK 0x78
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static int vce_v3_0_check_soft_reset(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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u32 srbm_soft_reset = 0;
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u32 tmp;
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/* VCE BUG: it is always busy, so skip its checking now */
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return 0;
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/* According to VCE team , we should use VCE_STATUS instead
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* SRBM_STATUS.VCE_BUSY bit for busy status checking.
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* GRBM_GFX_INDEX.INSTANCE_INDEX is used to specify which VCE
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* instance's registers are accessed
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* (0 for 1st instance, 10 for 2nd instance).
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*
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*VCE_STATUS
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*|UENC|ACPI|AUTO ACTIVE|RB1 |RB0 |RB2 | |FW_LOADED|JOB |
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*|----+----+-----------+----+----+----+----------+---------+----|
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*|bit8|bit7| bit6 |bit5|bit4|bit3| bit2 | bit1 |bit0|
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*
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* VCE team suggest use bit 3--bit 6 for busy status check
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*/
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tmp = RREG32(mmGRBM_GFX_INDEX);
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tmp = REG_SET_FIELD(tmp, GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
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WREG32(mmGRBM_GFX_INDEX, tmp);
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if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
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srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
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srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
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}
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tmp = RREG32(mmGRBM_GFX_INDEX);
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tmp = REG_SET_FIELD(tmp, GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10);
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WREG32(mmGRBM_GFX_INDEX, tmp);
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if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
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srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
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srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
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}
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tmp = RREG32(mmGRBM_GFX_INDEX);
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tmp = REG_SET_FIELD(tmp, GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
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WREG32(mmGRBM_GFX_INDEX, tmp);
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if (adev->vce.harvest_config & (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1))
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srbm_soft_reset = 0;
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if (srbm_soft_reset) {
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adev->ip_block_status[AMD_IP_BLOCK_TYPE_VCE].hang = true;
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adev->vce.srbm_soft_reset = srbm_soft_reset;
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} else {
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adev->ip_block_status[AMD_IP_BLOCK_TYPE_VCE].hang = false;
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adev->vce.srbm_soft_reset = 0;
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}
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return 0;
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}
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static int vce_v3_0_soft_reset(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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u32 mask = 0;
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u32 srbm_soft_reset;
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mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK;
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mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE1) ? 0 : SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK;
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if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_VCE].hang)
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return 0;
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srbm_soft_reset = adev->vce.srbm_soft_reset;
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if (srbm_soft_reset) {
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u32 tmp;
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tmp = RREG32(mmSRBM_SOFT_RESET);
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tmp |= srbm_soft_reset;
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dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
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WREG32(mmSRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmSRBM_SOFT_RESET);
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udelay(50);
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tmp &= ~srbm_soft_reset;
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WREG32(mmSRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmSRBM_SOFT_RESET);
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/* Wait a little for things to settle down */
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udelay(50);
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}
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return 0;
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}
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static int vce_v3_0_pre_soft_reset(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_VCE].hang)
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return 0;
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WREG32_P(mmSRBM_SOFT_RESET, mask,
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~(SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK |
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SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK));
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mdelay(5);
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return vce_v3_0_start(adev);
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return vce_v3_0_suspend(adev);
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}
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static int vce_v3_0_post_soft_reset(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_VCE].hang)
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return 0;
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mdelay(5);
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return vce_v3_0_resume(adev);
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}
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static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev,
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@ -751,7 +849,10 @@ const struct amd_ip_funcs vce_v3_0_ip_funcs = {
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.resume = vce_v3_0_resume,
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.is_idle = vce_v3_0_is_idle,
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.wait_for_idle = vce_v3_0_wait_for_idle,
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.check_soft_reset = vce_v3_0_check_soft_reset,
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.pre_soft_reset = vce_v3_0_pre_soft_reset,
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.soft_reset = vce_v3_0_soft_reset,
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.post_soft_reset = vce_v3_0_post_soft_reset,
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.set_clockgating_state = vce_v3_0_set_clockgating_state,
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.set_powergating_state = vce_v3_0_set_powergating_state,
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};
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