mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-06 10:57:46 +00:00
Third round of Renesas ARM SoC board updates for v3.10
Highlights: * Add Lager board support * Add ape6evm board support * Add Bock-W board support * Mackerel MMCIF/SDHI clean ups * Add ethernet support to kzm9g-reference This pull request is based on a merge of: git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux2-for-v3.10 git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-boards2-for-v3.10 The merge with renesas-pinmux2-for-v3.10 was made to provide run-time dependencies for the following changes: ARM: shmobile: APE6EVM LAN9220 support ARM: shmobile: APE6EVM PFC support -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJRW4ucAAoJENfPZGlqN0++oHQP/jpJ6AAAwuFfcfPSnpWIkJY6 cidxxBwf445EcW1OXAKez4Ki4gJ8+AcYBp39dm5nm1HUSrmJgOVgbeQ/benakUi/ 5/Qgj0Hi4HmiYzrDuZo1SgBu3iHZy38KzbzpUFwBXYJW3snlM4WYET08FHzun/3j hvWI5fEgYC4FBzbU68Vc6R1aCZM+yio1wezRz+zMjkSJ2f6dGwM16oXbh0nLgWKk VdvAOTmNbzFIs/3frATcozBI956SJPha7SMq7YUSE0MRIcjpTtvhGnnWFyq3NQH6 JeSs7qKcXBJ8foOE333J+KGyXpMp/FgJxQo0C3N3/fbaiPH6+eE0gkRL27MUPdRy EES9FPGSzuDEe6WPG9pUOJEbkD3BjBUuokC8LDCPrFK1jXdPtz2yAeNOAz+sLDLe oYpmlE2D8dG7DbxrFNRrhFGgujHI4gV9I54IM58xEq3+MpzK0GS4GYYf3+Qas7ob P5qDenAIEC5b+Ox578iRyy35kP8cwbm9BV7zLAXCLVTjWEjcAWPRi+6r9TYt7DV1 /FzW2csVqyN/ec6WljJblImty1tvV1GuuHPQ8azu6ZHlxXQDPAo5KIROTVW/ud7m daReu65vkGwN8PMPpT/jMh38b8wGBkR9TgI2vCLOQ95PTY1UVdkyZIynUkMV5jX8 PxkEzDA3qHoMDI4/XPbD =Zhif -----END PGP SIGNATURE----- Merge tag 'renesas-boards3-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards2 Third round of Renesas ARM SoC board updates for v3.10 Highlights: * Add Lager board support * Add ape6evm board support * Add Bock-W board support * Mackerel MMCIF/SDHI clean ups * Add ethernet support to kzm9g-reference This pull request is based on a merge of: git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux2-for-v3.10 git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-boards2-for-v3.10 The merge with renesas-pinmux2-for-v3.10 was made to provide run-time dependencies for the following changes: ARM: shmobile: APE6EVM LAN9220 support ARM: shmobile: APE6EVM PFC support * tag 'renesas-boards3-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (307 commits) ARM: shmobile: mackerel: clean up MMCIF vs. SDHI1 selection ARM: shmobile: mackerel: add interrupt names for SDHI0 ARM: shmobile: mackerel: switch SDHI and MMCIF interfaces to slot-gpio ARM: shmobile: mackerel: remove OCR masks, where regulators are used ARM: shmobile: mackerel: SDHI resources do not have to be numbered ARM: shmobile: Initial r8a7790 Lager board support ARM: shmobile: APE6EVM LAN9220 support ARM: shmobile: APE6EVM PFC support ARM: shmobile: APE6EVM base support ARM: shmobile: kzm9g-reference: add ethernet support ARM: shmobile: add R-Car M1A Bock-W platform support sh-pfc: r8a73a4: Remove unused GPIO bias data ARM: shmobile: r8a73a4: Remove all GPIO enums sh-pfc: r8a73a4: Remove function GPIOs ARM: shmobile: r8a73a4: Remove IRQC function GPIOs ARM: shmobile: r8a73a4: Remove SCIF function GPIOs sh-pfc: r8a73a4: Remove IRQC function GPIOS sh-pfc: r8a73a4: Remove SCIF function GPIOS sh-pfc: r8a73a4: Add IRQC pin groups and functions sh-pfc: r8a73a4: Add SCIF pin groups and functions ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
16eaaee4d8
141 changed files with 17258 additions and 7909 deletions
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@ -98,7 +98,7 @@ announce the pinrange to the pin ctrl subsystem. For example,
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compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
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reg = <0x1460 0x18>;
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gpio-controller;
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gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>;
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gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
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}
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@ -107,8 +107,8 @@ where,
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Next values specify the base pin and number of pins for the range
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handled by 'qe_pio_e' gpio. In the given example from base pin 20 to
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pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled
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by this gpio controller.
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pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under
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pinctrl2 with gpio offset 10 is handled by this gpio controller.
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The pinctrl node must have "#gpio-range-cells" property to show number of
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arguments to pass with phandle from gpio controllers node.
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@ -1,7 +1,9 @@
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One-register-per-pin type device tree based pinctrl driver
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Required properties:
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- compatible : "pinctrl-single"
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- compatible : "pinctrl-single" or "pinconf-single".
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"pinctrl-single" means that pinconf isn't supported.
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"pinconf-single" means that generic pinconf is supported.
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- reg : offset and length of the register set for the mux registers
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@ -14,9 +16,61 @@ Optional properties:
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- pinctrl-single,function-off : function off mode for disabled state if
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available and same for all registers; if not specified, disabling of
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pin functions is ignored
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- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
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more than one pin
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- pinctrl-single,drive-strength : array of value that are used to configure
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drive strength in the pinmux register. They're value of drive strength
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current and drive strength mask.
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/* drive strength current, mask */
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pinctrl-single,power-source = <0x30 0xf0>;
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- pinctrl-single,bias-pullup : array of value that are used to configure the
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input bias pullup in the pinmux register.
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/* input, enabled pullup bits, disabled pullup bits, mask */
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pinctrl-single,bias-pullup = <0 1 0 1>;
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- pinctrl-single,bias-pulldown : array of value that are used to configure the
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input bias pulldown in the pinmux register.
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/* input, enabled pulldown bits, disabled pulldown bits, mask */
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pinctrl-single,bias-pulldown = <2 2 0 2>;
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* Two bits to control input bias pullup and pulldown: User should use
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pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
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pullup, and the other one bit means pulldown.
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* Three bits to control input bias enable, pullup and pulldown. User should
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use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
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enable bit should be included in pullup or pulldown bits.
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* Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
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pinctrl-single,bias-disable. Because pinctrl single driver could implement
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it by calling pulldown, pullup disabled.
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- pinctrl-single,input-schmitt : array of value that are used to configure
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input schmitt in the pinmux register. In some silicons, there're two input
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schmitt value (rising-edge & falling-edge) in the pinmux register.
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/* input schmitt value, mask */
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pinctrl-single,input-schmitt = <0x30 0x70>;
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- pinctrl-single,input-schmitt-enable : array of value that are used to
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configure input schmitt enable or disable in the pinmux register.
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/* input, enable bits, disable bits, mask */
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pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
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- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
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range. They're value of subnode phandle, pin base in pinctrl device, pin
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number in this range, GPIO function value of this GPIO range.
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The number of parameters is depend on #pinctrl-single,gpio-range-cells
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property.
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/* pin base, nr pins & gpio function */
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pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
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This driver assumes that there is only one register for each pin (unless the
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pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
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specified in the pinctrl-bindings.txt document in this directory.
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@ -42,6 +96,20 @@ Where 0xdc is the offset from the pinctrl register base address for the
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device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
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be used when applying this change to the register.
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Optional sub-node: In case some pins could be configured as GPIO in the pinmux
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register, those pins could be defined as a GPIO range. This sub-node is required
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by pinctrl-single,gpio-range property.
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Required properties in sub-node:
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- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
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pinctrl-single,gpio-range property.
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range: gpio-range {
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#pinctrl-single,gpio-range-cells = <3>;
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};
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Example:
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/* SoC common file */
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@ -76,6 +144,29 @@ control_devconf0: pinmux@48002274 {
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pinctrl-single,function-mask = <0x5F>;
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};
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/* third controller instance for pins in gpio domain */
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pmx_gpio: pinmux@d401e000 {
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compatible = "pinconf-single";
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reg = <0xd401e000 0x0330>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <7>;
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/* sparse GPIO range could be supported */
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pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
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&range 12 1 0 &range 13 29 1
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&range 43 1 0 &range 44 49 1
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&range 94 1 1 &range 96 2 1>;
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range: gpio-range {
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#pinctrl-single,gpio-range-cells = <3>;
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};
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};
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/* board specific .dts file */
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&pmx_core {
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@ -96,6 +187,15 @@ control_devconf0: pinmux@48002274 {
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>;
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};
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uart0_pins: pinmux_uart0_pins {
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pinctrl-single,pins = <
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0x208 0 /* UART0_RXD (IOCFG138) */
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0x20c 0 /* UART0_TXD (IOCFG139) */
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>;
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pinctrl-single,bias-pulldown = <0 2 2>;
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pinctrl-single,bias-pullup = <0 1 1>;
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};
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/* map uart2 pins */
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uart2_pins: pinmux_uart2_pins {
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pinctrl-single,pins = <
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@ -122,6 +222,11 @@ control_devconf0: pinmux@48002274 {
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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@ -723,7 +723,7 @@ config ARCH_SHMOBILE
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select MULTI_IRQ_HANDLER
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select NEED_MACH_MEMORY_H
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select NO_IOPORT
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select PINCTRL
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select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
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select PM_GENERIC_DOMAINS if PM
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select SPARSE_IRQ
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help
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@ -136,7 +136,12 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
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ccu9540.dtb
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dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
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r8a7740-armadillo800eva.dtb \
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r8a7778-bockw.dtb \
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r8a7779-marzen-reference.dtb \
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r8a7790-lager.dtb \
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sh73a0-kzm9g.dtb \
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sh73a0-kzm9g-reference.dtb \
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r8a73a4-ape6evm.dtb \
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sh7372-mackerel.dtb
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dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
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socfpga_vt.dtb
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52
arch/arm/boot/dts/r8a73a4-ape6evm.dts
Normal file
52
arch/arm/boot/dts/r8a73a4-ape6evm.dts
Normal file
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@ -0,0 +1,52 @@
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/*
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* Device Tree Source for the APE6EVM board
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/dts-v1/;
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/include/ "r8a73a4.dtsi"
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/ {
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model = "APE6EVM";
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compatible = "renesas,ape6evm", "renesas,r8a73a4";
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chosen {
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bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp";
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x40000000>;
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};
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ape6evm_fixed_3v3: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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lbsc {
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#address-cells = <1>;
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#size-cells = <1>;
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ethernet@8000000 {
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compatible = "smsc,lan9118", "smsc,lan9115";
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reg = <0x08000000 0x1000>;
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interrupt-parent = <&irqc1>;
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interrupts = <8 0x4>;
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phy-mode = "mii";
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reg-io-width = <4>;
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smsc,irq-active-high;
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smsc,irq-push-pull;
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vdd33a-supply = <&ape6evm_fixed_3v3>;
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vddvario-supply = <&ape6evm_fixed_3v3>;
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};
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};
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};
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94
arch/arm/boot/dts/r8a73a4.dtsi
Normal file
94
arch/arm/boot/dts/r8a73a4.dtsi
Normal file
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@ -0,0 +1,94 @@
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/*
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* Device Tree Source for the r8a73a4 SoC
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/ {
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compatible = "renesas,r8a73a4";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1500000000>;
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};
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>,
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<0 0xf1002000 0 0x1000>,
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<0 0xf1004000 0 0x2000>,
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<0 0xf1006000 0 0x2000>;
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interrupts = <1 9 0xf04>;
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gic-cpuif@4 {
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compatible = "arm,gic-cpuif";
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cpuif-id = <4>;
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cpu = <&cpu0>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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irqc0: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupt-parent = <&gic>;
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interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>,
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<0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>,
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<0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>,
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<0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>,
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<0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>,
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<0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>,
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<0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>,
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<0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>;
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};
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irqc1: interrupt-controller@e61c0200 {
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compatible = "renesas,irqc";
|
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#interrupt-cells = <2>;
|
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interrupt-controller;
|
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reg = <0 0xe61c0200 0 0x200>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>,
|
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<0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>,
|
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<0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>,
|
||||
<0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>,
|
||||
<0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>,
|
||||
<0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>,
|
||||
<0 56 4>, <0 57 4>;
|
||||
};
|
||||
|
||||
thermal@e61f0000 {
|
||||
compatible = "renesas,rcar-thermal";
|
||||
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
|
||||
<0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 69 4>;
|
||||
};
|
||||
};
|
||||
32
arch/arm/boot/dts/r8a7778-bockw.dts
Normal file
32
arch/arm/boot/dts/r8a7778-bockw.dts
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Reference Device Tree Source for the Bock-W board
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
*
|
||||
* based on r8a7779
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Simon Horman
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "r8a7778.dtsi"
|
||||
|
||||
/ {
|
||||
model = "bockw";
|
||||
compatible = "renesas,bockw", "renesas,r8a7778";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttySC0,115200 ignore_loglevel";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x60000000 0x10000000>;
|
||||
};
|
||||
};
|
||||
35
arch/arm/boot/dts/r8a7778.dtsi
Normal file
35
arch/arm/boot/dts/r8a7778.dtsi
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Device Tree Source for Renesas r8a7778
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
*
|
||||
* based on r8a7779
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Simon Horman
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7778";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@fe438000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0xfe438000 0x1000>,
|
||||
<0xfe430000 0x100>;
|
||||
};
|
||||
};
|
||||
47
arch/arm/boot/dts/r8a7779-marzen-reference.dts
Normal file
47
arch/arm/boot/dts/r8a7779-marzen-reference.dts
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* Reference Device Tree Source for the Marzen board
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Simon Horman
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "r8a7779.dtsi"
|
||||
|
||||
/ {
|
||||
model = "marzen";
|
||||
compatible = "renesas,marzen-reference", "renesas,r8a7779";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x60000000 0x40000000>;
|
||||
};
|
||||
|
||||
fixedregulator3v3: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
lan0@18000000 {
|
||||
compatible = "smsc,lan9220", "smsc,lan9115";
|
||||
reg = <0x18000000 0x100>;
|
||||
phy-mode = "mii";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 28 0x4>;
|
||||
reg-io-width = <4>;
|
||||
vddvario-supply = <&fixedregulator3v3>;
|
||||
vdd33a-supply = <&fixedregulator3v3>;
|
||||
};
|
||||
};
|
||||
98
arch/arm/boot/dts/r8a7779.dtsi
Normal file
98
arch/arm/boot/dts/r8a7779.dtsi
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Device Tree Source for Renesas r8a7779
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Simon Horman
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7779";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
};
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <2>;
|
||||
};
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f0001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0xf0001000 0x1000>,
|
||||
<0xf0000100 0x100>;
|
||||
};
|
||||
|
||||
i2c0: i2c@0xffc70000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,rmobile-iic";
|
||||
reg = <0xffc70000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 79 0x4>;
|
||||
};
|
||||
|
||||
i2c1: i2c@0xffc71000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,rmobile-iic";
|
||||
reg = <0xffc71000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 82 0x4>;
|
||||
};
|
||||
|
||||
i2c2: i2c@0xffc72000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,rmobile-iic";
|
||||
reg = <0xffc72000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 80 0x4>;
|
||||
};
|
||||
|
||||
i2c3: i2c@0xffc73000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,rmobile-iic";
|
||||
reg = <0xffc73000 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 81 0x4>;
|
||||
};
|
||||
|
||||
thermal@ffc48000 {
|
||||
compatible = "renesas,rcar-thermal";
|
||||
reg = <0xffc48000 0x38>;
|
||||
};
|
||||
|
||||
sata: sata@fc600000 {
|
||||
compatible = "renesas,rcar-sata";
|
||||
reg = <0xfc600000 0x2000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 100 0x4>;
|
||||
};
|
||||
};
|
||||
31
arch/arm/boot/dts/r8a7790-lager.dts
Normal file
31
arch/arm/boot/dts/r8a7790-lager.dts
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Device Tree Source for the Lager board
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "r8a7790.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Lager";
|
||||
compatible = "renesas,lager", "renesas,r8a7790";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttySC6,115200 ignore_loglevel";
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000 0 0x80000000>;
|
||||
};
|
||||
|
||||
lbsc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
63
arch/arm/boot/dts/r8a7790.dtsi
Normal file
63
arch/arm/boot/dts/r8a7790.dtsi
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Device Tree Source for the r8a7790 SoC
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a7790";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
clock-frequency = <1300000000>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1001000 {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xf1001000 0 0x1000>,
|
||||
<0 0xf1002000 0 0x1000>,
|
||||
<0 0xf1004000 0 0x2000>,
|
||||
<0 0xf1006000 0 0x2000>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
|
||||
gic-cpuif@4 {
|
||||
compatible = "arm,gic-cpuif";
|
||||
cpuif-id = <4>;
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 13 0xf08>,
|
||||
<1 14 0xf08>,
|
||||
<1 11 0xf08>,
|
||||
<1 10 0xf08>;
|
||||
};
|
||||
|
||||
irqc0: interrupt-controller@e61c0000 {
|
||||
compatible = "renesas,irqc";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xe61c0000 0 0x200>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
|
||||
};
|
||||
};
|
||||
79
arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
Normal file
79
arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* Device Tree Source for the KZM-A9-GT board
|
||||
*
|
||||
* Copyright (C) 2012 Horms Solutions Ltd.
|
||||
*
|
||||
* Based on sh73a0-kzm9g.dts
|
||||
* Copyright (C) 2012 Renesas Solutions Corp.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "sh73a0.dtsi"
|
||||
|
||||
/ {
|
||||
model = "KZM-A9-GT";
|
||||
compatible = "renesas,kzm9g-reference", "renesas,sh73a0";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x41000000 0x1e800000>;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
lan9220@10000000 {
|
||||
compatible = "smsc,lan9220", "smsc,lan9115";
|
||||
reg = <0x10000000 0x100>;
|
||||
phy-mode = "mii";
|
||||
interrupt-parent = <&irqpin0>;
|
||||
interrupts = <3 0>; /* active low */
|
||||
reg-io-width = <4>;
|
||||
smsc,irq-push-pull;
|
||||
smsc,save-mac-address;
|
||||
vddvario-supply = <®_1p8v>;
|
||||
vdd33a-supply = <®_3p3v>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmcif {
|
||||
bus-width = <8>;
|
||||
vmmc-supply = <®_1p8v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
vmmc-supply = <®_3p3v>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
vmmc-supply = <®_3p3v>;
|
||||
bus-width = <4>;
|
||||
broken-cd;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
/*
|
||||
* Device Tree Source for the SH73A0 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Renesas Solutions Corp.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/include/ "sh73a0.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "renesas,sh73a0";
|
||||
|
||||
mmcif: mmcif@0x10010000 {
|
||||
compatible = "renesas,sh-mmcif";
|
||||
reg = <0xe6bd0000 0x100>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 140 0x4
|
||||
0 141 0x4>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
};
|
||||
|
|
@ -38,6 +38,87 @@ gic: interrupt-controller@f0001000 {
|
|||
<0xf0000100 0x100>;
|
||||
};
|
||||
|
||||
irqpin0: irqpin@e6900000 {
|
||||
compatible = "renesas,intc-irqpin";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0xe6900000 4>,
|
||||
<0xe6900010 4>,
|
||||
<0xe6900020 1>,
|
||||
<0xe6900040 1>,
|
||||
<0xe6900060 1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 1 0x4
|
||||
0 2 0x4
|
||||
0 3 0x4
|
||||
0 4 0x4
|
||||
0 5 0x4
|
||||
0 6 0x4
|
||||
0 7 0x4
|
||||
0 8 0x4>;
|
||||
};
|
||||
|
||||
irqpin1: irqpin@e6900004 {
|
||||
compatible = "renesas,intc-irqpin";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0xe6900004 4>,
|
||||
<0xe6900014 4>,
|
||||
<0xe6900024 1>,
|
||||
<0xe6900044 1>,
|
||||
<0xe6900064 1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 9 0x4
|
||||
0 10 0x4
|
||||
0 11 0x4
|
||||
0 12 0x4
|
||||
0 13 0x4
|
||||
0 14 0x4
|
||||
0 15 0x4
|
||||
0 16 0x4>;
|
||||
control-parent;
|
||||
};
|
||||
|
||||
irqpin2: irqpin@e6900008 {
|
||||
compatible = "renesas,intc-irqpin";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0xe6900008 4>,
|
||||
<0xe6900018 4>,
|
||||
<0xe6900028 1>,
|
||||
<0xe6900048 1>,
|
||||
<0xe6900068 1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 17 0x4
|
||||
0 18 0x4
|
||||
0 19 0x4
|
||||
0 20 0x4
|
||||
0 21 0x4
|
||||
0 22 0x4
|
||||
0 23 0x4
|
||||
0 24 0x4>;
|
||||
};
|
||||
|
||||
irqpin3: irqpin@e690000c {
|
||||
compatible = "renesas,intc-irqpin";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0xe690000c 4>,
|
||||
<0xe690001c 4>,
|
||||
<0xe690002c 1>,
|
||||
<0xe690004c 1>,
|
||||
<0xe690006c 1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 25 0x4
|
||||
0 26 0x4
|
||||
0 27 0x4
|
||||
0 28 0x4
|
||||
0 29 0x4
|
||||
0 30 0x4
|
||||
0 31 0x4
|
||||
0 32 0x4>;
|
||||
};
|
||||
|
||||
i2c0: i2c@0xe6820000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -97,4 +178,48 @@ i2c4: i2c@0xe6828000 {
|
|||
0 189 0x4
|
||||
0 190 0x4>;
|
||||
};
|
||||
|
||||
mmcif: mmcif@0x10010000 {
|
||||
compatible = "renesas,sh-mmcif";
|
||||
reg = <0xe6bd0000 0x100>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 140 0x4
|
||||
0 141 0x4>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi0: sdhi@0xee100000 {
|
||||
compatible = "renesas,r8a7740-sdhi";
|
||||
reg = <0xee100000 0x100>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 83 4
|
||||
0 84 4
|
||||
0 85 4>;
|
||||
cap-sd-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
|
||||
sdhi1: sdhi@0xee120000 {
|
||||
compatible = "renesas,r8a7740-sdhi";
|
||||
reg = <0xee120000 0x100>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 88 4
|
||||
0 89 4>;
|
||||
toshiba,mmc-wrprotect-disable;
|
||||
cap-sd-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sdhi@0xee140000 {
|
||||
compatible = "renesas,r8a7740-sdhi";
|
||||
reg = <0xee140000 0x100>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 104 4
|
||||
0 105 4>;
|
||||
toshiba,mmc-wrprotect-disable;
|
||||
cap-sd-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -89,7 +89,7 @@ gmac4: eth@5c700000 {
|
|||
pinmux: pinmux@e0700000 {
|
||||
compatible = "st,spear1310-pinmux";
|
||||
reg = <0xe0700000 0x1000>;
|
||||
#gpio-range-cells = <2>;
|
||||
#gpio-range-cells = <3>;
|
||||
};
|
||||
|
||||
apb {
|
||||
|
|
@ -212,7 +212,7 @@ gpiopinctrl: gpio@d8400000 {
|
|||
interrupt-controller;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinmux 0 246>;
|
||||
gpio-ranges = <&pinmux 0 0 246>;
|
||||
status = "disabled";
|
||||
|
||||
st-plgpio,ngpio = <246>;
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ i2s-rec@b2000000 {
|
|||
pinmux: pinmux@e0700000 {
|
||||
compatible = "st,spear1340-pinmux";
|
||||
reg = <0xe0700000 0x1000>;
|
||||
#gpio-range-cells = <2>;
|
||||
#gpio-range-cells = <3>;
|
||||
};
|
||||
|
||||
pwm: pwm@e0180000 {
|
||||
|
|
@ -127,7 +127,7 @@ gpiopinctrl: gpio@e2800000 {
|
|||
interrupt-controller;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinmux 0 252>;
|
||||
gpio-ranges = <&pinmux 0 0 252>;
|
||||
status = "disabled";
|
||||
|
||||
st-plgpio,ngpio = <250>;
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ ahb {
|
|||
pinmux: pinmux@b4000000 {
|
||||
compatible = "st,spear310-pinmux";
|
||||
reg = <0xb4000000 0x1000>;
|
||||
#gpio-range-cells = <2>;
|
||||
#gpio-range-cells = <3>;
|
||||
};
|
||||
|
||||
fsmc: flash@44000000 {
|
||||
|
|
@ -102,7 +102,7 @@ gpiopinctrl: gpio@b4000000 {
|
|||
interrupt-controller;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinmux 0 102>;
|
||||
gpio-ranges = <&pinmux 0 0 102>;
|
||||
status = "disabled";
|
||||
|
||||
st-plgpio,ngpio = <102>;
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ ahb {
|
|||
pinmux: pinmux@b3000000 {
|
||||
compatible = "st,spear320-pinmux";
|
||||
reg = <0xb3000000 0x1000>;
|
||||
#gpio-range-cells = <2>;
|
||||
#gpio-range-cells = <3>;
|
||||
};
|
||||
|
||||
clcd@90000000 {
|
||||
|
|
@ -130,7 +130,7 @@ gpiopinctrl: gpio@b3000000 {
|
|||
interrupt-controller;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinmux 0 102>;
|
||||
gpio-ranges = <&pinmux 0 0 102>;
|
||||
status = "disabled";
|
||||
|
||||
st-plgpio,ngpio = <102>;
|
||||
|
|
|
|||
66
arch/arm/configs/bockw_defconfig
Normal file
66
arch/arm/configs/bockw_defconfig
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
|
||||
CONFIG_KERNEL_LZMA=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=16
|
||||
CONFIG_SYSCTL_SYSCALL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_ARCH_SHMOBILE=y
|
||||
CONFIG_ARCH_R8A7778=y
|
||||
CONFIG_MACH_BOCKW=y
|
||||
CONFIG_MEMORY_START=0x60000000
|
||||
CONFIG_MEMORY_SIZE=0x10000000
|
||||
CONFIG_SHMOBILE_TIMER_HZ=1024
|
||||
# CONFIG_SH_TIMER_CMT is not set
|
||||
# CONFIG_EM_TIMER_STI is not set
|
||||
CONFIG_ARM_ERRATA_430973=y
|
||||
CONFIG_ARM_ERRATA_458693=y
|
||||
CONFIG_ARM_ERRATA_460075=y
|
||||
CONFIG_ARM_ERRATA_743622=y
|
||||
CONFIG_ARM_ERRATA_754322=y
|
||||
CONFIG_AEABI=y
|
||||
# CONFIG_OABI_COMPAT is not set
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_CMDLINE="console=ttySC0,115200 ignore_loglevel"
|
||||
CONFIG_CMDLINE_FORCE=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
# CONFIG_SUSPEND is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
# CONFIG_FW_LOADER is not set
|
||||
# CONFIG_INPUT is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
# CONFIG_DEVKMEM is not set
|
||||
CONFIG_SERIAL_SH_SCI=y
|
||||
CONFIG_SERIAL_SH_SCI_NR_UARTS=6
|
||||
CONFIG_SERIAL_SH_SCI_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_UIO=y
|
||||
CONFIG_UIO_PDRV_GENIRQ=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
# CONFIG_DNOTIFY is not set
|
||||
# CONFIG_INOTIFY_USER is not set
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
# CONFIG_ENABLE_WARN_DEPRECATED is not set
|
||||
# CONFIG_ENABLE_MUST_CHECK is not set
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
# CONFIG_ARM_UNWIND is not set
|
||||
CONFIG_KEYS=y
|
||||
CONFIG_CRYPTO=y
|
||||
CONFIG_AVERAGE=y
|
||||
|
|
@ -16,12 +16,30 @@ config ARCH_SH73A0
|
|||
select CPU_V7
|
||||
select I2C
|
||||
select SH_CLK_CPG
|
||||
select RENESAS_INTC_IRQPIN
|
||||
|
||||
config ARCH_R8A73A4
|
||||
bool "R-Mobile APE6 (R8A73A40)"
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select ARM_GIC
|
||||
select CPU_V7
|
||||
select ARM_ARCH_TIMER
|
||||
select SH_CLK_CPG
|
||||
select RENESAS_IRQC
|
||||
|
||||
config ARCH_R8A7740
|
||||
bool "R-Mobile A1 (R8A77400)"
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select ARM_GIC
|
||||
select CPU_V7
|
||||
select SH_CLK_CPG
|
||||
select RENESAS_INTC_IRQPIN
|
||||
|
||||
config ARCH_R8A7778
|
||||
bool "R-Car M1 (R8A77780)"
|
||||
select CPU_V7
|
||||
select SH_CLK_CPG
|
||||
select ARM_GIC
|
||||
|
||||
config ARCH_R8A7779
|
||||
bool "R-Car H1 (R8A77790)"
|
||||
|
|
@ -31,6 +49,16 @@ config ARCH_R8A7779
|
|||
select SH_CLK_CPG
|
||||
select USB_ARCH_HAS_EHCI
|
||||
select USB_ARCH_HAS_OHCI
|
||||
select RENESAS_INTC_IRQPIN
|
||||
|
||||
config ARCH_R8A7790
|
||||
bool "R-Car H2 (R8A77900)"
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select ARM_GIC
|
||||
select CPU_V7
|
||||
select ARM_ARCH_TIMER
|
||||
select SH_CLK_CPG
|
||||
select RENESAS_IRQC
|
||||
|
||||
config ARCH_EMEV2
|
||||
bool "Emma Mobile EV2"
|
||||
|
|
@ -68,6 +96,11 @@ config MACH_AG5EVM
|
|||
select REGULATOR_FIXED_VOLTAGE if REGULATOR
|
||||
select SH_LCD_MIPI_DSI
|
||||
|
||||
config MACH_APE6EVM
|
||||
bool "APE6EVM board"
|
||||
depends on ARCH_R8A73A4
|
||||
select USE_OF
|
||||
|
||||
config MACH_MACKEREL
|
||||
bool "mackerel board"
|
||||
depends on ARCH_SH7372
|
||||
|
|
@ -96,12 +129,36 @@ config MACH_ARMADILLO800EVA
|
|||
select SND_SOC_WM8978 if SND_SIMPLE_CARD
|
||||
select USE_OF
|
||||
|
||||
config MACH_BOCKW
|
||||
bool "BOCK-W platform"
|
||||
depends on ARCH_R8A7778
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select USE_OF
|
||||
|
||||
config MACH_MARZEN
|
||||
bool "MARZEN board"
|
||||
depends on ARCH_R8A7779
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select REGULATOR_FIXED_VOLTAGE if REGULATOR
|
||||
|
||||
config MACH_MARZEN_REFERENCE
|
||||
bool "MARZEN board - Reference Device Tree Implementation"
|
||||
depends on ARCH_R8A7779
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select REGULATOR_FIXED_VOLTAGE if REGULATOR
|
||||
select USE_OF
|
||||
---help---
|
||||
Use reference implementation of Marzen board support
|
||||
which makes use of device tree at the expense
|
||||
of not supporting a number of devices.
|
||||
|
||||
This is intended to aid developers
|
||||
|
||||
config MACH_LAGER
|
||||
bool "Lager board"
|
||||
depends on ARCH_R8A7790
|
||||
select USE_OF
|
||||
|
||||
config MACH_KZM9D
|
||||
bool "KZM9D board"
|
||||
depends on ARCH_EMEV2
|
||||
|
|
@ -116,6 +173,20 @@ config MACH_KZM9G
|
|||
select SND_SOC_AK4642 if SND_SIMPLE_CARD
|
||||
select USE_OF
|
||||
|
||||
config MACH_KZM9G_REFERENCE
|
||||
bool "KZM-A9-GT board - Reference Device Tree Implementation"
|
||||
depends on ARCH_SH73A0
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select REGULATOR_FIXED_VOLTAGE if REGULATOR
|
||||
select SND_SOC_AK4642 if SND_SIMPLE_CARD
|
||||
select USE_OF
|
||||
---help---
|
||||
Use reference implementation of KZM-A9-GT board support
|
||||
which makes as greater use of device tree at the expense
|
||||
of not supporting a number of devices.
|
||||
|
||||
This is intended to aid developers
|
||||
|
||||
comment "SH-Mobile System Configuration"
|
||||
|
||||
config CPU_HAS_INTEVT
|
||||
|
|
@ -128,7 +199,8 @@ config MEMORY_START
|
|||
hex "Physical memory start address"
|
||||
default "0x40000000" if MACH_AP4EVB || MACH_AG5EVM || \
|
||||
MACH_MACKEREL || MACH_BONITO || \
|
||||
MACH_ARMADILLO800EVA
|
||||
MACH_ARMADILLO800EVA || MACH_APE6EVM || \
|
||||
MACH_LAGER
|
||||
default "0x41000000" if MACH_KOTA2
|
||||
default "0x00000000"
|
||||
---help---
|
||||
|
|
@ -138,6 +210,8 @@ config MEMORY_START
|
|||
|
||||
config MEMORY_SIZE
|
||||
hex "Physical memory size"
|
||||
default "0x80000000" if MACH_LAGER
|
||||
default "0x40000000" if MACH_APE6EVM
|
||||
default "0x20000000" if MACH_AG5EVM || MACH_BONITO || \
|
||||
MACH_ARMADILLO800EVA
|
||||
default "0x1e000000" if MACH_KOTA2
|
||||
|
|
|
|||
|
|
@ -8,16 +8,18 @@ obj-y := timer.o console.o clock.o
|
|||
# CPU objects
|
||||
obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
|
||||
obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
|
||||
obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o
|
||||
obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
|
||||
obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o clock-r8a7778.o
|
||||
obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
|
||||
obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o clock-r8a7790.o
|
||||
obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o
|
||||
|
||||
# SMP objects
|
||||
smp-y := platsmp.o headsmp.o
|
||||
smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-sh73a0.o
|
||||
smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o
|
||||
smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o
|
||||
smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o
|
||||
smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o
|
||||
smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o
|
||||
|
||||
# IRQ objects
|
||||
obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
|
||||
|
|
@ -35,13 +37,18 @@ obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o
|
|||
# Board objects
|
||||
obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o
|
||||
obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o
|
||||
obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o
|
||||
obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
|
||||
obj-$(CONFIG_MACH_KOTA2) += board-kota2.o
|
||||
obj-$(CONFIG_MACH_BONITO) += board-bonito.o
|
||||
obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
|
||||
obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
|
||||
obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o
|
||||
obj-$(CONFIG_MACH_LAGER) += board-lager.o
|
||||
obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
|
||||
obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o
|
||||
obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o
|
||||
obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o
|
||||
|
||||
# Framework support
|
||||
obj-$(CONFIG_SMP) += $(smp-y)
|
||||
|
|
|
|||
|
|
@ -23,6 +23,8 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
|
|
@ -304,9 +306,9 @@ static int lcd_backlight_set_brightness(int brightness)
|
|||
|
||||
if (brightness == 0) {
|
||||
/* Reset the chip */
|
||||
gpio_set_value(GPIO_PORT235, 0);
|
||||
gpio_set_value(235, 0);
|
||||
mdelay(24);
|
||||
gpio_set_value(GPIO_PORT235, 1);
|
||||
gpio_set_value(235, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -406,7 +408,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
|
|||
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
|
||||
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
|
||||
.tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
|
||||
.cd_gpio = GPIO_PORT251,
|
||||
.cd_gpio = 251,
|
||||
};
|
||||
|
||||
static struct resource sdhi0_resources[] = {
|
||||
|
|
@ -461,7 +463,7 @@ static struct regulator_init_data cn4_power_init_data = {
|
|||
static struct fixed_voltage_config cn4_power_info = {
|
||||
.supply_name = "CN4 SD/MMC Vdd",
|
||||
.microvolts = 3300000,
|
||||
.gpio = GPIO_PORT114,
|
||||
.gpio = 114,
|
||||
.enable_high = 1,
|
||||
.init_data = &cn4_power_init_data,
|
||||
};
|
||||
|
|
@ -479,10 +481,10 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
|
|||
static int power_gpio = -EINVAL;
|
||||
|
||||
if (power_gpio < 0) {
|
||||
int ret = gpio_request_one(GPIO_PORT114, GPIOF_OUT_INIT_LOW,
|
||||
int ret = gpio_request_one(114, GPIOF_OUT_INIT_LOW,
|
||||
"sdhi1_power");
|
||||
if (!ret)
|
||||
power_gpio = GPIO_PORT114;
|
||||
power_gpio = 114;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -493,7 +495,7 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
|
|||
* regulator driver. We have to live with the race in case the driver
|
||||
* gets unloaded and the GPIO freed between these two steps.
|
||||
*/
|
||||
gpio_set_value(GPIO_PORT114, state);
|
||||
gpio_set_value(114, state);
|
||||
}
|
||||
|
||||
static struct sh_mobile_sdhi_info sh_sdhi1_info = {
|
||||
|
|
@ -550,6 +552,77 @@ static struct platform_device *ag5evm_devices[] __initdata = {
|
|||
&sdhi1_device,
|
||||
};
|
||||
|
||||
static unsigned long pin_pullup_conf[] = {
|
||||
PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
|
||||
};
|
||||
|
||||
static const struct pinctrl_map ag5evm_pinctrl_map[] = {
|
||||
/* FSIA */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
|
||||
"fsia_mclk_in", "fsia"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
|
||||
"fsia_sclk_in", "fsia"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
|
||||
"fsia_data_in", "fsia"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
|
||||
"fsia_data_out", "fsia"),
|
||||
/* I2C2 & I2C3 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.2", "pfc-sh73a0",
|
||||
"i2c2_0", "i2c2"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
|
||||
"i2c3_0", "i2c3"),
|
||||
/* IrDA */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_irda.0", "pfc-sh73a0",
|
||||
"irda_0", "irda"),
|
||||
/* KEYSC */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
|
||||
"keysc_in8", "keysc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
|
||||
"keysc_out04", "keysc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
|
||||
"keysc_out5", "keysc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
|
||||
"keysc_out6_0", "keysc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
|
||||
"keysc_out7_0", "keysc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
|
||||
"keysc_out8_0", "keysc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
|
||||
"keysc_out9_2", "keysc"),
|
||||
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
|
||||
"keysc_in8", pin_pullup_conf),
|
||||
/* MMCIF */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
|
||||
"mmc0_data8_0", "mmc0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
|
||||
"mmc0_ctrl_0", "mmc0"),
|
||||
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
|
||||
"PORT279", pin_pullup_conf),
|
||||
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
|
||||
"mmc0_data8_0", pin_pullup_conf),
|
||||
/* SCIFA2 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
|
||||
"scifa2_data_0", "scifa2"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
|
||||
"scifa2_ctrl_0", "scifa2"),
|
||||
/* SDHI0 (CN15 [SD I/F]) */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
|
||||
"sdhi0_data4", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
|
||||
"sdhi0_ctrl", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
|
||||
"sdhi0_wp", "sdhi0"),
|
||||
/* SDHI1 (CN4 [WLAN I/F]) */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
|
||||
"sdhi1_data4", "sdhi1"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
|
||||
"sdhi1_ctrl", "sdhi1"),
|
||||
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
|
||||
"sdhi1_data4", pin_pullup_conf),
|
||||
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
|
||||
"PORT263", pin_pullup_conf),
|
||||
};
|
||||
|
||||
static void __init ag5evm_init(void)
|
||||
{
|
||||
regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
|
||||
|
|
@ -558,96 +631,27 @@ static void __init ag5evm_init(void)
|
|||
ARRAY_SIZE(fixed2v8_power_consumers), 3300000);
|
||||
regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));
|
||||
|
||||
pinctrl_register_mappings(ag5evm_pinctrl_map,
|
||||
ARRAY_SIZE(ag5evm_pinctrl_map));
|
||||
sh73a0_pinmux_init();
|
||||
|
||||
/* enable SCIFA2 */
|
||||
gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
|
||||
|
||||
/* enable KEYSC */
|
||||
gpio_request(GPIO_FN_KEYIN0_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN1_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN2_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN3_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN4_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN5_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN6_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN7_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT0, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT1, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT2, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT3, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT4, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT5, NULL);
|
||||
gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
|
||||
gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT8, NULL);
|
||||
gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL);
|
||||
|
||||
/* enable I2C channel 2 and 3 */
|
||||
gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
|
||||
gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
|
||||
gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL);
|
||||
gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL);
|
||||
|
||||
/* enable MMCIF */
|
||||
gpio_request(GPIO_FN_MMCCLK0, NULL);
|
||||
gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
|
||||
gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
|
||||
gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
|
||||
|
||||
/* enable SMSC911X */
|
||||
gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */
|
||||
gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
|
||||
|
||||
/* FSI A */
|
||||
gpio_request(GPIO_FN_FSIACK, NULL);
|
||||
gpio_request(GPIO_FN_FSIAILR, NULL);
|
||||
gpio_request(GPIO_FN_FSIAIBT, NULL);
|
||||
gpio_request(GPIO_FN_FSIAISLD, NULL);
|
||||
gpio_request(GPIO_FN_FSIAOSLD, NULL);
|
||||
|
||||
/* IrDA */
|
||||
gpio_request(GPIO_FN_PORT241_IRDA_OUT, NULL);
|
||||
gpio_request(GPIO_FN_PORT242_IRDA_IN, NULL);
|
||||
gpio_request(GPIO_FN_PORT243_IRDA_FIRSEL, NULL);
|
||||
gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
|
||||
gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
|
||||
|
||||
/* LCD panel */
|
||||
gpio_request_one(GPIO_PORT217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
|
||||
gpio_request_one(217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
|
||||
mdelay(1);
|
||||
gpio_set_value(GPIO_PORT217, 1);
|
||||
gpio_set_value(217, 1);
|
||||
mdelay(100);
|
||||
|
||||
/* LCD backlight controller */
|
||||
gpio_request_one(GPIO_PORT235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
|
||||
gpio_request_one(235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
|
||||
lcd_backlight_set_brightness(0);
|
||||
|
||||
/* enable SDHI0 on CN15 [SD I/F] */
|
||||
gpio_request(GPIO_FN_SDHIWP0, NULL);
|
||||
gpio_request(GPIO_FN_SDHICMD0, NULL);
|
||||
gpio_request(GPIO_FN_SDHICLK0, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_3, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_2, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_1, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_0, NULL);
|
||||
|
||||
/* enable SDHI1 on CN4 [WLAN I/F] */
|
||||
gpio_request(GPIO_FN_SDHICLK1, NULL);
|
||||
gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
/* Shared attribute override enable, 64K*8way */
|
||||
l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@
|
|||
#include <linux/i2c.h>
|
||||
#include <linux/i2c/tsc2007.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/smsc911x.h>
|
||||
|
|
@ -273,11 +274,11 @@ static struct platform_device smc911x_device = {
|
|||
|
||||
/*
|
||||
* The card detect pin of the top SD/MMC slot (CN7) is active low and is
|
||||
* connected to GPIO A22 of SH7372 (GPIO_PORT41).
|
||||
* connected to GPIO A22 of SH7372 (GPIO 41).
|
||||
*/
|
||||
static int slot_cn7_get_cd(struct platform_device *pdev)
|
||||
{
|
||||
return !gpio_get_value(GPIO_PORT41);
|
||||
return !gpio_get_value(41);
|
||||
}
|
||||
/* MERAM */
|
||||
static struct sh_mobile_meram_info meram_info = {
|
||||
|
|
@ -838,22 +839,22 @@ static struct platform_device fsi_hdmi_device = {
|
|||
static struct gpio_led ap4evb_leds[] = {
|
||||
{
|
||||
.name = "led4",
|
||||
.gpio = GPIO_PORT185,
|
||||
.gpio = 185,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
},
|
||||
{
|
||||
.name = "led2",
|
||||
.gpio = GPIO_PORT186,
|
||||
.gpio = 186,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
},
|
||||
{
|
||||
.name = "led3",
|
||||
.gpio = GPIO_PORT187,
|
||||
.gpio = 187,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
},
|
||||
{
|
||||
.name = "led1",
|
||||
.gpio = GPIO_PORT188,
|
||||
.gpio = 188,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
}
|
||||
};
|
||||
|
|
@ -1026,10 +1027,10 @@ static void __init hdmi_init_pm_clock(void)
|
|||
/* TouchScreen */
|
||||
#ifdef CONFIG_AP4EVB_QHD
|
||||
# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
|
||||
# define GPIO_TSC_PORT GPIO_PORT123
|
||||
# define GPIO_TSC_PORT 123
|
||||
#else /* WVGA */
|
||||
# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40
|
||||
# define GPIO_TSC_PORT GPIO_PORT40
|
||||
# define GPIO_TSC_PORT 40
|
||||
#endif
|
||||
|
||||
#define IRQ28 evt2irq(0x3380) /* IRQ28A */
|
||||
|
|
@ -1084,6 +1085,28 @@ static struct i2c_board_info i2c1_devices[] = {
|
|||
};
|
||||
|
||||
|
||||
static const struct pinctrl_map ap4evb_pinctrl_map[] = {
|
||||
/* MMCIF */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
|
||||
"mmc0_data8_0", "mmc0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
|
||||
"mmc0_ctrl_0", "mmc0"),
|
||||
/* SDHI0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
|
||||
"sdhi0_data4", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
|
||||
"sdhi0_ctrl", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
|
||||
"sdhi0_cd", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
|
||||
"sdhi0_wp", "sdhi0"),
|
||||
/* SDHI1 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
|
||||
"sdhi1_data4", "sdhi1"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
|
||||
"sdhi1_ctrl", "sdhi1"),
|
||||
};
|
||||
|
||||
#define GPIO_PORT9CR IOMEM(0xE6051009)
|
||||
#define GPIO_PORT10CR IOMEM(0xE605100A)
|
||||
#define USCCR1 IOMEM(0xE6058144)
|
||||
|
|
@ -1110,6 +1133,8 @@ static void __init ap4evb_init(void)
|
|||
/* External clock source */
|
||||
clk_set_rate(&sh7372_dv_clki_clk, 27000000);
|
||||
|
||||
pinctrl_register_mappings(ap4evb_pinctrl_map,
|
||||
ARRAY_SIZE(ap4evb_pinctrl_map));
|
||||
sh7372_pinmux_init();
|
||||
|
||||
/* enable SCIFA0 */
|
||||
|
|
@ -1121,40 +1146,10 @@ static void __init ap4evb_init(void)
|
|||
gpio_request(GPIO_FN_IRQ6_39, NULL);
|
||||
|
||||
/* enable Debug switch (S6) */
|
||||
gpio_request_one(GPIO_PORT32, GPIOF_IN | GPIOF_EXPORT, NULL);
|
||||
gpio_request_one(GPIO_PORT33, GPIOF_IN | GPIOF_EXPORT, NULL);
|
||||
gpio_request_one(GPIO_PORT34, GPIOF_IN | GPIOF_EXPORT, NULL);
|
||||
gpio_request_one(GPIO_PORT35, GPIOF_IN | GPIOF_EXPORT, NULL);
|
||||
|
||||
/* SDHI0 */
|
||||
gpio_request(GPIO_FN_SDHICD0, NULL);
|
||||
gpio_request(GPIO_FN_SDHIWP0, NULL);
|
||||
gpio_request(GPIO_FN_SDHICMD0, NULL);
|
||||
gpio_request(GPIO_FN_SDHICLK0, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_3, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_2, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_1, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_0, NULL);
|
||||
|
||||
/* SDHI1 */
|
||||
gpio_request(GPIO_FN_SDHICMD1, NULL);
|
||||
gpio_request(GPIO_FN_SDHICLK1, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_3, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_2, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_1, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_0, NULL);
|
||||
|
||||
/* MMCIF */
|
||||
gpio_request(GPIO_FN_MMCD0_0, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_1, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_2, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_3, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_4, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_5, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_6, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_7, NULL);
|
||||
gpio_request(GPIO_FN_MMCCMD0, NULL);
|
||||
gpio_request(GPIO_FN_MMCCLK0, NULL);
|
||||
gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
|
||||
gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
|
||||
gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
|
||||
gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
|
||||
|
||||
/* USB enable */
|
||||
gpio_request(GPIO_FN_VBUS0_1, NULL);
|
||||
|
|
@ -1172,15 +1167,15 @@ static void __init ap4evb_init(void)
|
|||
gpio_request(GPIO_FN_FSIAILR, NULL);
|
||||
gpio_request(GPIO_FN_FSIAISLD, NULL);
|
||||
gpio_request(GPIO_FN_FSIAOSLD, NULL);
|
||||
gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
|
||||
gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
|
||||
|
||||
gpio_request(GPIO_PORT9, NULL);
|
||||
gpio_request(GPIO_PORT10, NULL);
|
||||
gpio_request(9, NULL);
|
||||
gpio_request(10, NULL);
|
||||
gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
|
||||
gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
|
||||
|
||||
/* card detect pin for MMC slot (CN7) */
|
||||
gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL);
|
||||
gpio_request_one(41, GPIOF_IN, NULL);
|
||||
|
||||
/* setup FSI2 port B (HDMI) */
|
||||
gpio_request(GPIO_FN_FSIBCK, NULL);
|
||||
|
|
@ -1268,8 +1263,8 @@ static void __init ap4evb_init(void)
|
|||
gpio_request(GPIO_FN_LCDDISP, NULL);
|
||||
gpio_request(GPIO_FN_LCDDCK, NULL);
|
||||
|
||||
gpio_request_one(GPIO_PORT189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
|
||||
gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
|
||||
gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
|
||||
gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
|
||||
|
||||
lcdc_info.clock_source = LCDC_CLK_BUS;
|
||||
lcdc_info.ch[0].interface_type = RGB18;
|
||||
|
|
|
|||
94
arch/arm/mach-shmobile/board-ape6evm.c
Normal file
94
arch/arm/mach-shmobile/board-ape6evm.c
Normal file
|
|
@ -0,0 +1,94 @@
|
|||
/*
|
||||
* APE6EVM board support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/smsc911x.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/r8a73a4.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
/* Dummy supplies, where voltage doesn't matter */
|
||||
static struct regulator_consumer_supply dummy_supplies[] = {
|
||||
REGULATOR_SUPPLY("vddvario", "smsc911x"),
|
||||
REGULATOR_SUPPLY("vdd33a", "smsc911x"),
|
||||
};
|
||||
|
||||
/* SMSC LAN9220 */
|
||||
static const struct resource lan9220_res[] = {
|
||||
DEFINE_RES_MEM(0x08000000, 0x1000),
|
||||
{
|
||||
.start = irq_pin(40), /* IRQ40 */
|
||||
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct smsc911x_platform_config lan9220_data = {
|
||||
.flags = SMSC911X_USE_32BIT,
|
||||
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
|
||||
};
|
||||
|
||||
static const struct pinctrl_map ape6evm_pinctrl_map[] = {
|
||||
/* SCIFA0 console */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4",
|
||||
"scifa0_data", "scifa0"),
|
||||
/* SMSC */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a73a4",
|
||||
"irqc_irq40", "irqc"),
|
||||
};
|
||||
|
||||
static void __init ape6evm_add_standard_devices(void)
|
||||
{
|
||||
r8a73a4_clock_init();
|
||||
pinctrl_register_mappings(ape6evm_pinctrl_map,
|
||||
ARRAY_SIZE(ape6evm_pinctrl_map));
|
||||
r8a73a4_pinmux_init();
|
||||
r8a73a4_add_standard_devices();
|
||||
|
||||
/* LAN9220 ethernet */
|
||||
gpio_request_one(270, GPIOF_OUT_INIT_HIGH, NULL); /* smsc9220 RESET */
|
||||
|
||||
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
|
||||
|
||||
platform_device_register_resndata(&platform_bus, "smsc911x", -1,
|
||||
lan9220_res, ARRAY_SIZE(lan9220_res),
|
||||
&lan9220_data, sizeof(lan9220_data));
|
||||
}
|
||||
|
||||
static const char *ape6evm_boards_compat_dt[] __initdata = {
|
||||
"renesas,ape6evm",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(APE6EVM_DT, "ape6evm")
|
||||
.init_irq = irqchip_init,
|
||||
.init_time = shmobile_timer_init,
|
||||
.init_machine = ape6evm_add_standard_devices,
|
||||
.dt_compat = ape6evm_boards_compat_dt,
|
||||
MACHINE_END
|
||||
|
|
@ -28,7 +28,10 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/regulator/driver.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/regulator/gpio-regulator.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/sh_eth.h>
|
||||
#include <linux/videodev2.h>
|
||||
|
|
@ -145,7 +148,7 @@
|
|||
* see
|
||||
* usbhsf_power_ctrl()
|
||||
*/
|
||||
#define IRQ7 evt2irq(0x02e0)
|
||||
#define IRQ7 irq_pin(7)
|
||||
#define USBCR1 IOMEM(0xe605810a)
|
||||
#define USBH 0xC6700000
|
||||
#define USBH_USBCTR 0x10834
|
||||
|
|
@ -227,7 +230,7 @@ static void usbhsf_power_ctrl(struct platform_device *pdev,
|
|||
|
||||
static int usbhsf_get_vbus(struct platform_device *pdev)
|
||||
{
|
||||
return gpio_get_value(GPIO_PORT209);
|
||||
return gpio_get_value(209);
|
||||
}
|
||||
|
||||
static irqreturn_t usbhsf_interrupt(int irq, void *data)
|
||||
|
|
@ -330,7 +333,7 @@ static struct resource usbhsf_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = evt2irq(0x0A20),
|
||||
.start = gic_spi(51),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -363,7 +366,7 @@ static struct resource sh_eth_resources[] = {
|
|||
.end = 0xe9a02000 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = evt2irq(0x0500),
|
||||
.start = gic_spi(110),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -417,7 +420,7 @@ static struct resource lcdc0_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = intcs_evt2irq(0x580),
|
||||
.start = gic_spi(177),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -452,7 +455,7 @@ static struct resource hdmi_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = evt2irq(0x1700),
|
||||
.start = gic_spi(131),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
|
|
@ -514,7 +517,7 @@ static struct resource hdmi_lcdc_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = intcs_evt2irq(0x1780),
|
||||
.start = gic_spi(178),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -535,10 +538,10 @@ static struct platform_device hdmi_lcdc_device = {
|
|||
{ .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ }
|
||||
|
||||
static struct gpio_keys_button gpio_buttons[] = {
|
||||
GPIO_KEY(KEY_POWER, GPIO_PORT99, "SW3", .wakeup = 1),
|
||||
GPIO_KEY(KEY_BACK, GPIO_PORT100, "SW4"),
|
||||
GPIO_KEY(KEY_MENU, GPIO_PORT97, "SW5"),
|
||||
GPIO_KEY(KEY_HOME, GPIO_PORT98, "SW6"),
|
||||
GPIO_KEY(KEY_POWER, 99, "SW3", .wakeup = 1),
|
||||
GPIO_KEY(KEY_BACK, 100, "SW4"),
|
||||
GPIO_KEY(KEY_MENU, 97, "SW5"),
|
||||
GPIO_KEY(KEY_HOME, 98, "SW6"),
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data gpio_key_info = {
|
||||
|
|
@ -554,17 +557,121 @@ static struct platform_device gpio_keys_device = {
|
|||
},
|
||||
};
|
||||
|
||||
/* Fixed 3.3V regulator to be used by SDHI0, SDHI1, MMCIF */
|
||||
static struct regulator_consumer_supply fixed3v3_power_consumers[] =
|
||||
{
|
||||
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
|
||||
REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
|
||||
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
|
||||
REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
|
||||
/* Fixed 3.3V regulator to be used by SDHI1, MMCIF */
|
||||
static struct regulator_consumer_supply fixed3v3_power_consumers[] = {
|
||||
REGULATOR_SUPPLY("vmmc", "sh_mmcif"),
|
||||
REGULATOR_SUPPLY("vqmmc", "sh_mmcif"),
|
||||
};
|
||||
|
||||
/* Fixed 3.3V regulator to be used by SDHI0 */
|
||||
static struct regulator_consumer_supply vcc_sdhi0_consumers[] = {
|
||||
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data vcc_sdhi0_init_data = {
|
||||
.constraints = {
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(vcc_sdhi0_consumers),
|
||||
.consumer_supplies = vcc_sdhi0_consumers,
|
||||
};
|
||||
|
||||
static struct fixed_voltage_config vcc_sdhi0_info = {
|
||||
.supply_name = "SDHI0 Vcc",
|
||||
.microvolts = 3300000,
|
||||
.gpio = GPIO_PORT75,
|
||||
.enable_high = 1,
|
||||
.init_data = &vcc_sdhi0_init_data,
|
||||
};
|
||||
|
||||
static struct platform_device vcc_sdhi0 = {
|
||||
.name = "reg-fixed-voltage",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &vcc_sdhi0_info,
|
||||
},
|
||||
};
|
||||
|
||||
/* 1.8 / 3.3V SDHI0 VccQ regulator */
|
||||
static struct regulator_consumer_supply vccq_sdhi0_consumers[] = {
|
||||
REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data vccq_sdhi0_init_data = {
|
||||
.constraints = {
|
||||
.input_uV = 3300000,
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 3300000,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(vccq_sdhi0_consumers),
|
||||
.consumer_supplies = vccq_sdhi0_consumers,
|
||||
};
|
||||
|
||||
static struct gpio vccq_sdhi0_gpios[] = {
|
||||
{GPIO_PORT17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
|
||||
};
|
||||
|
||||
static struct gpio_regulator_state vccq_sdhi0_states[] = {
|
||||
{ .value = 3300000, .gpios = (0 << 0) },
|
||||
{ .value = 1800000, .gpios = (1 << 0) },
|
||||
};
|
||||
|
||||
static struct gpio_regulator_config vccq_sdhi0_info = {
|
||||
.supply_name = "vqmmc",
|
||||
|
||||
.enable_gpio = GPIO_PORT74,
|
||||
.enable_high = 1,
|
||||
.enabled_at_boot = 0,
|
||||
|
||||
.gpios = vccq_sdhi0_gpios,
|
||||
.nr_gpios = ARRAY_SIZE(vccq_sdhi0_gpios),
|
||||
|
||||
.states = vccq_sdhi0_states,
|
||||
.nr_states = ARRAY_SIZE(vccq_sdhi0_states),
|
||||
|
||||
.type = REGULATOR_VOLTAGE,
|
||||
.init_data = &vccq_sdhi0_init_data,
|
||||
};
|
||||
|
||||
static struct platform_device vccq_sdhi0 = {
|
||||
.name = "gpio-regulator",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &vccq_sdhi0_info,
|
||||
},
|
||||
};
|
||||
|
||||
/* Fixed 3.3V regulator to be used by SDHI1 */
|
||||
static struct regulator_consumer_supply vcc_sdhi1_consumers[] = {
|
||||
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data vcc_sdhi1_init_data = {
|
||||
.constraints = {
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(vcc_sdhi1_consumers),
|
||||
.consumer_supplies = vcc_sdhi1_consumers,
|
||||
};
|
||||
|
||||
static struct fixed_voltage_config vcc_sdhi1_info = {
|
||||
.supply_name = "SDHI1 Vcc",
|
||||
.microvolts = 3300000,
|
||||
.gpio = GPIO_PORT16,
|
||||
.enable_high = 1,
|
||||
.init_data = &vcc_sdhi1_init_data,
|
||||
};
|
||||
|
||||
static struct platform_device vcc_sdhi1 = {
|
||||
.name = "reg-fixed-voltage",
|
||||
.id = 2,
|
||||
.dev = {
|
||||
.platform_data = &vcc_sdhi1_info,
|
||||
},
|
||||
};
|
||||
|
||||
/* SDHI0 */
|
||||
/*
|
||||
* FIXME
|
||||
|
|
@ -574,14 +681,14 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] =
|
|||
* We can use IRQ31 as card detect irq,
|
||||
* but it needs chattering removal operation
|
||||
*/
|
||||
#define IRQ31 evt2irq(0x33E0)
|
||||
#define IRQ31 irq_pin(31)
|
||||
static struct sh_mobile_sdhi_info sdhi0_info = {
|
||||
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
|
||||
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
|
||||
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |\
|
||||
MMC_CAP_NEEDS_POLL,
|
||||
.tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
|
||||
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
|
||||
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
|
||||
MMC_CAP_POWER_OFF_CARD,
|
||||
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
|
||||
.cd_gpio = GPIO_PORT167,
|
||||
};
|
||||
|
||||
static struct resource sdhi0_resources[] = {
|
||||
|
|
@ -596,12 +703,12 @@ static struct resource sdhi0_resources[] = {
|
|||
*/
|
||||
{
|
||||
.name = SH_MOBILE_SDHI_IRQ_SDCARD,
|
||||
.start = evt2irq(0x0E20),
|
||||
.start = gic_spi(118),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.name = SH_MOBILE_SDHI_IRQ_SDIO,
|
||||
.start = evt2irq(0x0E40),
|
||||
.start = gic_spi(119),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -620,9 +727,11 @@ static struct platform_device sdhi0_device = {
|
|||
static struct sh_mobile_sdhi_info sdhi1_info = {
|
||||
.dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
|
||||
.dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
|
||||
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
|
||||
.tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
|
||||
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
|
||||
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
|
||||
MMC_CAP_POWER_OFF_CARD,
|
||||
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
|
||||
/* Port72 cannot generate IRQs, will be used in polling mode. */
|
||||
.cd_gpio = GPIO_PORT72,
|
||||
};
|
||||
|
||||
static struct resource sdhi1_resources[] = {
|
||||
|
|
@ -633,15 +742,15 @@ static struct resource sdhi1_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = evt2irq(0x0E80),
|
||||
.start = gic_spi(121),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
.start = evt2irq(0x0EA0),
|
||||
.start = gic_spi(122),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
.start = evt2irq(0x0EC0),
|
||||
.start = gic_spi(123),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -656,10 +765,20 @@ static struct platform_device sdhi1_device = {
|
|||
.resource = sdhi1_resources,
|
||||
};
|
||||
|
||||
static const struct pinctrl_map eva_sdhi1_pinctrl_map[] = {
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
|
||||
"sdhi1_data4", "sdhi1"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
|
||||
"sdhi1_ctrl", "sdhi1"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
|
||||
"sdhi1_cd", "sdhi1"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
|
||||
"sdhi1_wp", "sdhi1"),
|
||||
};
|
||||
|
||||
/* MMCIF */
|
||||
static struct sh_mmcif_plat_data sh_mmcif_plat = {
|
||||
.sup_pclk = 0,
|
||||
.ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
|
||||
.caps = MMC_CAP_4_BIT_DATA |
|
||||
MMC_CAP_8_BIT_DATA |
|
||||
MMC_CAP_NONREMOVABLE,
|
||||
|
|
@ -674,12 +793,12 @@ static struct resource sh_mmcif_resources[] = {
|
|||
},
|
||||
[1] = {
|
||||
/* MMC ERR */
|
||||
.start = evt2irq(0x1AC0),
|
||||
.start = gic_spi(56),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
/* MMC NOR */
|
||||
.start = evt2irq(0x1AE0),
|
||||
.start = gic_spi(57),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -708,9 +827,9 @@ static int mt9t111_power(struct device *dev, int mode)
|
|||
/* video1 (= CON1 camera) expect 24MHz */
|
||||
clk_set_rate(mclk, clk_round_rate(mclk, 24000000));
|
||||
clk_enable(mclk);
|
||||
gpio_set_value(GPIO_PORT158, 1);
|
||||
gpio_set_value(158, 1);
|
||||
} else {
|
||||
gpio_set_value(GPIO_PORT158, 0);
|
||||
gpio_set_value(158, 0);
|
||||
clk_disable(mclk);
|
||||
}
|
||||
|
||||
|
|
@ -756,7 +875,7 @@ static struct resource ceu0_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = intcs_evt2irq(0x0500),
|
||||
.start = gic_spi(160),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
|
|
@ -798,7 +917,7 @@ static struct resource fsi_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = evt2irq(0x1840),
|
||||
.start = gic_spi(9),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -864,8 +983,8 @@ static struct platform_device fsi_hdmi_device = {
|
|||
|
||||
/* RTC: RTC connects i2c-gpio. */
|
||||
static struct i2c_gpio_platform_data i2c_gpio_data = {
|
||||
.sda_pin = GPIO_PORT208,
|
||||
.scl_pin = GPIO_PORT91,
|
||||
.sda_pin = 208,
|
||||
.scl_pin = 91,
|
||||
.udelay = 5, /* 100 kHz */
|
||||
};
|
||||
|
||||
|
|
@ -881,7 +1000,7 @@ static struct platform_device i2c_gpio_device = {
|
|||
static struct i2c_board_info i2c0_devices[] = {
|
||||
{
|
||||
I2C_BOARD_INFO("st1232-ts", 0x55),
|
||||
.irq = evt2irq(0x0340),
|
||||
.irq = irq_pin(10),
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("wm8978", 0x1a),
|
||||
|
|
@ -902,6 +1021,8 @@ static struct platform_device *eva_devices[] __initdata = {
|
|||
&lcdc0_device,
|
||||
&gpio_keys_device,
|
||||
&sh_eth_device,
|
||||
&vcc_sdhi0,
|
||||
&vccq_sdhi0,
|
||||
&sdhi0_device,
|
||||
&sh_mmcif_device,
|
||||
&hdmi_device,
|
||||
|
|
@ -914,6 +1035,28 @@ static struct platform_device *eva_devices[] __initdata = {
|
|||
&i2c_gpio_device,
|
||||
};
|
||||
|
||||
static const struct pinctrl_map eva_pinctrl_map[] = {
|
||||
/* LCD0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
|
||||
"lcd0_data24_0", "lcd0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
|
||||
"lcd0_lclk_1", "lcd0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
|
||||
"lcd0_sync", "lcd0"),
|
||||
/* MMCIF */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
|
||||
"mmc0_data8_1", "mmc0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
|
||||
"mmc0_ctrl_1", "mmc0"),
|
||||
/* SDHI0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
|
||||
"sdhi0_data4", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
|
||||
"sdhi0_ctrl", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
|
||||
"sdhi0_wp", "sdhi0"),
|
||||
};
|
||||
|
||||
static void __init eva_clock_init(void)
|
||||
{
|
||||
struct clk *system = clk_get(NULL, "system_clk");
|
||||
|
|
@ -961,6 +1104,8 @@ static void __init eva_init(void)
|
|||
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
|
||||
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
|
||||
|
||||
pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
|
||||
|
||||
r8a7740_pinmux_init();
|
||||
r8a7740_meram_workaround();
|
||||
|
||||
|
|
@ -970,42 +1115,13 @@ static void __init eva_init(void)
|
|||
|
||||
/* LCDC0 */
|
||||
gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D0, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D1, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D2, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D3, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D4, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D5, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D6, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D7, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D8, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D9, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D10, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D11, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D12, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D13, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D14, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D15, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D16, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D17, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D18_PORT40, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D19_PORT4, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D20_PORT3, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D21_PORT2, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D22_PORT0, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D23_PORT1, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_DCK, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_VSYN, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_HSYN, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_DISP, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
|
||||
|
||||
gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
|
||||
gpio_request_one(GPIO_PORT202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
|
||||
gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
|
||||
gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
|
||||
|
||||
/* Touchscreen */
|
||||
gpio_request(GPIO_FN_IRQ10, NULL); /* TP_INT */
|
||||
gpio_request_one(GPIO_PORT166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
|
||||
gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
|
||||
|
||||
/* GETHER */
|
||||
gpio_request(GPIO_FN_ET_CRS, NULL);
|
||||
|
|
@ -1028,12 +1144,12 @@ static void __init eva_init(void)
|
|||
gpio_request(GPIO_FN_ET_RX_DV, NULL);
|
||||
gpio_request(GPIO_FN_ET_RX_CLK, NULL);
|
||||
|
||||
gpio_request_one(GPIO_PORT18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
|
||||
gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
|
||||
|
||||
/* USB */
|
||||
gpio_request_one(GPIO_PORT159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */
|
||||
gpio_request_one(159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */
|
||||
|
||||
if (gpio_get_value(GPIO_PORT159)) {
|
||||
if (gpio_get_value(159)) {
|
||||
/* USB Host */
|
||||
} else {
|
||||
/* USB Func */
|
||||
|
|
@ -1042,47 +1158,15 @@ static void __init eva_init(void)
|
|||
* OTOH, usbhs interrupt needs its value (HI/LOW) to decide
|
||||
* USB connection/disconnection (usbhsf_get_vbus()).
|
||||
* This means we needs to select GPIO_FN_IRQ7_PORT209 first,
|
||||
* and select GPIO_PORT209 here
|
||||
* and select GPIO 209 here
|
||||
*/
|
||||
gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
|
||||
gpio_request_one(GPIO_PORT209, GPIOF_IN, NULL);
|
||||
gpio_request_one(209, GPIOF_IN, NULL);
|
||||
|
||||
platform_device_register(&usbhsf_device);
|
||||
usb = &usbhsf_device;
|
||||
}
|
||||
|
||||
/* SDHI0 */
|
||||
gpio_request(GPIO_FN_SDHI0_CMD, NULL);
|
||||
gpio_request(GPIO_FN_SDHI0_CLK, NULL);
|
||||
gpio_request(GPIO_FN_SDHI0_D0, NULL);
|
||||
gpio_request(GPIO_FN_SDHI0_D1, NULL);
|
||||
gpio_request(GPIO_FN_SDHI0_D2, NULL);
|
||||
gpio_request(GPIO_FN_SDHI0_D3, NULL);
|
||||
gpio_request(GPIO_FN_SDHI0_WP, NULL);
|
||||
|
||||
gpio_request_one(GPIO_PORT17, GPIOF_OUT_INIT_LOW, NULL); /* SDHI0_18/33_B */
|
||||
gpio_request_one(GPIO_PORT74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */
|
||||
gpio_request_one(GPIO_PORT75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */
|
||||
|
||||
/* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */
|
||||
|
||||
/*
|
||||
* MMCIF
|
||||
*
|
||||
* Here doesn't care SW1.4 status,
|
||||
* since CON2 is not mounted.
|
||||
*/
|
||||
gpio_request(GPIO_FN_MMC1_CLK_PORT103, NULL);
|
||||
gpio_request(GPIO_FN_MMC1_CMD_PORT104, NULL);
|
||||
gpio_request(GPIO_FN_MMC1_D0_PORT149, NULL);
|
||||
gpio_request(GPIO_FN_MMC1_D1_PORT148, NULL);
|
||||
gpio_request(GPIO_FN_MMC1_D2_PORT147, NULL);
|
||||
gpio_request(GPIO_FN_MMC1_D3_PORT146, NULL);
|
||||
gpio_request(GPIO_FN_MMC1_D4_PORT145, NULL);
|
||||
gpio_request(GPIO_FN_MMC1_D5_PORT144, NULL);
|
||||
gpio_request(GPIO_FN_MMC1_D6_PORT143, NULL);
|
||||
gpio_request(GPIO_FN_MMC1_D7_PORT142, NULL);
|
||||
|
||||
/* CEU0 */
|
||||
gpio_request(GPIO_FN_VIO0_D7, NULL);
|
||||
gpio_request(GPIO_FN_VIO0_D6, NULL);
|
||||
|
|
@ -1099,10 +1183,10 @@ static void __init eva_init(void)
|
|||
gpio_request(GPIO_FN_VIO_CKO, NULL);
|
||||
|
||||
/* CON1/CON15 Camera */
|
||||
gpio_request_one(GPIO_PORT173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */
|
||||
gpio_request_one(GPIO_PORT172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
|
||||
gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */
|
||||
gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
|
||||
/* see mt9t111_power() */
|
||||
gpio_request_one(GPIO_PORT158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */
|
||||
gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */
|
||||
|
||||
/* FSI-WM8978 */
|
||||
gpio_request(GPIO_FN_FSIAIBT, NULL);
|
||||
|
|
@ -1111,8 +1195,8 @@ static void __init eva_init(void)
|
|||
gpio_request(GPIO_FN_FSIAOSLD, NULL);
|
||||
gpio_request(GPIO_FN_FSIAISLD_PORT5, NULL);
|
||||
|
||||
gpio_request(GPIO_PORT7, NULL);
|
||||
gpio_request(GPIO_PORT8, NULL);
|
||||
gpio_request(7, NULL);
|
||||
gpio_request(8, NULL);
|
||||
gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
|
||||
gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
|
||||
|
||||
|
|
@ -1129,29 +1213,21 @@ static void __init eva_init(void)
|
|||
* DBGMD/LCDC0/FSIA MUX
|
||||
* DBGMD_SELECT_B should be set after setting PFC Function.
|
||||
*/
|
||||
gpio_request_one(GPIO_PORT176, GPIOF_OUT_INIT_HIGH, NULL);
|
||||
gpio_request_one(176, GPIOF_OUT_INIT_HIGH, NULL);
|
||||
|
||||
/*
|
||||
* We can switch CON8/CON14 by SW1.5,
|
||||
* but it needs after DBGMD_SELECT_B
|
||||
*/
|
||||
gpio_request_one(GPIO_PORT6, GPIOF_IN, NULL);
|
||||
if (gpio_get_value(GPIO_PORT6)) {
|
||||
gpio_request_one(6, GPIOF_IN, NULL);
|
||||
if (gpio_get_value(6)) {
|
||||
/* CON14 enable */
|
||||
} else {
|
||||
/* CON8 (SDHI1) enable */
|
||||
gpio_request(GPIO_FN_SDHI1_CLK, NULL);
|
||||
gpio_request(GPIO_FN_SDHI1_CMD, NULL);
|
||||
gpio_request(GPIO_FN_SDHI1_D0, NULL);
|
||||
gpio_request(GPIO_FN_SDHI1_D1, NULL);
|
||||
gpio_request(GPIO_FN_SDHI1_D2, NULL);
|
||||
gpio_request(GPIO_FN_SDHI1_D3, NULL);
|
||||
gpio_request(GPIO_FN_SDHI1_CD, NULL);
|
||||
gpio_request(GPIO_FN_SDHI1_WP, NULL);
|
||||
|
||||
/* SDSLOT2_PON */
|
||||
gpio_request_one(GPIO_PORT16, GPIOF_OUT_INIT_HIGH, NULL);
|
||||
pinctrl_register_mappings(eva_sdhi1_pinctrl_map,
|
||||
ARRAY_SIZE(eva_sdhi1_pinctrl_map));
|
||||
|
||||
platform_device_register(&vcc_sdhi1);
|
||||
platform_device_register(&sdhi1_device);
|
||||
}
|
||||
|
||||
|
|
@ -1207,7 +1283,6 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva")
|
|||
.map_io = r8a7740_map_io,
|
||||
.init_early = eva_add_early_devices,
|
||||
.init_irq = r8a7740_init_irq,
|
||||
.handle_irq = shmobile_handle_irq_intc,
|
||||
.init_machine = eva_init,
|
||||
.init_late = shmobile_init_late,
|
||||
.init_time = eva_earlytimer_init,
|
||||
|
|
|
|||
43
arch/arm/mach-shmobile/board-bockw.c
Normal file
43
arch/arm/mach-shmobile/board-bockw.c
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Bock-W board support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/r8a7778.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
static void __init bockw_init(void)
|
||||
{
|
||||
r8a7778_clock_init();
|
||||
r8a7778_add_standard_devices();
|
||||
}
|
||||
|
||||
static const char *bockw_boards_compat_dt[] __initdata = {
|
||||
"renesas,bockw",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(BOCKW_DT, "bockw")
|
||||
.init_early = r8a7778_init_delay,
|
||||
.init_irq = r8a7778_init_irq_dt,
|
||||
.init_machine = bockw_init,
|
||||
.init_time = shmobile_timer_init,
|
||||
.dt_compat = bockw_boards_compat_dt,
|
||||
MACHINE_END
|
||||
|
|
@ -24,6 +24,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
|
|
@ -288,6 +289,16 @@ static struct platform_device lcdc0_device = {
|
|||
},
|
||||
};
|
||||
|
||||
static const struct pinctrl_map lcdc0_pinctrl_map[] = {
|
||||
/* LCD0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
|
||||
"lcd0_data24_1", "lcd0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
|
||||
"lcd0_lclk_1", "lcd0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
|
||||
"lcd0_sync", "lcd0"),
|
||||
};
|
||||
|
||||
/*
|
||||
* SMSC 9221
|
||||
*/
|
||||
|
|
@ -392,8 +403,8 @@ static void __init bonito_init(void)
|
|||
/*
|
||||
* base board settings
|
||||
*/
|
||||
gpio_request_one(GPIO_PORT176, GPIOF_IN, NULL);
|
||||
if (!gpio_get_value(GPIO_PORT176)) {
|
||||
gpio_request_one(176, GPIOF_IN, NULL);
|
||||
if (!gpio_get_value(176)) {
|
||||
u16 bsw2;
|
||||
u16 bsw3;
|
||||
u16 bsw4;
|
||||
|
|
@ -430,38 +441,11 @@ static void __init bonito_init(void)
|
|||
*/
|
||||
if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
|
||||
BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
|
||||
gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D0, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D1, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D2, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D3, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D4, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D5, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D6, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D7, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D8, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D9, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D10, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D11, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D12, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D13, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D14, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D15, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D16, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D17, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_DCK, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_VSYN, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_HSYN, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_DISP, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
|
||||
pinctrl_register_mappings(lcdc0_pinctrl_map,
|
||||
ARRAY_SIZE(lcdc0_pinctrl_map));
|
||||
gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
|
||||
|
||||
gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH,
|
||||
gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
|
||||
NULL); /* LCDDON */
|
||||
|
||||
/* backlight on */
|
||||
|
|
|
|||
|
|
@ -24,6 +24,8 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
|
|
@ -135,17 +137,17 @@ static struct platform_device keysc_device = {
|
|||
#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
|
||||
|
||||
static struct gpio_keys_button gpio_buttons[] = {
|
||||
GPIO_KEY(KEY_VOLUMEUP, GPIO_PORT56, "+"), /* S2: VOL+ [IRQ9] */
|
||||
GPIO_KEY(KEY_VOLUMEDOWN, GPIO_PORT54, "-"), /* S3: VOL- [IRQ10] */
|
||||
GPIO_KEY(KEY_MENU, GPIO_PORT27, "Menu"), /* S4: MENU [IRQ30] */
|
||||
GPIO_KEY(KEY_HOMEPAGE, GPIO_PORT26, "Home"), /* S5: HOME [IRQ31] */
|
||||
GPIO_KEY(KEY_BACK, GPIO_PORT11, "Back"), /* S6: BACK [IRQ0] */
|
||||
GPIO_KEY(KEY_PHONE, GPIO_PORT238, "Tel"), /* S7: TEL [IRQ11] */
|
||||
GPIO_KEY(KEY_POWER, GPIO_PORT239, "C1"), /* S8: CAM [IRQ13] */
|
||||
GPIO_KEY(KEY_MAIL, GPIO_PORT224, "Mail"), /* S9: MAIL [IRQ3] */
|
||||
/* Omitted button "C3?": GPIO_PORT223 - S10: CUST [IRQ8] */
|
||||
GPIO_KEY(KEY_CAMERA, GPIO_PORT164, "C2"), /* S11: CAM_HALF [IRQ25] */
|
||||
/* Omitted button "?": GPIO_PORT152 - S12: CAM_FULL [No IRQ] */
|
||||
GPIO_KEY(KEY_VOLUMEUP, 56, "+"), /* S2: VOL+ [IRQ9] */
|
||||
GPIO_KEY(KEY_VOLUMEDOWN, 54, "-"), /* S3: VOL- [IRQ10] */
|
||||
GPIO_KEY(KEY_MENU, 27, "Menu"), /* S4: MENU [IRQ30] */
|
||||
GPIO_KEY(KEY_HOMEPAGE, 26, "Home"), /* S5: HOME [IRQ31] */
|
||||
GPIO_KEY(KEY_BACK, 11, "Back"), /* S6: BACK [IRQ0] */
|
||||
GPIO_KEY(KEY_PHONE, 238, "Tel"), /* S7: TEL [IRQ11] */
|
||||
GPIO_KEY(KEY_POWER, 239, "C1"), /* S8: CAM [IRQ13] */
|
||||
GPIO_KEY(KEY_MAIL, 224, "Mail"), /* S9: MAIL [IRQ3] */
|
||||
/* Omitted button "C3?": 223 - S10: CUST [IRQ8] */
|
||||
GPIO_KEY(KEY_CAMERA, 164, "C2"), /* S11: CAM_HALF [IRQ25] */
|
||||
/* Omitted button "?": 152 - S12: CAM_FULL [No IRQ] */
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data gpio_key_info = {
|
||||
|
|
@ -165,9 +167,9 @@ static struct platform_device gpio_keys_device = {
|
|||
#define GPIO_LED(n, g) { .name = n, .gpio = g }
|
||||
|
||||
static struct gpio_led gpio_leds[] = {
|
||||
GPIO_LED("G", GPIO_PORT20), /* PORT20 [GPO0] -> LED7 -> "G" */
|
||||
GPIO_LED("H", GPIO_PORT21), /* PORT21 [GPO1] -> LED8 -> "H" */
|
||||
GPIO_LED("J", GPIO_PORT22), /* PORT22 [GPO2] -> LED9 -> "J" */
|
||||
GPIO_LED("G", 20), /* PORT20 [GPO0] -> LED7 -> "G" */
|
||||
GPIO_LED("H", 21), /* PORT21 [GPO1] -> LED8 -> "H" */
|
||||
GPIO_LED("J", 22), /* PORT22 [GPO2] -> LED9 -> "J" */
|
||||
};
|
||||
|
||||
static struct gpio_led_platform_data gpio_leds_info = {
|
||||
|
|
@ -187,7 +189,7 @@ static struct platform_device gpio_leds_device = {
|
|||
static struct led_renesas_tpu_config led_renesas_tpu12_pdata = {
|
||||
.name = "V2513",
|
||||
.pin_gpio_fn = GPIO_FN_TPU1TO2,
|
||||
.pin_gpio = GPIO_PORT153,
|
||||
.pin_gpio = 153,
|
||||
.channel_offset = 0x90,
|
||||
.timer_bit = 2,
|
||||
.max_brightness = 1000,
|
||||
|
|
@ -215,7 +217,7 @@ static struct platform_device leds_tpu12_device = {
|
|||
static struct led_renesas_tpu_config led_renesas_tpu41_pdata = {
|
||||
.name = "V2514",
|
||||
.pin_gpio_fn = GPIO_FN_TPU4TO1,
|
||||
.pin_gpio = GPIO_PORT199,
|
||||
.pin_gpio = 199,
|
||||
.channel_offset = 0x50,
|
||||
.timer_bit = 1,
|
||||
.max_brightness = 1000,
|
||||
|
|
@ -243,7 +245,7 @@ static struct platform_device leds_tpu41_device = {
|
|||
static struct led_renesas_tpu_config led_renesas_tpu21_pdata = {
|
||||
.name = "V2515",
|
||||
.pin_gpio_fn = GPIO_FN_TPU2TO1,
|
||||
.pin_gpio = GPIO_PORT197,
|
||||
.pin_gpio = 197,
|
||||
.channel_offset = 0x50,
|
||||
.timer_bit = 1,
|
||||
.max_brightness = 1000,
|
||||
|
|
@ -271,7 +273,7 @@ static struct platform_device leds_tpu21_device = {
|
|||
static struct led_renesas_tpu_config led_renesas_tpu30_pdata = {
|
||||
.name = "KEYLED",
|
||||
.pin_gpio_fn = GPIO_FN_TPU3TO0,
|
||||
.pin_gpio = GPIO_PORT163,
|
||||
.pin_gpio = 163,
|
||||
.channel_offset = 0x10,
|
||||
.timer_bit = 0,
|
||||
.max_brightness = 1000,
|
||||
|
|
@ -433,6 +435,85 @@ static struct platform_device *kota2_devices[] __initdata = {
|
|||
&sdhi1_device,
|
||||
};
|
||||
|
||||
static unsigned long pin_pullup_conf[] = {
|
||||
PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
|
||||
};
|
||||
|
||||
static const struct pinctrl_map kota2_pinctrl_map[] = {
|
||||
/* KEYSC */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
|
||||
"keysc_in8", "keysc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
|
||||
"keysc_out04", "keysc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
|
||||
"keysc_out5", "keysc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
|
||||
"keysc_out6_0", "keysc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
|
||||
"keysc_out7_0", "keysc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
|
||||
"keysc_out8_0", "keysc"),
|
||||
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
|
||||
"keysc_in8", pin_pullup_conf),
|
||||
/* MMCIF */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
|
||||
"mmc0_data8_0", "mmc0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
|
||||
"mmc0_ctrl_0", "mmc0"),
|
||||
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
|
||||
"PORT279", pin_pullup_conf),
|
||||
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
|
||||
"mmc0_data8_0", pin_pullup_conf),
|
||||
/* SCIFA2 (UART2) */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
|
||||
"scifa2_data_0", "scifa2"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
|
||||
"scifa2_ctrl_0", "scifa2"),
|
||||
/* SCIFA4 (UART1) */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
|
||||
"scifa4_data", "scifa4"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
|
||||
"scifa4_ctrl", "scifa4"),
|
||||
/* SCIFB (BT) */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
|
||||
"scifb_data_0", "scifb"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
|
||||
"scifb_clk_0", "scifb"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
|
||||
"scifb_ctrl_0", "scifb"),
|
||||
/* SDHI0 (microSD) */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
|
||||
"sdhi0_data4", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
|
||||
"sdhi0_ctrl", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
|
||||
"sdhi0_cd", "sdhi0"),
|
||||
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
|
||||
"sdhi0_data4", pin_pullup_conf),
|
||||
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
|
||||
"PORT256", pin_pullup_conf),
|
||||
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
|
||||
"PORT251", pin_pullup_conf),
|
||||
/* SDHI1 (BCM4330) */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
|
||||
"sdhi1_data4", "sdhi1"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
|
||||
"sdhi1_ctrl", "sdhi1"),
|
||||
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
|
||||
"sdhi1_data4", pin_pullup_conf),
|
||||
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
|
||||
"PORT263", pin_pullup_conf),
|
||||
/* SMSC911X */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
|
||||
"bsc_data_0_7", "bsc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
|
||||
"bsc_data_8_15", "bsc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
|
||||
"bsc_cs5_a", "bsc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
|
||||
"bsc_we0", "bsc"),
|
||||
};
|
||||
|
||||
static void __init kota2_init(void)
|
||||
{
|
||||
regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
|
||||
|
|
@ -441,97 +522,16 @@ static void __init kota2_init(void)
|
|||
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
|
||||
regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
|
||||
|
||||
pinctrl_register_mappings(kota2_pinctrl_map,
|
||||
ARRAY_SIZE(kota2_pinctrl_map));
|
||||
sh73a0_pinmux_init();
|
||||
|
||||
/* SCIFA2 (UART2) */
|
||||
gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
|
||||
|
||||
/* SCIFA4 (UART1) */
|
||||
gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
|
||||
|
||||
/* SMSC911X */
|
||||
gpio_request(GPIO_FN_D0_NAF0, NULL);
|
||||
gpio_request(GPIO_FN_D1_NAF1, NULL);
|
||||
gpio_request(GPIO_FN_D2_NAF2, NULL);
|
||||
gpio_request(GPIO_FN_D3_NAF3, NULL);
|
||||
gpio_request(GPIO_FN_D4_NAF4, NULL);
|
||||
gpio_request(GPIO_FN_D5_NAF5, NULL);
|
||||
gpio_request(GPIO_FN_D6_NAF6, NULL);
|
||||
gpio_request(GPIO_FN_D7_NAF7, NULL);
|
||||
gpio_request(GPIO_FN_D8_NAF8, NULL);
|
||||
gpio_request(GPIO_FN_D9_NAF9, NULL);
|
||||
gpio_request(GPIO_FN_D10_NAF10, NULL);
|
||||
gpio_request(GPIO_FN_D11_NAF11, NULL);
|
||||
gpio_request(GPIO_FN_D12_NAF12, NULL);
|
||||
gpio_request(GPIO_FN_D13_NAF13, NULL);
|
||||
gpio_request(GPIO_FN_D14_NAF14, NULL);
|
||||
gpio_request(GPIO_FN_D15_NAF15, NULL);
|
||||
gpio_request(GPIO_FN_CS5A_, NULL);
|
||||
gpio_request(GPIO_FN_WE0__FWE, NULL);
|
||||
gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */
|
||||
gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
|
||||
|
||||
/* KEYSC */
|
||||
gpio_request(GPIO_FN_KEYIN0_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN1_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN2_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN3_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN4_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN5_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN6_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYIN7_PU, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT0, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT1, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT2, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT3, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT4, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT5, NULL);
|
||||
gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
|
||||
gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
|
||||
gpio_request(GPIO_FN_KEYOUT8, NULL);
|
||||
gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
|
||||
gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
|
||||
|
||||
/* MMCIF */
|
||||
gpio_request(GPIO_FN_MMCCLK0, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_0, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_1, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_2, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_3, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_4, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_5, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_6, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_7, NULL);
|
||||
gpio_request(GPIO_FN_MMCCMD0, NULL);
|
||||
gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
|
||||
|
||||
/* SDHI0 (microSD) */
|
||||
gpio_request(GPIO_FN_SDHICD0_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHICMD0_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHICLK0, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_3_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_2_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_1_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_0_PU, NULL);
|
||||
|
||||
/* SCIFB (BT) */
|
||||
gpio_request(GPIO_FN_PORT159_SCIFB_SCK, NULL);
|
||||
gpio_request(GPIO_FN_PORT160_SCIFB_TXD, NULL);
|
||||
gpio_request(GPIO_FN_PORT161_SCIFB_CTS_, NULL);
|
||||
gpio_request(GPIO_FN_PORT162_SCIFB_RXD, NULL);
|
||||
gpio_request(GPIO_FN_PORT163_SCIFB_RTS_, NULL);
|
||||
|
||||
/* SDHI1 (BCM4330) */
|
||||
gpio_request(GPIO_FN_SDHICLK1, NULL);
|
||||
gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
|
||||
gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
/* Early BRESP enable, Shared attribute override enable, 64K*8way */
|
||||
|
|
|
|||
107
arch/arm/mach-shmobile/board-kzm9g-reference.c
Normal file
107
arch/arm/mach-shmobile/board-kzm9g-reference.c
Normal file
|
|
@ -0,0 +1,107 @@
|
|||
/*
|
||||
* KZM-A9-GT board support - Reference Device Tree Implementation
|
||||
*
|
||||
* Copyright (C) 2012 Horms Solutions Ltd.
|
||||
*
|
||||
* Based on board-kzm9g.c
|
||||
* Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
#include <mach/sh73a0.h>
|
||||
#include <mach/common.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
static unsigned long pin_pullup_conf[] = {
|
||||
PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
|
||||
};
|
||||
|
||||
static const struct pinctrl_map kzm_pinctrl_map[] = {
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("e6826000.i2c", "pfc-sh73a0",
|
||||
"i2c3_1", "i2c3"),
|
||||
/* MMCIF */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
|
||||
"mmc0_data8_0", "mmc0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
|
||||
"mmc0_ctrl_0", "mmc0"),
|
||||
PIN_MAP_CONFIGS_PIN_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
|
||||
"PORT279", pin_pullup_conf),
|
||||
PIN_MAP_CONFIGS_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
|
||||
"mmc0_data8_0", pin_pullup_conf),
|
||||
/* SCIFA4 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
|
||||
"scifa4_data", "scifa4"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
|
||||
"scifa4_ctrl", "scifa4"),
|
||||
/* SDHI0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
|
||||
"sdhi0_data4", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
|
||||
"sdhi0_ctrl", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
|
||||
"sdhi0_cd", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
|
||||
"sdhi0_wp", "sdhi0"),
|
||||
/* SDHI2 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0",
|
||||
"sdhi2_data4", "sdhi2"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0",
|
||||
"sdhi2_ctrl", "sdhi2"),
|
||||
};
|
||||
|
||||
static void __init kzm_init(void)
|
||||
{
|
||||
sh73a0_add_standard_devices_dt();
|
||||
pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
|
||||
sh73a0_pinmux_init();
|
||||
|
||||
/* enable SD */
|
||||
gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
|
||||
gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
|
||||
|
||||
gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
/* Early BRESP enable, Shared attribute override enable, 64K*8way */
|
||||
l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
|
||||
#endif
|
||||
}
|
||||
|
||||
static const char *kzm9g_boards_compat_dt[] __initdata = {
|
||||
"renesas,kzm9g-reference",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
|
||||
.smp = smp_ops(sh73a0_smp_ops),
|
||||
.map_io = sh73a0_map_io,
|
||||
.init_early = sh73a0_init_delay,
|
||||
.nr_irqs = NR_IRQS_LEGACY,
|
||||
.init_irq = irqchip_init,
|
||||
.init_machine = kzm_init,
|
||||
.init_time = shmobile_timer_init,
|
||||
.dt_compat = kzm9g_boards_compat_dt,
|
||||
MACHINE_END
|
||||
|
|
@ -30,6 +30,8 @@
|
|||
#include <linux/mmc/sh_mmcif.h>
|
||||
#include <linux/mmc/sh_mobile_sdhi.h>
|
||||
#include <linux/mfd/tmio.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
|
|
@ -61,8 +63,8 @@
|
|||
|
||||
/* Dummy supplies, where voltage doesn't matter */
|
||||
static struct regulator_consumer_supply dummy_supplies[] = {
|
||||
REGULATOR_SUPPLY("vddvario", "smsc911x"),
|
||||
REGULATOR_SUPPLY("vdd33a", "smsc911x"),
|
||||
REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
|
||||
REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -81,7 +83,7 @@ static struct resource smsc9221_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = intcs_evt2irq(0x260), /* IRQ3 */
|
||||
.start = irq_pin(3), /* IRQ3 */
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -115,7 +117,7 @@ static struct resource usb_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = intcs_evt2irq(0x220), /* IRQ1 */
|
||||
.start = irq_pin(1), /* IRQ1 */
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -138,7 +140,7 @@ struct usbhs_private {
|
|||
struct renesas_usbhs_platform_info info;
|
||||
};
|
||||
|
||||
#define IRQ15 intcs_evt2irq(0x03e0)
|
||||
#define IRQ15 irq_pin(15)
|
||||
#define USB_PHY_MODE (1 << 4)
|
||||
#define USB_PHY_INT_EN ((1 << 3) | (1 << 2))
|
||||
#define USB_PHY_ON (1 << 1)
|
||||
|
|
@ -373,13 +375,64 @@ static struct platform_device mmc_device = {
|
|||
.resource = sh_mmcif_resources,
|
||||
};
|
||||
|
||||
/* Fixed 2.8V regulators to be used by SDHI0 and SDHI2 */
|
||||
static struct regulator_consumer_supply fixed2v8_power_consumers[] =
|
||||
/* Fixed 3.3V regulators to be used by SDHI0 */
|
||||
static struct regulator_consumer_supply vcc_sdhi0_consumers[] =
|
||||
{
|
||||
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
|
||||
REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data vcc_sdhi0_init_data = {
|
||||
.constraints = {
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(vcc_sdhi0_consumers),
|
||||
.consumer_supplies = vcc_sdhi0_consumers,
|
||||
};
|
||||
|
||||
static struct fixed_voltage_config vcc_sdhi0_info = {
|
||||
.supply_name = "SDHI0 Vcc",
|
||||
.microvolts = 3300000,
|
||||
.gpio = 15,
|
||||
.enable_high = 1,
|
||||
.init_data = &vcc_sdhi0_init_data,
|
||||
};
|
||||
|
||||
static struct platform_device vcc_sdhi0 = {
|
||||
.name = "reg-fixed-voltage",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &vcc_sdhi0_info,
|
||||
},
|
||||
};
|
||||
|
||||
/* Fixed 3.3V regulators to be used by SDHI2 */
|
||||
static struct regulator_consumer_supply vcc_sdhi2_consumers[] =
|
||||
{
|
||||
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.2"),
|
||||
REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.2"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data vcc_sdhi2_init_data = {
|
||||
.constraints = {
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(vcc_sdhi2_consumers),
|
||||
.consumer_supplies = vcc_sdhi2_consumers,
|
||||
};
|
||||
|
||||
static struct fixed_voltage_config vcc_sdhi2_info = {
|
||||
.supply_name = "SDHI2 Vcc",
|
||||
.microvolts = 3300000,
|
||||
.gpio = 14,
|
||||
.enable_high = 1,
|
||||
.init_data = &vcc_sdhi2_init_data,
|
||||
};
|
||||
|
||||
static struct platform_device vcc_sdhi2 = {
|
||||
.name = "reg-fixed-voltage",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &vcc_sdhi2_info,
|
||||
},
|
||||
};
|
||||
|
||||
/* SDHI */
|
||||
|
|
@ -387,8 +440,8 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
|
|||
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
|
||||
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
|
||||
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
|
||||
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
|
||||
.tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
|
||||
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
|
||||
MMC_CAP_POWER_OFF_CARD,
|
||||
};
|
||||
|
||||
static struct resource sdhi0_resources[] = {
|
||||
|
|
@ -431,9 +484,8 @@ static struct sh_mobile_sdhi_info sdhi2_info = {
|
|||
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT |
|
||||
TMIO_MMC_USE_GPIO_CD |
|
||||
TMIO_MMC_WRPROTECT_DISABLE,
|
||||
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
|
||||
.tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
|
||||
.cd_gpio = GPIO_PORT13,
|
||||
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_POWER_OFF_CARD,
|
||||
.cd_gpio = 13,
|
||||
};
|
||||
|
||||
static struct resource sdhi2_resources[] = {
|
||||
|
|
@ -563,25 +615,25 @@ static struct i2c_board_info i2c0_devices[] = {
|
|||
},
|
||||
{
|
||||
I2C_BOARD_INFO("ak8975", 0x0c),
|
||||
.irq = intcs_evt2irq(0x3380), /* IRQ28 */
|
||||
.irq = irq_pin(28), /* IRQ28 */
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("adxl34x", 0x1d),
|
||||
.irq = intcs_evt2irq(0x3340), /* IRQ26 */
|
||||
.irq = irq_pin(26), /* IRQ26 */
|
||||
},
|
||||
};
|
||||
|
||||
static struct i2c_board_info i2c1_devices[] = {
|
||||
{
|
||||
I2C_BOARD_INFO("st1232-ts", 0x55),
|
||||
.irq = intcs_evt2irq(0x300), /* IRQ8 */
|
||||
.irq = irq_pin(8), /* IRQ8 */
|
||||
},
|
||||
};
|
||||
|
||||
static struct i2c_board_info i2c3_devices[] = {
|
||||
{
|
||||
I2C_BOARD_INFO("pcf8575", 0x20),
|
||||
.irq = intcs_evt2irq(0x3260), /* IRQ19 */
|
||||
.irq = irq_pin(19), /* IRQ19 */
|
||||
.platform_data = &pcf8575_pdata,
|
||||
},
|
||||
};
|
||||
|
|
@ -592,6 +644,8 @@ static struct platform_device *kzm_devices[] __initdata = {
|
|||
&usbhs_device,
|
||||
&lcdc_device,
|
||||
&mmc_device,
|
||||
&vcc_sdhi0,
|
||||
&vcc_sdhi2,
|
||||
&sdhi0_device,
|
||||
&sdhi2_device,
|
||||
&gpio_keys_device,
|
||||
|
|
@ -599,6 +653,64 @@ static struct platform_device *kzm_devices[] __initdata = {
|
|||
&fsi_ak4648_device,
|
||||
};
|
||||
|
||||
static unsigned long pin_pullup_conf[] = {
|
||||
PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
|
||||
};
|
||||
|
||||
static const struct pinctrl_map kzm_pinctrl_map[] = {
|
||||
/* FSIA (AK4648) */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
|
||||
"fsia_mclk_in", "fsia"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
|
||||
"fsia_sclk_in", "fsia"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
|
||||
"fsia_data_in", "fsia"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
|
||||
"fsia_data_out", "fsia"),
|
||||
/* I2C3 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
|
||||
"i2c3_1", "i2c3"),
|
||||
/* LCD */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
|
||||
"lcd_data24", "lcd"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
|
||||
"lcd_sync", "lcd"),
|
||||
/* MMCIF */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
|
||||
"mmc0_data8_0", "mmc0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
|
||||
"mmc0_ctrl_0", "mmc0"),
|
||||
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
|
||||
"PORT279", pin_pullup_conf),
|
||||
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
|
||||
"mmc0_data8_0", pin_pullup_conf),
|
||||
/* SCIFA4 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
|
||||
"scifa4_data", "scifa4"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
|
||||
"scifa4_ctrl", "scifa4"),
|
||||
/* SDHI0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
|
||||
"sdhi0_data4", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
|
||||
"sdhi0_ctrl", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
|
||||
"sdhi0_cd", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
|
||||
"sdhi0_wp", "sdhi0"),
|
||||
/* SDHI2 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
|
||||
"sdhi2_data4", "sdhi2"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
|
||||
"sdhi2_ctrl", "sdhi2"),
|
||||
/* SMSC */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
|
||||
"bsc_cs4", "bsc"),
|
||||
/* USB */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-sh73a0",
|
||||
"usb_vbus", "usb"),
|
||||
};
|
||||
|
||||
/*
|
||||
* FIXME
|
||||
*
|
||||
|
|
@ -654,106 +766,26 @@ device_initcall(as3711_enable_lcdc_backlight);
|
|||
|
||||
static void __init kzm_init(void)
|
||||
{
|
||||
regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
|
||||
regulator_register_always_on(2, "fixed-1.8V", fixed1v8_power_consumers,
|
||||
ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
|
||||
regulator_register_always_on(1, "fixed-2.8V", fixed2v8_power_consumers,
|
||||
ARRAY_SIZE(fixed2v8_power_consumers), 2800000);
|
||||
regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
|
||||
regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));
|
||||
|
||||
pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
|
||||
|
||||
sh73a0_pinmux_init();
|
||||
|
||||
/* enable SCIFA4 */
|
||||
gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
|
||||
|
||||
/* CS4 for SMSC/USB */
|
||||
gpio_request(GPIO_FN_CS4_, NULL); /* CS4 */
|
||||
|
||||
/* SMSC */
|
||||
gpio_request_one(GPIO_PORT224, GPIOF_IN, NULL); /* IRQ3 */
|
||||
gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */
|
||||
|
||||
/* LCDC */
|
||||
gpio_request(GPIO_FN_LCDD23, NULL);
|
||||
gpio_request(GPIO_FN_LCDD22, NULL);
|
||||
gpio_request(GPIO_FN_LCDD21, NULL);
|
||||
gpio_request(GPIO_FN_LCDD20, NULL);
|
||||
gpio_request(GPIO_FN_LCDD19, NULL);
|
||||
gpio_request(GPIO_FN_LCDD18, NULL);
|
||||
gpio_request(GPIO_FN_LCDD17, NULL);
|
||||
gpio_request(GPIO_FN_LCDD16, NULL);
|
||||
gpio_request(GPIO_FN_LCDD15, NULL);
|
||||
gpio_request(GPIO_FN_LCDD14, NULL);
|
||||
gpio_request(GPIO_FN_LCDD13, NULL);
|
||||
gpio_request(GPIO_FN_LCDD12, NULL);
|
||||
gpio_request(GPIO_FN_LCDD11, NULL);
|
||||
gpio_request(GPIO_FN_LCDD10, NULL);
|
||||
gpio_request(GPIO_FN_LCDD9, NULL);
|
||||
gpio_request(GPIO_FN_LCDD8, NULL);
|
||||
gpio_request(GPIO_FN_LCDD7, NULL);
|
||||
gpio_request(GPIO_FN_LCDD6, NULL);
|
||||
gpio_request(GPIO_FN_LCDD5, NULL);
|
||||
gpio_request(GPIO_FN_LCDD4, NULL);
|
||||
gpio_request(GPIO_FN_LCDD3, NULL);
|
||||
gpio_request(GPIO_FN_LCDD2, NULL);
|
||||
gpio_request(GPIO_FN_LCDD1, NULL);
|
||||
gpio_request(GPIO_FN_LCDD0, NULL);
|
||||
gpio_request(GPIO_FN_LCDDISP, NULL);
|
||||
gpio_request(GPIO_FN_LCDDCK, NULL);
|
||||
|
||||
gpio_request_one(GPIO_PORT222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
|
||||
gpio_request_one(GPIO_PORT226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
|
||||
gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
|
||||
gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
|
||||
|
||||
/* Touchscreen */
|
||||
gpio_request_one(GPIO_PORT223, GPIOF_IN, NULL); /* IRQ8 */
|
||||
|
||||
/* enable MMCIF */
|
||||
gpio_request(GPIO_FN_MMCCLK0, NULL);
|
||||
gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
|
||||
gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
|
||||
|
||||
/* enable SD */
|
||||
gpio_request(GPIO_FN_SDHIWP0, NULL);
|
||||
gpio_request(GPIO_FN_SDHICD0, NULL);
|
||||
gpio_request(GPIO_FN_SDHICMD0, NULL);
|
||||
gpio_request(GPIO_FN_SDHICLK0, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_3, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_2, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_1, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_0, NULL);
|
||||
gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
|
||||
gpio_request_one(GPIO_PORT15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
|
||||
|
||||
/* enable Micro SD */
|
||||
gpio_request(GPIO_FN_SDHID2_0, NULL);
|
||||
gpio_request(GPIO_FN_SDHID2_1, NULL);
|
||||
gpio_request(GPIO_FN_SDHID2_2, NULL);
|
||||
gpio_request(GPIO_FN_SDHID2_3, NULL);
|
||||
gpio_request(GPIO_FN_SDHICMD2, NULL);
|
||||
gpio_request(GPIO_FN_SDHICLK2, NULL);
|
||||
gpio_request_one(GPIO_PORT14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
|
||||
|
||||
/* I2C 3 */
|
||||
gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
|
||||
gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
|
||||
|
||||
/* enable FSI2 port A (ak4648) */
|
||||
gpio_request(GPIO_FN_FSIACK, NULL);
|
||||
gpio_request(GPIO_FN_FSIAILR, NULL);
|
||||
gpio_request(GPIO_FN_FSIAIBT, NULL);
|
||||
gpio_request(GPIO_FN_FSIAISLD, NULL);
|
||||
gpio_request(GPIO_FN_FSIAOSLD, NULL);
|
||||
|
||||
/* enable USB */
|
||||
gpio_request(GPIO_FN_VBUS_0, NULL);
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
/* Early BRESP enable, Shared attribute override enable, 64K*8way */
|
||||
|
|
|
|||
46
arch/arm/mach-shmobile/board-lager.c
Normal file
46
arch/arm/mach-shmobile/board-lager.c
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* Lager board support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/r8a7790.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
static void __init lager_add_standard_devices(void)
|
||||
{
|
||||
r8a7790_clock_init();
|
||||
r8a7790_add_standard_devices();
|
||||
}
|
||||
|
||||
static const char *lager_boards_compat_dt[] __initdata = {
|
||||
"renesas,lager",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(LAGER_DT, "lager")
|
||||
.init_irq = irqchip_init,
|
||||
.init_time = shmobile_timer_init,
|
||||
.init_machine = lager_add_standard_devices,
|
||||
.dt_compat = lager_boards_compat_dt,
|
||||
MACHINE_END
|
||||
|
|
@ -40,6 +40,7 @@
|
|||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/mtd/sh_flctl.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/pm_clock.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
|
|
@ -363,7 +364,7 @@ static struct fb_videomode mackerel_lcdc_modes[] = {
|
|||
|
||||
static int mackerel_set_brightness(int brightness)
|
||||
{
|
||||
gpio_set_value(GPIO_PORT31, brightness);
|
||||
gpio_set_value(31, brightness);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -819,22 +820,22 @@ static struct platform_device usbhs1_device = {
|
|||
static struct gpio_led mackerel_leds[] = {
|
||||
{
|
||||
.name = "led0",
|
||||
.gpio = GPIO_PORT0,
|
||||
.gpio = 0,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
},
|
||||
{
|
||||
.name = "led1",
|
||||
.gpio = GPIO_PORT1,
|
||||
.gpio = 1,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
},
|
||||
{
|
||||
.name = "led2",
|
||||
.gpio = GPIO_PORT2,
|
||||
.gpio = 2,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
},
|
||||
{
|
||||
.name = "led3",
|
||||
.gpio = GPIO_PORT159,
|
||||
.gpio = 159,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
}
|
||||
};
|
||||
|
|
@ -962,40 +963,27 @@ static struct platform_device nand_flash_device = {
|
|||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* The card detect pin of the top SD/MMC slot (CN7) is active low and is
|
||||
* connected to GPIO A22 of SH7372 (GPIO_PORT41).
|
||||
*/
|
||||
static int slot_cn7_get_cd(struct platform_device *pdev)
|
||||
{
|
||||
return !gpio_get_value(GPIO_PORT41);
|
||||
}
|
||||
|
||||
/* SDHI0 */
|
||||
static struct sh_mobile_sdhi_info sdhi0_info = {
|
||||
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
|
||||
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
|
||||
.tmio_flags = TMIO_MMC_USE_GPIO_CD,
|
||||
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
|
||||
.cd_gpio = GPIO_PORT172,
|
||||
.cd_gpio = 172,
|
||||
};
|
||||
|
||||
static struct resource sdhi0_resources[] = {
|
||||
[0] = {
|
||||
{
|
||||
.name = "SDHI0",
|
||||
.start = 0xe6850000,
|
||||
.end = 0xe68500ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
}, {
|
||||
.name = SH_MOBILE_SDHI_IRQ_SDCARD,
|
||||
.start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
}, {
|
||||
.name = SH_MOBILE_SDHI_IRQ_SDIO,
|
||||
.start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
|
|
@ -1011,36 +999,30 @@ static struct platform_device sdhi0_device = {
|
|||
},
|
||||
};
|
||||
|
||||
#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
|
||||
#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
|
||||
/* SDHI1 */
|
||||
|
||||
/* GPIO 41 can trigger IRQ8, but it is used by USBHS1, we have to poll */
|
||||
static struct sh_mobile_sdhi_info sdhi1_info = {
|
||||
.dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
|
||||
.dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
|
||||
.tmio_ocr_mask = MMC_VDD_165_195,
|
||||
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
|
||||
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
|
||||
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
|
||||
MMC_CAP_NEEDS_POLL,
|
||||
.get_cd = slot_cn7_get_cd,
|
||||
.cd_gpio = 41,
|
||||
};
|
||||
|
||||
static struct resource sdhi1_resources[] = {
|
||||
[0] = {
|
||||
{
|
||||
.name = "SDHI1",
|
||||
.start = 0xe6860000,
|
||||
.end = 0xe68600ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
|
||||
.start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
}, {
|
||||
.name = SH_MOBILE_SDHI_IRQ_SDCARD,
|
||||
.start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
}, {
|
||||
.name = SH_MOBILE_SDHI_IRQ_SDIO,
|
||||
.start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
|
||||
.flags = IORESOURCE_IRQ,
|
||||
|
|
@ -1058,43 +1040,32 @@ static struct platform_device sdhi1_device = {
|
|||
};
|
||||
#endif
|
||||
|
||||
/* SDHI2 */
|
||||
|
||||
/*
|
||||
* The card detect pin of the top SD/MMC slot (CN23) is active low and is
|
||||
* connected to GPIO SCIFB_SCK of SH7372 (GPIO_PORT162).
|
||||
* connected to GPIO SCIFB_SCK of SH7372 (GPIO 162).
|
||||
*/
|
||||
static int slot_cn23_get_cd(struct platform_device *pdev)
|
||||
{
|
||||
return !gpio_get_value(GPIO_PORT162);
|
||||
}
|
||||
|
||||
/* SDHI2 */
|
||||
static struct sh_mobile_sdhi_info sdhi2_info = {
|
||||
.dma_slave_tx = SHDMA_SLAVE_SDHI2_TX,
|
||||
.dma_slave_rx = SHDMA_SLAVE_SDHI2_RX,
|
||||
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
|
||||
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
|
||||
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
|
||||
MMC_CAP_NEEDS_POLL,
|
||||
.get_cd = slot_cn23_get_cd,
|
||||
.cd_gpio = 162,
|
||||
};
|
||||
|
||||
static struct resource sdhi2_resources[] = {
|
||||
[0] = {
|
||||
{
|
||||
.name = "SDHI2",
|
||||
.start = 0xe6870000,
|
||||
.end = 0xe68700ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
|
||||
.start = evt2irq(0x1200), /* SDHI2_SDHI2I0 */
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
}, {
|
||||
.name = SH_MOBILE_SDHI_IRQ_SDCARD,
|
||||
.start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
}, {
|
||||
.name = SH_MOBILE_SDHI_IRQ_SDIO,
|
||||
.start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */
|
||||
.flags = IORESOURCE_IRQ,
|
||||
|
|
@ -1112,6 +1083,7 @@ static struct platform_device sdhi2_device = {
|
|||
};
|
||||
|
||||
/* SH_MMCIF */
|
||||
#if IS_ENABLED(CONFIG_MMC_SH_MMCIF)
|
||||
static struct resource sh_mmcif_resources[] = {
|
||||
[0] = {
|
||||
.name = "MMCIF",
|
||||
|
|
@ -1133,11 +1105,12 @@ static struct resource sh_mmcif_resources[] = {
|
|||
|
||||
static struct sh_mmcif_plat_data sh_mmcif_plat = {
|
||||
.sup_pclk = 0,
|
||||
.ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
|
||||
.caps = MMC_CAP_4_BIT_DATA |
|
||||
MMC_CAP_8_BIT_DATA |
|
||||
MMC_CAP_NEEDS_POLL,
|
||||
.get_cd = slot_cn7_get_cd,
|
||||
.use_cd_gpio = true,
|
||||
/* card detect pin for SD/MMC slot (CN7) */
|
||||
.cd_gpio = 41,
|
||||
.slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
|
||||
.slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
|
||||
};
|
||||
|
|
@ -1153,7 +1126,7 @@ static struct platform_device sh_mmcif_device = {
|
|||
.num_resources = ARRAY_SIZE(sh_mmcif_resources),
|
||||
.resource = sh_mmcif_resources,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
static int mackerel_camera_add(struct soc_camera_device *icd);
|
||||
static void mackerel_camera_del(struct soc_camera_device *icd);
|
||||
|
|
@ -1260,11 +1233,12 @@ static struct platform_device *mackerel_devices[] __initdata = {
|
|||
&fsi_hdmi_device,
|
||||
&nand_flash_device,
|
||||
&sdhi0_device,
|
||||
#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
|
||||
#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
|
||||
&sdhi1_device,
|
||||
#else
|
||||
&sh_mmcif_device,
|
||||
#endif
|
||||
&sdhi2_device,
|
||||
&sh_mmcif_device,
|
||||
&ceu_device,
|
||||
&mackerel_camera,
|
||||
&hdmi_device,
|
||||
|
|
@ -1328,6 +1302,34 @@ static struct i2c_board_info i2c1_devices[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static const struct pinctrl_map mackerel_pinctrl_map[] = {
|
||||
/* SDHI0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
|
||||
"sdhi0_data4", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
|
||||
"sdhi0_ctrl", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
|
||||
"sdhi0_wp", "sdhi0"),
|
||||
/* SDHI1 */
|
||||
#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
|
||||
"sdhi1_data4", "sdhi1"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
|
||||
"sdhi1_ctrl", "sdhi1"),
|
||||
#else
|
||||
/* MMCIF */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
|
||||
"mmc0_data8_0", "mmc0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
|
||||
"mmc0_ctrl_0", "mmc0"),
|
||||
#endif
|
||||
/* SDHI2 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
|
||||
"sdhi2_data4", "sdhi2"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
|
||||
"sdhi2_ctrl", "sdhi2"),
|
||||
};
|
||||
|
||||
#define GPIO_PORT9CR IOMEM(0xE6051009)
|
||||
#define GPIO_PORT10CR IOMEM(0xE605100A)
|
||||
#define GPIO_PORT167CR IOMEM(0xE60520A7)
|
||||
|
|
@ -1344,10 +1346,11 @@ static void __init mackerel_init(void)
|
|||
{ "A3SP", &usbhs0_device, },
|
||||
{ "A3SP", &usbhs1_device, },
|
||||
{ "A3SP", &nand_flash_device, },
|
||||
{ "A3SP", &sh_mmcif_device, },
|
||||
{ "A3SP", &sdhi0_device, },
|
||||
#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
|
||||
#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
|
||||
{ "A3SP", &sdhi1_device, },
|
||||
#else
|
||||
{ "A3SP", &sh_mmcif_device, },
|
||||
#endif
|
||||
{ "A3SP", &sdhi2_device, },
|
||||
{ "A4R", &ceu_device, },
|
||||
|
|
@ -1364,6 +1367,8 @@ static void __init mackerel_init(void)
|
|||
/* External clock source */
|
||||
clk_set_rate(&sh7372_dv_clki_clk, 27000000);
|
||||
|
||||
pinctrl_register_mappings(mackerel_pinctrl_map,
|
||||
ARRAY_SIZE(mackerel_pinctrl_map));
|
||||
sh7372_pinmux_init();
|
||||
|
||||
/* enable SCIFA0 */
|
||||
|
|
@ -1403,9 +1408,9 @@ static void __init mackerel_init(void)
|
|||
gpio_request(GPIO_FN_LCDDCK, NULL);
|
||||
|
||||
/* backlight, off by default */
|
||||
gpio_request_one(GPIO_PORT31, GPIOF_OUT_INIT_LOW, NULL);
|
||||
gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL);
|
||||
|
||||
gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
|
||||
gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
|
||||
|
||||
/* USBHS0 */
|
||||
gpio_request(GPIO_FN_VBUS0_0, NULL);
|
||||
|
|
@ -1421,10 +1426,10 @@ static void __init mackerel_init(void)
|
|||
gpio_request(GPIO_FN_FSIAILR, NULL);
|
||||
gpio_request(GPIO_FN_FSIAISLD, NULL);
|
||||
gpio_request(GPIO_FN_FSIAOSLD, NULL);
|
||||
gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
|
||||
gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
|
||||
|
||||
gpio_request(GPIO_PORT9, NULL);
|
||||
gpio_request(GPIO_PORT10, NULL);
|
||||
gpio_request(9, NULL);
|
||||
gpio_request(10, NULL);
|
||||
gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
|
||||
gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
|
||||
|
||||
|
|
@ -1453,53 +1458,9 @@ static void __init mackerel_init(void)
|
|||
gpio_request(GPIO_FN_IRQ21, NULL);
|
||||
irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
|
||||
|
||||
/* enable SDHI0 */
|
||||
gpio_request(GPIO_FN_SDHIWP0, NULL);
|
||||
gpio_request(GPIO_FN_SDHICMD0, NULL);
|
||||
gpio_request(GPIO_FN_SDHICLK0, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_3, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_2, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_1, NULL);
|
||||
gpio_request(GPIO_FN_SDHID0_0, NULL);
|
||||
|
||||
/* SDHI0 PORT172 card-detect IRQ26 */
|
||||
gpio_request(GPIO_FN_IRQ26_172, NULL);
|
||||
|
||||
#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
|
||||
/* enable SDHI1 */
|
||||
gpio_request(GPIO_FN_SDHICMD1, NULL);
|
||||
gpio_request(GPIO_FN_SDHICLK1, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_3, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_2, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_1, NULL);
|
||||
gpio_request(GPIO_FN_SDHID1_0, NULL);
|
||||
#endif
|
||||
/* card detect pin for MMC slot (CN7) */
|
||||
gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL);
|
||||
|
||||
/* enable SDHI2 */
|
||||
gpio_request(GPIO_FN_SDHICMD2, NULL);
|
||||
gpio_request(GPIO_FN_SDHICLK2, NULL);
|
||||
gpio_request(GPIO_FN_SDHID2_3, NULL);
|
||||
gpio_request(GPIO_FN_SDHID2_2, NULL);
|
||||
gpio_request(GPIO_FN_SDHID2_1, NULL);
|
||||
gpio_request(GPIO_FN_SDHID2_0, NULL);
|
||||
|
||||
/* card detect pin for microSD slot (CN23) */
|
||||
gpio_request_one(GPIO_PORT162, GPIOF_IN, NULL);
|
||||
|
||||
/* MMCIF */
|
||||
gpio_request(GPIO_FN_MMCD0_0, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_1, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_2, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_3, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_4, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_5, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_6, NULL);
|
||||
gpio_request(GPIO_FN_MMCD0_7, NULL);
|
||||
gpio_request(GPIO_FN_MMCCMD0, NULL);
|
||||
gpio_request(GPIO_FN_MMCCLK0, NULL);
|
||||
|
||||
/* FLCTL */
|
||||
gpio_request(GPIO_FN_D0_NAF0, NULL);
|
||||
gpio_request(GPIO_FN_D1_NAF1, NULL);
|
||||
|
|
|
|||
75
arch/arm/mach-shmobile/board-marzen-reference.c
Normal file
75
arch/arm/mach-shmobile/board-marzen-reference.c
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
/*
|
||||
* marzen board support - Reference DT implementation
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Magnus Damm
|
||||
* Copyright (C) 2013 Simon Horman
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <mach/r8a7779.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
static const struct pinctrl_map marzen_pinctrl_map[] = {
|
||||
/* SCIF2 (CN18: DEBUG0) */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
|
||||
"scif2_data_c", "scif2"),
|
||||
/* SCIF4 (CN19: DEBUG1) */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
|
||||
"scif4_data", "scif4"),
|
||||
/* SDHI0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
|
||||
"sdhi0_data4", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
|
||||
"sdhi0_ctrl", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
|
||||
"sdhi0_cd", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
|
||||
"sdhi0_wp", "sdhi0"),
|
||||
/* SMSC */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
|
||||
"intc_irq1_b", "intc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
|
||||
"lbsc_ex_cs0", "lbsc"),
|
||||
};
|
||||
|
||||
static void __init marzen_init(void)
|
||||
{
|
||||
pinctrl_register_mappings(marzen_pinctrl_map,
|
||||
ARRAY_SIZE(marzen_pinctrl_map));
|
||||
r8a7779_pinmux_init();
|
||||
|
||||
r8a7779_add_standard_devices_dt();
|
||||
}
|
||||
|
||||
static const char *marzen_boards_compat_dt[] __initdata = {
|
||||
"renesas,marzen-reference",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(MARZEN, "marzen")
|
||||
.smp = smp_ops(r8a7779_smp_ops),
|
||||
.map_io = r8a7779_map_io,
|
||||
.init_early = r8a7779_init_delay,
|
||||
.nr_irqs = NR_IRQS_LEGACY,
|
||||
.init_irq = r8a7779_init_irq_dt,
|
||||
.init_machine = marzen_init,
|
||||
.init_time = shmobile_timer_init,
|
||||
.dt_compat = marzen_boards_compat_dt,
|
||||
MACHINE_END
|
||||
|
|
@ -25,8 +25,9 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/smsc911x.h>
|
||||
|
|
@ -67,7 +68,7 @@ static struct resource smsc911x_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_spi(28), /* IRQ 1 */
|
||||
.start = gic_iid(0x3c), /* IRQ 1 */
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -97,7 +98,7 @@ static struct resource sdhi0_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_spi(104),
|
||||
.start = gic_iid(0x88),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -168,12 +169,43 @@ static struct platform_device usb_phy_device = {
|
|||
.num_resources = ARRAY_SIZE(usb_phy_resources),
|
||||
};
|
||||
|
||||
/* LEDS */
|
||||
static struct gpio_led marzen_leds[] = {
|
||||
{
|
||||
.name = "led2",
|
||||
.gpio = 157,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
}, {
|
||||
.name = "led3",
|
||||
.gpio = 158,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
}, {
|
||||
.name = "led4",
|
||||
.gpio = 159,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_led_platform_data marzen_leds_pdata = {
|
||||
.leds = marzen_leds,
|
||||
.num_leds = ARRAY_SIZE(marzen_leds),
|
||||
};
|
||||
|
||||
static struct platform_device leds_device = {
|
||||
.name = "leds-gpio",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &marzen_leds_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *marzen_devices[] __initdata = {
|
||||
ð_device,
|
||||
&sdhi0_device,
|
||||
&thermal_device,
|
||||
&hspi_device,
|
||||
&usb_phy_device,
|
||||
&leds_device,
|
||||
};
|
||||
|
||||
/* USB */
|
||||
|
|
@ -215,7 +247,7 @@ static struct resource ehci0_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_spi(44),
|
||||
.start = gic_iid(0x4c),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -239,7 +271,7 @@ static struct resource ehci1_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_spi(45),
|
||||
.start = gic_iid(0x4d),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -269,7 +301,7 @@ static struct resource ohci0_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_spi(44),
|
||||
.start = gic_iid(0x4c),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -293,7 +325,7 @@ static struct resource ohci1_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_spi(45),
|
||||
.start = gic_iid(0x4d),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -327,6 +359,41 @@ void __init marzen_init_late(void)
|
|||
ARRAY_SIZE(marzen_late_devices));
|
||||
}
|
||||
|
||||
static const struct pinctrl_map marzen_pinctrl_map[] = {
|
||||
/* HSPI0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779",
|
||||
"hspi0", "hspi0"),
|
||||
/* SCIF2 (CN18: DEBUG0) */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
|
||||
"scif2_data_c", "scif2"),
|
||||
/* SCIF4 (CN19: DEBUG1) */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
|
||||
"scif4_data", "scif4"),
|
||||
/* SDHI0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
|
||||
"sdhi0_data4", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
|
||||
"sdhi0_ctrl", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
|
||||
"sdhi0_cd", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
|
||||
"sdhi0_wp", "sdhi0"),
|
||||
/* SMSC */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
|
||||
"intc_irq1_b", "intc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
|
||||
"lbsc_ex_cs0", "lbsc"),
|
||||
/* USB0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
|
||||
"usb0", "usb0"),
|
||||
/* USB1 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
|
||||
"usb1", "usb1"),
|
||||
/* USB2 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779",
|
||||
"usb2", "usb2"),
|
||||
};
|
||||
|
||||
static void __init marzen_init(void)
|
||||
{
|
||||
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
|
||||
|
|
@ -334,44 +401,10 @@ static void __init marzen_init(void)
|
|||
regulator_register_fixed(1, dummy_supplies,
|
||||
ARRAY_SIZE(dummy_supplies));
|
||||
|
||||
pinctrl_register_mappings(marzen_pinctrl_map,
|
||||
ARRAY_SIZE(marzen_pinctrl_map));
|
||||
r8a7779_pinmux_init();
|
||||
|
||||
/* SCIF2 (CN18: DEBUG0) */
|
||||
gpio_request(GPIO_FN_TX2_C, NULL);
|
||||
gpio_request(GPIO_FN_RX2_C, NULL);
|
||||
|
||||
/* SCIF4 (CN19: DEBUG1) */
|
||||
gpio_request(GPIO_FN_TX4, NULL);
|
||||
gpio_request(GPIO_FN_RX4, NULL);
|
||||
|
||||
/* LAN89218 */
|
||||
gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
|
||||
gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
|
||||
|
||||
/* SD0 (CN20) */
|
||||
gpio_request(GPIO_FN_SD0_CLK, NULL);
|
||||
gpio_request(GPIO_FN_SD0_CMD, NULL);
|
||||
gpio_request(GPIO_FN_SD0_DAT0, NULL);
|
||||
gpio_request(GPIO_FN_SD0_DAT1, NULL);
|
||||
gpio_request(GPIO_FN_SD0_DAT2, NULL);
|
||||
gpio_request(GPIO_FN_SD0_DAT3, NULL);
|
||||
gpio_request(GPIO_FN_SD0_CD, NULL);
|
||||
gpio_request(GPIO_FN_SD0_WP, NULL);
|
||||
|
||||
/* HSPI 0 */
|
||||
gpio_request(GPIO_FN_HSPI_CLK0, NULL);
|
||||
gpio_request(GPIO_FN_HSPI_CS0, NULL);
|
||||
gpio_request(GPIO_FN_HSPI_TX0, NULL);
|
||||
gpio_request(GPIO_FN_HSPI_RX0, NULL);
|
||||
|
||||
/* USB (CN21) */
|
||||
gpio_request(GPIO_FN_USB_OVC0, NULL);
|
||||
gpio_request(GPIO_FN_USB_OVC1, NULL);
|
||||
gpio_request(GPIO_FN_USB_OVC2, NULL);
|
||||
|
||||
/* USB (CN22) */
|
||||
gpio_request(GPIO_FN_USB_PENC2, NULL);
|
||||
|
||||
r8a7779_add_standard_devices();
|
||||
platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
|
||||
}
|
||||
|
|
|
|||
115
arch/arm/mach-shmobile/clock-r8a73a4.c
Normal file
115
arch/arm/mach-shmobile/clock-r8a73a4.c
Normal file
|
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
* r8a73a4 clock framework support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
#define CPG_BASE 0xe6150000
|
||||
#define CPG_LEN 0x270
|
||||
|
||||
#define MPCKCR 0xe6150080
|
||||
#define SMSTPCR2 0xe6150138
|
||||
#define SMSTPCR5 0xe6150144
|
||||
|
||||
static struct clk_mapping cpg_mapping = {
|
||||
.phys = CPG_BASE,
|
||||
.len = CPG_LEN,
|
||||
};
|
||||
|
||||
static struct clk extalr_clk = {
|
||||
.rate = 32768,
|
||||
.mapping = &cpg_mapping,
|
||||
};
|
||||
|
||||
static struct clk extal1_clk = {
|
||||
.rate = 26000000,
|
||||
.mapping = &cpg_mapping,
|
||||
};
|
||||
|
||||
static struct clk extal2_clk = {
|
||||
.rate = 48000000,
|
||||
.mapping = &cpg_mapping,
|
||||
};
|
||||
|
||||
static struct clk *main_clks[] = {
|
||||
&extalr_clk,
|
||||
&extal1_clk,
|
||||
&extal2_clk,
|
||||
};
|
||||
|
||||
enum {
|
||||
MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
|
||||
MSTP522,
|
||||
MSTP_NR
|
||||
};
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
|
||||
[MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
|
||||
[MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
|
||||
[MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
|
||||
[MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
|
||||
[MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */
|
||||
[MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
|
||||
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
|
||||
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
|
||||
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
|
||||
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
|
||||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
|
||||
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
|
||||
|
||||
/* for DT */
|
||||
CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
|
||||
};
|
||||
|
||||
void __init r8a73a4_clock_init(void)
|
||||
{
|
||||
void __iomem *cpg_base, *reg;
|
||||
int k, ret = 0;
|
||||
|
||||
/* fix MPCLK to EXTAL2 for now.
|
||||
* this is needed until more detailed clock topology is supported
|
||||
*/
|
||||
cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN);
|
||||
BUG_ON(!cpg_base);
|
||||
reg = cpg_base + (MPCKCR - CPG_BASE);
|
||||
iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */
|
||||
iounmap(cpg_base);
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
if (!ret)
|
||||
shmobile_clk_init();
|
||||
else
|
||||
panic("failed to setup r8a73a4 clocks\n");
|
||||
}
|
||||
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <mach/clock.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/r8a7740.h>
|
||||
|
||||
|
|
@ -97,42 +98,13 @@ static struct clk dv_clk = {
|
|||
.rate = 27000000,
|
||||
};
|
||||
|
||||
static unsigned long div_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate / (int)(clk->priv);
|
||||
}
|
||||
SH_CLK_RATIO(div2, 1, 2);
|
||||
SH_CLK_RATIO(div1k, 1, 1024);
|
||||
|
||||
static struct sh_clk_ops div_clk_ops = {
|
||||
.recalc = div_recalc,
|
||||
};
|
||||
|
||||
/* extal1 / 2 */
|
||||
static struct clk extal1_div2_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)2,
|
||||
.parent = &extal1_clk,
|
||||
};
|
||||
|
||||
/* extal1 / 1024 */
|
||||
static struct clk extal1_div1024_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)1024,
|
||||
.parent = &extal1_clk,
|
||||
};
|
||||
|
||||
/* extal1 / 2 / 1024 */
|
||||
static struct clk extal1_div2048_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)1024,
|
||||
.parent = &extal1_div2_clk,
|
||||
};
|
||||
|
||||
/* extal2 / 2 */
|
||||
static struct clk extal2_div2_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)2,
|
||||
.parent = &extal2_clk,
|
||||
};
|
||||
SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2);
|
||||
SH_FIXED_RATIO_CLK(extal1_div1024_clk, extal1_clk, div1k);
|
||||
SH_FIXED_RATIO_CLK(extal1_div2048_clk, extal1_div2_clk, div1k);
|
||||
SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2);
|
||||
|
||||
static struct sh_clk_ops followparent_clk_ops = {
|
||||
.recalc = followparent_recalc,
|
||||
|
|
@ -143,11 +115,7 @@ static struct clk system_clk = {
|
|||
.ops = &followparent_clk_ops,
|
||||
};
|
||||
|
||||
static struct clk system_div2_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)2,
|
||||
.parent = &system_clk,
|
||||
};
|
||||
SH_FIXED_RATIO_CLK(system_div2_clk, system_clk, div2);
|
||||
|
||||
/* r_clk */
|
||||
static struct clk r_clk = {
|
||||
|
|
@ -184,11 +152,7 @@ static struct clk pllc1_clk = {
|
|||
};
|
||||
|
||||
/* PLLC1 / 2 */
|
||||
static struct clk pllc1_div2_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)2,
|
||||
.parent = &pllc1_clk,
|
||||
};
|
||||
SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
|
||||
|
||||
/* USB clock */
|
||||
/*
|
||||
|
|
@ -323,6 +287,7 @@ struct clk *main_clks[] = {
|
|||
&fsibck_clk,
|
||||
};
|
||||
|
||||
/* DIV4 clocks */
|
||||
static void div4_kick(struct clk *clk)
|
||||
{
|
||||
unsigned long value;
|
||||
|
|
@ -346,6 +311,26 @@ static struct clk_div4_table div4_table = {
|
|||
.kick = div4_kick,
|
||||
};
|
||||
|
||||
enum {
|
||||
DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
|
||||
DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
|
||||
DIV4_NR
|
||||
};
|
||||
|
||||
struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
|
||||
[DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
|
||||
[DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
|
||||
[DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
|
||||
[DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
|
||||
[DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
|
||||
[DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
|
||||
};
|
||||
|
||||
/* DIV6 reparent */
|
||||
enum {
|
||||
DIV6_HDMI,
|
||||
|
|
@ -391,6 +376,16 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
|
|||
fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
|
||||
};
|
||||
|
||||
/* DIV6 clocks */
|
||||
enum {
|
||||
DIV6_SUB,
|
||||
DIV6_NR
|
||||
};
|
||||
|
||||
static struct clk div6_clks[DIV6_NR] = {
|
||||
[DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
|
||||
};
|
||||
|
||||
/* HDMI1/2 clock */
|
||||
static unsigned long hdmi12_recalc(struct clk *clk)
|
||||
{
|
||||
|
|
@ -455,35 +450,6 @@ static struct clk fsidivs[] = {
|
|||
};
|
||||
|
||||
/* MSTP */
|
||||
enum {
|
||||
DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
|
||||
DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
|
||||
DIV4_NR
|
||||
};
|
||||
|
||||
struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
|
||||
[DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
|
||||
[DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
|
||||
[DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
|
||||
[DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
|
||||
[DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
|
||||
[DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
|
||||
};
|
||||
|
||||
enum {
|
||||
DIV6_SUB,
|
||||
DIV6_NR
|
||||
};
|
||||
|
||||
static struct clk div6_clks[DIV6_NR] = {
|
||||
[DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
|
||||
};
|
||||
|
||||
enum {
|
||||
MSTP128, MSTP127, MSTP125,
|
||||
MSTP116, MSTP111, MSTP100, MSTP117,
|
||||
|
|
@ -593,29 +559,42 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP128]),
|
||||
|
||||
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
|
||||
CLKDEV_DEV_ID("e6c80000.sci", &mstp_clks[MSTP200]),
|
||||
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]),
|
||||
CLKDEV_DEV_ID("e6c70000.sci", &mstp_clks[MSTP201]),
|
||||
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]),
|
||||
CLKDEV_DEV_ID("e6c60000.sci", &mstp_clks[MSTP202]),
|
||||
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
|
||||
CLKDEV_DEV_ID("e6c50000.sci", &mstp_clks[MSTP203]),
|
||||
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
|
||||
CLKDEV_DEV_ID("e6c40000.sci", &mstp_clks[MSTP204]),
|
||||
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
|
||||
CLKDEV_DEV_ID("e6c30000.sci", &mstp_clks[MSTP206]),
|
||||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
|
||||
CLKDEV_DEV_ID("e6cb0000.sci", &mstp_clks[MSTP207]),
|
||||
CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]),
|
||||
CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]),
|
||||
CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]),
|
||||
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
|
||||
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
|
||||
CLKDEV_DEV_ID("e6cd0000.sci", &mstp_clks[MSTP222]),
|
||||
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
|
||||
CLKDEV_DEV_ID("e6cc0000.sci", &mstp_clks[MSTP230]),
|
||||
|
||||
CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
|
||||
CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]),
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
|
||||
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]),
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
|
||||
CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]),
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
|
||||
CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]),
|
||||
CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]),
|
||||
CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]),
|
||||
CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]),
|
||||
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]),
|
||||
CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]),
|
||||
|
||||
/* ICK */
|
||||
CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]),
|
||||
|
|
|
|||
104
arch/arm/mach-shmobile/clock-r8a7778.c
Normal file
104
arch/arm/mach-shmobile/clock-r8a7778.c
Normal file
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* r8a7778 clock framework support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
*
|
||||
* based on r8a7779
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
#define MSTPCR0 IOMEM(0xffc80030)
|
||||
#define MSTPCR1 IOMEM(0xffc80034)
|
||||
#define MSTPCR3 IOMEM(0xffc8003c)
|
||||
#define MSTPSR1 IOMEM(0xffc80044)
|
||||
#define MSTPSR4 IOMEM(0xffc80048)
|
||||
#define MSTPSR6 IOMEM(0xffc8004c)
|
||||
#define MSTPCR4 IOMEM(0xffc80050)
|
||||
#define MSTPCR5 IOMEM(0xffc80054)
|
||||
#define MSTPCR6 IOMEM(0xffc80058)
|
||||
|
||||
/* ioremap() through clock mapping mandatory to avoid
|
||||
* collision with ARM coherent DMA virtual memory range.
|
||||
*/
|
||||
|
||||
static struct clk_mapping cpg_mapping = {
|
||||
.phys = 0xffc80000,
|
||||
.len = 0x80,
|
||||
};
|
||||
|
||||
static struct clk clkp = {
|
||||
.rate = 62500000, /* FIXME: shortcut */
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
.mapping = &cpg_mapping,
|
||||
};
|
||||
|
||||
static struct clk *main_clks[] = {
|
||||
&clkp,
|
||||
};
|
||||
|
||||
enum {
|
||||
MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
|
||||
MSTP016, MSTP015,
|
||||
MSTP_NR };
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */
|
||||
[MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */
|
||||
[MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */
|
||||
[MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */
|
||||
[MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */
|
||||
[MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */
|
||||
[MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */
|
||||
[MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* MSTP32 clocks */
|
||||
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
|
||||
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
|
||||
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
|
||||
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
|
||||
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
|
||||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
|
||||
CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
|
||||
CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
|
||||
};
|
||||
|
||||
void __init r8a7778_clock_init(void)
|
||||
{
|
||||
int k, ret = 0;
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
if (!ret)
|
||||
shmobile_clk_init();
|
||||
else
|
||||
panic("failed to setup r8a7778 clocks\n");
|
||||
}
|
||||
|
|
@ -17,13 +17,17 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <mach/clock.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
#define MD(nr) BIT(nr)
|
||||
|
||||
#define FRQMR IOMEM(0xffc80014)
|
||||
#define MSTPCR0 IOMEM(0xffc80030)
|
||||
#define MSTPCR1 IOMEM(0xffc80034)
|
||||
|
|
@ -36,6 +40,9 @@
|
|||
#define MSTPCR6 IOMEM(0xffc80058)
|
||||
#define MSTPCR7 IOMEM(0xffc80040)
|
||||
|
||||
#define MODEMR 0xffcc0020
|
||||
|
||||
|
||||
/* ioremap() through clock mapping mandatory to avoid
|
||||
* collision with ARM coherent DMA virtual memory range.
|
||||
*/
|
||||
|
|
@ -50,44 +57,44 @@ static struct clk_mapping cpg_mapping = {
|
|||
* from the platform code.
|
||||
*/
|
||||
static struct clk plla_clk = {
|
||||
.rate = 1500000000,
|
||||
/* .rate will be updated on r8a7779_clock_init() */
|
||||
.mapping = &cpg_mapping,
|
||||
};
|
||||
|
||||
/*
|
||||
* clock ratio of these clock will be updated
|
||||
* on r8a7779_clock_init()
|
||||
*/
|
||||
SH_FIXED_RATIO_CLK_SET(clkz_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clkzs_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clki_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clks_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clks1_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clks3_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clks4_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clkb_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clkout_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clkp_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clkg_clk, plla_clk, 1, 1);
|
||||
|
||||
static struct clk *main_clks[] = {
|
||||
&plla_clk,
|
||||
};
|
||||
|
||||
static int divisors[] = { 0, 0, 0, 6, 8, 12, 16, 0, 24, 32, 36, 0, 0, 0, 0, 0 };
|
||||
|
||||
static struct clk_div_mult_table div4_div_mult_table = {
|
||||
.divisors = divisors,
|
||||
.nr_divisors = ARRAY_SIZE(divisors),
|
||||
};
|
||||
|
||||
static struct clk_div4_table div4_table = {
|
||||
.div_mult_table = &div4_div_mult_table,
|
||||
};
|
||||
|
||||
enum { DIV4_S, DIV4_OUT, DIV4_S4, DIV4_S3, DIV4_S1, DIV4_P, DIV4_NR };
|
||||
|
||||
static struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_S] = SH_CLK_DIV4(&plla_clk, FRQMR, 20,
|
||||
0x0018, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_OUT] = SH_CLK_DIV4(&plla_clk, FRQMR, 16,
|
||||
0x0700, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_S4] = SH_CLK_DIV4(&plla_clk, FRQMR, 12,
|
||||
0x0040, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_S3] = SH_CLK_DIV4(&plla_clk, FRQMR, 8,
|
||||
0x0010, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_S1] = SH_CLK_DIV4(&plla_clk, FRQMR, 4,
|
||||
0x0060, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_P] = SH_CLK_DIV4(&plla_clk, FRQMR, 0,
|
||||
0x0300, CLK_ENABLE_ON_INIT),
|
||||
&clkz_clk,
|
||||
&clkzs_clk,
|
||||
&clki_clk,
|
||||
&clks_clk,
|
||||
&clks1_clk,
|
||||
&clks3_clk,
|
||||
&clks4_clk,
|
||||
&clkb_clk,
|
||||
&clkout_clk,
|
||||
&clkp_clk,
|
||||
&clkg_clk,
|
||||
};
|
||||
|
||||
enum { MSTP323, MSTP322, MSTP321, MSTP320,
|
||||
MSTP101, MSTP100,
|
||||
MSTP115,
|
||||
MSTP103, MSTP101, MSTP100,
|
||||
MSTP030,
|
||||
MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
|
||||
MSTP016, MSTP015, MSTP014,
|
||||
|
|
@ -95,50 +102,28 @@ enum { MSTP323, MSTP322, MSTP321, MSTP320,
|
|||
MSTP_NR };
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), /* SDHI0 */
|
||||
[MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
|
||||
[MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
|
||||
[MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
|
||||
[MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */
|
||||
[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */
|
||||
[MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */
|
||||
[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), /* I2C1 */
|
||||
[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), /* I2C2 */
|
||||
[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), /* I2C3 */
|
||||
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
|
||||
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
|
||||
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
|
||||
[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */
|
||||
[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */
|
||||
[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */
|
||||
[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */
|
||||
[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */
|
||||
[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */
|
||||
[MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR0, 7, 0), /* HSPI */
|
||||
};
|
||||
|
||||
static unsigned long mul4_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate * 4;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops mul4_clk_ops = {
|
||||
.recalc = mul4_recalc,
|
||||
};
|
||||
|
||||
struct clk clkz_clk = {
|
||||
.ops = &mul4_clk_ops,
|
||||
.parent = &div4_clks[DIV4_S],
|
||||
};
|
||||
|
||||
struct clk clkzs_clk = {
|
||||
/* clks x 4 / 4 = clks */
|
||||
.parent = &div4_clks[DIV4_S],
|
||||
};
|
||||
|
||||
static struct clk *late_main_clks[] = {
|
||||
&clkz_clk,
|
||||
&clkzs_clk,
|
||||
[MSTP323] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 23, 0), /* SDHI0 */
|
||||
[MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
|
||||
[MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
|
||||
[MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
|
||||
[MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
|
||||
[MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */
|
||||
[MSTP101] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 1, 0), /* USB2 */
|
||||
[MSTP100] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 0, 0), /* USB0/1 */
|
||||
[MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */
|
||||
[MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */
|
||||
[MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */
|
||||
[MSTP027] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 27, 0), /* I2C3 */
|
||||
[MSTP026] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 26, 0), /* SCIF0 */
|
||||
[MSTP025] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 25, 0), /* SCIF1 */
|
||||
[MSTP024] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 24, 0), /* SCIF2 */
|
||||
[MSTP023] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 23, 0), /* SCIF3 */
|
||||
[MSTP022] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 22, 0), /* SCIF4 */
|
||||
[MSTP021] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 21, 0), /* SCIF5 */
|
||||
[MSTP016] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 16, 0), /* TMU0 */
|
||||
[MSTP015] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 15, 0), /* TMU1 */
|
||||
[MSTP014] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 14, 0), /* TMU2 */
|
||||
[MSTP007] = SH_CLK_MSTP32(&clks_clk, MSTPCR0, 7, 0), /* HSPI */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
|
|
@ -148,14 +133,16 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_CON_ID("clkzs_clk", &clkzs_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]),
|
||||
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_OUT]),
|
||||
CLKDEV_CON_ID("shyway4_clk", &div4_clks[DIV4_S4]),
|
||||
CLKDEV_CON_ID("shyway3_clk", &div4_clks[DIV4_S3]),
|
||||
CLKDEV_CON_ID("shyway1_clk", &div4_clks[DIV4_S1]),
|
||||
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
|
||||
CLKDEV_CON_ID("shyway_clk", &clks_clk),
|
||||
CLKDEV_CON_ID("bus_clk", &clkout_clk),
|
||||
CLKDEV_CON_ID("shyway4_clk", &clks4_clk),
|
||||
CLKDEV_CON_ID("shyway3_clk", &clks3_clk),
|
||||
CLKDEV_CON_ID("shyway1_clk", &clks1_clk),
|
||||
CLKDEV_CON_ID("peripheral_clk", &clkp_clk),
|
||||
|
||||
/* MSTP32 clocks */
|
||||
CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
|
||||
CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
|
||||
CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
|
||||
CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
|
||||
CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
|
||||
|
|
@ -180,24 +167,65 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
|
||||
CLKDEV_DEV_ID("rcar-du.0", &mstp_clks[MSTP103]), /* DU */
|
||||
};
|
||||
|
||||
void __init r8a7779_clock_init(void)
|
||||
{
|
||||
void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
|
||||
u32 mode;
|
||||
int k, ret = 0;
|
||||
|
||||
BUG_ON(!modemr);
|
||||
mode = ioread32(modemr);
|
||||
iounmap(modemr);
|
||||
|
||||
if (mode & MD(1)) {
|
||||
plla_clk.rate = 1500000000;
|
||||
|
||||
SH_CLK_SET_RATIO(&clkz_clk_ratio, 2, 3);
|
||||
SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 6);
|
||||
SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2);
|
||||
SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 6);
|
||||
SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 12);
|
||||
SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8);
|
||||
SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16);
|
||||
SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 24);
|
||||
SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24);
|
||||
if (mode & MD(2)) {
|
||||
SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 36);
|
||||
SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 36);
|
||||
} else {
|
||||
SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24);
|
||||
SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24);
|
||||
}
|
||||
} else {
|
||||
plla_clk.rate = 1600000000;
|
||||
|
||||
SH_CLK_SET_RATIO(&clkz_clk_ratio, 1, 2);
|
||||
SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 8);
|
||||
SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2);
|
||||
SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 8);
|
||||
SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 16);
|
||||
SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8);
|
||||
SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16);
|
||||
SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 32);
|
||||
SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24);
|
||||
if (mode & MD(2)) {
|
||||
SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 32);
|
||||
SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 32);
|
||||
} else {
|
||||
SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24);
|
||||
SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24);
|
||||
}
|
||||
}
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
|
||||
ret = clk_register(late_main_clks[k]);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
if (!ret)
|
||||
|
|
|
|||
93
arch/arm/mach-shmobile/clock-r8a7790.c
Normal file
93
arch/arm/mach-shmobile/clock-r8a7790.c
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
* r8a7790 clock framework support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
#define CPG_BASE 0xe6150000
|
||||
#define CPG_LEN 0x1000
|
||||
|
||||
#define SMSTPCR2 0xe6150138
|
||||
#define SMSTPCR7 0xe615014c
|
||||
|
||||
static struct clk_mapping cpg_mapping = {
|
||||
.phys = CPG_BASE,
|
||||
.len = CPG_LEN,
|
||||
};
|
||||
|
||||
static struct clk p_clk = {
|
||||
.rate = 65000000, /* shortcut for now */
|
||||
.mapping = &cpg_mapping,
|
||||
};
|
||||
|
||||
static struct clk mp_clk = {
|
||||
.rate = 52000000, /* shortcut for now */
|
||||
.mapping = &cpg_mapping,
|
||||
};
|
||||
|
||||
static struct clk *main_clks[] = {
|
||||
&p_clk,
|
||||
&mp_clk,
|
||||
};
|
||||
|
||||
enum { MSTP721, MSTP720,
|
||||
MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
|
||||
[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
|
||||
[MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
|
||||
[MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
|
||||
[MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
|
||||
[MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
|
||||
[MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
|
||||
[MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
|
||||
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
|
||||
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
|
||||
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
|
||||
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
|
||||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
|
||||
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
|
||||
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
|
||||
};
|
||||
|
||||
void __init r8a7790_clock_init(void)
|
||||
{
|
||||
int k, ret = 0;
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
if (!ret)
|
||||
shmobile_clk_init();
|
||||
else
|
||||
panic("failed to setup r8a7790 clocks\n");
|
||||
}
|
||||
|
|
@ -21,6 +21,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <mach/clock.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
/* SH7372 registers */
|
||||
|
|
@ -83,39 +84,12 @@ struct clk sh7372_extal2_clk = {
|
|||
.rate = 48000000,
|
||||
};
|
||||
|
||||
/* A fixed divide-by-2 block */
|
||||
static unsigned long div2_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate / 2;
|
||||
}
|
||||
SH_CLK_RATIO(div2, 1, 2);
|
||||
|
||||
static struct sh_clk_ops div2_clk_ops = {
|
||||
.recalc = div2_recalc,
|
||||
};
|
||||
|
||||
/* Divide dv_clki by two */
|
||||
struct clk sh7372_dv_clki_div2_clk = {
|
||||
.ops = &div2_clk_ops,
|
||||
.parent = &sh7372_dv_clki_clk,
|
||||
};
|
||||
|
||||
/* Divide extal1 by two */
|
||||
static struct clk extal1_div2_clk = {
|
||||
.ops = &div2_clk_ops,
|
||||
.parent = &sh7372_extal1_clk,
|
||||
};
|
||||
|
||||
/* Divide extal2 by two */
|
||||
static struct clk extal2_div2_clk = {
|
||||
.ops = &div2_clk_ops,
|
||||
.parent = &sh7372_extal2_clk,
|
||||
};
|
||||
|
||||
/* Divide extal2 by four */
|
||||
static struct clk extal2_div4_clk = {
|
||||
.ops = &div2_clk_ops,
|
||||
.parent = &extal2_div2_clk,
|
||||
};
|
||||
SH_FIXED_RATIO_CLKg(sh7372_dv_clki_div2_clk, sh7372_dv_clki_clk, div2);
|
||||
SH_FIXED_RATIO_CLK(extal1_div2_clk, sh7372_extal1_clk, div2);
|
||||
SH_FIXED_RATIO_CLK(extal2_div2_clk, sh7372_extal2_clk, div2);
|
||||
SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_div2_clk, div2);
|
||||
|
||||
/* PLLC0 and PLLC1 */
|
||||
static unsigned long pllc01_recalc(struct clk *clk)
|
||||
|
|
@ -147,10 +121,7 @@ static struct clk pllc1_clk = {
|
|||
};
|
||||
|
||||
/* Divide PLLC1 by two */
|
||||
static struct clk pllc1_div2_clk = {
|
||||
.ops = &div2_clk_ops,
|
||||
.parent = &pllc1_clk,
|
||||
};
|
||||
SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
|
||||
|
||||
/* PLLC2 */
|
||||
|
||||
|
|
@ -342,7 +313,7 @@ static struct clk_div4_table div4_table = {
|
|||
};
|
||||
|
||||
enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
|
||||
DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP,
|
||||
DIV4_ZX, DIV4_HP,
|
||||
DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
|
||||
DIV4_DDRP, DIV4_NR };
|
||||
|
||||
|
|
@ -355,8 +326,6 @@ static struct clk div4_clks[DIV4_NR] = {
|
|||
[DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
|
||||
[DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0),
|
||||
[DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0),
|
||||
[DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
|
||||
[DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
|
||||
[DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
|
||||
|
|
@ -516,8 +485,6 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
|
||||
CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
|
||||
CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
|
||||
CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
|
||||
CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
|
||||
CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
|
||||
CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
|
||||
CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
|
||||
|
|
@ -654,5 +621,4 @@ void __init sh7372_clock_init(void)
|
|||
shmobile_clk_init();
|
||||
else
|
||||
panic("failed to setup sh7372 clocks\n");
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -21,6 +21,8 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <asm/processor.h>
|
||||
#include <mach/clock.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
#define FRQCRA IOMEM(0xe6150000)
|
||||
|
|
@ -82,61 +84,16 @@ struct clk sh73a0_extal2_clk = {
|
|||
.rate = 48000000,
|
||||
};
|
||||
|
||||
/* A fixed divide-by-2 block */
|
||||
static unsigned long div2_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate / 2;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops div2_clk_ops = {
|
||||
.recalc = div2_recalc,
|
||||
};
|
||||
|
||||
static unsigned long div7_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate / 7;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops div7_clk_ops = {
|
||||
.recalc = div7_recalc,
|
||||
};
|
||||
|
||||
static unsigned long div13_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate / 13;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops div13_clk_ops = {
|
||||
.recalc = div13_recalc,
|
||||
};
|
||||
|
||||
/* Divide extal1 by two */
|
||||
static struct clk extal1_div2_clk = {
|
||||
.ops = &div2_clk_ops,
|
||||
.parent = &sh73a0_extal1_clk,
|
||||
};
|
||||
|
||||
/* Divide extal2 by two */
|
||||
static struct clk extal2_div2_clk = {
|
||||
.ops = &div2_clk_ops,
|
||||
.parent = &sh73a0_extal2_clk,
|
||||
};
|
||||
|
||||
static struct sh_clk_ops main_clk_ops = {
|
||||
.recalc = followparent_recalc,
|
||||
};
|
||||
|
||||
/* Main clock */
|
||||
static struct clk main_clk = {
|
||||
/* .parent wll be set on sh73a0_clock_init() */
|
||||
.ops = &main_clk_ops,
|
||||
};
|
||||
|
||||
/* Divide Main clock by two */
|
||||
static struct clk main_div2_clk = {
|
||||
.ops = &div2_clk_ops,
|
||||
.parent = &main_clk,
|
||||
};
|
||||
|
||||
/* PLL0, PLL1, PLL2, PLL3 */
|
||||
static unsigned long pll_recalc(struct clk *clk)
|
||||
{
|
||||
|
|
@ -192,21 +149,17 @@ static struct clk pll3_clk = {
|
|||
.enable_bit = 3,
|
||||
};
|
||||
|
||||
/* Divide PLL */
|
||||
static struct clk pll1_div2_clk = {
|
||||
.ops = &div2_clk_ops,
|
||||
.parent = &pll1_clk,
|
||||
};
|
||||
/* A fixed divide block */
|
||||
SH_CLK_RATIO(div2, 1, 2);
|
||||
SH_CLK_RATIO(div7, 1, 7);
|
||||
SH_CLK_RATIO(div13, 1, 13);
|
||||
|
||||
static struct clk pll1_div7_clk = {
|
||||
.ops = &div7_clk_ops,
|
||||
.parent = &pll1_clk,
|
||||
};
|
||||
|
||||
static struct clk pll1_div13_clk = {
|
||||
.ops = &div13_clk_ops,
|
||||
.parent = &pll1_clk,
|
||||
};
|
||||
SH_FIXED_RATIO_CLK(extal1_div2_clk, sh73a0_extal1_clk, div2);
|
||||
SH_FIXED_RATIO_CLK(extal2_div2_clk, sh73a0_extal2_clk, div2);
|
||||
SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2);
|
||||
SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
|
||||
SH_FIXED_RATIO_CLK(pll1_div7_clk, pll1_clk, div7);
|
||||
SH_FIXED_RATIO_CLK(pll1_div13_clk, pll1_clk, div13);
|
||||
|
||||
/* External input clock */
|
||||
struct clk sh73a0_extcki_clk = {
|
||||
|
|
@ -234,14 +187,24 @@ static struct clk *main_clks[] = {
|
|||
&sh73a0_extalr_clk,
|
||||
};
|
||||
|
||||
static int frqcr_kick(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* set KICK bit in FRQCRB to update hardware setting, check success */
|
||||
__raw_writel(__raw_readl(FRQCRB) | (1 << 31), FRQCRB);
|
||||
for (i = 1000; i; i--)
|
||||
if (__raw_readl(FRQCRB) & (1 << 31))
|
||||
cpu_relax();
|
||||
else
|
||||
return i;
|
||||
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static void div4_kick(struct clk *clk)
|
||||
{
|
||||
unsigned long value;
|
||||
|
||||
/* set KICK bit in FRQCRB to update hardware setting */
|
||||
value = __raw_readl(FRQCRB);
|
||||
value |= (1 << 31);
|
||||
__raw_writel(value, FRQCRB);
|
||||
frqcr_kick();
|
||||
}
|
||||
|
||||
static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
|
||||
|
|
@ -258,25 +221,37 @@ static struct clk_div4_table div4_table = {
|
|||
};
|
||||
|
||||
enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
|
||||
DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR };
|
||||
DIV4_Z, DIV4_ZX, DIV4_HP, DIV4_NR };
|
||||
|
||||
#define DIV4(_reg, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
|
||||
|
||||
static struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
|
||||
[DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
|
||||
[DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0),
|
||||
[DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
|
||||
[DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
|
||||
[DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0),
|
||||
[DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
|
||||
[DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0),
|
||||
};
|
||||
|
||||
static unsigned long twd_recalc(struct clk *clk)
|
||||
{
|
||||
return clk_get_rate(clk->parent) / 4;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops twd_clk_ops = {
|
||||
.recalc = twd_recalc,
|
||||
};
|
||||
|
||||
static struct clk twd_clk = {
|
||||
.parent = &div4_clks[DIV4_Z],
|
||||
.ops = &twd_clk_ops,
|
||||
};
|
||||
|
||||
enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
|
||||
DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
|
||||
DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
|
||||
|
|
@ -471,6 +446,7 @@ static struct clk dsi1phy_clk = {
|
|||
static struct clk *late_main_clks[] = {
|
||||
&dsi0phy_clk,
|
||||
&dsi1phy_clk,
|
||||
&twd_clk,
|
||||
};
|
||||
|
||||
enum { MSTP001,
|
||||
|
|
@ -535,6 +511,7 @@ static struct clk mstp_clks[MSTP_NR] = {
|
|||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("r_clk", &r_clk),
|
||||
CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
|
||||
|
||||
/* DIV6 clocks */
|
||||
CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
|
||||
|
|
@ -581,10 +558,13 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
|
||||
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
|
||||
CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
|
||||
CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
|
||||
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
|
||||
CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
|
||||
CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */
|
||||
CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */
|
||||
CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */
|
||||
CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */
|
||||
|
|
|
|||
|
|
@ -23,6 +23,19 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/export.h>
|
||||
#include <mach/clock.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk)
|
||||
{
|
||||
struct clk_ratio *p = clk->priv;
|
||||
|
||||
return clk->parent->rate / p->div * p->mul;
|
||||
};
|
||||
|
||||
struct sh_clk_ops shmobile_fixed_ratio_clk_ops = {
|
||||
.recalc = shmobile_fixed_ratio_clk_recalc,
|
||||
};
|
||||
|
||||
int __init shmobile_clk_init(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SMP support for SoC sh73a0
|
||||
* Shared SCU setup for mach-shmobile
|
||||
*
|
||||
* Copyright (C) 2012 Bastian Hecht
|
||||
*
|
||||
|
|
@ -35,11 +35,12 @@
|
|||
* the physical address as the MMU is still turned off.
|
||||
*/
|
||||
.align 12
|
||||
ENTRY(sh73a0_secondary_vector)
|
||||
ENTRY(shmobile_secondary_vector_scu)
|
||||
mrc p15, 0, r0, c0, c0, 5 @ read MIPDR
|
||||
and r0, r0, #3 @ mask out cpu ID
|
||||
lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits
|
||||
mov r1, #0xf0000000 @ SCU base address
|
||||
ldr r1, 2f
|
||||
ldr r1, [r1] @ SCU base address
|
||||
ldr r2, [r1, #8] @ SCU Power Status Register
|
||||
mov r3, #3
|
||||
bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode)
|
||||
|
|
@ -47,4 +48,10 @@ ENTRY(sh73a0_secondary_vector)
|
|||
|
||||
ldr pc, 1f
|
||||
1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
|
||||
ENDPROC(sh73a0_secondary_vector)
|
||||
2: .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET
|
||||
ENDPROC(shmobile_secondary_vector_scu)
|
||||
|
||||
.text
|
||||
.globl shmobile_scu_base
|
||||
shmobile_scu_base:
|
||||
.space 4
|
||||
|
|
@ -1,68 +0,0 @@
|
|||
/*
|
||||
* SMP support for R-Mobile / SH-Mobile
|
||||
*
|
||||
* Copyright (C) 2010 Magnus Damm
|
||||
*
|
||||
* Based on realview, Copyright (C) 2002 ARM Ltd, All Rights Reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/cpumask.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/of.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/r8a7779.h>
|
||||
#include <mach/emev2.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
static cpumask_t dead_cpus;
|
||||
|
||||
void shmobile_cpu_die(unsigned int cpu)
|
||||
{
|
||||
/* hardware shutdown code running on the CPU that is being offlined */
|
||||
flush_cache_all();
|
||||
dsb();
|
||||
|
||||
/* notify platform_cpu_kill() that hardware shutdown is finished */
|
||||
cpumask_set_cpu(cpu, &dead_cpus);
|
||||
|
||||
/* wait for SoC code in platform_cpu_kill() to shut off CPU core
|
||||
* power. CPU bring up starts from the reset vector.
|
||||
*/
|
||||
while (1) {
|
||||
/*
|
||||
* here's the WFI
|
||||
*/
|
||||
asm(".word 0xe320f003\n"
|
||||
:
|
||||
:
|
||||
: "memory", "cc");
|
||||
}
|
||||
}
|
||||
|
||||
int shmobile_cpu_disable(unsigned int cpu)
|
||||
{
|
||||
cpumask_clear_cpu(cpu, &dead_cpus);
|
||||
/*
|
||||
* we don't allow CPU 0 to be shutdown (it is still too special
|
||||
* e.g. clock tick interrupts)
|
||||
*/
|
||||
return cpu == 0 ? -EPERM : 0;
|
||||
}
|
||||
|
||||
int shmobile_cpu_disable_any(unsigned int cpu)
|
||||
{
|
||||
cpumask_clear_cpu(cpu, &dead_cpus);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int shmobile_cpu_is_dead(unsigned int cpu)
|
||||
{
|
||||
return cpumask_test_cpu(cpu, &dead_cpus);
|
||||
}
|
||||
39
arch/arm/mach-shmobile/include/mach/clock.h
Normal file
39
arch/arm/mach-shmobile/include/mach/clock.h
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
#ifndef CLOCK_H
|
||||
#define CLOCK_H
|
||||
|
||||
unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk);
|
||||
extern struct sh_clk_ops shmobile_fixed_ratio_clk_ops;
|
||||
|
||||
/* clock ratio */
|
||||
struct clk_ratio {
|
||||
int mul;
|
||||
int div;
|
||||
};
|
||||
|
||||
#define SH_CLK_RATIO(name, m, d) \
|
||||
static struct clk_ratio name ##_ratio = { \
|
||||
.mul = m, \
|
||||
.div = d, \
|
||||
}
|
||||
|
||||
#define SH_FIXED_RATIO_CLKg(name, p, r) \
|
||||
struct clk name = { \
|
||||
.parent = &p, \
|
||||
.ops = &shmobile_fixed_ratio_clk_ops,\
|
||||
.priv = &r ## _ratio, \
|
||||
}
|
||||
|
||||
#define SH_FIXED_RATIO_CLK(name, p, r) \
|
||||
static SH_FIXED_RATIO_CLKg(name, p, r);
|
||||
|
||||
#define SH_FIXED_RATIO_CLK_SET(name, p, m, d) \
|
||||
SH_CLK_RATIO(name, m, d); \
|
||||
SH_FIXED_RATIO_CLK(name, p, name);
|
||||
|
||||
#define SH_CLK_SET_RATIO(p, m, d) \
|
||||
{ \
|
||||
(p)->mul = m; \
|
||||
(p)->div = d; \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -8,6 +8,7 @@ extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
|
|||
struct twd_local_timer;
|
||||
extern void shmobile_setup_console(void);
|
||||
extern void shmobile_secondary_vector(void);
|
||||
extern void shmobile_secondary_vector_scu(void);
|
||||
struct clk;
|
||||
extern int shmobile_clk_init(void);
|
||||
extern void shmobile_handle_irq_intc(struct pt_regs *);
|
||||
|
|
@ -18,58 +19,6 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev,
|
|||
struct cpuidle_driver *drv, int index);
|
||||
extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
|
||||
|
||||
extern void sh7372_init_irq(void);
|
||||
extern void sh7372_map_io(void);
|
||||
extern void sh7372_earlytimer_init(void);
|
||||
extern void sh7372_add_early_devices(void);
|
||||
extern void sh7372_add_standard_devices(void);
|
||||
extern void sh7372_add_early_devices_dt(void);
|
||||
extern void sh7372_add_standard_devices_dt(void);
|
||||
extern void sh7372_clock_init(void);
|
||||
extern void sh7372_pinmux_init(void);
|
||||
extern void sh7372_pm_init(void);
|
||||
extern void sh7372_resume_core_standby_sysc(void);
|
||||
extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
|
||||
extern struct clk sh7372_extal1_clk;
|
||||
extern struct clk sh7372_extal2_clk;
|
||||
|
||||
extern void sh73a0_init_irq(void);
|
||||
extern void sh73a0_init_irq_dt(void);
|
||||
extern void sh73a0_map_io(void);
|
||||
extern void sh73a0_earlytimer_init(void);
|
||||
extern void sh73a0_add_early_devices(void);
|
||||
extern void sh73a0_add_early_devices_dt(void);
|
||||
extern void sh73a0_add_standard_devices(void);
|
||||
extern void sh73a0_add_standard_devices_dt(void);
|
||||
extern void sh73a0_clock_init(void);
|
||||
extern void sh73a0_pinmux_init(void);
|
||||
extern void sh73a0_pm_init(void);
|
||||
extern void sh73a0_secondary_vector(void);
|
||||
extern struct clk sh73a0_extal1_clk;
|
||||
extern struct clk sh73a0_extal2_clk;
|
||||
extern struct clk sh73a0_extcki_clk;
|
||||
extern struct clk sh73a0_extalr_clk;
|
||||
|
||||
extern void r8a7740_init_irq(void);
|
||||
extern void r8a7740_map_io(void);
|
||||
extern void r8a7740_add_early_devices(void);
|
||||
extern void r8a7740_add_standard_devices(void);
|
||||
extern void r8a7740_clock_init(u8 md_ck);
|
||||
extern void r8a7740_pinmux_init(void);
|
||||
extern void r8a7740_pm_init(void);
|
||||
|
||||
extern void r8a7779_init_irq(void);
|
||||
extern void r8a7779_map_io(void);
|
||||
extern void r8a7779_earlytimer_init(void);
|
||||
extern void r8a7779_add_early_devices(void);
|
||||
extern void r8a7779_add_standard_devices(void);
|
||||
extern void r8a7779_clock_init(void);
|
||||
extern void r8a7779_pinmux_init(void);
|
||||
extern void r8a7779_pm_init(void);
|
||||
extern void r8a7740_meram_workaround(void);
|
||||
|
||||
extern void r8a7779_register_twd(void);
|
||||
|
||||
#ifdef CONFIG_SUSPEND
|
||||
int shmobile_suspend_init(void);
|
||||
#else
|
||||
|
|
@ -82,16 +31,7 @@ int shmobile_cpuidle_init(void);
|
|||
static inline int shmobile_cpuidle_init(void) { return 0; }
|
||||
#endif
|
||||
|
||||
extern void shmobile_cpu_die(unsigned int cpu);
|
||||
extern int shmobile_cpu_disable(unsigned int cpu);
|
||||
extern int shmobile_cpu_disable_any(unsigned int cpu);
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
extern int shmobile_cpu_is_dead(unsigned int cpu);
|
||||
#else
|
||||
static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; }
|
||||
#endif
|
||||
|
||||
extern void __iomem *shmobile_scu_base;
|
||||
extern void shmobile_smp_init_cpus(unsigned int ncores);
|
||||
|
||||
static inline void __init shmobile_init_late(void)
|
||||
|
|
|
|||
|
|
@ -5,10 +5,15 @@
|
|||
|
||||
/* GIC */
|
||||
#define gic_spi(nr) ((nr) + 32)
|
||||
#define gic_iid(nr) (nr) /* ICCIAR / interrupt ID */
|
||||
|
||||
/* INTCS */
|
||||
#define INTCS_VECT_BASE 0x3400
|
||||
#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect))
|
||||
#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt))
|
||||
|
||||
/* External IRQ pins */
|
||||
#define IRQPIN_BASE 2000
|
||||
#define irq_pin(nr) ((nr) + IRQPIN_BASE)
|
||||
|
||||
#endif /* __ASM_MACH_IRQS_H */
|
||||
|
|
|
|||
8
arch/arm/mach-shmobile/include/mach/r8a73a4.h
Normal file
8
arch/arm/mach-shmobile/include/mach/r8a73a4.h
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
#ifndef __ASM_R8A73A4_H__
|
||||
#define __ASM_R8A73A4_H__
|
||||
|
||||
void r8a73a4_add_standard_devices(void);
|
||||
void r8a73a4_clock_init(void);
|
||||
void r8a73a4_pinmux_init(void);
|
||||
|
||||
#endif /* __ASM_R8A73A4_H__ */
|
||||
|
|
@ -241,48 +241,9 @@ enum {
|
|||
|
||||
/* LCD0 */
|
||||
GPIO_FN_LCDC0_SELECT,
|
||||
GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2,
|
||||
GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5,
|
||||
GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8,
|
||||
GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11,
|
||||
GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14,
|
||||
GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17,
|
||||
GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC,
|
||||
|
||||
GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */
|
||||
GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */
|
||||
|
||||
GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */
|
||||
GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */
|
||||
|
||||
GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162,
|
||||
GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158,
|
||||
GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159,
|
||||
GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */
|
||||
|
||||
GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4,
|
||||
GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2,
|
||||
GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1,
|
||||
GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */
|
||||
|
||||
/* LCD1 */
|
||||
GPIO_FN_LCDC1_SELECT,
|
||||
GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2,
|
||||
GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5,
|
||||
GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8,
|
||||
GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11,
|
||||
GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14,
|
||||
GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17,
|
||||
GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20,
|
||||
GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23,
|
||||
GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC,
|
||||
GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC,
|
||||
|
||||
GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */
|
||||
GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */
|
||||
|
||||
GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */
|
||||
GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */
|
||||
|
||||
/* RSPI */
|
||||
GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
|
||||
|
|
@ -346,26 +307,6 @@ enum {
|
|||
GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
|
||||
GPIO_FN_SIM_D_PORT199,
|
||||
|
||||
/* SDHI0 */
|
||||
GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2,
|
||||
GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP,
|
||||
GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK,
|
||||
|
||||
/* SDHI1 */
|
||||
GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2,
|
||||
GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP,
|
||||
GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK,
|
||||
|
||||
/* SDHI2 */
|
||||
GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2,
|
||||
GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD,
|
||||
|
||||
GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
|
||||
GPIO_FN_SDHI2_WP_PORT25,
|
||||
|
||||
GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
|
||||
GPIO_FN_SDHI2_CD_PORT202,
|
||||
|
||||
/* MSIOF2 */
|
||||
GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
|
||||
GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
|
||||
|
|
@ -417,21 +358,6 @@ enum {
|
|||
GPIO_FN_MEMC_DREQ1,
|
||||
GPIO_FN_MEMC_A0,
|
||||
|
||||
/* MMC */
|
||||
GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69,
|
||||
GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71,
|
||||
GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73,
|
||||
GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75,
|
||||
GPIO_FN_MMC0_CLK_PORT66,
|
||||
GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */
|
||||
|
||||
GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148,
|
||||
GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146,
|
||||
GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144,
|
||||
GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142,
|
||||
GPIO_FN_MMC1_CLK_PORT103,
|
||||
GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */
|
||||
|
||||
/* MSIOF0 */
|
||||
GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
|
||||
GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
|
||||
|
|
@ -606,6 +532,15 @@ enum {
|
|||
SHDMA_SLAVE_USBHS_RX,
|
||||
};
|
||||
|
||||
extern void r8a7740_meram_workaround(void);
|
||||
extern void r8a7740_init_irq(void);
|
||||
extern void r8a7740_map_io(void);
|
||||
extern void r8a7740_add_early_devices(void);
|
||||
extern void r8a7740_add_standard_devices(void);
|
||||
extern void r8a7740_clock_init(u8 md_ck);
|
||||
extern void r8a7740_pinmux_init(void);
|
||||
extern void r8a7740_pm_init(void);
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
extern void __init r8a7740_init_pm_domains(void);
|
||||
#else
|
||||
|
|
|
|||
28
arch/arm/mach-shmobile/include/mach/r8a7778.h
Normal file
28
arch/arm/mach-shmobile/include/mach/r8a7778.h
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#ifndef __ASM_R8A7778_H__
|
||||
#define __ASM_R8A7778_H__
|
||||
|
||||
extern void r8a7778_add_standard_devices(void);
|
||||
extern void r8a7778_add_standard_devices_dt(void);
|
||||
extern void r8a7778_init_delay(void);
|
||||
extern void r8a7778_init_irq(void);
|
||||
extern void r8a7778_init_irq_dt(void);
|
||||
extern void r8a7778_clock_init(void);
|
||||
|
||||
#endif /* __ASM_R8A7778_H__ */
|
||||
|
|
@ -4,327 +4,6 @@
|
|||
#include <linux/sh_clk.h>
|
||||
#include <linux/pm_domain.h>
|
||||
|
||||
/* Pin Function Controller:
|
||||
* GPIO_FN_xx - GPIO used to select pin function
|
||||
* GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
|
||||
*/
|
||||
enum {
|
||||
GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
|
||||
GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
|
||||
GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
|
||||
GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
|
||||
GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
|
||||
GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
|
||||
GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
|
||||
GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
|
||||
|
||||
GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
|
||||
GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
|
||||
GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
|
||||
GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
|
||||
GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
|
||||
GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
|
||||
GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
|
||||
GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
|
||||
|
||||
GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
|
||||
GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
|
||||
GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
|
||||
GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
|
||||
GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
|
||||
GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
|
||||
GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
|
||||
GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
|
||||
|
||||
GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
|
||||
GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
|
||||
GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
|
||||
GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
|
||||
GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
|
||||
GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
|
||||
GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
|
||||
GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
|
||||
|
||||
GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
|
||||
GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
|
||||
GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
|
||||
GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
|
||||
GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
|
||||
GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
|
||||
GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
|
||||
GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
|
||||
|
||||
GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
|
||||
GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
|
||||
GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
|
||||
GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
|
||||
GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
|
||||
GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
|
||||
GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
|
||||
GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
|
||||
|
||||
GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
|
||||
GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
|
||||
GPIO_GP_6_8,
|
||||
|
||||
GPIO_FN_AVS1, GPIO_FN_AVS2, GPIO_FN_A17, GPIO_FN_A18,
|
||||
GPIO_FN_A19,
|
||||
|
||||
/* IPSR0 */
|
||||
GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
|
||||
GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
|
||||
GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
|
||||
GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
|
||||
GPIO_FN_MMC0_D3, GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D,
|
||||
GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B,
|
||||
GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0,
|
||||
GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1,
|
||||
GPIO_FN_A24, GPIO_FN_SD1_CD, GPIO_FN_MMC0_D4, GPIO_FN_FD4,
|
||||
GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
|
||||
GPIO_FN_SD1_WP, GPIO_FN_MMC0_D5, GPIO_FN_FD5, GPIO_FN_HSPI_RX2,
|
||||
GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B,
|
||||
GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0,
|
||||
GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2,
|
||||
GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
|
||||
GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C,
|
||||
|
||||
/* IPSR1 */
|
||||
GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, GPIO_FN_MMC0_D6,
|
||||
GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_MMC0_D7, GPIO_FN_FD7,
|
||||
GPIO_FN_EX_CS2, GPIO_FN_SD1_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_FALE,
|
||||
GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_SD1_CMD, GPIO_FN_MMC0_CMD,
|
||||
GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B,
|
||||
GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B,
|
||||
GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_SD1_DAT0, GPIO_FN_MMC0_D0,
|
||||
GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B,
|
||||
GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9,
|
||||
GPIO_FN_EX_CS5, GPIO_FN_SD1_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FD1,
|
||||
GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E,
|
||||
GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
|
||||
GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4,
|
||||
GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_RX4, GPIO_FN_HTX0,
|
||||
GPIO_FN_TX1, GPIO_FN_SDATA, GPIO_FN_CTS0_C, GPIO_FN_SUB_TCK,
|
||||
GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
|
||||
GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
|
||||
|
||||
/* IPSR2 */
|
||||
GPIO_FN_HRX0, GPIO_FN_RX1, GPIO_FN_SCKZ, GPIO_FN_RTS0_C_TANS_C,
|
||||
GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
|
||||
GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
|
||||
GPIO_FN_HSCK0, GPIO_FN_SCK1, GPIO_FN_MTS, GPIO_FN_PWM5,
|
||||
GPIO_FN_SCK0_C, GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
|
||||
GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
|
||||
GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, GPIO_FN_CTS1,
|
||||
GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_RX0_C, GPIO_FN_SCIF_CLK_C,
|
||||
GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
|
||||
GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS,
|
||||
GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
|
||||
GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_DU0_DR0,
|
||||
GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
|
||||
GPIO_FN_TX5_C, GPIO_FN_DU0_DR1, GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
|
||||
GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C,
|
||||
GPIO_FN_DU0_DR2, GPIO_FN_LCDOUT2, GPIO_FN_DU0_DR3, GPIO_FN_LCDOUT3,
|
||||
GPIO_FN_DU0_DR4, GPIO_FN_LCDOUT4, GPIO_FN_DU0_DR5, GPIO_FN_LCDOUT5,
|
||||
GPIO_FN_DU0_DR6, GPIO_FN_LCDOUT6, GPIO_FN_DU0_DR7, GPIO_FN_LCDOUT7,
|
||||
GPIO_FN_DU0_DG0, GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
|
||||
GPIO_FN_AUDATA2,
|
||||
|
||||
/* IPSR3 */
|
||||
GPIO_FN_DU0_DG1, GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
|
||||
GPIO_FN_AUDATA3, GPIO_FN_DU0_DG2, GPIO_FN_LCDOUT10, GPIO_FN_DU0_DG3,
|
||||
GPIO_FN_LCDOUT11, GPIO_FN_DU0_DG4, GPIO_FN_LCDOUT12, GPIO_FN_DU0_DG5,
|
||||
GPIO_FN_LCDOUT13, GPIO_FN_DU0_DG6, GPIO_FN_LCDOUT14, GPIO_FN_DU0_DG7,
|
||||
GPIO_FN_LCDOUT15, GPIO_FN_DU0_DB0, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
|
||||
GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_DU0_DB1,
|
||||
GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
|
||||
GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_DU0_DB2, GPIO_FN_LCDOUT18,
|
||||
GPIO_FN_DU0_DB3, GPIO_FN_LCDOUT19, GPIO_FN_DU0_DB4, GPIO_FN_LCDOUT20,
|
||||
GPIO_FN_DU0_DB5, GPIO_FN_LCDOUT21, GPIO_FN_DU0_DB6, GPIO_FN_LCDOUT22,
|
||||
GPIO_FN_DU0_DB7, GPIO_FN_LCDOUT23, GPIO_FN_DU0_DOTCLKIN,
|
||||
GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B,
|
||||
GPIO_FN_DU0_DOTCLKOUT0, GPIO_FN_QCLK, GPIO_FN_DU0_DOTCLKOUT1,
|
||||
GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B,
|
||||
GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
|
||||
GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_QSTH_QHS,
|
||||
GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE,
|
||||
GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
|
||||
GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
|
||||
|
||||
/* IPSR4 */
|
||||
GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C,
|
||||
GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C,
|
||||
GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_DU1_DR0,
|
||||
GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK,
|
||||
GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
|
||||
GPIO_FN_DU1_DR1, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
|
||||
GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC,
|
||||
GPIO_FN_CTS0_D, GPIO_FN_DU1_DR2, GPIO_FN_VI2_G0, GPIO_FN_DU1_DR3,
|
||||
GPIO_FN_VI2_G1, GPIO_FN_DU1_DR4, GPIO_FN_VI2_G2, GPIO_FN_DU1_DR5,
|
||||
GPIO_FN_VI2_G3, GPIO_FN_DU1_DR6, GPIO_FN_VI2_G4, GPIO_FN_DU1_DR7,
|
||||
GPIO_FN_VI2_G5, GPIO_FN_DU1_DG0, GPIO_FN_VI2_DATA2_VI2_B2,
|
||||
GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6,
|
||||
GPIO_FN_TX0_D, GPIO_FN_DU1_DG1, GPIO_FN_VI2_DATA3_VI2_B3,
|
||||
GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7,
|
||||
GPIO_FN_RX0_D, GPIO_FN_DU1_DG2, GPIO_FN_VI2_G6, GPIO_FN_DU1_DG3,
|
||||
GPIO_FN_VI2_G7, GPIO_FN_DU1_DG4, GPIO_FN_VI2_R0, GPIO_FN_DU1_DG5,
|
||||
GPIO_FN_VI2_R1, GPIO_FN_DU1_DG6, GPIO_FN_VI2_R2, GPIO_FN_DU1_DG7,
|
||||
GPIO_FN_VI2_R3, GPIO_FN_DU1_DB0, GPIO_FN_VI2_DATA4_VI2_B4,
|
||||
GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D,
|
||||
|
||||
/* IPSR5 */
|
||||
GPIO_FN_DU1_DB1, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
|
||||
GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D,
|
||||
GPIO_FN_DU1_DB2, GPIO_FN_VI2_R4, GPIO_FN_DU1_DB3, GPIO_FN_VI2_R5,
|
||||
GPIO_FN_DU1_DB4, GPIO_FN_VI2_R6, GPIO_FN_DU1_DB5, GPIO_FN_VI2_R7,
|
||||
GPIO_FN_DU1_DB6, GPIO_FN_SCL2_D, GPIO_FN_DU1_DB7, GPIO_FN_SDA2_D,
|
||||
GPIO_FN_DU1_DOTCLKIN, GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1,
|
||||
GPIO_FN_SCL1_D, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_VI2_FIELD,
|
||||
GPIO_FN_SDA1_D, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_VI2_HSYNC,
|
||||
GPIO_FN_VI3_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_VI2_VSYNC,
|
||||
GPIO_FN_VI3_VSYNC, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
|
||||
GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD,
|
||||
GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
|
||||
GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN,
|
||||
GPIO_FN_GPS_SIGN_D, GPIO_FN_DU1_DISP, GPIO_FN_VI2_DATA6_VI2_B6,
|
||||
GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1,
|
||||
GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
|
||||
GPIO_FN_DU1_CDE, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B,
|
||||
GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
|
||||
GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C,
|
||||
GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
|
||||
GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0,
|
||||
GPIO_FN_MOUT0,
|
||||
|
||||
/* IPSR6 */
|
||||
GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_MOUT1,
|
||||
GPIO_FN_SSI_WS0129, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_MOUT2,
|
||||
GPIO_FN_SSI_SDATA0, GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_MOUT5,
|
||||
GPIO_FN_SSI_SDATA1, GPIO_FN_CAN_DEBUGOUT4, GPIO_FN_MOUT6,
|
||||
GPIO_FN_SSI_SDATA2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK34,
|
||||
GPIO_FN_CAN_DEBUGOUT6, GPIO_FN_CAN0_TX_B, GPIO_FN_IERX,
|
||||
GPIO_FN_SSI_SCK9_C, GPIO_FN_SSI_WS34, GPIO_FN_CAN_DEBUGOUT7,
|
||||
GPIO_FN_CAN0_RX_B, GPIO_FN_IETX, GPIO_FN_SSI_WS9_C,
|
||||
GPIO_FN_SSI_SDATA3, GPIO_FN_PWM0_C, GPIO_FN_CAN_DEBUGOUT8,
|
||||
GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
|
||||
GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
|
||||
GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
|
||||
GPIO_FN_SCK3, GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
|
||||
GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_TX3_IRDA_TX, GPIO_FN_SSI_SDATA5,
|
||||
GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_RX3_IRDA_RX,
|
||||
GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
|
||||
|
||||
/* IPSR7 */
|
||||
GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
|
||||
GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
|
||||
GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B,
|
||||
GPIO_FN_SSI_SCK9_B, GPIO_FN_HSPI_CLK1_C, GPIO_FN_SSI_WS78,
|
||||
GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B,
|
||||
GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
|
||||
GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C,
|
||||
GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C,
|
||||
GPIO_FN_SD0_CLK, GPIO_FN_ATACS01, GPIO_FN_SCK1_B, GPIO_FN_SD0_CMD,
|
||||
GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, GPIO_FN_SD0_DAT0,
|
||||
GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, GPIO_FN_SD0_DAT1,
|
||||
GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, GPIO_FN_SD0_DAT2,
|
||||
GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, GPIO_FN_SD0_DAT3,
|
||||
GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, GPIO_FN_SD0_CD,
|
||||
GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_SD0_WP, GPIO_FN_DACK2,
|
||||
GPIO_FN_CTS1_B,
|
||||
|
||||
/* IPSR8 */
|
||||
GPIO_FN_HSPI_CLK0, GPIO_FN_CTS0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
|
||||
GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
|
||||
GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0,
|
||||
GPIO_FN_RTS0_TANS, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI,
|
||||
GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
|
||||
GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0,
|
||||
GPIO_FN_TX0, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
|
||||
GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
|
||||
GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0,
|
||||
GPIO_FN_RX0, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
|
||||
GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
|
||||
GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
|
||||
GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
|
||||
GPIO_FN_VI0_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C,
|
||||
GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C,
|
||||
GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
|
||||
GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_MMC1_CMD, GPIO_FN_HSCK1_B,
|
||||
GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
|
||||
GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C,
|
||||
|
||||
/* IPSR9 */
|
||||
GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
|
||||
GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
|
||||
GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_MMC1_D0, GPIO_FN_VI0_DATA3_VI0_B3,
|
||||
GPIO_FN_MMC1_D1, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_MMC1_D2,
|
||||
GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_MMC1_D3, GPIO_FN_VI0_DATA6_VI0_B6,
|
||||
GPIO_FN_MMC1_D4, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
|
||||
GPIO_FN_MMC1_D5, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
|
||||
GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2,
|
||||
GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1,
|
||||
GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
|
||||
GPIO_FN_MMC1_D6, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
|
||||
GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_MMC1_D7,
|
||||
GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
|
||||
GPIO_FN_ETH_TX_EN, GPIO_FN_SD2_DAT0_B, GPIO_FN_ARM_TRACEDATA_6,
|
||||
GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_SD2_DAT1_B,
|
||||
GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
|
||||
GPIO_FN_SD2_DAT2_B, GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
|
||||
GPIO_FN_ETH_RXD1, GPIO_FN_SD2_DAT3_B, GPIO_FN_ARM_TRACEDATA_9,
|
||||
|
||||
/* IPSR10 */
|
||||
GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B,
|
||||
GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
|
||||
GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
|
||||
GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
|
||||
GPIO_FN_SD2_CLK_B, GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12,
|
||||
GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_SD2_CMD_B, GPIO_FN_IRQ3,
|
||||
GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
|
||||
GPIO_FN_SD2_CD_B, GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14,
|
||||
GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
|
||||
GPIO_FN_SD2_WP_B, GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15,
|
||||
GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
|
||||
GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK,
|
||||
GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
|
||||
GPIO_FN_DACK2_C, GPIO_FN_HSPI_RX1_B, GPIO_FN_SCIF_CLK_D,
|
||||
GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
|
||||
GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
|
||||
GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
|
||||
GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_SSI_WS4, GPIO_FN_SIM_CLK,
|
||||
GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
|
||||
|
||||
/* IPSR11 */
|
||||
GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SD2_DAT0, GPIO_FN_SIM_RST,
|
||||
GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
|
||||
GPIO_FN_SD2_DAT1, GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
|
||||
GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SD2_DAT2,
|
||||
GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
|
||||
GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SD2_DAT3, GPIO_FN_MT0_BEN,
|
||||
GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
|
||||
GPIO_FN_SD2_CLK, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
|
||||
GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
|
||||
GPIO_FN_SD2_CMD, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
|
||||
GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
|
||||
GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
|
||||
GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM,
|
||||
GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
|
||||
GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2,
|
||||
GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
|
||||
GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2,
|
||||
GPIO_FN_HRTS0_B,
|
||||
|
||||
/* IPSR12 */
|
||||
GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
|
||||
GPIO_FN_SCK2, GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
|
||||
GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
|
||||
GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
|
||||
GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
|
||||
GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_TX4_B, GPIO_FN_SIM_D_B,
|
||||
GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
|
||||
GPIO_FN_RX4_B, GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
|
||||
GPIO_FN_GPS_MAG, GPIO_FN_FCE, GPIO_FN_SCK4_B,
|
||||
};
|
||||
|
||||
struct platform_device;
|
||||
|
||||
struct r8a7779_pm_ch {
|
||||
|
|
@ -343,6 +22,19 @@ static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
|
|||
return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
|
||||
}
|
||||
|
||||
extern void r8a7779_init_delay(void);
|
||||
extern void r8a7779_init_irq(void);
|
||||
extern void r8a7779_init_irq_extpin(int irlm);
|
||||
extern void r8a7779_init_irq_dt(void);
|
||||
extern void r8a7779_map_io(void);
|
||||
extern void r8a7779_earlytimer_init(void);
|
||||
extern void r8a7779_add_early_devices(void);
|
||||
extern void r8a7779_add_standard_devices(void);
|
||||
extern void r8a7779_add_standard_devices_dt(void);
|
||||
extern void r8a7779_clock_init(void);
|
||||
extern void r8a7779_pinmux_init(void);
|
||||
extern void r8a7779_pm_init(void);
|
||||
extern void r8a7779_register_twd(void);
|
||||
extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch);
|
||||
extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch);
|
||||
|
||||
|
|
|
|||
8
arch/arm/mach-shmobile/include/mach/r8a7790.h
Normal file
8
arch/arm/mach-shmobile/include/mach/r8a7790.h
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
#ifndef __ASM_R8A7790_H__
|
||||
#define __ASM_R8A7790_H__
|
||||
|
||||
void r8a7790_add_standard_devices(void);
|
||||
void r8a7790_clock_init(void);
|
||||
void r8a7790_pinmux_init(void);
|
||||
|
||||
#endif /* __ASM_R8A7790_H__ */
|
||||
|
|
@ -294,21 +294,6 @@ enum {
|
|||
GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, GPIO_FN_D14_NAF14,
|
||||
GPIO_FN_D15_NAF15,
|
||||
|
||||
/*
|
||||
* MMCIF(1) (PORT 84, 85, 86, 87, 88, 89,
|
||||
* 90, 91, 92, 99)
|
||||
*/
|
||||
GPIO_FN_MMCD0_0, GPIO_FN_MMCD0_1, GPIO_FN_MMCD0_2,
|
||||
GPIO_FN_MMCD0_3, GPIO_FN_MMCD0_4, GPIO_FN_MMCD0_5,
|
||||
GPIO_FN_MMCD0_6, GPIO_FN_MMCD0_7,
|
||||
GPIO_FN_MMCCMD0, GPIO_FN_MMCCLK0,
|
||||
|
||||
/* MMCIF(2) (PORT 54, 55, 56, 57, 58, 59, 60, 61, 66, 67) */
|
||||
GPIO_FN_MMCD1_0, GPIO_FN_MMCD1_1, GPIO_FN_MMCD1_2,
|
||||
GPIO_FN_MMCD1_3, GPIO_FN_MMCD1_4, GPIO_FN_MMCD1_5,
|
||||
GPIO_FN_MMCD1_6, GPIO_FN_MMCD1_7,
|
||||
GPIO_FN_MMCCLK1, GPIO_FN_MMCCMD1,
|
||||
|
||||
/* SPU2 (PORT 65) */
|
||||
GPIO_FN_VINT_I,
|
||||
|
||||
|
|
@ -416,20 +401,6 @@ enum {
|
|||
/* HDMI (PORT 169, 170) */
|
||||
GPIO_FN_HDMI_HPD, GPIO_FN_HDMI_CEC,
|
||||
|
||||
/* SDHI0 (PORT 171, 172, 173, 174, 175, 176, 177, 178) */
|
||||
GPIO_FN_SDHICLK0, GPIO_FN_SDHICD0,
|
||||
GPIO_FN_SDHICMD0, GPIO_FN_SDHIWP0,
|
||||
GPIO_FN_SDHID0_0, GPIO_FN_SDHID0_1,
|
||||
GPIO_FN_SDHID0_2, GPIO_FN_SDHID0_3,
|
||||
|
||||
/* SDHI1 (PORT 179, 180, 181, 182, 183, 184) */
|
||||
GPIO_FN_SDHICLK1, GPIO_FN_SDHICMD1, GPIO_FN_SDHID1_0,
|
||||
GPIO_FN_SDHID1_1, GPIO_FN_SDHID1_2, GPIO_FN_SDHID1_3,
|
||||
|
||||
/* SDHI2 (PORT 185, 186, 187, 188, 189, 190) */
|
||||
GPIO_FN_SDHICLK2, GPIO_FN_SDHICMD2, GPIO_FN_SDHID2_0,
|
||||
GPIO_FN_SDHID2_1, GPIO_FN_SDHID2_2, GPIO_FN_SDHID2_3,
|
||||
|
||||
/* SDENC see MSEL4CR 19 */
|
||||
GPIO_FN_SDENC_CPG,
|
||||
GPIO_FN_SDENC_DV_CLKI,
|
||||
|
|
@ -478,6 +449,18 @@ extern struct clk sh7372_dv_clki_clk;
|
|||
extern struct clk sh7372_dv_clki_div2_clk;
|
||||
extern struct clk sh7372_pllc2_clk;
|
||||
|
||||
extern void sh7372_init_irq(void);
|
||||
extern void sh7372_map_io(void);
|
||||
extern void sh7372_earlytimer_init(void);
|
||||
extern void sh7372_add_early_devices(void);
|
||||
extern void sh7372_add_standard_devices(void);
|
||||
extern void sh7372_add_early_devices_dt(void);
|
||||
extern void sh7372_add_standard_devices_dt(void);
|
||||
extern void sh7372_clock_init(void);
|
||||
extern void sh7372_pinmux_init(void);
|
||||
extern void sh7372_pm_init(void);
|
||||
extern void sh7372_resume_core_standby_sysc(void);
|
||||
extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
|
||||
extern void sh7372_intcs_suspend(void);
|
||||
extern void sh7372_intcs_resume(void);
|
||||
extern void sh7372_intca_suspend(void);
|
||||
|
|
|
|||
|
|
@ -94,8 +94,7 @@ enum {
|
|||
GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
|
||||
|
||||
/* Table 25-1 (Function 0-7) */
|
||||
GPIO_FN_VBUS_0,
|
||||
GPIO_FN_GPI0,
|
||||
GPIO_FN_GPI0 = 310,
|
||||
GPIO_FN_GPI1,
|
||||
GPIO_FN_GPI2,
|
||||
GPIO_FN_GPI3,
|
||||
|
|
@ -103,15 +102,11 @@ enum {
|
|||
GPIO_FN_GPI5,
|
||||
GPIO_FN_GPI6,
|
||||
GPIO_FN_GPI7,
|
||||
GPIO_FN_SCIFA7_RXD,
|
||||
GPIO_FN_SCIFA7_CTS_,
|
||||
GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
|
||||
GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
|
||||
GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \
|
||||
GPIO_FN_GPO5,
|
||||
GPIO_FN_PORT16_VIO_CKOR,
|
||||
GPIO_FN_SCIFA0_TXD,
|
||||
GPIO_FN_SCIFA7_TXD,
|
||||
GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
|
||||
GPIO_FN_PORT19_VIO_CKO2,
|
||||
GPIO_FN_GPO0,
|
||||
GPIO_FN_GPO1,
|
||||
GPIO_FN_GPO2, GPIO_FN_STATUS0,
|
||||
|
|
@ -119,83 +114,44 @@ enum {
|
|||
GPIO_FN_GPO4, GPIO_FN_STATUS2,
|
||||
GPIO_FN_VINT,
|
||||
GPIO_FN_TCKON,
|
||||
GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \
|
||||
GPIO_FN_XDVFS1,
|
||||
GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
|
||||
GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \
|
||||
GPIO_FN_XDVFS2,
|
||||
GPIO_FN_PORT28_TPU1TO1,
|
||||
GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
|
||||
GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
|
||||
GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
|
||||
GPIO_FN_SCIFA4_TXD,
|
||||
GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
|
||||
GPIO_FN_SCIFA4_RTS_,
|
||||
GPIO_FN_SCIFA4_CTS_,
|
||||
GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
|
||||
GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
|
||||
GPIO_FN_FSIBOSLD,
|
||||
GPIO_FN_FSIBISLD,
|
||||
GPIO_FN_XWUP,
|
||||
GPIO_FN_VACK,
|
||||
GPIO_FN_XTAL1L,
|
||||
GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2,
|
||||
GPIO_FN_SCIFA0_RXD,
|
||||
GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1,
|
||||
GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
|
||||
GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
|
||||
GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
|
||||
GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD,
|
||||
GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \
|
||||
GPIO_FN_FSIAOMC,
|
||||
GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
|
||||
GPIO_FN_PORT49_IROUT,
|
||||
GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2,
|
||||
|
||||
GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
|
||||
GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
|
||||
GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
|
||||
GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
|
||||
GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
|
||||
GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
|
||||
GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
|
||||
GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3,
|
||||
GPIO_FN_BBIF2_TXD2,
|
||||
GPIO_FN_TPU3TO3,
|
||||
GPIO_FN_TPU3TO2,
|
||||
GPIO_FN_TPU0TO0,
|
||||
GPIO_FN_A0, GPIO_FN_BS_,
|
||||
GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
|
||||
GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
|
||||
GPIO_FN_A14, GPIO_FN_KEYOUT5,
|
||||
GPIO_FN_A15, GPIO_FN_KEYOUT4,
|
||||
GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1,
|
||||
GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
|
||||
GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
|
||||
GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD,
|
||||
GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK,
|
||||
GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
|
||||
GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0,
|
||||
GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1,
|
||||
GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD,
|
||||
GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2,
|
||||
GPIO_FN_A26, GPIO_FN_KEYIN6,
|
||||
GPIO_FN_KEYIN7,
|
||||
GPIO_FN_D0_NAF0,
|
||||
GPIO_FN_D1_NAF1,
|
||||
GPIO_FN_D2_NAF2,
|
||||
GPIO_FN_D3_NAF3,
|
||||
GPIO_FN_D4_NAF4,
|
||||
GPIO_FN_D5_NAF5,
|
||||
GPIO_FN_D6_NAF6,
|
||||
GPIO_FN_D7_NAF7,
|
||||
GPIO_FN_D8_NAF8,
|
||||
GPIO_FN_D9_NAF9,
|
||||
GPIO_FN_D10_NAF10,
|
||||
GPIO_FN_D11_NAF11,
|
||||
GPIO_FN_D12_NAF12,
|
||||
GPIO_FN_D13_NAF13,
|
||||
GPIO_FN_D14_NAF14,
|
||||
GPIO_FN_D15_NAF15,
|
||||
GPIO_FN_CS4_,
|
||||
GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
|
||||
GPIO_FN_CS5B_, GPIO_FN_FCE1_,
|
||||
GPIO_FN_CS6B_, GPIO_FN_DACK0,
|
||||
GPIO_FN_FCE0_, GPIO_FN_CS6A_,
|
||||
GPIO_FN_A12, GPIO_FN_TPU4TO2,
|
||||
GPIO_FN_A13, GPIO_FN_TPU0TO1,
|
||||
GPIO_FN_A14,
|
||||
GPIO_FN_A15,
|
||||
GPIO_FN_A16, GPIO_FN_MSIOF0_SS1,
|
||||
GPIO_FN_A17, GPIO_FN_MSIOF0_TSYNC,
|
||||
GPIO_FN_A18, GPIO_FN_MSIOF0_TSCK,
|
||||
GPIO_FN_A19, GPIO_FN_MSIOF0_TXD,
|
||||
GPIO_FN_A20, GPIO_FN_MSIOF0_RSCK,
|
||||
GPIO_FN_A21, GPIO_FN_MSIOF0_RSYNC,
|
||||
GPIO_FN_A22, GPIO_FN_MSIOF0_MCK0,
|
||||
GPIO_FN_A23, GPIO_FN_MSIOF0_MCK1,
|
||||
GPIO_FN_A24, GPIO_FN_MSIOF0_RXD,
|
||||
GPIO_FN_A25, GPIO_FN_MSIOF0_SS2,
|
||||
GPIO_FN_A26,
|
||||
GPIO_FN_FCE1_,
|
||||
GPIO_FN_DACK0,
|
||||
GPIO_FN_FCE0_,
|
||||
GPIO_FN_WAIT_, GPIO_FN_DREQ0,
|
||||
GPIO_FN_RD__FSC,
|
||||
GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
|
||||
GPIO_FN_WE1_,
|
||||
GPIO_FN_FRB,
|
||||
GPIO_FN_CKO,
|
||||
GPIO_FN_NBRSTOUT_,
|
||||
|
|
@ -204,145 +160,118 @@ enum {
|
|||
GPIO_FN_BBIF2_RXD,
|
||||
GPIO_FN_BBIF2_SYNC,
|
||||
GPIO_FN_BBIF2_SCK,
|
||||
GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2,
|
||||
GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1,
|
||||
GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1,
|
||||
GPIO_FN_SCIFA3_TXD,
|
||||
GPIO_FN_MFG3_IN2,
|
||||
GPIO_FN_MFG3_IN1,
|
||||
GPIO_FN_BBIF1_SS2, GPIO_FN_MFG3_OUT1,
|
||||
GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
|
||||
GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
|
||||
GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
|
||||
GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
|
||||
GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \
|
||||
GPIO_FN_PORT115_I2C_SCL3,
|
||||
GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
|
||||
GPIO_FN_PORT116_I2C_SDA3,
|
||||
GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK,
|
||||
GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC,
|
||||
GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
|
||||
GPIO_FN_HSI_TX_FLAG,
|
||||
GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \
|
||||
GPIO_FN_LCD2D0,
|
||||
GPIO_FN_VIO_VD, GPIO_FN_VIO2_VD,
|
||||
|
||||
GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \
|
||||
GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1,
|
||||
GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10,
|
||||
GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
|
||||
GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11,
|
||||
GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
|
||||
GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12,
|
||||
GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13,
|
||||
GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14,
|
||||
GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15,
|
||||
GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16,
|
||||
GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17,
|
||||
GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
|
||||
GPIO_FN_LCD2D6,
|
||||
GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
|
||||
GPIO_FN_LCD2D7,
|
||||
GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8,
|
||||
GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9,
|
||||
GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
|
||||
GPIO_FN_LCD2D2,
|
||||
GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
|
||||
GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3,
|
||||
GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
|
||||
GPIO_FN_LCD2D4,
|
||||
GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
|
||||
GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
|
||||
GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
|
||||
GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
|
||||
GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
|
||||
GPIO_FN_VIO_HD,
|
||||
GPIO_FN_VIO2_HD,
|
||||
GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD,
|
||||
GPIO_FN_VIO_D1, GPIO_FN_PORT131_MSIOF2_SS1,
|
||||
GPIO_FN_VIO_D2, GPIO_FN_PORT132_MSIOF2_SS2,
|
||||
GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC,
|
||||
GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD,
|
||||
GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK,
|
||||
GPIO_FN_VIO_D6,
|
||||
GPIO_FN_VIO_D7,
|
||||
GPIO_FN_VIO_D8, GPIO_FN_VIO2_D0,
|
||||
GPIO_FN_VIO_D9, GPIO_FN_VIO2_D1,
|
||||
GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2,
|
||||
GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3,
|
||||
GPIO_FN_VIO_D12, GPIO_FN_VIO2_D4,
|
||||
GPIO_FN_VIO_D13,
|
||||
GPIO_FN_VIO2_D5,
|
||||
GPIO_FN_VIO_D14, GPIO_FN_VIO2_D6,
|
||||
GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3,
|
||||
GPIO_FN_VIO2_D7,
|
||||
GPIO_FN_VIO_CLK,
|
||||
GPIO_FN_VIO2_CLK,
|
||||
GPIO_FN_VIO_FIELD, GPIO_FN_VIO2_FIELD,
|
||||
GPIO_FN_VIO_CKO,
|
||||
GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
|
||||
GPIO_FN_PORT149_KEYOUT9,
|
||||
GPIO_FN_A27, GPIO_FN_MFG0_IN1,
|
||||
GPIO_FN_MFG0_IN2,
|
||||
GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
|
||||
GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
|
||||
GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
|
||||
GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
|
||||
GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
|
||||
GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2,
|
||||
GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD,
|
||||
GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
|
||||
GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
|
||||
GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
|
||||
GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
|
||||
GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
|
||||
GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
|
||||
GPIO_FN_MSIOF2_MCK0,
|
||||
GPIO_FN_MSIOF2_MCK1,
|
||||
GPIO_FN_PORT156_MSIOF2_SS2,
|
||||
GPIO_FN_PORT157_MSIOF2_RXD,
|
||||
GPIO_FN_DINT_, GPIO_FN_TS_SCK3,
|
||||
GPIO_FN_NMI,
|
||||
GPIO_FN_TPU3TO0,
|
||||
GPIO_FN_LCDD0,
|
||||
GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
|
||||
GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
|
||||
GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
|
||||
GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
|
||||
GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
|
||||
GPIO_FN_BBIF2_TSYNC1,
|
||||
GPIO_FN_BBIF2_TSCK1,
|
||||
GPIO_FN_BBIF2_TXD1,
|
||||
GPIO_FN_MFG2_OUT2,
|
||||
GPIO_FN_TPU2TO1,
|
||||
GPIO_FN_LCDD6,
|
||||
GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
|
||||
GPIO_FN_LCDD8, GPIO_FN_D16,
|
||||
GPIO_FN_LCDD9, GPIO_FN_D17,
|
||||
GPIO_FN_LCDD10, GPIO_FN_D18,
|
||||
GPIO_FN_LCDD11, GPIO_FN_D19,
|
||||
GPIO_FN_LCDD12, GPIO_FN_D20,
|
||||
GPIO_FN_LCDD13, GPIO_FN_D21,
|
||||
GPIO_FN_LCDD14, GPIO_FN_D22,
|
||||
GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
|
||||
GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
|
||||
GPIO_FN_LCDD17, GPIO_FN_D25,
|
||||
GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
|
||||
GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
|
||||
GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
|
||||
GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
|
||||
GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
|
||||
GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
|
||||
GPIO_FN_LCDDCK, GPIO_FN_LCDWR_,
|
||||
GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \
|
||||
GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
|
||||
GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
|
||||
GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
|
||||
GPIO_FN_D16,
|
||||
GPIO_FN_D17,
|
||||
GPIO_FN_D18,
|
||||
GPIO_FN_D19,
|
||||
GPIO_FN_D20,
|
||||
GPIO_FN_D21,
|
||||
GPIO_FN_D22,
|
||||
GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
|
||||
GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
|
||||
GPIO_FN_D25,
|
||||
GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
|
||||
GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
|
||||
GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
|
||||
GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
|
||||
GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
|
||||
GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
|
||||
GPIO_FN_DACK2,
|
||||
GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3,
|
||||
GPIO_FN_DACK3,
|
||||
GPIO_FN_PORT218_VIO_CKOR,
|
||||
GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
|
||||
GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
|
||||
GPIO_FN_LCD2DCK_2,
|
||||
GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
|
||||
GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
|
||||
GPIO_FN_DREQ1,
|
||||
GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
|
||||
GPIO_FN_PORT221_LCD2HSYN,
|
||||
GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \
|
||||
GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN,
|
||||
GPIO_FN_DACK1, GPIO_FN_OVCN,
|
||||
GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3,
|
||||
|
||||
GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
|
||||
GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
|
||||
GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN,
|
||||
GPIO_FN_SCIFA1_RXD,
|
||||
GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1,
|
||||
GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2,
|
||||
GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_,
|
||||
GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
|
||||
GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
|
||||
GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
|
||||
GPIO_FN_LCD2D20,
|
||||
GPIO_FN_OVCN2,
|
||||
GPIO_FN_EXTLP, GPIO_FN_PORT226_VIO_CKO2,
|
||||
GPIO_FN_IDIN,
|
||||
GPIO_FN_MFG1_IN1,
|
||||
GPIO_FN_MSIOF1_TXD,
|
||||
GPIO_FN_MSIOF1_TSYNC,
|
||||
GPIO_FN_MSIOF1_TSCK,
|
||||
GPIO_FN_MSIOF1_RXD,
|
||||
GPIO_FN_MSIOF1_RSCK, GPIO_FN_VIO2_CLK2,
|
||||
GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
|
||||
GPIO_FN_LCD2D21,
|
||||
GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
|
||||
GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
|
||||
GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22,
|
||||
GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23,
|
||||
GPIO_FN_SCIFA6_TXD,
|
||||
GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
|
||||
GPIO_FN_MSIOF1_MCK0,
|
||||
GPIO_FN_MSIOF1_MCK1,
|
||||
GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2,
|
||||
GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2,
|
||||
GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
|
||||
GPIO_FN_TPU4TO0,
|
||||
GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
|
||||
GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
|
||||
GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \
|
||||
GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD,
|
||||
GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \
|
||||
GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD,
|
||||
GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \
|
||||
GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
|
||||
GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \
|
||||
GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
|
||||
GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \
|
||||
GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \
|
||||
GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
|
||||
GPIO_FN_MFG4_IN2,
|
||||
GPIO_FN_PORT243_VIO_CKO2,
|
||||
GPIO_FN_MFG2_IN1,
|
||||
GPIO_FN_MSIOF2R_RXD,
|
||||
GPIO_FN_MFG2_IN2,
|
||||
GPIO_FN_MSIOF2R_TXD,
|
||||
GPIO_FN_MFG1_OUT1,
|
||||
GPIO_FN_TPU1TO0,
|
||||
GPIO_FN_MFG3_OUT2,
|
||||
GPIO_FN_TPU3TO1,
|
||||
GPIO_FN_MFG2_OUT1,
|
||||
GPIO_FN_TPU2TO0,
|
||||
GPIO_FN_MSIOF2R_TSCK,
|
||||
GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
|
||||
GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
|
||||
GPIO_FN_MSIOF2R_TSYNC,
|
||||
GPIO_FN_SDHICLK0,
|
||||
GPIO_FN_SDHICD0,
|
||||
GPIO_FN_SDHID0_0,
|
||||
|
|
@ -435,54 +364,12 @@ enum {
|
|||
GPIO_FN_IRQ9_MEM_INT,
|
||||
GPIO_FN_IRQ9_MCP_INT,
|
||||
GPIO_FN_A11,
|
||||
GPIO_FN_KEYOUT8,
|
||||
GPIO_FN_TPU4TO3,
|
||||
GPIO_FN_RESETA_N_PU_ON,
|
||||
GPIO_FN_RESETA_N_PU_OFF,
|
||||
GPIO_FN_EDBGREQ_PD,
|
||||
GPIO_FN_EDBGREQ_PU,
|
||||
|
||||
/* Functions with pull-ups */
|
||||
GPIO_FN_KEYIN0_PU,
|
||||
GPIO_FN_KEYIN1_PU,
|
||||
GPIO_FN_KEYIN2_PU,
|
||||
GPIO_FN_KEYIN3_PU,
|
||||
GPIO_FN_KEYIN4_PU,
|
||||
GPIO_FN_KEYIN5_PU,
|
||||
GPIO_FN_KEYIN6_PU,
|
||||
GPIO_FN_KEYIN7_PU,
|
||||
GPIO_FN_SDHICD0_PU,
|
||||
GPIO_FN_SDHID0_0_PU,
|
||||
GPIO_FN_SDHID0_1_PU,
|
||||
GPIO_FN_SDHID0_2_PU,
|
||||
GPIO_FN_SDHID0_3_PU,
|
||||
GPIO_FN_SDHICMD0_PU,
|
||||
GPIO_FN_SDHIWP0_PU,
|
||||
GPIO_FN_SDHID1_0_PU,
|
||||
GPIO_FN_SDHID1_1_PU,
|
||||
GPIO_FN_SDHID1_2_PU,
|
||||
GPIO_FN_SDHID1_3_PU,
|
||||
GPIO_FN_SDHICMD1_PU,
|
||||
GPIO_FN_SDHID2_0_PU,
|
||||
GPIO_FN_SDHID2_1_PU,
|
||||
GPIO_FN_SDHID2_2_PU,
|
||||
GPIO_FN_SDHID2_3_PU,
|
||||
GPIO_FN_SDHICMD2_PU,
|
||||
GPIO_FN_MMCCMD0_PU,
|
||||
GPIO_FN_MMCCMD1_PU,
|
||||
GPIO_FN_MMCD0_0_PU,
|
||||
GPIO_FN_MMCD0_1_PU,
|
||||
GPIO_FN_MMCD0_2_PU,
|
||||
GPIO_FN_MMCD0_3_PU,
|
||||
GPIO_FN_MMCD0_4_PU,
|
||||
GPIO_FN_MMCD0_5_PU,
|
||||
GPIO_FN_MMCD0_6_PU,
|
||||
GPIO_FN_MMCD0_7_PU,
|
||||
GPIO_FN_FSIACK_PU,
|
||||
GPIO_FN_FSIAILR_PU,
|
||||
GPIO_FN_FSIAIBT_PU,
|
||||
GPIO_FN_FSIAISLD_PU,
|
||||
|
||||
/* end of GPIO */
|
||||
GPIO_NR,
|
||||
};
|
||||
|
|
@ -557,6 +444,21 @@ enum {
|
|||
#define SH73A0_PINT0_IRQ(irq) ((irq) + 700)
|
||||
#define SH73A0_PINT1_IRQ(irq) ((irq) + 732)
|
||||
|
||||
extern void sh73a0_init_delay(void);
|
||||
extern void sh73a0_init_irq(void);
|
||||
extern void sh73a0_init_irq_dt(void);
|
||||
extern void sh73a0_map_io(void);
|
||||
extern void sh73a0_earlytimer_init(void);
|
||||
extern void sh73a0_add_early_devices(void);
|
||||
extern void sh73a0_add_standard_devices(void);
|
||||
extern void sh73a0_add_standard_devices_dt(void);
|
||||
extern void sh73a0_clock_init(void);
|
||||
extern void sh73a0_pinmux_init(void);
|
||||
extern void sh73a0_pm_init(void);
|
||||
extern struct clk sh73a0_extal1_clk;
|
||||
extern struct clk sh73a0_extal2_clk;
|
||||
extern struct clk sh73a0_extcki_clk;
|
||||
extern struct clk sh73a0_extalr_clk;
|
||||
extern struct smp_operations sh73a0_smp_ops;
|
||||
|
||||
#endif /* __ASM_SH73A0_H__ */
|
||||
|
|
|
|||
|
|
@ -18,620 +18,39 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sh_intc.h>
|
||||
#include <mach/intc.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
/*
|
||||
* INTCA
|
||||
*/
|
||||
enum {
|
||||
UNUSED_INTCA = 0,
|
||||
|
||||
/* interrupt sources INTCA */
|
||||
DIRC,
|
||||
ATAPI,
|
||||
IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI,
|
||||
AP_ARM_COMMTX, AP_ARM_COMMRX,
|
||||
MFI, MFIS,
|
||||
BBIF1, BBIF2,
|
||||
USBHSDMAC,
|
||||
USBF_OUL_SOF, USBF_IXL_INT,
|
||||
SGX540,
|
||||
CMT1_0, CMT1_1, CMT1_2, CMT1_3,
|
||||
CMT2,
|
||||
CMT3,
|
||||
KEYSC,
|
||||
SCIFA0, SCIFA1, SCIFA2, SCIFA3,
|
||||
MSIOF2, MSIOF1,
|
||||
SCIFA4, SCIFA5, SCIFB,
|
||||
FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
|
||||
SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3,
|
||||
SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3,
|
||||
AP_ARM_L2CINT,
|
||||
IRDA,
|
||||
TPU0,
|
||||
SCIFA6, SCIFA7,
|
||||
GbEther,
|
||||
ICBS0,
|
||||
DDM,
|
||||
SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3,
|
||||
RWDT0,
|
||||
DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
|
||||
DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
|
||||
DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
|
||||
DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
|
||||
DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
|
||||
DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
|
||||
SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
|
||||
HDMI,
|
||||
USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
|
||||
RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
|
||||
SPU2_0, SPU2_1,
|
||||
FSI, FMSI,
|
||||
HDMI_SSS, HDMI_KEY,
|
||||
IPMMU,
|
||||
AP_ARM_CTIIRQ, AP_ARM_PMURQ,
|
||||
MFIS2,
|
||||
CPORTR2S,
|
||||
CMT14, CMT15,
|
||||
MMCIF_0, MMCIF_1, MMCIF_2,
|
||||
SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
|
||||
STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4,
|
||||
|
||||
/* interrupt groups INTCA */
|
||||
DMAC1_1, DMAC1_2,
|
||||
DMAC2_1, DMAC2_2,
|
||||
DMAC3_1, DMAC3_2,
|
||||
AP_ARM1, AP_ARM2,
|
||||
SDHI0, SDHI1, SDHI2,
|
||||
SHWYSTAT,
|
||||
USBF, USBH1, USBH2,
|
||||
RSPI, SPU2, FLCTL, IIC1,
|
||||
};
|
||||
|
||||
static struct intc_vect intca_vectors[] __initdata = {
|
||||
INTC_VECT(DIRC, 0x0560),
|
||||
INTC_VECT(ATAPI, 0x05E0),
|
||||
INTC_VECT(IIC1_ALI, 0x0780),
|
||||
INTC_VECT(IIC1_TACKI, 0x07A0),
|
||||
INTC_VECT(IIC1_WAITI, 0x07C0),
|
||||
INTC_VECT(IIC1_DTEI, 0x07E0),
|
||||
INTC_VECT(AP_ARM_COMMTX, 0x0840),
|
||||
INTC_VECT(AP_ARM_COMMRX, 0x0860),
|
||||
INTC_VECT(MFI, 0x0900),
|
||||
INTC_VECT(MFIS, 0x0920),
|
||||
INTC_VECT(BBIF1, 0x0940),
|
||||
INTC_VECT(BBIF2, 0x0960),
|
||||
INTC_VECT(USBHSDMAC, 0x0A00),
|
||||
INTC_VECT(USBF_OUL_SOF, 0x0A20),
|
||||
INTC_VECT(USBF_IXL_INT, 0x0A40),
|
||||
INTC_VECT(SGX540, 0x0A60),
|
||||
INTC_VECT(CMT1_0, 0x0B00),
|
||||
INTC_VECT(CMT1_1, 0x0B20),
|
||||
INTC_VECT(CMT1_2, 0x0B40),
|
||||
INTC_VECT(CMT1_3, 0x0B60),
|
||||
INTC_VECT(CMT2, 0x0B80),
|
||||
INTC_VECT(CMT3, 0x0BA0),
|
||||
INTC_VECT(KEYSC, 0x0BE0),
|
||||
INTC_VECT(SCIFA0, 0x0C00),
|
||||
INTC_VECT(SCIFA1, 0x0C20),
|
||||
INTC_VECT(SCIFA2, 0x0C40),
|
||||
INTC_VECT(SCIFA3, 0x0C60),
|
||||
INTC_VECT(MSIOF2, 0x0C80),
|
||||
INTC_VECT(MSIOF1, 0x0D00),
|
||||
INTC_VECT(SCIFA4, 0x0D20),
|
||||
INTC_VECT(SCIFA5, 0x0D40),
|
||||
INTC_VECT(SCIFB, 0x0D60),
|
||||
INTC_VECT(FLCTL_FLSTEI, 0x0D80),
|
||||
INTC_VECT(FLCTL_FLTENDI, 0x0DA0),
|
||||
INTC_VECT(FLCTL_FLTREQ0I, 0x0DC0),
|
||||
INTC_VECT(FLCTL_FLTREQ1I, 0x0DE0),
|
||||
INTC_VECT(SDHI0_0, 0x0E00),
|
||||
INTC_VECT(SDHI0_1, 0x0E20),
|
||||
INTC_VECT(SDHI0_2, 0x0E40),
|
||||
INTC_VECT(SDHI0_3, 0x0E60),
|
||||
INTC_VECT(SDHI1_0, 0x0E80),
|
||||
INTC_VECT(SDHI1_1, 0x0EA0),
|
||||
INTC_VECT(SDHI1_2, 0x0EC0),
|
||||
INTC_VECT(SDHI1_3, 0x0EE0),
|
||||
INTC_VECT(AP_ARM_L2CINT, 0x0FA0),
|
||||
INTC_VECT(IRDA, 0x0480),
|
||||
INTC_VECT(TPU0, 0x04A0),
|
||||
INTC_VECT(SCIFA6, 0x04C0),
|
||||
INTC_VECT(SCIFA7, 0x04E0),
|
||||
INTC_VECT(GbEther, 0x0500),
|
||||
INTC_VECT(ICBS0, 0x0540),
|
||||
INTC_VECT(DDM, 0x1140),
|
||||
INTC_VECT(SDHI2_0, 0x1200),
|
||||
INTC_VECT(SDHI2_1, 0x1220),
|
||||
INTC_VECT(SDHI2_2, 0x1240),
|
||||
INTC_VECT(SDHI2_3, 0x1260),
|
||||
INTC_VECT(RWDT0, 0x1280),
|
||||
INTC_VECT(DMAC1_1_DEI0, 0x2000),
|
||||
INTC_VECT(DMAC1_1_DEI1, 0x2020),
|
||||
INTC_VECT(DMAC1_1_DEI2, 0x2040),
|
||||
INTC_VECT(DMAC1_1_DEI3, 0x2060),
|
||||
INTC_VECT(DMAC1_2_DEI4, 0x2080),
|
||||
INTC_VECT(DMAC1_2_DEI5, 0x20A0),
|
||||
INTC_VECT(DMAC1_2_DADERR, 0x20C0),
|
||||
INTC_VECT(DMAC2_1_DEI0, 0x2100),
|
||||
INTC_VECT(DMAC2_1_DEI1, 0x2120),
|
||||
INTC_VECT(DMAC2_1_DEI2, 0x2140),
|
||||
INTC_VECT(DMAC2_1_DEI3, 0x2160),
|
||||
INTC_VECT(DMAC2_2_DEI4, 0x2180),
|
||||
INTC_VECT(DMAC2_2_DEI5, 0x21A0),
|
||||
INTC_VECT(DMAC2_2_DADERR, 0x21C0),
|
||||
INTC_VECT(DMAC3_1_DEI0, 0x2200),
|
||||
INTC_VECT(DMAC3_1_DEI1, 0x2220),
|
||||
INTC_VECT(DMAC3_1_DEI2, 0x2240),
|
||||
INTC_VECT(DMAC3_1_DEI3, 0x2260),
|
||||
INTC_VECT(DMAC3_2_DEI4, 0x2280),
|
||||
INTC_VECT(DMAC3_2_DEI5, 0x22A0),
|
||||
INTC_VECT(DMAC3_2_DADERR, 0x22C0),
|
||||
INTC_VECT(SHWYSTAT_RT, 0x1300),
|
||||
INTC_VECT(SHWYSTAT_HS, 0x1320),
|
||||
INTC_VECT(SHWYSTAT_COM, 0x1340),
|
||||
INTC_VECT(USBH_INT, 0x1540),
|
||||
INTC_VECT(USBH_OHCI, 0x1560),
|
||||
INTC_VECT(USBH_EHCI, 0x1580),
|
||||
INTC_VECT(USBH_PME, 0x15A0),
|
||||
INTC_VECT(USBH_BIND, 0x15C0),
|
||||
INTC_VECT(HDMI, 0x1700),
|
||||
INTC_VECT(RSPI_OVRF, 0x1780),
|
||||
INTC_VECT(RSPI_SPTEF, 0x17A0),
|
||||
INTC_VECT(RSPI_SPRF, 0x17C0),
|
||||
INTC_VECT(SPU2_0, 0x1800),
|
||||
INTC_VECT(SPU2_1, 0x1820),
|
||||
INTC_VECT(FSI, 0x1840),
|
||||
INTC_VECT(FMSI, 0x1860),
|
||||
INTC_VECT(HDMI_SSS, 0x18A0),
|
||||
INTC_VECT(HDMI_KEY, 0x18C0),
|
||||
INTC_VECT(IPMMU, 0x1920),
|
||||
INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
|
||||
INTC_VECT(AP_ARM_PMURQ, 0x19A0),
|
||||
INTC_VECT(MFIS2, 0x1A00),
|
||||
INTC_VECT(CPORTR2S, 0x1A20),
|
||||
INTC_VECT(CMT14, 0x1A40),
|
||||
INTC_VECT(CMT15, 0x1A60),
|
||||
INTC_VECT(MMCIF_0, 0x1AA0),
|
||||
INTC_VECT(MMCIF_1, 0x1AC0),
|
||||
INTC_VECT(MMCIF_2, 0x1AE0),
|
||||
INTC_VECT(SIM_ERI, 0x1C00),
|
||||
INTC_VECT(SIM_RXI, 0x1C20),
|
||||
INTC_VECT(SIM_TXI, 0x1C40),
|
||||
INTC_VECT(SIM_TEI, 0x1C60),
|
||||
INTC_VECT(STPRO_0, 0x1C80),
|
||||
INTC_VECT(STPRO_1, 0x1CA0),
|
||||
INTC_VECT(STPRO_2, 0x1CC0),
|
||||
INTC_VECT(STPRO_3, 0x1CE0),
|
||||
INTC_VECT(STPRO_4, 0x1D00),
|
||||
};
|
||||
|
||||
static struct intc_group intca_groups[] __initdata = {
|
||||
INTC_GROUP(DMAC1_1,
|
||||
DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
|
||||
INTC_GROUP(DMAC1_2,
|
||||
DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR),
|
||||
INTC_GROUP(DMAC2_1,
|
||||
DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
|
||||
INTC_GROUP(DMAC2_2,
|
||||
DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR),
|
||||
INTC_GROUP(DMAC3_1,
|
||||
DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
|
||||
INTC_GROUP(DMAC3_2,
|
||||
DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR),
|
||||
INTC_GROUP(AP_ARM1,
|
||||
AP_ARM_COMMTX, AP_ARM_COMMRX),
|
||||
INTC_GROUP(AP_ARM2,
|
||||
AP_ARM_CTIIRQ, AP_ARM_PMURQ),
|
||||
INTC_GROUP(USBF,
|
||||
USBF_OUL_SOF, USBF_IXL_INT),
|
||||
INTC_GROUP(SDHI0,
|
||||
SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3),
|
||||
INTC_GROUP(SDHI1,
|
||||
SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3),
|
||||
INTC_GROUP(SDHI2,
|
||||
SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3),
|
||||
INTC_GROUP(SHWYSTAT,
|
||||
SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
|
||||
INTC_GROUP(USBH1, /* FIXME */
|
||||
USBH_INT, USBH_OHCI),
|
||||
INTC_GROUP(USBH2, /* FIXME */
|
||||
USBH_EHCI,
|
||||
USBH_PME, USBH_BIND),
|
||||
INTC_GROUP(RSPI,
|
||||
RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF),
|
||||
INTC_GROUP(SPU2,
|
||||
SPU2_0, SPU2_1),
|
||||
INTC_GROUP(FLCTL,
|
||||
FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
|
||||
INTC_GROUP(IIC1,
|
||||
IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg intca_mask_registers[] __initdata = {
|
||||
{ /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8,
|
||||
{ DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
|
||||
0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
|
||||
{ /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8,
|
||||
{ ATAPI, 0, DIRC, 0,
|
||||
DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
|
||||
{ /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8,
|
||||
{ 0, 0, 0, 0,
|
||||
BBIF1, BBIF2, MFIS, MFI } },
|
||||
{ /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8,
|
||||
{ DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
|
||||
DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
|
||||
{ /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8,
|
||||
{ DDM, 0, 0, 0,
|
||||
0, 0, 0, 0 } },
|
||||
{ /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8,
|
||||
{ KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
|
||||
SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
|
||||
{ /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8,
|
||||
{ SCIFB, SCIFA5, SCIFA4, MSIOF1,
|
||||
0, 0, MSIOF2, 0 } },
|
||||
{ /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8,
|
||||
{ SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0,
|
||||
FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
|
||||
{ /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8,
|
||||
{ SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0,
|
||||
0, USBHSDMAC, 0, AP_ARM_L2CINT } },
|
||||
{ /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8,
|
||||
{ CMT1_3, CMT1_2, CMT1_1, CMT1_0,
|
||||
CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } },
|
||||
{ /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8,
|
||||
{ 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
|
||||
0, 0, 0, 0 } },
|
||||
{ /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8,
|
||||
{ IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI,
|
||||
ICBS0, 0, 0, 0 } },
|
||||
{ /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8,
|
||||
{ 0, 0, TPU0, SCIFA6,
|
||||
SCIFA7, GbEther, 0, 0 } },
|
||||
{ /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8,
|
||||
{ SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0,
|
||||
0, CMT3, 0, RWDT0 } },
|
||||
{ /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8,
|
||||
{ SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
|
||||
0, 0, 0, 0 } },
|
||||
/* IMR1A3 / IMCR1A3 */
|
||||
{ /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8,
|
||||
{ 0, 0, USBH_INT, USBH_OHCI,
|
||||
USBH_EHCI, USBH_PME, USBH_BIND, 0 } },
|
||||
/* IMR3A3 / IMCR3A3 */
|
||||
{ /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8,
|
||||
{ HDMI, 0, 0, 0,
|
||||
RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } },
|
||||
{ /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8,
|
||||
{ SPU2_0, SPU2_1, FSI, FMSI,
|
||||
0, HDMI_SSS, HDMI_KEY, 0 } },
|
||||
{ /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8,
|
||||
{ 0, IPMMU, 0, 0,
|
||||
AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } },
|
||||
{ /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8,
|
||||
{ MFIS2, CPORTR2S, CMT14, CMT15,
|
||||
0, MMCIF_0, MMCIF_1, MMCIF_2 } },
|
||||
/* IMR8A3 / IMCR8A3 */
|
||||
{ /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8,
|
||||
{ SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
|
||||
STPRO_0, STPRO_1, STPRO_2, STPRO_3 } },
|
||||
{ /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8,
|
||||
{ STPRO_4, 0, 0, 0,
|
||||
0, 0, 0, 0 } },
|
||||
};
|
||||
|
||||
static struct intc_prio_reg intca_prio_registers[] __initdata = {
|
||||
{ 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } },
|
||||
{ 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
|
||||
{ 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } },
|
||||
{ 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } },
|
||||
{ 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } },
|
||||
{ 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2,
|
||||
SGX540, CMT1_0 } },
|
||||
{ 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
|
||||
SCIFA2, SCIFA3 } },
|
||||
{ 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC,
|
||||
FLCTL, SDHI0 } },
|
||||
{ 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } },
|
||||
{ 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
|
||||
AP_ARM_L2CINT, 0 } },
|
||||
{ 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } },
|
||||
{ 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6,
|
||||
SCIFA7, GbEther } },
|
||||
{ 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
|
||||
{ 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
|
||||
{ 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
|
||||
{ 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
|
||||
/* IPRBA3 */
|
||||
/* IPRCA3 */
|
||||
/* IPRDA3 */
|
||||
{ 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } },
|
||||
{ 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } },
|
||||
/* IPRGA3 */
|
||||
/* IPRHA3 */
|
||||
{ 0xe6950020, 0, 16, 4, /* IPRIA3 */ { HDMI, 0, 0, 0 } },
|
||||
{ 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } },
|
||||
{ 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
|
||||
{ 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, HDMI_SSS, HDMI_KEY, 0 } },
|
||||
{ 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } },
|
||||
{ 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
|
||||
{ 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
|
||||
CMT14, CMT15 } },
|
||||
{ 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
|
||||
/* IPRQA3 */
|
||||
/* IPRRA3 */
|
||||
{ 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI,
|
||||
SIM_TXI, SIM_TEI } },
|
||||
{ 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1,
|
||||
STPRO_2, STPRO_3 } },
|
||||
{ 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca",
|
||||
intca_vectors, intca_groups,
|
||||
intca_mask_registers, intca_prio_registers,
|
||||
NULL);
|
||||
|
||||
INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
|
||||
INTC_VECT, "r8a7740-intca-irq-pins");
|
||||
|
||||
|
||||
/*
|
||||
* INTCS
|
||||
*/
|
||||
enum {
|
||||
UNUSED_INTCS = 0,
|
||||
|
||||
INTCS,
|
||||
|
||||
/* interrupt sources INTCS */
|
||||
|
||||
/* HUDI */
|
||||
/* STPRO */
|
||||
/* RTDMAC(1) */
|
||||
VPU5HA2,
|
||||
_2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT,
|
||||
/* MFI */
|
||||
/* BBIF2 */
|
||||
VPU5F,
|
||||
_2DG_BRK_INT,
|
||||
/* SGX540 */
|
||||
/* 2DDMAC */
|
||||
/* IPMMU */
|
||||
/* RTDMAC 2 */
|
||||
/* KEYSC */
|
||||
/* MSIOF */
|
||||
IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI,
|
||||
TMU0_0, TMU0_1, TMU0_2,
|
||||
CMT0,
|
||||
/* CMT2 */
|
||||
LMB,
|
||||
CTI,
|
||||
VOU,
|
||||
/* RWDT0 */
|
||||
ICB,
|
||||
VIO6C,
|
||||
CEU20, CEU21,
|
||||
JPU,
|
||||
LCDC0,
|
||||
LCRC,
|
||||
/* RTDMAC2(1) */
|
||||
/* RTDMAC2(2) */
|
||||
LCDC1,
|
||||
/* SPU2 */
|
||||
/* FSI */
|
||||
/* FMSI */
|
||||
TMU1_0, TMU1_1, TMU1_2,
|
||||
CMT4,
|
||||
DISP,
|
||||
DSRV,
|
||||
/* MFIS2 */
|
||||
CPORTS2R,
|
||||
|
||||
/* interrupt groups INTCS */
|
||||
_2DG1,
|
||||
IIC0, TMU1,
|
||||
};
|
||||
|
||||
static struct intc_vect intcs_vectors[] = {
|
||||
/* HUDI */
|
||||
/* STPRO */
|
||||
/* RTDMAC(1) */
|
||||
INTCS_VECT(VPU5HA2, 0x0880),
|
||||
INTCS_VECT(_2DG_TRAP, 0x08A0),
|
||||
INTCS_VECT(_2DG_GPM_INT, 0x08C0),
|
||||
INTCS_VECT(_2DG_CER_INT, 0x08E0),
|
||||
/* MFI */
|
||||
/* BBIF2 */
|
||||
INTCS_VECT(VPU5F, 0x0980),
|
||||
INTCS_VECT(_2DG_BRK_INT, 0x09A0),
|
||||
/* SGX540 */
|
||||
/* 2DDMAC */
|
||||
/* IPMMU */
|
||||
/* RTDMAC(2) */
|
||||
/* KEYSC */
|
||||
/* MSIOF */
|
||||
INTCS_VECT(IIC0_ALI, 0x0E00),
|
||||
INTCS_VECT(IIC0_TACKI, 0x0E20),
|
||||
INTCS_VECT(IIC0_WAITI, 0x0E40),
|
||||
INTCS_VECT(IIC0_DTEI, 0x0E60),
|
||||
INTCS_VECT(TMU0_0, 0x0E80),
|
||||
INTCS_VECT(TMU0_1, 0x0EA0),
|
||||
INTCS_VECT(TMU0_2, 0x0EC0),
|
||||
INTCS_VECT(CMT0, 0x0F00),
|
||||
/* CMT2 */
|
||||
INTCS_VECT(LMB, 0x0F60),
|
||||
INTCS_VECT(CTI, 0x0400),
|
||||
INTCS_VECT(VOU, 0x0420),
|
||||
/* RWDT0 */
|
||||
INTCS_VECT(ICB, 0x0480),
|
||||
INTCS_VECT(VIO6C, 0x04E0),
|
||||
INTCS_VECT(CEU20, 0x0500),
|
||||
INTCS_VECT(CEU21, 0x0520),
|
||||
INTCS_VECT(JPU, 0x0560),
|
||||
INTCS_VECT(LCDC0, 0x0580),
|
||||
INTCS_VECT(LCRC, 0x05A0),
|
||||
/* RTDMAC2(1) */
|
||||
/* RTDMAC2(2) */
|
||||
INTCS_VECT(LCDC1, 0x1780),
|
||||
/* SPU2 */
|
||||
/* FSI */
|
||||
/* FMSI */
|
||||
INTCS_VECT(TMU1_0, 0x1900),
|
||||
INTCS_VECT(TMU1_1, 0x1920),
|
||||
INTCS_VECT(TMU1_2, 0x1940),
|
||||
INTCS_VECT(CMT4, 0x1980),
|
||||
INTCS_VECT(DISP, 0x19A0),
|
||||
INTCS_VECT(DSRV, 0x19C0),
|
||||
/* MFIS2 */
|
||||
INTCS_VECT(CPORTS2R, 0x1A20),
|
||||
|
||||
INTC_VECT(INTCS, 0xf80),
|
||||
};
|
||||
|
||||
static struct intc_group intcs_groups[] __initdata = {
|
||||
INTC_GROUP(_2DG1, /*FIXME*/
|
||||
_2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP),
|
||||
INTC_GROUP(IIC0,
|
||||
IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI),
|
||||
INTC_GROUP(TMU1,
|
||||
TMU1_0, TMU1_1, TMU1_2),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg intcs_mask_registers[] = {
|
||||
/* IMR0SA / IMCR0SA */ /* all 0 */
|
||||
{ /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8,
|
||||
{ _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2,
|
||||
0, 0, 0, 0 /*STPRO*/ } },
|
||||
{ /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8,
|
||||
{ 0/*STPRO*/, 0, CEU21, VPU5F,
|
||||
0/*BBIF2*/, 0, 0, 0/*MFI*/ } },
|
||||
{ /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8,
|
||||
{ 0, 0, 0, 0, /*2DDMAC*/
|
||||
VIO6C, 0, 0, ICB } },
|
||||
{ /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8,
|
||||
{ 0, 0, VOU, CTI,
|
||||
JPU, 0, LCRC, LCDC0 } },
|
||||
/* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/
|
||||
/* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/
|
||||
{ /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8,
|
||||
{ 0, TMU0_2, TMU0_1, TMU0_0,
|
||||
0, 0, 0, 0 } },
|
||||
{ /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8,
|
||||
{ 0, 0, 0, 0,
|
||||
CEU20, 0, 0, 0 } },
|
||||
{ /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8,
|
||||
{ 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0,
|
||||
0, 0, 0, 0 } },
|
||||
/* IMR10SA / IMCR10SA */ /*IPMMU*/
|
||||
{ /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8,
|
||||
{ IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI,
|
||||
0, _2DG_BRK_INT, LMB, 0 } },
|
||||
/* IMR12SA / IMCR12SA */
|
||||
/* IMR13SA / IMCR13SA */
|
||||
/* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/
|
||||
/* IMR1SA3 / IMCR1SA3 */
|
||||
/* IMR2SA3 / IMCR2SA3 */
|
||||
/* IMR3SA3 / IMCR3SA3 */
|
||||
{ /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8,
|
||||
{ 0, 0, 0, 0,
|
||||
LCDC1, 0, 0, 0 } },
|
||||
/* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */
|
||||
{ /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8,
|
||||
{ TMU1_0, TMU1_1, TMU1_2, 0,
|
||||
CMT4, DISP, DSRV, 0 } },
|
||||
{ /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8,
|
||||
{ 0/*MFIS2*/, CPORTS2R, 0, 0,
|
||||
0, 0, 0, 0 } },
|
||||
{ /* INTAMASK */ 0xffd20104, 0, 16,
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, INTCS } },
|
||||
};
|
||||
|
||||
/* Priority is needed for INTCA to receive the INTCS interrupt */
|
||||
static struct intc_prio_reg intcs_prio_registers[] = {
|
||||
{ 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } },
|
||||
{ 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } },
|
||||
/* IPRCS */ /*BBIF2*/
|
||||
/* IPRDS */
|
||||
{ 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2,
|
||||
0/*MFI*/, VPU5F } },
|
||||
{ 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/,
|
||||
0/*CMT2*/, CMT0 } },
|
||||
{ 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1,
|
||||
TMU0_2, _2DG1 } },
|
||||
{ 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/,
|
||||
_2DG_BRK_INT/*FIXME*/ } },
|
||||
{ 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } },
|
||||
{ 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } },
|
||||
{ 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } },
|
||||
{ 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } },
|
||||
/* IPRMS */ /*RWDT0*/
|
||||
/* IPRAS3 */ /*RTDMAC2(1)*/
|
||||
/* IPRBS3 */ /*RTDMAC2(2)*/
|
||||
/* IPRCS3 */
|
||||
/* IPRDS3 */
|
||||
/* IPRES3 */
|
||||
/* IPRFS3 */
|
||||
/* IPRGS3 */
|
||||
/* IPRHS3 */
|
||||
/* IPRIS3 */
|
||||
{ 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } },
|
||||
/* IPRKS3 */ /*SPU2/FSI/FMSi*/
|
||||
/* IPRLS3 */
|
||||
{ 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
|
||||
{ 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } },
|
||||
{ 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } },
|
||||
/* IPRPS3 */
|
||||
};
|
||||
|
||||
static struct resource intcs_resources[] __initdata = {
|
||||
[0] = {
|
||||
.start = 0xffd20000,
|
||||
.end = 0xffd201ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 0xffd50000,
|
||||
.end = 0xffd501ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static struct intc_desc intcs_desc __initdata = {
|
||||
.name = "r8a7740-intcs",
|
||||
.resource = intcs_resources,
|
||||
.num_resources = ARRAY_SIZE(intcs_resources),
|
||||
.hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
|
||||
intcs_prio_registers, NULL, NULL),
|
||||
};
|
||||
|
||||
static void intcs_demux(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
void __iomem *reg = (void *)irq_get_handler_data(irq);
|
||||
unsigned int evtcodeas = ioread32(reg);
|
||||
|
||||
generic_handle_irq(intcs_evt2irq(evtcodeas));
|
||||
}
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
void __init r8a7740_init_irq(void)
|
||||
{
|
||||
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
|
||||
void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
|
||||
void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
|
||||
void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
|
||||
void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
|
||||
void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
|
||||
|
||||
register_intc_controller(&intca_desc);
|
||||
register_intc_controller(&intca_irq_pins_desc);
|
||||
register_intc_controller(&intcs_desc);
|
||||
/* initialize the Generic Interrupt Controller PL390 r0p0 */
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
|
||||
/* demux using INTEVTSA */
|
||||
irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
|
||||
irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
|
||||
/* route signals to GIC */
|
||||
iowrite32(0x0, pfc_inta_ctrl);
|
||||
|
||||
/*
|
||||
* To mask the shared interrupt to SPI 149 we must ensure to set
|
||||
* PRIO *and* MASK. Else we run into IRQ floods when registering
|
||||
* the intc_irqpin devices
|
||||
*/
|
||||
iowrite32(0x0, intc_prio_base + 0x0);
|
||||
iowrite32(0x0, intc_prio_base + 0x4);
|
||||
iowrite32(0x0, intc_prio_base + 0x8);
|
||||
iowrite32(0x0, intc_prio_base + 0xc);
|
||||
iowrite8(0xff, intc_msk_base + 0x0);
|
||||
iowrite8(0xff, intc_msk_base + 0x4);
|
||||
iowrite8(0xff, intc_msk_base + 0x8);
|
||||
iowrite8(0xff, intc_msk_base + 0xc);
|
||||
|
||||
iounmap(intc_prio_base);
|
||||
iounmap(intc_msk_base);
|
||||
iounmap(pfc_inta_ctrl);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -19,12 +19,16 @@
|
|||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/platform_data/irq-renesas-intc-irqpin.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/intc.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/r8a7779.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
|
@ -38,18 +42,61 @@
|
|||
#define INT2NTSR0 IOMEM(0xfe700060)
|
||||
#define INT2NTSR1 IOMEM(0xfe700064)
|
||||
|
||||
static struct renesas_intc_irqpin_config irqpin0_platform_data = {
|
||||
.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
|
||||
.sense_bitfield_width = 2,
|
||||
};
|
||||
|
||||
static struct resource irqpin0_resources[] = {
|
||||
DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
|
||||
DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
|
||||
DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
|
||||
DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
|
||||
DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
|
||||
DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
|
||||
DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
|
||||
DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
|
||||
DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
|
||||
};
|
||||
|
||||
static struct platform_device irqpin0_device = {
|
||||
.name = "renesas_intc_irqpin",
|
||||
.id = 0,
|
||||
.resource = irqpin0_resources,
|
||||
.num_resources = ARRAY_SIZE(irqpin0_resources),
|
||||
.dev = {
|
||||
.platform_data = &irqpin0_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
void __init r8a7779_init_irq_extpin(int irlm)
|
||||
{
|
||||
void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
|
||||
unsigned long tmp;
|
||||
|
||||
if (icr0) {
|
||||
tmp = ioread32(icr0);
|
||||
if (irlm)
|
||||
tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
|
||||
else
|
||||
tmp &= ~(1 << 23); /* IRL mode - not supported */
|
||||
tmp |= (1 << 21); /* LVLMODE = 1 */
|
||||
iowrite32(tmp, icr0);
|
||||
iounmap(icr0);
|
||||
|
||||
if (irlm)
|
||||
platform_device_register(&irqpin0_device);
|
||||
} else
|
||||
pr_warn("r8a7779: unable to setup external irq pin mode\n");
|
||||
}
|
||||
|
||||
static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
|
||||
{
|
||||
return 0; /* always allow wakeup */
|
||||
}
|
||||
|
||||
void __init r8a7779_init_irq(void)
|
||||
static void __init r8a7779_init_irq_common(void)
|
||||
{
|
||||
void __iomem *gic_dist_base = IOMEM(0xf0001000);
|
||||
void __iomem *gic_cpu_base = IOMEM(0xf0000100);
|
||||
|
||||
/* use GIC to handle interrupts */
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
gic_arch_extn.irq_set_wake = r8a7779_set_wake;
|
||||
|
||||
/* route all interrupts to ARM */
|
||||
|
|
@ -63,3 +110,22 @@ void __init r8a7779_init_irq(void)
|
|||
__raw_writel(0xbffffffc, INT2SMSKCR3);
|
||||
__raw_writel(0x003fee3f, INT2SMSKCR4);
|
||||
}
|
||||
|
||||
void __init r8a7779_init_irq(void)
|
||||
{
|
||||
void __iomem *gic_dist_base = IOMEM(0xf0001000);
|
||||
void __iomem *gic_cpu_base = IOMEM(0xf0000100);
|
||||
|
||||
/* use GIC to handle interrupts */
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
|
||||
r8a7779_init_irq_common();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
void __init r8a7779_init_irq_dt(void)
|
||||
{
|
||||
irqchip_init();
|
||||
r8a7779_init_irq_common();
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -260,108 +260,6 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
|
|||
return 0; /* always allow wakeup */
|
||||
}
|
||||
|
||||
#define RELOC_BASE 0x1200
|
||||
|
||||
/* INTCA IRQ pins at INTCS + RELOC_BASE to make space for GIC+INTC handling */
|
||||
#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE)
|
||||
|
||||
INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
|
||||
INTCS_VECT_RELOC, "sh73a0-intca-irq-pins");
|
||||
|
||||
static int to_gic_irq(struct irq_data *data)
|
||||
{
|
||||
unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE;
|
||||
|
||||
if (vect >= 0x3200)
|
||||
vect -= 0x3000;
|
||||
else
|
||||
vect -= 0x0200;
|
||||
|
||||
return gic_spi((vect >> 5) + 1);
|
||||
}
|
||||
|
||||
static int to_intca_reloc_irq(struct irq_data *data)
|
||||
{
|
||||
return data->irq + (RELOC_BASE >> 5);
|
||||
}
|
||||
|
||||
#define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq))
|
||||
#define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p)
|
||||
|
||||
static void intca_gic_enable(struct irq_data *data)
|
||||
{
|
||||
irq_cb(irq_unmask, to_intca_reloc_irq(data));
|
||||
irq_cb(irq_unmask, to_gic_irq(data));
|
||||
}
|
||||
|
||||
static void intca_gic_disable(struct irq_data *data)
|
||||
{
|
||||
irq_cb(irq_mask, to_gic_irq(data));
|
||||
irq_cb(irq_mask, to_intca_reloc_irq(data));
|
||||
}
|
||||
|
||||
static void intca_gic_mask_ack(struct irq_data *data)
|
||||
{
|
||||
irq_cb(irq_mask, to_gic_irq(data));
|
||||
irq_cb(irq_mask_ack, to_intca_reloc_irq(data));
|
||||
}
|
||||
|
||||
static void intca_gic_eoi(struct irq_data *data)
|
||||
{
|
||||
irq_cb(irq_eoi, to_gic_irq(data));
|
||||
}
|
||||
|
||||
static int intca_gic_set_type(struct irq_data *data, unsigned int type)
|
||||
{
|
||||
return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static int intca_gic_set_affinity(struct irq_data *data,
|
||||
const struct cpumask *cpumask,
|
||||
bool force)
|
||||
{
|
||||
return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force);
|
||||
}
|
||||
#endif
|
||||
|
||||
struct irq_chip intca_gic_irq_chip = {
|
||||
.name = "INTCA-GIC",
|
||||
.irq_mask = intca_gic_disable,
|
||||
.irq_unmask = intca_gic_enable,
|
||||
.irq_mask_ack = intca_gic_mask_ack,
|
||||
.irq_eoi = intca_gic_eoi,
|
||||
.irq_enable = intca_gic_enable,
|
||||
.irq_disable = intca_gic_disable,
|
||||
.irq_shutdown = intca_gic_disable,
|
||||
.irq_set_type = intca_gic_set_type,
|
||||
.irq_set_wake = sh73a0_set_wake,
|
||||
#ifdef CONFIG_SMP
|
||||
.irq_set_affinity = intca_gic_set_affinity,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int to_intc_vect(int irq)
|
||||
{
|
||||
unsigned int irq_pin = irq - gic_spi(1);
|
||||
unsigned int offs;
|
||||
|
||||
if (irq_pin < 16)
|
||||
offs = 0x0200;
|
||||
else
|
||||
offs = 0x3000;
|
||||
|
||||
return offs + (irq_pin << 5);
|
||||
}
|
||||
|
||||
static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id)
|
||||
{
|
||||
generic_handle_irq(intcs_evt2irq(to_intc_vect(irq)));
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction sh73a0_irq_pin_cascade[32];
|
||||
|
||||
#define PINTER0_PHYS 0xe69000a0
|
||||
#define PINTER1_PHYS 0xe69000a4
|
||||
#define PINTER0_VIRT IOMEM(0xe69000a0)
|
||||
|
|
@ -422,13 +320,11 @@ void __init sh73a0_init_irq(void)
|
|||
void __iomem *gic_dist_base = IOMEM(0xf0001000);
|
||||
void __iomem *gic_cpu_base = IOMEM(0xf0000100);
|
||||
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
|
||||
int k, n;
|
||||
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
gic_arch_extn.irq_set_wake = sh73a0_set_wake;
|
||||
|
||||
register_intc_controller(&intcs_desc);
|
||||
register_intc_controller(&intca_irq_pins_desc);
|
||||
register_intc_controller(&intc_pint0_desc);
|
||||
register_intc_controller(&intc_pint1_desc);
|
||||
|
||||
|
|
@ -438,19 +334,6 @@ void __init sh73a0_init_irq(void)
|
|||
sh73a0_intcs_cascade.dev_id = intevtsa;
|
||||
setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
|
||||
|
||||
/* IRQ pins require special handling through INTCA and GIC */
|
||||
for (k = 0; k < 32; k++) {
|
||||
sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade";
|
||||
sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux;
|
||||
setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]);
|
||||
|
||||
n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k)));
|
||||
WARN_ON(irq_alloc_desc_at(n, numa_node_id()) != n);
|
||||
irq_set_chip_and_handler_name(n, &intca_gic_irq_chip,
|
||||
handle_level_irq, "level");
|
||||
set_irq_flags(n, IRQF_VALID); /* yuck */
|
||||
}
|
||||
|
||||
/* PINT pins are sanely tied to the GIC as SPI */
|
||||
sh73a0_pint0_cascade.name = "PINT0 cascade";
|
||||
sh73a0_pint0_cascade.handler = sh73a0_pint0_demux;
|
||||
|
|
@ -460,11 +343,3 @@ void __init sh73a0_init_irq(void)
|
|||
sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
|
||||
setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
void __init sh73a0_init_irq_dt(void)
|
||||
{
|
||||
irqchip_init();
|
||||
gic_arch_extn.irq_set_wake = sh73a0_set_wake;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -404,7 +404,7 @@ void __init emev2_add_standard_devices(void)
|
|||
ARRAY_SIZE(emev2_late_devices));
|
||||
}
|
||||
|
||||
void __init emev2_init_delay(void)
|
||||
static void __init emev2_init_delay(void)
|
||||
{
|
||||
shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
|
||||
}
|
||||
|
|
@ -439,7 +439,7 @@ static const struct of_dev_auxdata emev2_auxdata_lookup[] __initconst = {
|
|||
{ }
|
||||
};
|
||||
|
||||
void __init emev2_add_standard_devices_dt(void)
|
||||
static void __init emev2_add_standard_devices_dt(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
emev2_auxdata_lookup, NULL);
|
||||
|
|
|
|||
202
arch/arm/mach-shmobile/setup-r8a73a4.c
Normal file
202
arch/arm/mach-shmobile/setup-r8a73a4.c
Normal file
|
|
@ -0,0 +1,202 @@
|
|||
/*
|
||||
* r8a73a4 processor support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_data/irq-renesas-irqc.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/r8a73a4.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
static const struct resource pfc_resources[] = {
|
||||
DEFINE_RES_MEM(0xe6050000, 0x9000),
|
||||
};
|
||||
|
||||
void __init r8a73a4_pinmux_init(void)
|
||||
{
|
||||
platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources,
|
||||
ARRAY_SIZE(pfc_resources));
|
||||
}
|
||||
|
||||
#define SCIF_COMMON(scif_type, baseaddr, irq) \
|
||||
.type = scif_type, \
|
||||
.mapbase = baseaddr, \
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
|
||||
.scbrr_algo_id = SCBRR_ALGO_4, \
|
||||
.irqs = SCIx_IRQ_MUXED(irq)
|
||||
|
||||
#define SCIFA_DATA(index, baseaddr, irq) \
|
||||
[index] = { \
|
||||
SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
|
||||
}
|
||||
|
||||
#define SCIFB_DATA(index, baseaddr, irq) \
|
||||
[index] = { \
|
||||
SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
|
||||
.scscr = SCSCR_RE | SCSCR_TE, \
|
||||
}
|
||||
|
||||
enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
|
||||
|
||||
static const struct plat_sci_port scif[] = {
|
||||
SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
|
||||
SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
|
||||
SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */
|
||||
SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
|
||||
SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
|
||||
SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
|
||||
};
|
||||
|
||||
static inline void r8a73a4_register_scif(int idx)
|
||||
{
|
||||
platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
|
||||
sizeof(struct plat_sci_port));
|
||||
}
|
||||
|
||||
static const struct renesas_irqc_config irqc0_data = {
|
||||
.irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
|
||||
};
|
||||
|
||||
static const struct resource irqc0_resources[] = {
|
||||
DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
|
||||
DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
|
||||
DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
|
||||
DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
|
||||
DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
|
||||
DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
|
||||
DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
|
||||
DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
|
||||
DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
|
||||
DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
|
||||
DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
|
||||
DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
|
||||
DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
|
||||
DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
|
||||
DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
|
||||
DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
|
||||
DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
|
||||
DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
|
||||
DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
|
||||
DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
|
||||
DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
|
||||
DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
|
||||
DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
|
||||
DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
|
||||
DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
|
||||
DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
|
||||
DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
|
||||
DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
|
||||
DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
|
||||
DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
|
||||
DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
|
||||
DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
|
||||
DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
|
||||
};
|
||||
|
||||
static const struct renesas_irqc_config irqc1_data = {
|
||||
.irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
|
||||
};
|
||||
|
||||
static const struct resource irqc1_resources[] = {
|
||||
DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
|
||||
DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
|
||||
DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
|
||||
DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
|
||||
DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
|
||||
DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
|
||||
DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
|
||||
DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
|
||||
DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
|
||||
DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
|
||||
DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
|
||||
DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
|
||||
DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
|
||||
DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
|
||||
DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
|
||||
DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
|
||||
DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
|
||||
DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
|
||||
DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
|
||||
DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
|
||||
DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
|
||||
DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
|
||||
DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
|
||||
DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
|
||||
DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
|
||||
DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
|
||||
DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
|
||||
};
|
||||
|
||||
#define r8a73a4_register_irqc(idx) \
|
||||
platform_device_register_resndata(&platform_bus, "renesas_irqc", \
|
||||
idx, irqc##idx##_resources, \
|
||||
ARRAY_SIZE(irqc##idx##_resources), \
|
||||
&irqc##idx##_data, \
|
||||
sizeof(struct renesas_irqc_config))
|
||||
|
||||
/* Thermal0 -> Thermal2 */
|
||||
static const struct resource thermal0_resources[] = {
|
||||
DEFINE_RES_MEM(0xe61f0000, 0x14),
|
||||
DEFINE_RES_MEM(0xe61f0100, 0x38),
|
||||
DEFINE_RES_MEM(0xe61f0200, 0x38),
|
||||
DEFINE_RES_MEM(0xe61f0300, 0x38),
|
||||
DEFINE_RES_IRQ(gic_spi(69)),
|
||||
};
|
||||
|
||||
#define r8a73a4_register_thermal() \
|
||||
platform_device_register_simple("rcar_thermal", -1, \
|
||||
thermal0_resources, \
|
||||
ARRAY_SIZE(thermal0_resources))
|
||||
|
||||
void __init r8a73a4_add_standard_devices(void)
|
||||
{
|
||||
r8a73a4_register_scif(SCIFA0);
|
||||
r8a73a4_register_scif(SCIFA1);
|
||||
r8a73a4_register_scif(SCIFB0);
|
||||
r8a73a4_register_scif(SCIFB1);
|
||||
r8a73a4_register_scif(SCIFB2);
|
||||
r8a73a4_register_scif(SCIFB3);
|
||||
r8a73a4_register_irqc(0);
|
||||
r8a73a4_register_irqc(1);
|
||||
r8a73a4_register_thermal();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USE_OF
|
||||
void __init r8a73a4_add_standard_devices_dt(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static const char *r8a73a4_boards_compat_dt[] __initdata = {
|
||||
"renesas,r8a73a4",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
|
||||
.init_irq = irqchip_init,
|
||||
.init_machine = r8a73a4_add_standard_devices_dt,
|
||||
.init_time = shmobile_timer_init,
|
||||
.dt_compat = r8a73a4_boards_compat_dt,
|
||||
MACHINE_END
|
||||
#endif /* CONFIG_USE_OF */
|
||||
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_data/irq-renesas-intc-irqpin.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/serial_sci.h>
|
||||
|
|
@ -94,6 +95,126 @@ void __init r8a7740_pinmux_init(void)
|
|||
platform_device_register(&r8a7740_pfc_device);
|
||||
}
|
||||
|
||||
static struct renesas_intc_irqpin_config irqpin0_platform_data = {
|
||||
.irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
|
||||
};
|
||||
|
||||
static struct resource irqpin0_resources[] = {
|
||||
DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
|
||||
DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
|
||||
DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
|
||||
DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
|
||||
DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
|
||||
};
|
||||
|
||||
static struct platform_device irqpin0_device = {
|
||||
.name = "renesas_intc_irqpin",
|
||||
.id = 0,
|
||||
.resource = irqpin0_resources,
|
||||
.num_resources = ARRAY_SIZE(irqpin0_resources),
|
||||
.dev = {
|
||||
.platform_data = &irqpin0_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct renesas_intc_irqpin_config irqpin1_platform_data = {
|
||||
.irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
|
||||
};
|
||||
|
||||
static struct resource irqpin1_resources[] = {
|
||||
DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
|
||||
DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
|
||||
DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
|
||||
DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
|
||||
DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
|
||||
};
|
||||
|
||||
static struct platform_device irqpin1_device = {
|
||||
.name = "renesas_intc_irqpin",
|
||||
.id = 1,
|
||||
.resource = irqpin1_resources,
|
||||
.num_resources = ARRAY_SIZE(irqpin1_resources),
|
||||
.dev = {
|
||||
.platform_data = &irqpin1_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct renesas_intc_irqpin_config irqpin2_platform_data = {
|
||||
.irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
|
||||
};
|
||||
|
||||
static struct resource irqpin2_resources[] = {
|
||||
DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
|
||||
DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
|
||||
DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
|
||||
DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
|
||||
DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
|
||||
};
|
||||
|
||||
static struct platform_device irqpin2_device = {
|
||||
.name = "renesas_intc_irqpin",
|
||||
.id = 2,
|
||||
.resource = irqpin2_resources,
|
||||
.num_resources = ARRAY_SIZE(irqpin2_resources),
|
||||
.dev = {
|
||||
.platform_data = &irqpin2_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct renesas_intc_irqpin_config irqpin3_platform_data = {
|
||||
.irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
|
||||
};
|
||||
|
||||
static struct resource irqpin3_resources[] = {
|
||||
DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
|
||||
DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
|
||||
DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
|
||||
DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
|
||||
DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
|
||||
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
|
||||
};
|
||||
|
||||
static struct platform_device irqpin3_device = {
|
||||
.name = "renesas_intc_irqpin",
|
||||
.id = 3,
|
||||
.resource = irqpin3_resources,
|
||||
.num_resources = ARRAY_SIZE(irqpin3_resources),
|
||||
.dev = {
|
||||
.platform_data = &irqpin3_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* SCIFA0 */
|
||||
static struct plat_sci_port scif0_platform_data = {
|
||||
.mapbase = 0xe6c40000,
|
||||
|
|
@ -101,7 +222,7 @@ static struct plat_sci_port scif0_platform_data = {
|
|||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFA,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
|
||||
.irqs = SCIx_IRQ_MUXED(gic_spi(100)),
|
||||
};
|
||||
|
||||
static struct platform_device scif0_device = {
|
||||
|
|
@ -119,7 +240,7 @@ static struct plat_sci_port scif1_platform_data = {
|
|||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFA,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
|
||||
.irqs = SCIx_IRQ_MUXED(gic_spi(101)),
|
||||
};
|
||||
|
||||
static struct platform_device scif1_device = {
|
||||
|
|
@ -137,7 +258,7 @@ static struct plat_sci_port scif2_platform_data = {
|
|||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFA,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
|
||||
.irqs = SCIx_IRQ_MUXED(gic_spi(102)),
|
||||
};
|
||||
|
||||
static struct platform_device scif2_device = {
|
||||
|
|
@ -155,7 +276,7 @@ static struct plat_sci_port scif3_platform_data = {
|
|||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFA,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
|
||||
.irqs = SCIx_IRQ_MUXED(gic_spi(103)),
|
||||
};
|
||||
|
||||
static struct platform_device scif3_device = {
|
||||
|
|
@ -173,7 +294,7 @@ static struct plat_sci_port scif4_platform_data = {
|
|||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFA,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
|
||||
.irqs = SCIx_IRQ_MUXED(gic_spi(104)),
|
||||
};
|
||||
|
||||
static struct platform_device scif4_device = {
|
||||
|
|
@ -191,7 +312,7 @@ static struct plat_sci_port scif5_platform_data = {
|
|||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFA,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
|
||||
.irqs = SCIx_IRQ_MUXED(gic_spi(105)),
|
||||
};
|
||||
|
||||
static struct platform_device scif5_device = {
|
||||
|
|
@ -209,7 +330,7 @@ static struct plat_sci_port scif6_platform_data = {
|
|||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFA,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
|
||||
.irqs = SCIx_IRQ_MUXED(gic_spi(106)),
|
||||
};
|
||||
|
||||
static struct platform_device scif6_device = {
|
||||
|
|
@ -227,7 +348,7 @@ static struct plat_sci_port scif7_platform_data = {
|
|||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFA,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
|
||||
.irqs = SCIx_IRQ_MUXED(gic_spi(107)),
|
||||
};
|
||||
|
||||
static struct platform_device scif7_device = {
|
||||
|
|
@ -245,7 +366,7 @@ static struct plat_sci_port scifb_platform_data = {
|
|||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFB,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
|
||||
.irqs = SCIx_IRQ_MUXED(gic_spi(108)),
|
||||
};
|
||||
|
||||
static struct platform_device scifb_device = {
|
||||
|
|
@ -273,7 +394,7 @@ static struct resource cmt10_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = evt2irq(0x0b00),
|
||||
.start = gic_spi(58),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -304,7 +425,7 @@ static struct resource tmu00_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = intcs_evt2irq(0xe80),
|
||||
.start = gic_spi(198),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -334,7 +455,7 @@ static struct resource tmu01_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = intcs_evt2irq(0xea0),
|
||||
.start = gic_spi(199),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -364,7 +485,7 @@ static struct resource tmu02_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = intcs_evt2irq(0xec0),
|
||||
.start = gic_spi(200),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -411,6 +532,10 @@ static struct platform_device ipmmu_device = {
|
|||
};
|
||||
|
||||
static struct platform_device *r8a7740_early_devices[] __initdata = {
|
||||
&irqpin0_device,
|
||||
&irqpin1_device,
|
||||
&irqpin2_device,
|
||||
&irqpin3_device,
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
|
|
@ -525,14 +650,14 @@ static struct resource r8a7740_dmae0_resources[] = {
|
|||
},
|
||||
{
|
||||
.name = "error_irq",
|
||||
.start = evt2irq(0x20c0),
|
||||
.end = evt2irq(0x20c0),
|
||||
.start = gic_spi(34),
|
||||
.end = gic_spi(34),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 0-5 */
|
||||
.start = evt2irq(0x2000),
|
||||
.end = evt2irq(0x20a0),
|
||||
.start = gic_spi(28),
|
||||
.end = gic_spi(33),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -553,14 +678,14 @@ static struct resource r8a7740_dmae1_resources[] = {
|
|||
},
|
||||
{
|
||||
.name = "error_irq",
|
||||
.start = evt2irq(0x21c0),
|
||||
.end = evt2irq(0x21c0),
|
||||
.start = gic_spi(41),
|
||||
.end = gic_spi(41),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 0-5 */
|
||||
.start = evt2irq(0x2100),
|
||||
.end = evt2irq(0x21a0),
|
||||
.start = gic_spi(35),
|
||||
.end = gic_spi(40),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -581,14 +706,14 @@ static struct resource r8a7740_dmae2_resources[] = {
|
|||
},
|
||||
{
|
||||
.name = "error_irq",
|
||||
.start = evt2irq(0x22c0),
|
||||
.end = evt2irq(0x22c0),
|
||||
.start = gic_spi(48),
|
||||
.end = gic_spi(48),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 0-5 */
|
||||
.start = evt2irq(0x2200),
|
||||
.end = evt2irq(0x22a0),
|
||||
.start = gic_spi(42),
|
||||
.end = gic_spi(47),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -677,8 +802,8 @@ static struct resource r8a7740_usb_dma_resources[] = {
|
|||
},
|
||||
{
|
||||
/* IRQ for channels */
|
||||
.start = evt2irq(0x0a00),
|
||||
.end = evt2irq(0x0a00),
|
||||
.start = gic_spi(49),
|
||||
.end = gic_spi(49),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -702,8 +827,8 @@ static struct resource i2c0_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = intcs_evt2irq(0xe00),
|
||||
.end = intcs_evt2irq(0xe60),
|
||||
.start = gic_spi(201),
|
||||
.end = gic_spi(204),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -716,8 +841,8 @@ static struct resource i2c1_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = evt2irq(0x780), /* IIC1_ALI1 */
|
||||
.end = evt2irq(0x7e0), /* IIC1_DTEI1 */
|
||||
.start = gic_spi(70), /* IIC1_ALI1 */
|
||||
.end = gic_spi(73), /* IIC1_DTEI1 */
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -738,8 +863,8 @@ static struct platform_device i2c1_device = {
|
|||
|
||||
static struct resource pmu_resources[] = {
|
||||
[0] = {
|
||||
.start = evt2irq(0x19a0),
|
||||
.end = evt2irq(0x19a0),
|
||||
.start = gic_spi(83),
|
||||
.end = gic_spi(83),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -904,7 +1029,6 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
|
|||
.map_io = r8a7740_map_io,
|
||||
.init_early = r8a7740_add_early_devices_dt,
|
||||
.init_irq = r8a7740_init_irq,
|
||||
.handle_irq = shmobile_handle_irq_intc,
|
||||
.init_machine = r8a7740_add_standard_devices_dt,
|
||||
.init_time = shmobile_timer_init,
|
||||
.dt_compat = r8a7740_boards_compat_dt,
|
||||
|
|
|
|||
193
arch/arm/mach-shmobile/setup-r8a7778.c
Normal file
193
arch/arm/mach-shmobile/setup-r8a7778.c
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* r8a7778 processor support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/r8a7778.h>
|
||||
#include <mach/common.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
|
||||
/* SCIF */
|
||||
#define SCIF_INFO(baseaddr, irq) \
|
||||
{ \
|
||||
.mapbase = baseaddr, \
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
|
||||
.scbrr_algo_id = SCBRR_ALGO_2, \
|
||||
.type = PORT_SCIF, \
|
||||
.irqs = SCIx_IRQ_MUXED(irq), \
|
||||
}
|
||||
|
||||
static struct plat_sci_port scif_platform_data[] = {
|
||||
SCIF_INFO(0xffe40000, gic_iid(0x66)),
|
||||
SCIF_INFO(0xffe41000, gic_iid(0x67)),
|
||||
SCIF_INFO(0xffe42000, gic_iid(0x68)),
|
||||
SCIF_INFO(0xffe43000, gic_iid(0x69)),
|
||||
SCIF_INFO(0xffe44000, gic_iid(0x6a)),
|
||||
SCIF_INFO(0xffe45000, gic_iid(0x6b)),
|
||||
};
|
||||
|
||||
/* TMU */
|
||||
static struct resource sh_tmu0_resources[] = {
|
||||
DEFINE_RES_MEM(0xffd80008, 12),
|
||||
DEFINE_RES_IRQ(gic_iid(0x40)),
|
||||
};
|
||||
|
||||
static struct sh_timer_config sh_tmu0_platform_data = {
|
||||
.name = "TMU00",
|
||||
.channel_offset = 0x4,
|
||||
.timer_bit = 0,
|
||||
.clockevent_rating = 200,
|
||||
};
|
||||
|
||||
static struct resource sh_tmu1_resources[] = {
|
||||
DEFINE_RES_MEM(0xffd80014, 12),
|
||||
DEFINE_RES_IRQ(gic_iid(0x41)),
|
||||
};
|
||||
|
||||
static struct sh_timer_config sh_tmu1_platform_data = {
|
||||
.name = "TMU01",
|
||||
.channel_offset = 0x10,
|
||||
.timer_bit = 1,
|
||||
.clocksource_rating = 200,
|
||||
};
|
||||
|
||||
#define PLATFORM_INFO(n, i) \
|
||||
{ \
|
||||
.parent = &platform_bus, \
|
||||
.name = #n, \
|
||||
.id = i, \
|
||||
.res = n ## i ## _resources, \
|
||||
.num_res = ARRAY_SIZE(n ## i ##_resources), \
|
||||
.data = &n ## i ##_platform_data, \
|
||||
.size_data = sizeof(n ## i ## _platform_data), \
|
||||
}
|
||||
|
||||
struct platform_device_info platform_devinfo[] = {
|
||||
PLATFORM_INFO(sh_tmu, 0),
|
||||
PLATFORM_INFO(sh_tmu, 1),
|
||||
};
|
||||
|
||||
void __init r8a7778_add_standard_devices(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
|
||||
if (base) {
|
||||
/*
|
||||
* Early BRESP enable, Shared attribute override enable, 64K*16way
|
||||
* don't call iounmap(base)
|
||||
*/
|
||||
l2x0_init(base, 0x40470000, 0x82000fff);
|
||||
}
|
||||
#endif
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++)
|
||||
platform_device_register_data(&platform_bus, "sh-sci", i,
|
||||
&scif_platform_data[i],
|
||||
sizeof(struct plat_sci_port));
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(platform_devinfo); i++)
|
||||
platform_device_register_full(&platform_devinfo[i]);
|
||||
}
|
||||
|
||||
#define INT2SMSKCR0 0x82288 /* 0xfe782288 */
|
||||
#define INT2SMSKCR1 0x8228c /* 0xfe78228c */
|
||||
|
||||
#define INT2NTSR0 0x00018 /* 0xfe700018 */
|
||||
#define INT2NTSR1 0x0002c /* 0xfe70002c */
|
||||
static void __init r8a7778_init_irq_common(void)
|
||||
{
|
||||
void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
|
||||
|
||||
BUG_ON(!base);
|
||||
|
||||
/* route all interrupts to ARM */
|
||||
__raw_writel(0x73ffffff, base + INT2NTSR0);
|
||||
__raw_writel(0xffffffff, base + INT2NTSR1);
|
||||
|
||||
/* unmask all known interrupts in INTCS2 */
|
||||
__raw_writel(0x08330773, base + INT2SMSKCR0);
|
||||
__raw_writel(0x00311110, base + INT2SMSKCR1);
|
||||
|
||||
iounmap(base);
|
||||
}
|
||||
|
||||
void __init r8a7778_init_irq(void)
|
||||
{
|
||||
void __iomem *gic_dist_base;
|
||||
void __iomem *gic_cpu_base;
|
||||
|
||||
gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE);
|
||||
gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE);
|
||||
BUG_ON(!gic_dist_base || !gic_cpu_base);
|
||||
|
||||
/* use GIC to handle interrupts */
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
|
||||
r8a7778_init_irq_common();
|
||||
}
|
||||
|
||||
void __init r8a7778_init_delay(void)
|
||||
{
|
||||
shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USE_OF
|
||||
void __init r8a7778_init_irq_dt(void)
|
||||
{
|
||||
irqchip_init();
|
||||
r8a7778_init_irq_common();
|
||||
}
|
||||
|
||||
static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = {
|
||||
{},
|
||||
};
|
||||
|
||||
void __init r8a7778_add_standard_devices_dt(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
r8a7778_auxdata_lookup, NULL);
|
||||
}
|
||||
|
||||
static const char *r8a7778_compat_dt[] __initdata = {
|
||||
"renesas,r8a7778",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
|
||||
.init_early = r8a7778_init_delay,
|
||||
.init_irq = r8a7778_init_irq_dt,
|
||||
.init_machine = r8a7778_add_standard_devices_dt,
|
||||
.init_time = shmobile_timer_init,
|
||||
.dt_compat = r8a7778_compat_dt,
|
||||
MACHINE_END
|
||||
|
||||
#endif /* CONFIG_USE_OF */
|
||||
|
|
@ -21,6 +21,8 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_data/gpio-rcar.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/input.h>
|
||||
|
|
@ -28,6 +30,7 @@
|
|||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_intc.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/r8a7779.h>
|
||||
|
|
@ -66,11 +69,6 @@ static struct resource r8a7779_pfc_resources[] = {
|
|||
.end = 0xfffc023b,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 0xffc40000,
|
||||
.end = 0xffc46fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device r8a7779_pfc_device = {
|
||||
|
|
@ -80,9 +78,59 @@ static struct platform_device r8a7779_pfc_device = {
|
|||
.num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
|
||||
};
|
||||
|
||||
#define R8A7779_GPIO(idx, npins) \
|
||||
static struct resource r8a7779_gpio##idx##_resources[] = { \
|
||||
[0] = { \
|
||||
.start = 0xffc40000 + 0x1000 * (idx), \
|
||||
.end = 0xffc4002b + 0x1000 * (idx), \
|
||||
.flags = IORESOURCE_MEM, \
|
||||
}, \
|
||||
[1] = { \
|
||||
.start = gic_iid(0xad + (idx)), \
|
||||
.flags = IORESOURCE_IRQ, \
|
||||
} \
|
||||
}; \
|
||||
\
|
||||
static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \
|
||||
.gpio_base = 32 * (idx), \
|
||||
.irq_base = 0, \
|
||||
.number_of_pins = npins, \
|
||||
.pctl_name = "pfc-r8a7779", \
|
||||
}; \
|
||||
\
|
||||
static struct platform_device r8a7779_gpio##idx##_device = { \
|
||||
.name = "gpio_rcar", \
|
||||
.id = idx, \
|
||||
.resource = r8a7779_gpio##idx##_resources, \
|
||||
.num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \
|
||||
.dev = { \
|
||||
.platform_data = &r8a7779_gpio##idx##_platform_data, \
|
||||
}, \
|
||||
}
|
||||
|
||||
R8A7779_GPIO(0, 32);
|
||||
R8A7779_GPIO(1, 32);
|
||||
R8A7779_GPIO(2, 32);
|
||||
R8A7779_GPIO(3, 32);
|
||||
R8A7779_GPIO(4, 32);
|
||||
R8A7779_GPIO(5, 32);
|
||||
R8A7779_GPIO(6, 9);
|
||||
|
||||
static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
|
||||
&r8a7779_pfc_device,
|
||||
&r8a7779_gpio0_device,
|
||||
&r8a7779_gpio1_device,
|
||||
&r8a7779_gpio2_device,
|
||||
&r8a7779_gpio3_device,
|
||||
&r8a7779_gpio4_device,
|
||||
&r8a7779_gpio5_device,
|
||||
&r8a7779_gpio6_device,
|
||||
};
|
||||
|
||||
void __init r8a7779_pinmux_init(void)
|
||||
{
|
||||
platform_device_register(&r8a7779_pfc_device);
|
||||
platform_add_devices(r8a7779_pinctrl_devices,
|
||||
ARRAY_SIZE(r8a7779_pinctrl_devices));
|
||||
}
|
||||
|
||||
static struct plat_sci_port scif0_platform_data = {
|
||||
|
|
@ -91,7 +139,7 @@ static struct plat_sci_port scif0_platform_data = {
|
|||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = SCIx_IRQ_MUXED(gic_spi(88)),
|
||||
.irqs = SCIx_IRQ_MUXED(gic_iid(0x78)),
|
||||
};
|
||||
|
||||
static struct platform_device scif0_device = {
|
||||
|
|
@ -108,7 +156,7 @@ static struct plat_sci_port scif1_platform_data = {
|
|||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = SCIx_IRQ_MUXED(gic_spi(89)),
|
||||
.irqs = SCIx_IRQ_MUXED(gic_iid(0x79)),
|
||||
};
|
||||
|
||||
static struct platform_device scif1_device = {
|
||||
|
|
@ -125,7 +173,7 @@ static struct plat_sci_port scif2_platform_data = {
|
|||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = SCIx_IRQ_MUXED(gic_spi(90)),
|
||||
.irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)),
|
||||
};
|
||||
|
||||
static struct platform_device scif2_device = {
|
||||
|
|
@ -142,7 +190,7 @@ static struct plat_sci_port scif3_platform_data = {
|
|||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = SCIx_IRQ_MUXED(gic_spi(91)),
|
||||
.irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)),
|
||||
};
|
||||
|
||||
static struct platform_device scif3_device = {
|
||||
|
|
@ -159,7 +207,7 @@ static struct plat_sci_port scif4_platform_data = {
|
|||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = SCIx_IRQ_MUXED(gic_spi(92)),
|
||||
.irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)),
|
||||
};
|
||||
|
||||
static struct platform_device scif4_device = {
|
||||
|
|
@ -176,7 +224,7 @@ static struct plat_sci_port scif5_platform_data = {
|
|||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = SCIx_IRQ_MUXED(gic_spi(93)),
|
||||
.irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)),
|
||||
};
|
||||
|
||||
static struct platform_device scif5_device = {
|
||||
|
|
@ -203,7 +251,7 @@ static struct resource tmu00_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_spi(32),
|
||||
.start = gic_iid(0x40),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -233,7 +281,7 @@ static struct resource tmu01_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_spi(33),
|
||||
.start = gic_iid(0x41),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -255,7 +303,7 @@ static struct resource rcar_i2c0_res[] = {
|
|||
.end = 0xffc70fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = gic_spi(79),
|
||||
.start = gic_iid(0x6f),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -273,7 +321,7 @@ static struct resource rcar_i2c1_res[] = {
|
|||
.end = 0xffc71fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = gic_spi(82),
|
||||
.start = gic_iid(0x72),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -291,7 +339,7 @@ static struct resource rcar_i2c2_res[] = {
|
|||
.end = 0xffc72fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = gic_spi(80),
|
||||
.start = gic_iid(0x70),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -309,7 +357,7 @@ static struct resource rcar_i2c3_res[] = {
|
|||
.end = 0xffc73fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = gic_spi(81),
|
||||
.start = gic_iid(0x71),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
|
@ -321,7 +369,31 @@ static struct platform_device i2c3_device = {
|
|||
.num_resources = ARRAY_SIZE(rcar_i2c3_res),
|
||||
};
|
||||
|
||||
static struct platform_device *r8a7779_early_devices[] __initdata = {
|
||||
static struct resource sata_resources[] = {
|
||||
[0] = {
|
||||
.name = "rcar-sata",
|
||||
.start = 0xfc600000,
|
||||
.end = 0xfc601fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_iid(0x84),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device sata_device = {
|
||||
.name = "sata_rcar",
|
||||
.id = -1,
|
||||
.resource = sata_resources,
|
||||
.num_resources = ARRAY_SIZE(sata_resources),
|
||||
.dev = {
|
||||
.dma_mask = &sata_device.dev.coherent_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *r8a7779_devices_dt[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
|
|
@ -330,13 +402,14 @@ static struct platform_device *r8a7779_early_devices[] __initdata = {
|
|||
&scif5_device,
|
||||
&tmu00_device,
|
||||
&tmu01_device,
|
||||
};
|
||||
|
||||
static struct platform_device *r8a7779_late_devices[] __initdata = {
|
||||
&i2c0_device,
|
||||
&i2c1_device,
|
||||
&i2c2_device,
|
||||
&i2c3_device,
|
||||
};
|
||||
|
||||
static struct platform_device *r8a7779_late_devices[] __initdata = {
|
||||
&sata_device,
|
||||
};
|
||||
|
||||
void __init r8a7779_add_standard_devices(void)
|
||||
|
|
@ -349,8 +422,8 @@ void __init r8a7779_add_standard_devices(void)
|
|||
|
||||
r8a7779_init_pm_domains();
|
||||
|
||||
platform_add_devices(r8a7779_early_devices,
|
||||
ARRAY_SIZE(r8a7779_early_devices));
|
||||
platform_add_devices(r8a7779_devices_dt,
|
||||
ARRAY_SIZE(r8a7779_devices_dt));
|
||||
platform_add_devices(r8a7779_late_devices,
|
||||
ARRAY_SIZE(r8a7779_late_devices));
|
||||
}
|
||||
|
|
@ -367,8 +440,8 @@ void __init r8a7779_earlytimer_init(void)
|
|||
|
||||
void __init r8a7779_add_early_devices(void)
|
||||
{
|
||||
early_platform_add_devices(r8a7779_early_devices,
|
||||
ARRAY_SIZE(r8a7779_early_devices));
|
||||
early_platform_add_devices(r8a7779_devices_dt,
|
||||
ARRAY_SIZE(r8a7779_devices_dt));
|
||||
|
||||
/* Early serial console setup is not included here due to
|
||||
* memory map collisions. The SCIF serial ports in r8a7779
|
||||
|
|
@ -386,3 +459,40 @@ void __init r8a7779_add_early_devices(void)
|
|||
* command line in case of the marzen board.
|
||||
*/
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USE_OF
|
||||
void __init r8a7779_init_delay(void)
|
||||
{
|
||||
shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
|
||||
}
|
||||
|
||||
static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = {
|
||||
{},
|
||||
};
|
||||
|
||||
void __init r8a7779_add_standard_devices_dt(void)
|
||||
{
|
||||
/* clocks are setup late during boot in the case of DT */
|
||||
r8a7779_clock_init();
|
||||
|
||||
platform_add_devices(r8a7779_devices_dt,
|
||||
ARRAY_SIZE(r8a7779_devices_dt));
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
r8a7779_auxdata_lookup, NULL);
|
||||
}
|
||||
|
||||
static const char *r8a7779_compat_dt[] __initdata = {
|
||||
"renesas,r8a7779",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
|
||||
.map_io = r8a7779_map_io,
|
||||
.init_early = r8a7779_init_delay,
|
||||
.nr_irqs = NR_IRQS_LEGACY,
|
||||
.init_irq = r8a7779_init_irq_dt,
|
||||
.init_machine = r8a7779_add_standard_devices_dt,
|
||||
.init_time = shmobile_timer_init,
|
||||
.dt_compat = r8a7779_compat_dt,
|
||||
MACHINE_END
|
||||
#endif /* CONFIG_USE_OF */
|
||||
|
|
|
|||
137
arch/arm/mach-shmobile/setup-r8a7790.c
Normal file
137
arch/arm/mach-shmobile/setup-r8a7790.c
Normal file
|
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* r8a7790 processor support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/platform_data/irq-renesas-irqc.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/r8a7790.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
static const struct resource pfc_resources[] = {
|
||||
DEFINE_RES_MEM(0xe6060000, 0x250),
|
||||
};
|
||||
|
||||
void __init r8a7790_pinmux_init(void)
|
||||
{
|
||||
platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
|
||||
ARRAY_SIZE(pfc_resources));
|
||||
}
|
||||
|
||||
#define SCIF_COMMON(scif_type, baseaddr, irq) \
|
||||
.type = scif_type, \
|
||||
.mapbase = baseaddr, \
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
|
||||
.irqs = SCIx_IRQ_MUXED(irq)
|
||||
|
||||
#define SCIFA_DATA(index, baseaddr, irq) \
|
||||
[index] = { \
|
||||
SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
|
||||
.scbrr_algo_id = SCBRR_ALGO_4, \
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
|
||||
}
|
||||
|
||||
#define SCIFB_DATA(index, baseaddr, irq) \
|
||||
[index] = { \
|
||||
SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
|
||||
.scbrr_algo_id = SCBRR_ALGO_4, \
|
||||
.scscr = SCSCR_RE | SCSCR_TE, \
|
||||
}
|
||||
|
||||
#define SCIF_DATA(index, baseaddr, irq) \
|
||||
[index] = { \
|
||||
SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
|
||||
.scbrr_algo_id = SCBRR_ALGO_2, \
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
|
||||
}
|
||||
|
||||
enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 };
|
||||
|
||||
static const struct plat_sci_port scif[] = {
|
||||
SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
|
||||
SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
|
||||
SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
|
||||
SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
|
||||
SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
|
||||
SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
|
||||
SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
|
||||
SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
|
||||
};
|
||||
|
||||
static inline void r8a7790_register_scif(int idx)
|
||||
{
|
||||
platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
|
||||
sizeof(struct plat_sci_port));
|
||||
}
|
||||
|
||||
static struct renesas_irqc_config irqc0_data = {
|
||||
.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
|
||||
};
|
||||
|
||||
static struct resource irqc0_resources[] = {
|
||||
DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
|
||||
DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
|
||||
DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
|
||||
DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
|
||||
DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
|
||||
};
|
||||
|
||||
#define r8a7790_register_irqc(idx) \
|
||||
platform_device_register_resndata(&platform_bus, "renesas_irqc", \
|
||||
idx, irqc##idx##_resources, \
|
||||
ARRAY_SIZE(irqc##idx##_resources), \
|
||||
&irqc##idx##_data, \
|
||||
sizeof(struct renesas_irqc_config))
|
||||
|
||||
void __init r8a7790_add_standard_devices(void)
|
||||
{
|
||||
r8a7790_register_scif(SCIFA0);
|
||||
r8a7790_register_scif(SCIFA1);
|
||||
r8a7790_register_scif(SCIFB0);
|
||||
r8a7790_register_scif(SCIFB1);
|
||||
r8a7790_register_scif(SCIFB2);
|
||||
r8a7790_register_scif(SCIFA2);
|
||||
r8a7790_register_scif(SCIF0);
|
||||
r8a7790_register_scif(SCIF1);
|
||||
r8a7790_register_irqc(0);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USE_OF
|
||||
void __init r8a7790_add_standard_devices_dt(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static const char *r8a7790_boards_compat_dt[] __initdata = {
|
||||
"renesas,r8a7790",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
|
||||
.init_irq = irqchip_init,
|
||||
.init_machine = r8a7790_add_standard_devices_dt,
|
||||
.init_time = shmobile_timer_init,
|
||||
.dt_compat = r8a7790_boards_compat_dt,
|
||||
MACHINE_END
|
||||
#endif /* CONFIG_USE_OF */
|
||||
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/delay.h>
|
||||
|
|
@ -32,6 +33,7 @@
|
|||
#include <linux/sh_intc.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <linux/platform_data/sh_ipmmu.h>
|
||||
#include <linux/platform_data/irq-renesas-intc-irqpin.h>
|
||||
#include <mach/dma-register.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/irqs.h>
|
||||
|
|
@ -810,7 +812,128 @@ static struct platform_device ipmmu_device = {
|
|||
.num_resources = ARRAY_SIZE(ipmmu_resources),
|
||||
};
|
||||
|
||||
static struct platform_device *sh73a0_early_devices_dt[] __initdata = {
|
||||
static struct renesas_intc_irqpin_config irqpin0_platform_data = {
|
||||
.irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
|
||||
};
|
||||
|
||||
static struct resource irqpin0_resources[] = {
|
||||
DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
|
||||
DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
|
||||
DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
|
||||
DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
|
||||
DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
|
||||
DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
|
||||
DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
|
||||
DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
|
||||
DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
|
||||
DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
|
||||
DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
|
||||
DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
|
||||
DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
|
||||
};
|
||||
|
||||
static struct platform_device irqpin0_device = {
|
||||
.name = "renesas_intc_irqpin",
|
||||
.id = 0,
|
||||
.resource = irqpin0_resources,
|
||||
.num_resources = ARRAY_SIZE(irqpin0_resources),
|
||||
.dev = {
|
||||
.platform_data = &irqpin0_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct renesas_intc_irqpin_config irqpin1_platform_data = {
|
||||
.irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
|
||||
.control_parent = true, /* Disable spurious IRQ10 */
|
||||
};
|
||||
|
||||
static struct resource irqpin1_resources[] = {
|
||||
DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
|
||||
DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
|
||||
DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
|
||||
DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
|
||||
DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
|
||||
DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
|
||||
DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
|
||||
DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
|
||||
DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
|
||||
DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
|
||||
DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
|
||||
DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
|
||||
DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
|
||||
};
|
||||
|
||||
static struct platform_device irqpin1_device = {
|
||||
.name = "renesas_intc_irqpin",
|
||||
.id = 1,
|
||||
.resource = irqpin1_resources,
|
||||
.num_resources = ARRAY_SIZE(irqpin1_resources),
|
||||
.dev = {
|
||||
.platform_data = &irqpin1_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct renesas_intc_irqpin_config irqpin2_platform_data = {
|
||||
.irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
|
||||
};
|
||||
|
||||
static struct resource irqpin2_resources[] = {
|
||||
DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
|
||||
DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
|
||||
DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
|
||||
DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
|
||||
DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
|
||||
DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
|
||||
DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
|
||||
DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
|
||||
DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
|
||||
DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
|
||||
DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
|
||||
DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
|
||||
DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
|
||||
};
|
||||
|
||||
static struct platform_device irqpin2_device = {
|
||||
.name = "renesas_intc_irqpin",
|
||||
.id = 2,
|
||||
.resource = irqpin2_resources,
|
||||
.num_resources = ARRAY_SIZE(irqpin2_resources),
|
||||
.dev = {
|
||||
.platform_data = &irqpin2_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct renesas_intc_irqpin_config irqpin3_platform_data = {
|
||||
.irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
|
||||
};
|
||||
|
||||
static struct resource irqpin3_resources[] = {
|
||||
DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
|
||||
DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
|
||||
DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
|
||||
DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
|
||||
DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
|
||||
DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
|
||||
DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
|
||||
DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
|
||||
DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
|
||||
DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
|
||||
DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
|
||||
DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
|
||||
DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
|
||||
};
|
||||
|
||||
static struct platform_device irqpin3_device = {
|
||||
.name = "renesas_intc_irqpin",
|
||||
.id = 3,
|
||||
.resource = irqpin3_resources,
|
||||
.num_resources = ARRAY_SIZE(irqpin3_resources),
|
||||
.dev = {
|
||||
.platform_data = &irqpin3_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *sh73a0_devices_dt[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
|
|
@ -838,6 +961,10 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
|
|||
&dma0_device,
|
||||
&mpdma0_device,
|
||||
&pmu_device,
|
||||
&irqpin0_device,
|
||||
&irqpin1_device,
|
||||
&irqpin2_device,
|
||||
&irqpin3_device,
|
||||
};
|
||||
|
||||
#define SRCR2 IOMEM(0xe61580b0)
|
||||
|
|
@ -847,8 +974,8 @@ void __init sh73a0_add_standard_devices(void)
|
|||
/* Clear software reset bit on SY-DMAC module */
|
||||
__raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
|
||||
|
||||
platform_add_devices(sh73a0_early_devices_dt,
|
||||
ARRAY_SIZE(sh73a0_early_devices_dt));
|
||||
platform_add_devices(sh73a0_devices_dt,
|
||||
ARRAY_SIZE(sh73a0_devices_dt));
|
||||
platform_add_devices(sh73a0_early_devices,
|
||||
ARRAY_SIZE(sh73a0_early_devices));
|
||||
platform_add_devices(sh73a0_late_devices,
|
||||
|
|
@ -867,8 +994,8 @@ void __init sh73a0_earlytimer_init(void)
|
|||
|
||||
void __init sh73a0_add_early_devices(void)
|
||||
{
|
||||
early_platform_add_devices(sh73a0_early_devices_dt,
|
||||
ARRAY_SIZE(sh73a0_early_devices_dt));
|
||||
early_platform_add_devices(sh73a0_devices_dt,
|
||||
ARRAY_SIZE(sh73a0_devices_dt));
|
||||
early_platform_add_devices(sh73a0_early_devices,
|
||||
ARRAY_SIZE(sh73a0_early_devices));
|
||||
|
||||
|
|
@ -878,23 +1005,9 @@ void __init sh73a0_add_early_devices(void)
|
|||
|
||||
#ifdef CONFIG_USE_OF
|
||||
|
||||
/* Please note that the clock initialisation shcheme used in
|
||||
* sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt()
|
||||
* does not work with SMP as there is a yet to be resolved lock-up in
|
||||
* workqueue initialisation.
|
||||
*
|
||||
* CONFIG_SMP should be disabled when using this code.
|
||||
*/
|
||||
|
||||
void __init sh73a0_add_early_devices_dt(void)
|
||||
void __init sh73a0_init_delay(void)
|
||||
{
|
||||
shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
|
||||
|
||||
early_platform_add_devices(sh73a0_early_devices_dt,
|
||||
ARRAY_SIZE(sh73a0_early_devices_dt));
|
||||
|
||||
/* setup early console here as well */
|
||||
shmobile_setup_console();
|
||||
}
|
||||
|
||||
static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
|
||||
|
|
@ -906,8 +1019,8 @@ void __init sh73a0_add_standard_devices_dt(void)
|
|||
/* clocks are setup late during boot in the case of DT */
|
||||
sh73a0_clock_init();
|
||||
|
||||
platform_add_devices(sh73a0_early_devices_dt,
|
||||
ARRAY_SIZE(sh73a0_early_devices_dt));
|
||||
platform_add_devices(sh73a0_devices_dt,
|
||||
ARRAY_SIZE(sh73a0_devices_dt));
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
sh73a0_auxdata_lookup, NULL);
|
||||
}
|
||||
|
|
@ -918,10 +1031,11 @@ static const char *sh73a0_boards_compat_dt[] __initdata = {
|
|||
};
|
||||
|
||||
DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
|
||||
.smp = smp_ops(sh73a0_smp_ops),
|
||||
.map_io = sh73a0_map_io,
|
||||
.init_early = sh73a0_add_early_devices_dt,
|
||||
.init_early = sh73a0_init_delay,
|
||||
.nr_irqs = NR_IRQS_LEGACY,
|
||||
.init_irq = sh73a0_init_irq_dt,
|
||||
.init_irq = irqchip_init,
|
||||
.init_machine = sh73a0_add_standard_devices_dt,
|
||||
.init_time = shmobile_timer_init,
|
||||
.dt_compat = sh73a0_boards_compat_dt,
|
||||
|
|
|
|||
|
|
@ -28,63 +28,9 @@
|
|||
#include <mach/emev2.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#define EMEV2_SCU_BASE 0x1e000000
|
||||
|
||||
static DEFINE_SPINLOCK(scu_lock);
|
||||
static void __iomem *scu_base;
|
||||
|
||||
static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
|
||||
{
|
||||
unsigned long tmp;
|
||||
|
||||
/* we assume this code is running on a different cpu
|
||||
* than the one that is changing coherency setting */
|
||||
spin_lock(&scu_lock);
|
||||
tmp = readl(scu_base + 8);
|
||||
tmp &= ~clr;
|
||||
tmp |= set;
|
||||
writel(tmp, scu_base + 8);
|
||||
spin_unlock(&scu_lock);
|
||||
|
||||
}
|
||||
|
||||
static unsigned int __init emev2_get_core_count(void)
|
||||
{
|
||||
if (!scu_base) {
|
||||
scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
|
||||
emev2_clock_init(); /* need ioremapped SMU */
|
||||
}
|
||||
|
||||
WARN_ON_ONCE(!scu_base);
|
||||
|
||||
return scu_base ? scu_get_core_count(scu_base) : 1;
|
||||
}
|
||||
|
||||
static int emev2_platform_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
return 0; /* not supported yet */
|
||||
}
|
||||
|
||||
static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
int k;
|
||||
|
||||
/* this function is running on another CPU than the offline target,
|
||||
* here we need wait for shutdown code in platform_cpu_die() to
|
||||
* finish before asking SoC-specific code to power off the CPU core.
|
||||
*/
|
||||
for (k = 0; k < 1000; k++) {
|
||||
if (shmobile_cpu_is_dead(cpu))
|
||||
return emev2_platform_cpu_kill(cpu);
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static void __cpuinit emev2_secondary_init(unsigned int cpu)
|
||||
{
|
||||
gic_secondary_init(0);
|
||||
|
|
@ -92,31 +38,30 @@ static void __cpuinit emev2_secondary_init(unsigned int cpu)
|
|||
|
||||
static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
cpu = cpu_logical_map(cpu);
|
||||
|
||||
/* enable cache coherency */
|
||||
modify_scu_cpu_psr(0, 3 << (cpu * 8));
|
||||
|
||||
/* Tell ROM loader about our vector (in headsmp.S) */
|
||||
emev2_set_boot_vector(__pa(shmobile_secondary_vector));
|
||||
|
||||
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
|
||||
arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu)));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
int cpu = cpu_logical_map(0);
|
||||
scu_enable(shmobile_scu_base);
|
||||
|
||||
scu_enable(scu_base);
|
||||
/* Tell ROM loader about our vector (in headsmp-scu.S) */
|
||||
emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu));
|
||||
|
||||
/* enable cache coherency on CPU0 */
|
||||
modify_scu_cpu_psr(0, 3 << (cpu * 8));
|
||||
/* enable cache coherency on booting CPU */
|
||||
scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
|
||||
}
|
||||
|
||||
static void __init emev2_smp_init_cpus(void)
|
||||
{
|
||||
unsigned int ncores = emev2_get_core_count();
|
||||
unsigned int ncores;
|
||||
|
||||
/* setup EMEV2 specific SCU base */
|
||||
shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
|
||||
emev2_clock_init(); /* need ioremapped SMU */
|
||||
|
||||
ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1;
|
||||
|
||||
shmobile_smp_init_cpus(ncores);
|
||||
}
|
||||
|
|
@ -126,9 +71,4 @@ struct smp_operations emev2_smp_ops __initdata = {
|
|||
.smp_prepare_cpus = emev2_smp_prepare_cpus,
|
||||
.smp_secondary_init = emev2_secondary_init,
|
||||
.smp_boot_secondary = emev2_boot_secondary,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_kill = emev2_cpu_kill,
|
||||
.cpu_die = shmobile_cpu_die,
|
||||
.cpu_disable = shmobile_cpu_disable,
|
||||
#endif
|
||||
};
|
||||
|
|
|
|||
|
|
@ -26,11 +26,13 @@
|
|||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/r8a7779.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/smp_twd.h>
|
||||
|
||||
#define AVECR IOMEM(0xfe700040)
|
||||
#define R8A7779_SCU_BASE 0xf0000000
|
||||
|
||||
static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
|
||||
.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
|
||||
|
|
@ -56,44 +58,14 @@ static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
|
|||
[3] = &r8a7779_ch_cpu3,
|
||||
};
|
||||
|
||||
static void __iomem *scu_base_addr(void)
|
||||
{
|
||||
return (void __iomem *)0xf0000000;
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(scu_lock);
|
||||
static unsigned long tmp;
|
||||
|
||||
#ifdef CONFIG_HAVE_ARM_TWD
|
||||
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
|
||||
|
||||
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29);
|
||||
void __init r8a7779_register_twd(void)
|
||||
{
|
||||
twd_local_timer_register(&twd_local_timer);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
|
||||
{
|
||||
void __iomem *scu_base = scu_base_addr();
|
||||
|
||||
spin_lock(&scu_lock);
|
||||
tmp = __raw_readl(scu_base + 8);
|
||||
tmp &= ~clr;
|
||||
tmp |= set;
|
||||
spin_unlock(&scu_lock);
|
||||
|
||||
/* disable cache coherency after releasing the lock */
|
||||
__raw_writel(tmp, scu_base + 8);
|
||||
}
|
||||
|
||||
static unsigned int __init r8a7779_get_core_count(void)
|
||||
{
|
||||
void __iomem *scu_base = scu_base_addr();
|
||||
|
||||
return scu_get_core_count(scu_base);
|
||||
}
|
||||
|
||||
static int r8a7779_platform_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
struct r8a7779_pm_ch *ch = NULL;
|
||||
|
|
@ -101,9 +73,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
|
|||
|
||||
cpu = cpu_logical_map(cpu);
|
||||
|
||||
/* disable cache coherency */
|
||||
modify_scu_cpu_psr(3 << (cpu * 8), 0);
|
||||
|
||||
if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
|
||||
ch = r8a7779_ch_cpu[cpu];
|
||||
|
||||
|
|
@ -113,25 +82,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
|
|||
return ret ? ret : 1;
|
||||
}
|
||||
|
||||
static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
int k;
|
||||
|
||||
/* this function is running on another CPU than the offline target,
|
||||
* here we need wait for shutdown code in platform_cpu_die() to
|
||||
* finish before asking SoC-specific code to power off the CPU core.
|
||||
*/
|
||||
for (k = 0; k < 1000; k++) {
|
||||
if (shmobile_cpu_is_dead(cpu))
|
||||
return r8a7779_platform_cpu_kill(cpu);
|
||||
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
|
||||
{
|
||||
gic_secondary_init(0);
|
||||
|
|
@ -144,9 +94,6 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
|
|||
|
||||
cpu = cpu_logical_map(cpu);
|
||||
|
||||
/* enable cache coherency */
|
||||
modify_scu_cpu_psr(0, 3 << (cpu * 8));
|
||||
|
||||
if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
|
||||
ch = r8a7779_ch_cpu[cpu];
|
||||
|
||||
|
|
@ -158,15 +105,13 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
|
|||
|
||||
static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
int cpu = cpu_logical_map(0);
|
||||
scu_enable(shmobile_scu_base);
|
||||
|
||||
scu_enable(scu_base_addr());
|
||||
/* Map the reset vector (in headsmp-scu.S) */
|
||||
__raw_writel(__pa(shmobile_secondary_vector_scu), AVECR);
|
||||
|
||||
/* Map the reset vector (in headsmp.S) */
|
||||
__raw_writel(__pa(shmobile_secondary_vector), AVECR);
|
||||
|
||||
/* enable cache coherency on CPU0 */
|
||||
modify_scu_cpu_psr(0, 3 << (cpu * 8));
|
||||
/* enable cache coherency on booting CPU */
|
||||
scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
|
||||
|
||||
r8a7779_pm_init();
|
||||
|
||||
|
|
@ -178,11 +123,61 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
|
|||
|
||||
static void __init r8a7779_smp_init_cpus(void)
|
||||
{
|
||||
unsigned int ncores = r8a7779_get_core_count();
|
||||
/* setup r8a7779 specific SCU base */
|
||||
shmobile_scu_base = IOMEM(R8A7779_SCU_BASE);
|
||||
|
||||
shmobile_smp_init_cpus(ncores);
|
||||
shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
static int r8a7779_scu_psr_core_disabled(int cpu)
|
||||
{
|
||||
unsigned long mask = 3 << (cpu * 8);
|
||||
|
||||
if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int r8a7779_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
int k;
|
||||
|
||||
/* this function is running on another CPU than the offline target,
|
||||
* here we need wait for shutdown code in platform_cpu_die() to
|
||||
* finish before asking SoC-specific code to power off the CPU core.
|
||||
*/
|
||||
for (k = 0; k < 1000; k++) {
|
||||
if (r8a7779_scu_psr_core_disabled(cpu))
|
||||
return r8a7779_platform_cpu_kill(cpu);
|
||||
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void r8a7779_cpu_die(unsigned int cpu)
|
||||
{
|
||||
dsb();
|
||||
flush_cache_all();
|
||||
|
||||
/* disable cache coherency */
|
||||
scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
|
||||
|
||||
/* Endless loop until power off from r8a7779_cpu_kill() */
|
||||
while (1)
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static int r8a7779_cpu_disable(unsigned int cpu)
|
||||
{
|
||||
/* only CPU1->3 have power domains, do not allow hotplug of CPU0 */
|
||||
return cpu == 0 ? -EPERM : 0;
|
||||
}
|
||||
#endif /* CONFIG_HOTPLUG_CPU */
|
||||
|
||||
struct smp_operations r8a7779_smp_ops __initdata = {
|
||||
.smp_init_cpus = r8a7779_smp_init_cpus,
|
||||
.smp_prepare_cpus = r8a7779_smp_prepare_cpus,
|
||||
|
|
@ -190,7 +185,7 @@ struct smp_operations r8a7779_smp_ops __initdata = {
|
|||
.smp_boot_secondary = r8a7779_boot_secondary,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_kill = r8a7779_cpu_kill,
|
||||
.cpu_die = shmobile_cpu_die,
|
||||
.cpu_disable = shmobile_cpu_disable,
|
||||
.cpu_die = r8a7779_cpu_die,
|
||||
.cpu_disable = r8a7779_cpu_disable,
|
||||
#endif
|
||||
};
|
||||
|
|
|
|||
|
|
@ -39,26 +39,16 @@
|
|||
|
||||
#define PSTR_SHUTDOWN_MODE 3
|
||||
|
||||
static void __iomem *scu_base_addr(void)
|
||||
{
|
||||
return (void __iomem *)0xf0000000;
|
||||
}
|
||||
#define SH73A0_SCU_BASE 0xf0000000
|
||||
|
||||
#ifdef CONFIG_HAVE_ARM_TWD
|
||||
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
|
||||
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
|
||||
void __init sh73a0_register_twd(void)
|
||||
{
|
||||
twd_local_timer_register(&twd_local_timer);
|
||||
}
|
||||
#endif
|
||||
|
||||
static unsigned int __init sh73a0_get_core_count(void)
|
||||
{
|
||||
void __iomem *scu_base = scu_base_addr();
|
||||
|
||||
return scu_get_core_count(scu_base);
|
||||
}
|
||||
|
||||
static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
|
||||
{
|
||||
gic_secondary_init(0);
|
||||
|
|
@ -78,21 +68,22 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
|
|||
|
||||
static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
scu_enable(scu_base_addr());
|
||||
scu_enable(shmobile_scu_base);
|
||||
|
||||
/* Map the reset vector (in headsmp-sh73a0.S) */
|
||||
/* Map the reset vector (in headsmp-scu.S) */
|
||||
__raw_writel(0, APARMBAREA); /* 4k */
|
||||
__raw_writel(__pa(sh73a0_secondary_vector), SBAR);
|
||||
__raw_writel(__pa(shmobile_secondary_vector_scu), SBAR);
|
||||
|
||||
/* enable cache coherency on booting CPU */
|
||||
scu_power_mode(scu_base_addr(), SCU_PM_NORMAL);
|
||||
scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
|
||||
}
|
||||
|
||||
static void __init sh73a0_smp_init_cpus(void)
|
||||
{
|
||||
unsigned int ncores = sh73a0_get_core_count();
|
||||
/* setup sh73a0 specific SCU base */
|
||||
shmobile_scu_base = IOMEM(SH73A0_SCU_BASE);
|
||||
|
||||
shmobile_smp_init_cpus(ncores);
|
||||
shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
|
|
@ -128,11 +119,16 @@ static void sh73a0_cpu_die(unsigned int cpu)
|
|||
flush_cache_all();
|
||||
|
||||
/* Set power off mode. This takes the CPU out of the MP cluster */
|
||||
scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF);
|
||||
scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
|
||||
|
||||
/* Enter shutdown mode */
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static int sh73a0_cpu_disable(unsigned int cpu)
|
||||
{
|
||||
return 0; /* CPU0 and CPU1 supported */
|
||||
}
|
||||
#endif /* CONFIG_HOTPLUG_CPU */
|
||||
|
||||
struct smp_operations sh73a0_smp_ops __initdata = {
|
||||
|
|
@ -143,6 +139,6 @@ struct smp_operations sh73a0_smp_ops __initdata = {
|
|||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_kill = sh73a0_cpu_kill,
|
||||
.cpu_die = sh73a0_cpu_die,
|
||||
.cpu_disable = shmobile_cpu_disable_any,
|
||||
.cpu_disable = sh73a0_cpu_disable,
|
||||
#endif
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,12 +8,23 @@
|
|||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <cpu/pfc.h>
|
||||
|
||||
static struct resource sh7203_pfc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xfffe3800,
|
||||
.end = 0xfffe3a9f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init plat_pinmux_setup(void)
|
||||
{
|
||||
return sh_pfc_register("pfc-sh7203", NULL, 0);
|
||||
return sh_pfc_register("pfc-sh7203", sh7203_pfc_resources,
|
||||
ARRAY_SIZE(sh7203_pfc_resources));
|
||||
}
|
||||
arch_initcall(plat_pinmux_setup);
|
||||
|
|
|
|||
|
|
@ -8,12 +8,23 @@
|
|||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <cpu/pfc.h>
|
||||
|
||||
static struct resource sh7264_pfc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xfffe3800,
|
||||
.end = 0xfffe393f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init plat_pinmux_setup(void)
|
||||
{
|
||||
return sh_pfc_register("pfc-sh7264", NULL, 0);
|
||||
return sh_pfc_register("pfc-sh7264", sh7264_pfc_resources,
|
||||
ARRAY_SIZE(sh7264_pfc_resources));
|
||||
}
|
||||
arch_initcall(plat_pinmux_setup);
|
||||
|
|
|
|||
|
|
@ -9,12 +9,23 @@
|
|||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <cpu/pfc.h>
|
||||
|
||||
static struct resource sh7269_pfc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xfffe3800,
|
||||
.end = 0xfffe391f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init plat_pinmux_setup(void)
|
||||
{
|
||||
return sh_pfc_register("pfc-sh7269", NULL, 0);
|
||||
return sh_pfc_register("pfc-sh7269", sh7269_pfc_resources,
|
||||
ARRAY_SIZE(sh7269_pfc_resources));
|
||||
}
|
||||
arch_initcall(plat_pinmux_setup);
|
||||
|
|
|
|||
|
|
@ -8,13 +8,23 @@
|
|||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <cpu/pfc.h>
|
||||
|
||||
static struct resource sh7720_pfc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xa4050100,
|
||||
.end = 0xa405016f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init plat_pinmux_setup(void)
|
||||
{
|
||||
return sh_pfc_register("pfc-sh7720", NULL, 0);
|
||||
return sh_pfc_register("pfc-sh7720", sh7720_pfc_resources,
|
||||
ARRAY_SIZE(sh7720_pfc_resources));
|
||||
}
|
||||
|
||||
arch_initcall(plat_pinmux_setup);
|
||||
|
|
|
|||
|
|
@ -1,10 +1,20 @@
|
|||
#include <linux/bug.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <cpu/pfc.h>
|
||||
|
||||
static struct resource sh7722_pfc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xa4050100,
|
||||
.end = 0xa405018f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init plat_pinmux_setup(void)
|
||||
{
|
||||
return sh_pfc_register("pfc-sh7722", NULL, 0);
|
||||
return sh_pfc_register("pfc-sh7722", sh7722_pfc_resources,
|
||||
ARRAY_SIZE(sh7722_pfc_resources));
|
||||
}
|
||||
|
||||
arch_initcall(plat_pinmux_setup);
|
||||
|
|
|
|||
|
|
@ -8,13 +8,23 @@
|
|||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <cpu/pfc.h>
|
||||
|
||||
static struct resource sh7723_pfc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xa4050100,
|
||||
.end = 0xa405016f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init plat_pinmux_setup(void)
|
||||
{
|
||||
return sh_pfc_register("pfc-sh7723", NULL, 0);
|
||||
return sh_pfc_register("pfc-sh7723", sh7723_pfc_resources,
|
||||
ARRAY_SIZE(sh7723_pfc_resources));
|
||||
}
|
||||
|
||||
arch_initcall(plat_pinmux_setup);
|
||||
|
|
|
|||
|
|
@ -13,12 +13,23 @@
|
|||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <cpu/pfc.h>
|
||||
|
||||
static struct resource sh7724_pfc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xa4050100,
|
||||
.end = 0xa405016f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init plat_pinmux_setup(void)
|
||||
{
|
||||
return sh_pfc_register("pfc-sh7724", NULL, 0);
|
||||
return sh_pfc_register("pfc-sh7724", sh7724_pfc_resources,
|
||||
ARRAY_SIZE(sh7724_pfc_resources));
|
||||
}
|
||||
arch_initcall(plat_pinmux_setup);
|
||||
|
|
|
|||
|
|
@ -13,12 +13,23 @@
|
|||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <cpu/pfc.h>
|
||||
|
||||
static struct resource sh7757_pfc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xffec0000,
|
||||
.end = 0xffec008f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init plat_pinmux_setup(void)
|
||||
{
|
||||
return sh_pfc_register("pfc-sh7757", NULL, 0);
|
||||
return sh_pfc_register("pfc-sh7757", sh7757_pfc_resources,
|
||||
ARRAY_SIZE(sh7757_pfc_resources));
|
||||
}
|
||||
arch_initcall(plat_pinmux_setup);
|
||||
|
|
|
|||
|
|
@ -8,13 +8,23 @@
|
|||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <cpu/pfc.h>
|
||||
|
||||
static struct resource sh7785_pfc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xffe70000,
|
||||
.end = 0xffe7008f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init plat_pinmux_setup(void)
|
||||
{
|
||||
return sh_pfc_register("pfc-sh7785", NULL, 0);
|
||||
return sh_pfc_register("pfc-sh7785", sh7785_pfc_resources,
|
||||
ARRAY_SIZE(sh7785_pfc_resources));
|
||||
}
|
||||
|
||||
arch_initcall(plat_pinmux_setup);
|
||||
|
|
|
|||
|
|
@ -13,13 +13,23 @@
|
|||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <cpu/pfc.h>
|
||||
|
||||
static struct resource sh7786_pfc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xffcc0000,
|
||||
.end = 0xffcc008f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init plat_pinmux_setup(void)
|
||||
{
|
||||
return sh_pfc_register("pfc-sh7786", NULL, 0);
|
||||
return sh_pfc_register("pfc-sh7786", sh7786_pfc_resources,
|
||||
ARRAY_SIZE(sh7786_pfc_resources));
|
||||
}
|
||||
|
||||
arch_initcall(plat_pinmux_setup);
|
||||
|
|
|
|||
|
|
@ -7,12 +7,23 @@
|
|||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/bug.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <cpu/pfc.h>
|
||||
|
||||
static int __init shx3_pinmux_setup(void)
|
||||
static struct resource shx3_pfc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xffc70000,
|
||||
.end = 0xffc7001f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init plat_pinmux_setup(void)
|
||||
{
|
||||
return sh_pfc_register("pfc-shx3", NULL, 0);
|
||||
return sh_pfc_register("pfc-shx3", shx3_pfc_resources,
|
||||
ARRAY_SIZE(shx3_pfc_resources));
|
||||
}
|
||||
arch_initcall(shx3_pinmux_setup);
|
||||
arch_initcall(plat_pinmux_setup);
|
||||
|
|
|
|||
|
|
@ -204,6 +204,12 @@ config GPIO_PXA
|
|||
help
|
||||
Say yes here to support the PXA GPIO device
|
||||
|
||||
config GPIO_RCAR
|
||||
tristate "Renesas R-Car GPIO"
|
||||
depends on ARM
|
||||
help
|
||||
Say yes here to support GPIO on Renesas R-Car SoCs.
|
||||
|
||||
config GPIO_SPEAR_SPICS
|
||||
bool "ST SPEAr13xx SPI Chip Select as GPIO support"
|
||||
depends on PLAT_SPEAR
|
||||
|
|
|
|||
|
|
@ -57,6 +57,7 @@ obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
|
|||
obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
|
||||
obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
|
||||
obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
|
||||
obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
|
||||
obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o
|
||||
obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
|
||||
obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/workqueue.h>
|
||||
#include <linux/gpio.h>
|
||||
|
|
@ -22,6 +23,7 @@
|
|||
#include <linux/amba/bus.h>
|
||||
#include <linux/amba/pl061.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/pm.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
|
|
@ -51,8 +53,7 @@ struct pl061_gpio {
|
|||
spinlock_t lock;
|
||||
|
||||
void __iomem *base;
|
||||
int irq_base;
|
||||
struct irq_chip_generic *irq_gc;
|
||||
struct irq_domain *domain;
|
||||
struct gpio_chip gc;
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
|
@ -60,6 +61,17 @@ struct pl061_gpio {
|
|||
#endif
|
||||
};
|
||||
|
||||
static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
/*
|
||||
* Map back to global GPIO space and request muxing, the direction
|
||||
* parameter does not matter for this controller.
|
||||
*/
|
||||
int gpio = chip->base + offset;
|
||||
|
||||
return pinctrl_request_gpio(gpio);
|
||||
}
|
||||
|
||||
static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
|
||||
{
|
||||
struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
|
||||
|
|
@ -122,24 +134,20 @@ static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
|
|||
{
|
||||
struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
|
||||
|
||||
if (chip->irq_base <= 0)
|
||||
return -EINVAL;
|
||||
|
||||
return chip->irq_base + offset;
|
||||
return irq_create_mapping(chip->domain, offset);
|
||||
}
|
||||
|
||||
static int pl061_irq_type(struct irq_data *d, unsigned trigger)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
struct pl061_gpio *chip = gc->private;
|
||||
int offset = d->irq - chip->irq_base;
|
||||
struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
|
||||
int offset = irqd_to_hwirq(d);
|
||||
unsigned long flags;
|
||||
u8 gpiois, gpioibe, gpioiev;
|
||||
|
||||
if (offset < 0 || offset >= PL061_GPIO_NR)
|
||||
return -EINVAL;
|
||||
|
||||
raw_spin_lock_irqsave(&gc->lock, flags);
|
||||
spin_lock_irqsave(&chip->lock, flags);
|
||||
|
||||
gpioiev = readb(chip->base + GPIOIEV);
|
||||
|
||||
|
|
@ -168,7 +176,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
|
|||
|
||||
writeb(gpioiev, chip->base + GPIOIEV);
|
||||
|
||||
raw_spin_unlock_irqrestore(&gc->lock, flags);
|
||||
spin_unlock_irqrestore(&chip->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -192,31 +200,61 @@ static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
|
|||
chained_irq_exit(irqchip, desc);
|
||||
}
|
||||
|
||||
static void __init pl061_init_gc(struct pl061_gpio *chip, int irq_base)
|
||||
static void pl061_irq_mask(struct irq_data *d)
|
||||
{
|
||||
struct irq_chip_type *ct;
|
||||
struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
|
||||
u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
|
||||
u8 gpioie;
|
||||
|
||||
chip->irq_gc = irq_alloc_generic_chip("gpio-pl061", 1, irq_base,
|
||||
chip->base, handle_simple_irq);
|
||||
chip->irq_gc->private = chip;
|
||||
|
||||
ct = chip->irq_gc->chip_types;
|
||||
ct->chip.irq_mask = irq_gc_mask_clr_bit;
|
||||
ct->chip.irq_unmask = irq_gc_mask_set_bit;
|
||||
ct->chip.irq_set_type = pl061_irq_type;
|
||||
ct->chip.irq_set_wake = irq_gc_set_wake;
|
||||
ct->regs.mask = GPIOIE;
|
||||
|
||||
irq_setup_generic_chip(chip->irq_gc, IRQ_MSK(PL061_GPIO_NR),
|
||||
IRQ_GC_INIT_NESTED_LOCK, IRQ_NOREQUEST, 0);
|
||||
spin_lock(&chip->lock);
|
||||
gpioie = readb(chip->base + GPIOIE) & ~mask;
|
||||
writeb(gpioie, chip->base + GPIOIE);
|
||||
spin_unlock(&chip->lock);
|
||||
}
|
||||
|
||||
static void pl061_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
|
||||
u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
|
||||
u8 gpioie;
|
||||
|
||||
spin_lock(&chip->lock);
|
||||
gpioie = readb(chip->base + GPIOIE) | mask;
|
||||
writeb(gpioie, chip->base + GPIOIE);
|
||||
spin_unlock(&chip->lock);
|
||||
}
|
||||
|
||||
static struct irq_chip pl061_irqchip = {
|
||||
.name = "pl061 gpio",
|
||||
.irq_mask = pl061_irq_mask,
|
||||
.irq_unmask = pl061_irq_unmask,
|
||||
.irq_set_type = pl061_irq_type,
|
||||
};
|
||||
|
||||
static int pl061_irq_map(struct irq_domain *d, unsigned int virq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
struct pl061_gpio *chip = d->host_data;
|
||||
|
||||
irq_set_chip_and_handler_name(virq, &pl061_irqchip, handle_simple_irq,
|
||||
"pl061");
|
||||
irq_set_chip_data(virq, chip);
|
||||
irq_set_irq_type(virq, IRQ_TYPE_NONE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops pl061_domain_ops = {
|
||||
.map = pl061_irq_map,
|
||||
.xlate = irq_domain_xlate_twocell,
|
||||
};
|
||||
|
||||
static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
|
||||
{
|
||||
struct device *dev = &adev->dev;
|
||||
struct pl061_platform_data *pdata = dev->platform_data;
|
||||
struct pl061_gpio *chip;
|
||||
int ret, irq, i;
|
||||
int ret, irq, i, irq_base;
|
||||
|
||||
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
|
||||
if (chip == NULL)
|
||||
|
|
@ -224,24 +262,31 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
|
|||
|
||||
if (pdata) {
|
||||
chip->gc.base = pdata->gpio_base;
|
||||
chip->irq_base = pdata->irq_base;
|
||||
} else if (adev->dev.of_node) {
|
||||
irq_base = pdata->irq_base;
|
||||
if (irq_base <= 0)
|
||||
return -ENODEV;
|
||||
} else {
|
||||
chip->gc.base = -1;
|
||||
chip->irq_base = 0;
|
||||
} else
|
||||
return -ENODEV;
|
||||
irq_base = 0;
|
||||
}
|
||||
|
||||
if (!devm_request_mem_region(dev, adev->res.start,
|
||||
resource_size(&adev->res), "pl061"))
|
||||
resource_size(&adev->res), "pl061"))
|
||||
return -EBUSY;
|
||||
|
||||
chip->base = devm_ioremap(dev, adev->res.start,
|
||||
resource_size(&adev->res));
|
||||
if (chip->base == NULL)
|
||||
resource_size(&adev->res));
|
||||
if (!chip->base)
|
||||
return -ENOMEM;
|
||||
|
||||
chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR,
|
||||
irq_base, &pl061_domain_ops, chip);
|
||||
if (!chip->domain)
|
||||
return -ENODEV;
|
||||
|
||||
spin_lock_init(&chip->lock);
|
||||
|
||||
chip->gc.request = pl061_gpio_request;
|
||||
chip->gc.direction_input = pl061_direction_input;
|
||||
chip->gc.direction_output = pl061_direction_output;
|
||||
chip->gc.get = pl061_get_value;
|
||||
|
|
@ -259,12 +304,6 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
|
|||
/*
|
||||
* irq_chip support
|
||||
*/
|
||||
|
||||
if (chip->irq_base <= 0)
|
||||
return 0;
|
||||
|
||||
pl061_init_gc(chip, chip->irq_base);
|
||||
|
||||
writeb(0, chip->base + GPIOIE); /* disable irqs */
|
||||
irq = adev->irq[0];
|
||||
if (irq < 0)
|
||||
|
|
|
|||
396
drivers/gpio/gpio-rcar.c
Normal file
396
drivers/gpio/gpio-rcar.c
Normal file
|
|
@ -0,0 +1,396 @@
|
|||
/*
|
||||
* Renesas R-Car GPIO Support
|
||||
*
|
||||
* Copyright (C) 2013 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/platform_data/gpio-rcar.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
struct gpio_rcar_priv {
|
||||
void __iomem *base;
|
||||
spinlock_t lock;
|
||||
struct gpio_rcar_config config;
|
||||
struct platform_device *pdev;
|
||||
struct gpio_chip gpio_chip;
|
||||
struct irq_chip irq_chip;
|
||||
struct irq_domain *irq_domain;
|
||||
};
|
||||
|
||||
#define IOINTSEL 0x00
|
||||
#define INOUTSEL 0x04
|
||||
#define OUTDT 0x08
|
||||
#define INDT 0x0c
|
||||
#define INTDT 0x10
|
||||
#define INTCLR 0x14
|
||||
#define INTMSK 0x18
|
||||
#define MSKCLR 0x1c
|
||||
#define POSNEG 0x20
|
||||
#define EDGLEVEL 0x24
|
||||
#define FILONOFF 0x28
|
||||
|
||||
static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
|
||||
{
|
||||
return ioread32(p->base + offs);
|
||||
}
|
||||
|
||||
static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
|
||||
u32 value)
|
||||
{
|
||||
iowrite32(value, p->base + offs);
|
||||
}
|
||||
|
||||
static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
|
||||
int bit, bool value)
|
||||
{
|
||||
u32 tmp = gpio_rcar_read(p, offs);
|
||||
|
||||
if (value)
|
||||
tmp |= BIT(bit);
|
||||
else
|
||||
tmp &= ~BIT(bit);
|
||||
|
||||
gpio_rcar_write(p, offs, tmp);
|
||||
}
|
||||
|
||||
static void gpio_rcar_irq_disable(struct irq_data *d)
|
||||
{
|
||||
struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
|
||||
|
||||
gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
|
||||
}
|
||||
|
||||
static void gpio_rcar_irq_enable(struct irq_data *d)
|
||||
{
|
||||
struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
|
||||
|
||||
gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
|
||||
}
|
||||
|
||||
static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
|
||||
unsigned int hwirq,
|
||||
bool active_high_rising_edge,
|
||||
bool level_trigger)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
/* follow steps in the GPIO documentation for
|
||||
* "Setting Edge-Sensitive Interrupt Input Mode" and
|
||||
* "Setting Level-Sensitive Interrupt Input Mode"
|
||||
*/
|
||||
|
||||
spin_lock_irqsave(&p->lock, flags);
|
||||
|
||||
/* Configure postive or negative logic in POSNEG */
|
||||
gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
|
||||
|
||||
/* Configure edge or level trigger in EDGLEVEL */
|
||||
gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
|
||||
|
||||
/* Select "Interrupt Input Mode" in IOINTSEL */
|
||||
gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
|
||||
|
||||
/* Write INTCLR in case of edge trigger */
|
||||
if (!level_trigger)
|
||||
gpio_rcar_write(p, INTCLR, BIT(hwirq));
|
||||
|
||||
spin_unlock_irqrestore(&p->lock, flags);
|
||||
}
|
||||
|
||||
static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
|
||||
unsigned int hwirq = irqd_to_hwirq(d);
|
||||
|
||||
dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
|
||||
|
||||
switch (type & IRQ_TYPE_SENSE_MASK) {
|
||||
case IRQ_TYPE_LEVEL_HIGH:
|
||||
gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true);
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true);
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_RISING:
|
||||
gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false);
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct gpio_rcar_priv *p = dev_id;
|
||||
u32 pending;
|
||||
unsigned int offset, irqs_handled = 0;
|
||||
|
||||
while ((pending = gpio_rcar_read(p, INTDT))) {
|
||||
offset = __ffs(pending);
|
||||
gpio_rcar_write(p, INTCLR, BIT(offset));
|
||||
generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
|
||||
irqs_handled++;
|
||||
}
|
||||
|
||||
return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
|
||||
}
|
||||
|
||||
static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
|
||||
{
|
||||
return container_of(chip, struct gpio_rcar_priv, gpio_chip);
|
||||
}
|
||||
|
||||
static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
|
||||
unsigned int gpio,
|
||||
bool output)
|
||||
{
|
||||
struct gpio_rcar_priv *p = gpio_to_priv(chip);
|
||||
unsigned long flags;
|
||||
|
||||
/* follow steps in the GPIO documentation for
|
||||
* "Setting General Output Mode" and
|
||||
* "Setting General Input Mode"
|
||||
*/
|
||||
|
||||
spin_lock_irqsave(&p->lock, flags);
|
||||
|
||||
/* Configure postive logic in POSNEG */
|
||||
gpio_rcar_modify_bit(p, POSNEG, gpio, false);
|
||||
|
||||
/* Select "General Input/Output Mode" in IOINTSEL */
|
||||
gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
|
||||
|
||||
/* Select Input Mode or Output Mode in INOUTSEL */
|
||||
gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
|
||||
|
||||
spin_unlock_irqrestore(&p->lock, flags);
|
||||
}
|
||||
|
||||
static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
return pinctrl_request_gpio(chip->base + offset);
|
||||
}
|
||||
|
||||
static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
pinctrl_free_gpio(chip->base + offset);
|
||||
|
||||
/* Set the GPIO as an input to ensure that the next GPIO request won't
|
||||
* drive the GPIO pin as an output.
|
||||
*/
|
||||
gpio_rcar_config_general_input_output_mode(chip, offset, false);
|
||||
}
|
||||
|
||||
static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
gpio_rcar_config_general_input_output_mode(chip, offset, false);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & BIT(offset));
|
||||
}
|
||||
|
||||
static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
{
|
||||
struct gpio_rcar_priv *p = gpio_to_priv(chip);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&p->lock, flags);
|
||||
gpio_rcar_modify_bit(p, OUTDT, offset, value);
|
||||
spin_unlock_irqrestore(&p->lock, flags);
|
||||
}
|
||||
|
||||
static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
|
||||
int value)
|
||||
{
|
||||
/* write GPIO value to output before selecting output mode of pin */
|
||||
gpio_rcar_set(chip, offset, value);
|
||||
gpio_rcar_config_general_input_output_mode(chip, offset, true);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
|
||||
}
|
||||
|
||||
static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int virq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
struct gpio_rcar_priv *p = h->host_data;
|
||||
|
||||
dev_dbg(&p->pdev->dev, "map hw irq = %d, virq = %d\n", (int)hw, virq);
|
||||
|
||||
irq_set_chip_data(virq, h->host_data);
|
||||
irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
|
||||
set_irq_flags(virq, IRQF_VALID); /* kill me now */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
|
||||
.map = gpio_rcar_irq_domain_map,
|
||||
};
|
||||
|
||||
static int gpio_rcar_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct gpio_rcar_config *pdata = pdev->dev.platform_data;
|
||||
struct gpio_rcar_priv *p;
|
||||
struct resource *io, *irq;
|
||||
struct gpio_chip *gpio_chip;
|
||||
struct irq_chip *irq_chip;
|
||||
const char *name = dev_name(&pdev->dev);
|
||||
int ret;
|
||||
|
||||
p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
|
||||
if (!p) {
|
||||
dev_err(&pdev->dev, "failed to allocate driver data\n");
|
||||
ret = -ENOMEM;
|
||||
goto err0;
|
||||
}
|
||||
|
||||
/* deal with driver instance configuration */
|
||||
if (pdata)
|
||||
p->config = *pdata;
|
||||
|
||||
p->pdev = pdev;
|
||||
platform_set_drvdata(pdev, p);
|
||||
spin_lock_init(&p->lock);
|
||||
|
||||
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
|
||||
if (!io || !irq) {
|
||||
dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
|
||||
ret = -EINVAL;
|
||||
goto err0;
|
||||
}
|
||||
|
||||
p->base = devm_ioremap_nocache(&pdev->dev, io->start,
|
||||
resource_size(io));
|
||||
if (!p->base) {
|
||||
dev_err(&pdev->dev, "failed to remap I/O memory\n");
|
||||
ret = -ENXIO;
|
||||
goto err0;
|
||||
}
|
||||
|
||||
gpio_chip = &p->gpio_chip;
|
||||
gpio_chip->request = gpio_rcar_request;
|
||||
gpio_chip->free = gpio_rcar_free;
|
||||
gpio_chip->direction_input = gpio_rcar_direction_input;
|
||||
gpio_chip->get = gpio_rcar_get;
|
||||
gpio_chip->direction_output = gpio_rcar_direction_output;
|
||||
gpio_chip->set = gpio_rcar_set;
|
||||
gpio_chip->to_irq = gpio_rcar_to_irq;
|
||||
gpio_chip->label = name;
|
||||
gpio_chip->owner = THIS_MODULE;
|
||||
gpio_chip->base = p->config.gpio_base;
|
||||
gpio_chip->ngpio = p->config.number_of_pins;
|
||||
|
||||
irq_chip = &p->irq_chip;
|
||||
irq_chip->name = name;
|
||||
irq_chip->irq_mask = gpio_rcar_irq_disable;
|
||||
irq_chip->irq_unmask = gpio_rcar_irq_enable;
|
||||
irq_chip->irq_enable = gpio_rcar_irq_enable;
|
||||
irq_chip->irq_disable = gpio_rcar_irq_disable;
|
||||
irq_chip->irq_set_type = gpio_rcar_irq_set_type;
|
||||
irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED;
|
||||
|
||||
p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
|
||||
p->config.number_of_pins,
|
||||
p->config.irq_base,
|
||||
&gpio_rcar_irq_domain_ops, p);
|
||||
if (!p->irq_domain) {
|
||||
ret = -ENXIO;
|
||||
dev_err(&pdev->dev, "cannot initialize irq domain\n");
|
||||
goto err1;
|
||||
}
|
||||
|
||||
if (devm_request_irq(&pdev->dev, irq->start,
|
||||
gpio_rcar_irq_handler, 0, name, p)) {
|
||||
dev_err(&pdev->dev, "failed to request IRQ\n");
|
||||
ret = -ENOENT;
|
||||
goto err1;
|
||||
}
|
||||
|
||||
ret = gpiochip_add(gpio_chip);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to add GPIO controller\n");
|
||||
goto err1;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins);
|
||||
|
||||
/* warn in case of mismatch if irq base is specified */
|
||||
if (p->config.irq_base) {
|
||||
ret = irq_find_mapping(p->irq_domain, 0);
|
||||
if (p->config.irq_base != ret)
|
||||
dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n",
|
||||
p->config.irq_base, ret);
|
||||
}
|
||||
|
||||
ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
|
||||
gpio_chip->base, gpio_chip->ngpio);
|
||||
if (ret < 0)
|
||||
dev_warn(&pdev->dev, "failed to add pin range\n");
|
||||
|
||||
return 0;
|
||||
|
||||
err1:
|
||||
irq_domain_remove(p->irq_domain);
|
||||
err0:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int gpio_rcar_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
|
||||
int ret;
|
||||
|
||||
ret = gpiochip_remove(&p->gpio_chip);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
irq_domain_remove(p->irq_domain);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver gpio_rcar_device_driver = {
|
||||
.probe = gpio_rcar_probe,
|
||||
.remove = gpio_rcar_remove,
|
||||
.driver = {
|
||||
.name = "gpio_rcar",
|
||||
}
|
||||
};
|
||||
|
||||
module_platform_driver(gpio_rcar_device_driver);
|
||||
|
||||
MODULE_AUTHOR("Magnus Damm");
|
||||
MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -193,7 +193,7 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
|
|||
if (!np)
|
||||
return;
|
||||
|
||||
do {
|
||||
for (;; index++) {
|
||||
ret = of_parse_phandle_with_args(np, "gpio-ranges",
|
||||
"#gpio-range-cells", index, &pinspec);
|
||||
if (ret)
|
||||
|
|
@ -203,27 +203,15 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
|
|||
if (!pctldev)
|
||||
break;
|
||||
|
||||
/*
|
||||
* This assumes that the n GPIO pins are consecutive in the
|
||||
* GPIO number space, and that the pins are also consecutive
|
||||
* in their local number space. Currently it is not possible
|
||||
* to add different ranges for one and the same GPIO chip,
|
||||
* as the code assumes that we have one consecutive range
|
||||
* on both, mapping 1-to-1.
|
||||
*
|
||||
* TODO: make the OF bindings handle multiple sparse ranges
|
||||
* on the same GPIO chip.
|
||||
*/
|
||||
ret = gpiochip_add_pin_range(chip,
|
||||
pinctrl_dev_get_devname(pctldev),
|
||||
0, /* offset in gpiochip */
|
||||
pinspec.args[0],
|
||||
pinspec.args[1]);
|
||||
pinspec.args[1],
|
||||
pinspec.args[2]);
|
||||
|
||||
if (ret)
|
||||
break;
|
||||
|
||||
} while (index++);
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -25,6 +25,14 @@ config ARM_VIC_NR
|
|||
The maximum number of VICs available in the system, for
|
||||
power management.
|
||||
|
||||
config RENESAS_INTC_IRQPIN
|
||||
bool
|
||||
select IRQ_DOMAIN
|
||||
|
||||
config RENESAS_IRQC
|
||||
bool
|
||||
select IRQ_DOMAIN
|
||||
|
||||
config VERSATILE_FPGA_IRQ
|
||||
bool
|
||||
select IRQ_DOMAIN
|
||||
|
|
|
|||
|
|
@ -8,4 +8,6 @@ obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o
|
|||
obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
|
||||
obj-$(CONFIG_ARM_GIC) += irq-gic.o
|
||||
obj-$(CONFIG_ARM_VIC) += irq-vic.o
|
||||
obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
|
||||
obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
|
||||
obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
|
||||
|
|
|
|||
547
drivers/irqchip/irq-renesas-intc-irqpin.c
Normal file
547
drivers/irqchip/irq-renesas-intc-irqpin.c
Normal file
|
|
@ -0,0 +1,547 @@
|
|||
/*
|
||||
* Renesas INTC External IRQ Pin Driver
|
||||
*
|
||||
* Copyright (C) 2013 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_data/irq-renesas-intc-irqpin.h>
|
||||
|
||||
#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
|
||||
|
||||
#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
|
||||
#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
|
||||
#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
|
||||
#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
|
||||
#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
|
||||
#define INTC_IRQPIN_REG_NR 5
|
||||
|
||||
/* INTC external IRQ PIN hardware register access:
|
||||
*
|
||||
* SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
|
||||
* PRIO is read-write 32-bit with 4-bits per IRQ (**)
|
||||
* SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
|
||||
* MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
|
||||
* CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
|
||||
*
|
||||
* (*) May be accessed by more than one driver instance - lock needed
|
||||
* (**) Read-modify-write access by one driver instance - lock needed
|
||||
* (***) Accessed by one driver instance only - no locking needed
|
||||
*/
|
||||
|
||||
struct intc_irqpin_iomem {
|
||||
void __iomem *iomem;
|
||||
unsigned long (*read)(void __iomem *iomem);
|
||||
void (*write)(void __iomem *iomem, unsigned long data);
|
||||
int width;
|
||||
};
|
||||
|
||||
struct intc_irqpin_irq {
|
||||
int hw_irq;
|
||||
int requested_irq;
|
||||
int domain_irq;
|
||||
struct intc_irqpin_priv *p;
|
||||
};
|
||||
|
||||
struct intc_irqpin_priv {
|
||||
struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
|
||||
struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
|
||||
struct renesas_intc_irqpin_config config;
|
||||
unsigned int number_of_irqs;
|
||||
struct platform_device *pdev;
|
||||
struct irq_chip irq_chip;
|
||||
struct irq_domain *irq_domain;
|
||||
bool shared_irqs;
|
||||
u8 shared_irq_mask;
|
||||
};
|
||||
|
||||
static unsigned long intc_irqpin_read32(void __iomem *iomem)
|
||||
{
|
||||
return ioread32(iomem);
|
||||
}
|
||||
|
||||
static unsigned long intc_irqpin_read8(void __iomem *iomem)
|
||||
{
|
||||
return ioread8(iomem);
|
||||
}
|
||||
|
||||
static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
|
||||
{
|
||||
iowrite32(data, iomem);
|
||||
}
|
||||
|
||||
static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
|
||||
{
|
||||
iowrite8(data, iomem);
|
||||
}
|
||||
|
||||
static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
|
||||
int reg)
|
||||
{
|
||||
struct intc_irqpin_iomem *i = &p->iomem[reg];
|
||||
|
||||
return i->read(i->iomem);
|
||||
}
|
||||
|
||||
static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
|
||||
int reg, unsigned long data)
|
||||
{
|
||||
struct intc_irqpin_iomem *i = &p->iomem[reg];
|
||||
|
||||
i->write(i->iomem, data);
|
||||
}
|
||||
|
||||
static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
|
||||
int reg, int hw_irq)
|
||||
{
|
||||
return BIT((p->iomem[reg].width - 1) - hw_irq);
|
||||
}
|
||||
|
||||
static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
|
||||
int reg, int hw_irq)
|
||||
{
|
||||
intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
|
||||
}
|
||||
|
||||
static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
|
||||
|
||||
static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
|
||||
int reg, int shift,
|
||||
int width, int value)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned long tmp;
|
||||
|
||||
raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
|
||||
|
||||
tmp = intc_irqpin_read(p, reg);
|
||||
tmp &= ~(((1 << width) - 1) << shift);
|
||||
tmp |= value << shift;
|
||||
intc_irqpin_write(p, reg, tmp);
|
||||
|
||||
raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
|
||||
}
|
||||
|
||||
static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
|
||||
int irq, int do_mask)
|
||||
{
|
||||
int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */
|
||||
int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */
|
||||
|
||||
intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
|
||||
shift, bitfield_width,
|
||||
do_mask ? 0 : (1 << bitfield_width) - 1);
|
||||
}
|
||||
|
||||
static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
|
||||
{
|
||||
int bitfield_width = p->config.sense_bitfield_width;
|
||||
int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */
|
||||
|
||||
dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
|
||||
|
||||
if (value >= (1 << bitfield_width))
|
||||
return -EINVAL;
|
||||
|
||||
intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
|
||||
bitfield_width, value);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
|
||||
{
|
||||
dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
|
||||
str, i->requested_irq, i->hw_irq, i->domain_irq);
|
||||
}
|
||||
|
||||
static void intc_irqpin_irq_enable(struct irq_data *d)
|
||||
{
|
||||
struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
|
||||
int hw_irq = irqd_to_hwirq(d);
|
||||
|
||||
intc_irqpin_dbg(&p->irq[hw_irq], "enable");
|
||||
intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
|
||||
}
|
||||
|
||||
static void intc_irqpin_irq_disable(struct irq_data *d)
|
||||
{
|
||||
struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
|
||||
int hw_irq = irqd_to_hwirq(d);
|
||||
|
||||
intc_irqpin_dbg(&p->irq[hw_irq], "disable");
|
||||
intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
|
||||
}
|
||||
|
||||
static void intc_irqpin_shared_irq_enable(struct irq_data *d)
|
||||
{
|
||||
struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
|
||||
int hw_irq = irqd_to_hwirq(d);
|
||||
|
||||
intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
|
||||
intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
|
||||
|
||||
p->shared_irq_mask &= ~BIT(hw_irq);
|
||||
}
|
||||
|
||||
static void intc_irqpin_shared_irq_disable(struct irq_data *d)
|
||||
{
|
||||
struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
|
||||
int hw_irq = irqd_to_hwirq(d);
|
||||
|
||||
intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
|
||||
intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
|
||||
|
||||
p->shared_irq_mask |= BIT(hw_irq);
|
||||
}
|
||||
|
||||
static void intc_irqpin_irq_enable_force(struct irq_data *d)
|
||||
{
|
||||
struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
|
||||
int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
|
||||
|
||||
intc_irqpin_irq_enable(d);
|
||||
|
||||
/* enable interrupt through parent interrupt controller,
|
||||
* assumes non-shared interrupt with 1:1 mapping
|
||||
* needed for busted IRQs on some SoCs like sh73a0
|
||||
*/
|
||||
irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
|
||||
}
|
||||
|
||||
static void intc_irqpin_irq_disable_force(struct irq_data *d)
|
||||
{
|
||||
struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
|
||||
int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
|
||||
|
||||
/* disable interrupt through parent interrupt controller,
|
||||
* assumes non-shared interrupt with 1:1 mapping
|
||||
* needed for busted IRQs on some SoCs like sh73a0
|
||||
*/
|
||||
irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
|
||||
intc_irqpin_irq_disable(d);
|
||||
}
|
||||
|
||||
#define INTC_IRQ_SENSE_VALID 0x10
|
||||
#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
|
||||
|
||||
static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
|
||||
[IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
|
||||
[IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
|
||||
[IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
|
||||
[IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
|
||||
[IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
|
||||
};
|
||||
|
||||
static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
|
||||
struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
|
||||
|
||||
if (!(value & INTC_IRQ_SENSE_VALID))
|
||||
return -EINVAL;
|
||||
|
||||
return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
|
||||
value ^ INTC_IRQ_SENSE_VALID);
|
||||
}
|
||||
|
||||
static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct intc_irqpin_irq *i = dev_id;
|
||||
struct intc_irqpin_priv *p = i->p;
|
||||
unsigned long bit;
|
||||
|
||||
intc_irqpin_dbg(i, "demux1");
|
||||
bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
|
||||
|
||||
if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
|
||||
intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
|
||||
intc_irqpin_dbg(i, "demux2");
|
||||
generic_handle_irq(i->domain_irq);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct intc_irqpin_priv *p = dev_id;
|
||||
unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
|
||||
irqreturn_t status = IRQ_NONE;
|
||||
int k;
|
||||
|
||||
for (k = 0; k < 8; k++) {
|
||||
if (reg_source & BIT(7 - k)) {
|
||||
if (BIT(k) & p->shared_irq_mask)
|
||||
continue;
|
||||
|
||||
status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
struct intc_irqpin_priv *p = h->host_data;
|
||||
|
||||
p->irq[hw].domain_irq = virq;
|
||||
p->irq[hw].hw_irq = hw;
|
||||
|
||||
intc_irqpin_dbg(&p->irq[hw], "map");
|
||||
irq_set_chip_data(virq, h->host_data);
|
||||
irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
|
||||
set_irq_flags(virq, IRQF_VALID); /* kill me now */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_domain_ops intc_irqpin_irq_domain_ops = {
|
||||
.map = intc_irqpin_irq_domain_map,
|
||||
.xlate = irq_domain_xlate_twocell,
|
||||
};
|
||||
|
||||
static int intc_irqpin_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct renesas_intc_irqpin_config *pdata = pdev->dev.platform_data;
|
||||
struct intc_irqpin_priv *p;
|
||||
struct intc_irqpin_iomem *i;
|
||||
struct resource *io[INTC_IRQPIN_REG_NR];
|
||||
struct resource *irq;
|
||||
struct irq_chip *irq_chip;
|
||||
void (*enable_fn)(struct irq_data *d);
|
||||
void (*disable_fn)(struct irq_data *d);
|
||||
const char *name = dev_name(&pdev->dev);
|
||||
int ref_irq;
|
||||
int ret;
|
||||
int k;
|
||||
|
||||
p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
|
||||
if (!p) {
|
||||
dev_err(&pdev->dev, "failed to allocate driver data\n");
|
||||
ret = -ENOMEM;
|
||||
goto err0;
|
||||
}
|
||||
|
||||
/* deal with driver instance configuration */
|
||||
if (pdata)
|
||||
memcpy(&p->config, pdata, sizeof(*pdata));
|
||||
if (!p->config.sense_bitfield_width)
|
||||
p->config.sense_bitfield_width = 4; /* default to 4 bits */
|
||||
|
||||
p->pdev = pdev;
|
||||
platform_set_drvdata(pdev, p);
|
||||
|
||||
/* get hold of manadatory IOMEM */
|
||||
for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
|
||||
io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
|
||||
if (!io[k]) {
|
||||
dev_err(&pdev->dev, "not enough IOMEM resources\n");
|
||||
ret = -EINVAL;
|
||||
goto err0;
|
||||
}
|
||||
}
|
||||
|
||||
/* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
|
||||
for (k = 0; k < INTC_IRQPIN_MAX; k++) {
|
||||
irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
|
||||
if (!irq)
|
||||
break;
|
||||
|
||||
p->irq[k].p = p;
|
||||
p->irq[k].requested_irq = irq->start;
|
||||
}
|
||||
|
||||
p->number_of_irqs = k;
|
||||
if (p->number_of_irqs < 1) {
|
||||
dev_err(&pdev->dev, "not enough IRQ resources\n");
|
||||
ret = -EINVAL;
|
||||
goto err0;
|
||||
}
|
||||
|
||||
/* ioremap IOMEM and setup read/write callbacks */
|
||||
for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
|
||||
i = &p->iomem[k];
|
||||
|
||||
switch (resource_size(io[k])) {
|
||||
case 1:
|
||||
i->width = 8;
|
||||
i->read = intc_irqpin_read8;
|
||||
i->write = intc_irqpin_write8;
|
||||
break;
|
||||
case 4:
|
||||
i->width = 32;
|
||||
i->read = intc_irqpin_read32;
|
||||
i->write = intc_irqpin_write32;
|
||||
break;
|
||||
default:
|
||||
dev_err(&pdev->dev, "IOMEM size mismatch\n");
|
||||
ret = -EINVAL;
|
||||
goto err0;
|
||||
}
|
||||
|
||||
i->iomem = devm_ioremap_nocache(&pdev->dev, io[k]->start,
|
||||
resource_size(io[k]));
|
||||
if (!i->iomem) {
|
||||
dev_err(&pdev->dev, "failed to remap IOMEM\n");
|
||||
ret = -ENXIO;
|
||||
goto err0;
|
||||
}
|
||||
}
|
||||
|
||||
/* mask all interrupts using priority */
|
||||
for (k = 0; k < p->number_of_irqs; k++)
|
||||
intc_irqpin_mask_unmask_prio(p, k, 1);
|
||||
|
||||
/* clear all pending interrupts */
|
||||
intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
|
||||
|
||||
/* scan for shared interrupt lines */
|
||||
ref_irq = p->irq[0].requested_irq;
|
||||
p->shared_irqs = true;
|
||||
for (k = 1; k < p->number_of_irqs; k++) {
|
||||
if (ref_irq != p->irq[k].requested_irq) {
|
||||
p->shared_irqs = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* use more severe masking method if requested */
|
||||
if (p->config.control_parent) {
|
||||
enable_fn = intc_irqpin_irq_enable_force;
|
||||
disable_fn = intc_irqpin_irq_disable_force;
|
||||
} else if (!p->shared_irqs) {
|
||||
enable_fn = intc_irqpin_irq_enable;
|
||||
disable_fn = intc_irqpin_irq_disable;
|
||||
} else {
|
||||
enable_fn = intc_irqpin_shared_irq_enable;
|
||||
disable_fn = intc_irqpin_shared_irq_disable;
|
||||
}
|
||||
|
||||
irq_chip = &p->irq_chip;
|
||||
irq_chip->name = name;
|
||||
irq_chip->irq_mask = disable_fn;
|
||||
irq_chip->irq_unmask = enable_fn;
|
||||
irq_chip->irq_enable = enable_fn;
|
||||
irq_chip->irq_disable = disable_fn;
|
||||
irq_chip->irq_set_type = intc_irqpin_irq_set_type;
|
||||
irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
|
||||
|
||||
p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
|
||||
p->number_of_irqs,
|
||||
p->config.irq_base,
|
||||
&intc_irqpin_irq_domain_ops, p);
|
||||
if (!p->irq_domain) {
|
||||
ret = -ENXIO;
|
||||
dev_err(&pdev->dev, "cannot initialize irq domain\n");
|
||||
goto err0;
|
||||
}
|
||||
|
||||
if (p->shared_irqs) {
|
||||
/* request one shared interrupt */
|
||||
if (devm_request_irq(&pdev->dev, p->irq[0].requested_irq,
|
||||
intc_irqpin_shared_irq_handler,
|
||||
IRQF_SHARED, name, p)) {
|
||||
dev_err(&pdev->dev, "failed to request low IRQ\n");
|
||||
ret = -ENOENT;
|
||||
goto err1;
|
||||
}
|
||||
} else {
|
||||
/* request interrupts one by one */
|
||||
for (k = 0; k < p->number_of_irqs; k++) {
|
||||
if (devm_request_irq(&pdev->dev,
|
||||
p->irq[k].requested_irq,
|
||||
intc_irqpin_irq_handler,
|
||||
0, name, &p->irq[k])) {
|
||||
dev_err(&pdev->dev,
|
||||
"failed to request low IRQ\n");
|
||||
ret = -ENOENT;
|
||||
goto err1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* unmask all interrupts on prio level */
|
||||
for (k = 0; k < p->number_of_irqs; k++)
|
||||
intc_irqpin_mask_unmask_prio(p, k, 0);
|
||||
|
||||
dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
|
||||
|
||||
/* warn in case of mismatch if irq base is specified */
|
||||
if (p->config.irq_base) {
|
||||
if (p->config.irq_base != p->irq[0].domain_irq)
|
||||
dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
|
||||
p->config.irq_base, p->irq[0].domain_irq);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err1:
|
||||
irq_domain_remove(p->irq_domain);
|
||||
err0:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int intc_irqpin_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
|
||||
|
||||
irq_domain_remove(p->irq_domain);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id intc_irqpin_dt_ids[] = {
|
||||
{ .compatible = "renesas,intc-irqpin", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
|
||||
|
||||
static struct platform_driver intc_irqpin_device_driver = {
|
||||
.probe = intc_irqpin_probe,
|
||||
.remove = intc_irqpin_remove,
|
||||
.driver = {
|
||||
.name = "renesas_intc_irqpin",
|
||||
.of_match_table = intc_irqpin_dt_ids,
|
||||
.owner = THIS_MODULE,
|
||||
}
|
||||
};
|
||||
|
||||
static int __init intc_irqpin_init(void)
|
||||
{
|
||||
return platform_driver_register(&intc_irqpin_device_driver);
|
||||
}
|
||||
postcore_initcall(intc_irqpin_init);
|
||||
|
||||
static void __exit intc_irqpin_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&intc_irqpin_device_driver);
|
||||
}
|
||||
module_exit(intc_irqpin_exit);
|
||||
|
||||
MODULE_AUTHOR("Magnus Damm");
|
||||
MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
307
drivers/irqchip/irq-renesas-irqc.c
Normal file
307
drivers/irqchip/irq-renesas-irqc.c
Normal file
|
|
@ -0,0 +1,307 @@
|
|||
/*
|
||||
* Renesas IRQC Driver
|
||||
*
|
||||
* Copyright (C) 2013 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_data/irq-renesas-irqc.h>
|
||||
|
||||
#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
|
||||
|
||||
#define IRQC_REQ_STS 0x00
|
||||
#define IRQC_EN_STS 0x04
|
||||
#define IRQC_EN_SET 0x08
|
||||
#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
|
||||
#define DETECT_STATUS 0x100
|
||||
#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
|
||||
|
||||
struct irqc_irq {
|
||||
int hw_irq;
|
||||
int requested_irq;
|
||||
int domain_irq;
|
||||
struct irqc_priv *p;
|
||||
};
|
||||
|
||||
struct irqc_priv {
|
||||
void __iomem *iomem;
|
||||
void __iomem *cpu_int_base;
|
||||
struct irqc_irq irq[IRQC_IRQ_MAX];
|
||||
struct renesas_irqc_config config;
|
||||
unsigned int number_of_irqs;
|
||||
struct platform_device *pdev;
|
||||
struct irq_chip irq_chip;
|
||||
struct irq_domain *irq_domain;
|
||||
};
|
||||
|
||||
static void irqc_dbg(struct irqc_irq *i, char *str)
|
||||
{
|
||||
dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
|
||||
str, i->requested_irq, i->hw_irq, i->domain_irq);
|
||||
}
|
||||
|
||||
static void irqc_irq_enable(struct irq_data *d)
|
||||
{
|
||||
struct irqc_priv *p = irq_data_get_irq_chip_data(d);
|
||||
int hw_irq = irqd_to_hwirq(d);
|
||||
|
||||
irqc_dbg(&p->irq[hw_irq], "enable");
|
||||
iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET);
|
||||
}
|
||||
|
||||
static void irqc_irq_disable(struct irq_data *d)
|
||||
{
|
||||
struct irqc_priv *p = irq_data_get_irq_chip_data(d);
|
||||
int hw_irq = irqd_to_hwirq(d);
|
||||
|
||||
irqc_dbg(&p->irq[hw_irq], "disable");
|
||||
iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS);
|
||||
}
|
||||
|
||||
#define INTC_IRQ_SENSE_VALID 0x10
|
||||
#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
|
||||
|
||||
static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
|
||||
[IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x01),
|
||||
[IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x02),
|
||||
[IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x04), /* Synchronous */
|
||||
[IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x08), /* Synchronous */
|
||||
[IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x0c), /* Synchronous */
|
||||
};
|
||||
|
||||
static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
struct irqc_priv *p = irq_data_get_irq_chip_data(d);
|
||||
int hw_irq = irqd_to_hwirq(d);
|
||||
unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];
|
||||
unsigned long tmp;
|
||||
|
||||
irqc_dbg(&p->irq[hw_irq], "sense");
|
||||
|
||||
if (!(value & INTC_IRQ_SENSE_VALID))
|
||||
return -EINVAL;
|
||||
|
||||
tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
|
||||
tmp &= ~0x3f;
|
||||
tmp |= value ^ INTC_IRQ_SENSE_VALID;
|
||||
iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t irqc_irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct irqc_irq *i = dev_id;
|
||||
struct irqc_priv *p = i->p;
|
||||
unsigned long bit = BIT(i->hw_irq);
|
||||
|
||||
irqc_dbg(i, "demux1");
|
||||
|
||||
if (ioread32(p->iomem + DETECT_STATUS) & bit) {
|
||||
iowrite32(bit, p->iomem + DETECT_STATUS);
|
||||
irqc_dbg(i, "demux2");
|
||||
generic_handle_irq(i->domain_irq);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
struct irqc_priv *p = h->host_data;
|
||||
|
||||
p->irq[hw].domain_irq = virq;
|
||||
p->irq[hw].hw_irq = hw;
|
||||
|
||||
irqc_dbg(&p->irq[hw], "map");
|
||||
irq_set_chip_data(virq, h->host_data);
|
||||
irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
|
||||
set_irq_flags(virq, IRQF_VALID); /* kill me now */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_domain_ops irqc_irq_domain_ops = {
|
||||
.map = irqc_irq_domain_map,
|
||||
.xlate = irq_domain_xlate_twocell,
|
||||
};
|
||||
|
||||
static int irqc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct renesas_irqc_config *pdata = pdev->dev.platform_data;
|
||||
struct irqc_priv *p;
|
||||
struct resource *io;
|
||||
struct resource *irq;
|
||||
struct irq_chip *irq_chip;
|
||||
const char *name = dev_name(&pdev->dev);
|
||||
int ret;
|
||||
int k;
|
||||
|
||||
p = kzalloc(sizeof(*p), GFP_KERNEL);
|
||||
if (!p) {
|
||||
dev_err(&pdev->dev, "failed to allocate driver data\n");
|
||||
ret = -ENOMEM;
|
||||
goto err0;
|
||||
}
|
||||
|
||||
/* deal with driver instance configuration */
|
||||
if (pdata)
|
||||
memcpy(&p->config, pdata, sizeof(*pdata));
|
||||
|
||||
p->pdev = pdev;
|
||||
platform_set_drvdata(pdev, p);
|
||||
|
||||
/* get hold of manadatory IOMEM */
|
||||
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!io) {
|
||||
dev_err(&pdev->dev, "not enough IOMEM resources\n");
|
||||
ret = -EINVAL;
|
||||
goto err1;
|
||||
}
|
||||
|
||||
/* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
|
||||
for (k = 0; k < IRQC_IRQ_MAX; k++) {
|
||||
irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
|
||||
if (!irq)
|
||||
break;
|
||||
|
||||
p->irq[k].p = p;
|
||||
p->irq[k].requested_irq = irq->start;
|
||||
}
|
||||
|
||||
p->number_of_irqs = k;
|
||||
if (p->number_of_irqs < 1) {
|
||||
dev_err(&pdev->dev, "not enough IRQ resources\n");
|
||||
ret = -EINVAL;
|
||||
goto err1;
|
||||
}
|
||||
|
||||
/* ioremap IOMEM and setup read/write callbacks */
|
||||
p->iomem = ioremap_nocache(io->start, resource_size(io));
|
||||
if (!p->iomem) {
|
||||
dev_err(&pdev->dev, "failed to remap IOMEM\n");
|
||||
ret = -ENXIO;
|
||||
goto err2;
|
||||
}
|
||||
|
||||
p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */
|
||||
|
||||
irq_chip = &p->irq_chip;
|
||||
irq_chip->name = name;
|
||||
irq_chip->irq_mask = irqc_irq_disable;
|
||||
irq_chip->irq_unmask = irqc_irq_enable;
|
||||
irq_chip->irq_enable = irqc_irq_enable;
|
||||
irq_chip->irq_disable = irqc_irq_disable;
|
||||
irq_chip->irq_set_type = irqc_irq_set_type;
|
||||
irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
|
||||
|
||||
p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
|
||||
p->number_of_irqs,
|
||||
p->config.irq_base,
|
||||
&irqc_irq_domain_ops, p);
|
||||
if (!p->irq_domain) {
|
||||
ret = -ENXIO;
|
||||
dev_err(&pdev->dev, "cannot initialize irq domain\n");
|
||||
goto err2;
|
||||
}
|
||||
|
||||
/* request interrupts one by one */
|
||||
for (k = 0; k < p->number_of_irqs; k++) {
|
||||
if (request_irq(p->irq[k].requested_irq, irqc_irq_handler,
|
||||
0, name, &p->irq[k])) {
|
||||
dev_err(&pdev->dev, "failed to request IRQ\n");
|
||||
ret = -ENOENT;
|
||||
goto err3;
|
||||
}
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
|
||||
|
||||
/* warn in case of mismatch if irq base is specified */
|
||||
if (p->config.irq_base) {
|
||||
if (p->config.irq_base != p->irq[0].domain_irq)
|
||||
dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
|
||||
p->config.irq_base, p->irq[0].domain_irq);
|
||||
}
|
||||
|
||||
return 0;
|
||||
err3:
|
||||
for (; k >= 0; k--)
|
||||
free_irq(p->irq[k - 1].requested_irq, &p->irq[k - 1]);
|
||||
|
||||
irq_domain_remove(p->irq_domain);
|
||||
err2:
|
||||
iounmap(p->iomem);
|
||||
err1:
|
||||
kfree(p);
|
||||
err0:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int irqc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct irqc_priv *p = platform_get_drvdata(pdev);
|
||||
int k;
|
||||
|
||||
for (k = 0; k < p->number_of_irqs; k++)
|
||||
free_irq(p->irq[k].requested_irq, &p->irq[k]);
|
||||
|
||||
irq_domain_remove(p->irq_domain);
|
||||
iounmap(p->iomem);
|
||||
kfree(p);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id irqc_dt_ids[] = {
|
||||
{ .compatible = "renesas,irqc", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, irqc_dt_ids);
|
||||
|
||||
static struct platform_driver irqc_device_driver = {
|
||||
.probe = irqc_probe,
|
||||
.remove = irqc_remove,
|
||||
.driver = {
|
||||
.name = "renesas_irqc",
|
||||
.of_match_table = irqc_dt_ids,
|
||||
.owner = THIS_MODULE,
|
||||
}
|
||||
};
|
||||
|
||||
static int __init irqc_init(void)
|
||||
{
|
||||
return platform_driver_register(&irqc_device_driver);
|
||||
}
|
||||
postcore_initcall(irqc_init);
|
||||
|
||||
static void __exit irqc_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&irqc_device_driver);
|
||||
}
|
||||
module_exit(irqc_exit);
|
||||
|
||||
MODULE_AUTHOR("Magnus Damm");
|
||||
MODULE_DESCRIPTION("Renesas IRQC Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -166,6 +166,7 @@ config PINCTRL_SINGLE
|
|||
depends on OF
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
help
|
||||
This selects the device tree based generic pinctrl driver.
|
||||
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <asm-generic/gpio.h>
|
||||
#include "core.h"
|
||||
#include "devicetree.h"
|
||||
#include "pinmux.h"
|
||||
|
|
@ -276,6 +277,39 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
|
|||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* pinctrl_ready_for_gpio_range() - check if other GPIO pins of
|
||||
* the same GPIO chip are in range
|
||||
* @gpio: gpio pin to check taken from the global GPIO pin space
|
||||
*
|
||||
* This function is complement of pinctrl_match_gpio_range(). If the return
|
||||
* value of pinctrl_match_gpio_range() is NULL, this function could be used
|
||||
* to check whether pinctrl device is ready or not. Maybe some GPIO pins
|
||||
* of the same GPIO chip don't have back-end pinctrl interface.
|
||||
* If the return value is true, it means that pinctrl device is ready & the
|
||||
* certain GPIO pin doesn't have back-end pinctrl device. If the return value
|
||||
* is false, it means that pinctrl device may not be ready.
|
||||
*/
|
||||
static bool pinctrl_ready_for_gpio_range(unsigned gpio)
|
||||
{
|
||||
struct pinctrl_dev *pctldev;
|
||||
struct pinctrl_gpio_range *range = NULL;
|
||||
struct gpio_chip *chip = gpio_to_chip(gpio);
|
||||
|
||||
/* Loop over the pin controllers */
|
||||
list_for_each_entry(pctldev, &pinctrldev_list, node) {
|
||||
/* Loop over the ranges */
|
||||
list_for_each_entry(range, &pctldev->gpio_ranges, node) {
|
||||
/* Check if any gpio range overlapped with gpio chip */
|
||||
if (range->base + range->npins - 1 < chip->base ||
|
||||
range->base > chip->base + chip->ngpio - 1)
|
||||
continue;
|
||||
return true;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
/**
|
||||
* pinctrl_get_device_gpio_range() - find device for GPIO range
|
||||
* @gpio: the pin to locate the pin controller for
|
||||
|
|
@ -443,6 +477,8 @@ int pinctrl_request_gpio(unsigned gpio)
|
|||
|
||||
ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
|
||||
if (ret) {
|
||||
if (pinctrl_ready_for_gpio_range(gpio))
|
||||
ret = 0;
|
||||
mutex_unlock(&pinctrl_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -979,9 +1015,8 @@ static int devm_pinctrl_match(struct device *dev, void *res, void *data)
|
|||
*/
|
||||
void devm_pinctrl_put(struct pinctrl *p)
|
||||
{
|
||||
WARN_ON(devres_destroy(p->dev, devm_pinctrl_release,
|
||||
WARN_ON(devres_release(p->dev, devm_pinctrl_release,
|
||||
devm_pinctrl_match, p));
|
||||
pinctrl_put(p);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(devm_pinctrl_put);
|
||||
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ static void dt_free_map(struct pinctrl_dev *pctldev,
|
|||
struct pinctrl_map *map, unsigned num_maps)
|
||||
{
|
||||
if (pctldev) {
|
||||
struct pinctrl_ops *ops = pctldev->desc->pctlops;
|
||||
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
|
||||
ops->dt_free_map(pctldev, map, num_maps);
|
||||
} else {
|
||||
/* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
|
||||
|
|
@ -122,7 +122,7 @@ static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
|
|||
{
|
||||
struct device_node *np_pctldev;
|
||||
struct pinctrl_dev *pctldev;
|
||||
struct pinctrl_ops *ops;
|
||||
const struct pinctrl_ops *ops;
|
||||
int ret;
|
||||
struct pinctrl_map *map;
|
||||
unsigned num_maps;
|
||||
|
|
|
|||
|
|
@ -263,7 +263,7 @@ static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
|
|||
return;
|
||||
}
|
||||
|
||||
static struct pinconf_ops mvebu_pinconf_ops = {
|
||||
static const struct pinconf_ops mvebu_pinconf_ops = {
|
||||
.pin_config_group_get = mvebu_pinconf_group_get,
|
||||
.pin_config_group_set = mvebu_pinconf_group_set,
|
||||
.pin_config_group_dbg_show = mvebu_pinconf_group_dbg_show,
|
||||
|
|
@ -369,7 +369,7 @@ static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
|
|||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static struct pinmux_ops mvebu_pinmux_ops = {
|
||||
static const struct pinmux_ops mvebu_pinmux_ops = {
|
||||
.get_functions_count = mvebu_pinmux_get_funcs_count,
|
||||
.get_function_name = mvebu_pinmux_get_func_name,
|
||||
.get_function_groups = mvebu_pinmux_get_groups,
|
||||
|
|
@ -470,7 +470,7 @@ static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
|
|||
kfree(map);
|
||||
}
|
||||
|
||||
static struct pinctrl_ops mvebu_pinctrl_ops = {
|
||||
static const struct pinctrl_ops mvebu_pinctrl_ops = {
|
||||
.get_groups_count = mvebu_pinctrl_get_groups_count,
|
||||
.get_group_name = mvebu_pinctrl_get_group_name,
|
||||
.get_group_pins = mvebu_pinctrl_get_group_pins,
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#define pr_fmt(fmt) "generic pinconfig core: " fmt
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/slab.h>
|
||||
|
|
@ -120,4 +121,17 @@ void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
|
|||
}
|
||||
}
|
||||
|
||||
void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s, unsigned long config)
|
||||
{
|
||||
int i;
|
||||
|
||||
for(i = 0; i < ARRAY_SIZE(conf_items); i++) {
|
||||
if (pinconf_to_config_param(config) != conf_items[i].param)
|
||||
continue;
|
||||
seq_printf(s, "%s: 0x%x", conf_items[i].display,
|
||||
pinconf_to_config_argument(config));
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pinconf_generic_dump_config);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -622,7 +622,7 @@ static const struct file_operations pinconf_dbg_pinname_fops = {
|
|||
static int pinconf_dbg_state_print(struct seq_file *s, void *d)
|
||||
{
|
||||
if (strlen(dbg_state_name))
|
||||
seq_printf(s, "%s\n", dbg_pinname);
|
||||
seq_printf(s, "%s\n", dbg_state_name);
|
||||
else
|
||||
seq_printf(s, "No pin state set\n");
|
||||
return 0;
|
||||
|
|
@ -670,7 +670,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
|
|||
struct pinctrl_maps *maps_node;
|
||||
struct pinctrl_map const *map;
|
||||
struct pinctrl_dev *pctldev = NULL;
|
||||
struct pinconf_ops *confops = NULL;
|
||||
const struct pinconf_ops *confops = NULL;
|
||||
int i, j;
|
||||
bool found = false;
|
||||
|
||||
|
|
|
|||
|
|
@ -90,7 +90,7 @@ static inline void pinconf_init_device_debugfs(struct dentry *devroot,
|
|||
* pin config.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_GENERIC_PINCONF
|
||||
#if defined(CONFIG_GENERIC_PINCONF) && defined(CONFIG_DEBUG_FS)
|
||||
|
||||
void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s, unsigned pin);
|
||||
|
|
@ -98,6 +98,8 @@ void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
|
|||
void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s, const char *gname);
|
||||
|
||||
void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s, unsigned long config);
|
||||
#else
|
||||
|
||||
static inline void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
|
||||
|
|
@ -114,4 +116,10 @@ static inline void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
|
|||
return;
|
||||
}
|
||||
|
||||
static inline void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
|
||||
struct seq_file *s,
|
||||
unsigned long config)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -422,7 +422,7 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
|
|||
}
|
||||
|
||||
/* check if pin use AlternateFunction register */
|
||||
if ((af.alt_bit1 == UNUSED) && (af.alt_bit1 == UNUSED))
|
||||
if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED))
|
||||
return mode;
|
||||
/*
|
||||
* if pin GPIOSEL bit is set and pin supports alternate function,
|
||||
|
|
@ -656,7 +656,7 @@ static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
|
|||
{
|
||||
}
|
||||
|
||||
static struct pinmux_ops abx500_pinmux_ops = {
|
||||
static const struct pinmux_ops abx500_pinmux_ops = {
|
||||
.get_functions_count = abx500_pmx_get_funcs_cnt,
|
||||
.get_function_name = abx500_pmx_get_func_name,
|
||||
.get_function_groups = abx500_pmx_get_func_groups,
|
||||
|
|
@ -704,7 +704,7 @@ static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
|
|||
chip->base + offset - 1);
|
||||
}
|
||||
|
||||
static struct pinctrl_ops abx500_pinctrl_ops = {
|
||||
static const struct pinctrl_ops abx500_pinctrl_ops = {
|
||||
.get_groups_count = abx500_get_groups_cnt,
|
||||
.get_group_name = abx500_get_group_name,
|
||||
.get_group_pins = abx500_get_group_pins,
|
||||
|
|
@ -778,7 +778,7 @@ int abx500_pin_config_set(struct pinctrl_dev *pctldev,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static struct pinconf_ops abx500_pinconf_ops = {
|
||||
static const struct pinconf_ops abx500_pinconf_ops = {
|
||||
.pin_config_get = abx500_pin_config_get,
|
||||
.pin_config_set = abx500_pin_config_set,
|
||||
};
|
||||
|
|
@ -834,6 +834,7 @@ static const struct of_device_id abx500_gpio_match[] = {
|
|||
{ .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, },
|
||||
{ .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, },
|
||||
{ .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, },
|
||||
{ }
|
||||
};
|
||||
|
||||
static int abx500_gpio_probe(struct platform_device *pdev)
|
||||
|
|
|
|||
|
|
@ -294,7 +294,7 @@ static void at91_dt_free_map(struct pinctrl_dev *pctldev,
|
|||
{
|
||||
}
|
||||
|
||||
static struct pinctrl_ops at91_pctrl_ops = {
|
||||
static const struct pinctrl_ops at91_pctrl_ops = {
|
||||
.get_groups_count = at91_get_groups_count,
|
||||
.get_group_name = at91_get_group_name,
|
||||
.get_group_pins = at91_get_group_pins,
|
||||
|
|
@ -696,7 +696,7 @@ static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
|
|||
/* Set the pin to some default state, GPIO is usually default */
|
||||
}
|
||||
|
||||
static struct pinmux_ops at91_pmx_ops = {
|
||||
static const struct pinmux_ops at91_pmx_ops = {
|
||||
.get_functions_count = at91_pmx_get_funcs_count,
|
||||
.get_function_name = at91_pmx_get_func_name,
|
||||
.get_function_groups = at91_pmx_get_groups,
|
||||
|
|
@ -776,7 +776,7 @@ static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
|
|||
{
|
||||
}
|
||||
|
||||
static struct pinconf_ops at91_pinconf_ops = {
|
||||
static const struct pinconf_ops at91_pinconf_ops = {
|
||||
.pin_config_get = at91_pinconf_get,
|
||||
.pin_config_set = at91_pinconf_set,
|
||||
.pin_config_dbg_show = at91_pinconf_dbg_show,
|
||||
|
|
|
|||
|
|
@ -795,7 +795,7 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
|||
return err;
|
||||
}
|
||||
|
||||
static struct pinctrl_ops bcm2835_pctl_ops = {
|
||||
static const struct pinctrl_ops bcm2835_pctl_ops = {
|
||||
.get_groups_count = bcm2835_pctl_get_groups_count,
|
||||
.get_group_name = bcm2835_pctl_get_group_name,
|
||||
.get_group_pins = bcm2835_pctl_get_group_pins,
|
||||
|
|
@ -872,7 +872,7 @@ static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct pinmux_ops bcm2835_pmx_ops = {
|
||||
static const struct pinmux_ops bcm2835_pmx_ops = {
|
||||
.get_functions_count = bcm2835_pmx_get_functions_count,
|
||||
.get_function_name = bcm2835_pmx_get_function_name,
|
||||
.get_function_groups = bcm2835_pmx_get_function_groups,
|
||||
|
|
@ -916,7 +916,7 @@ static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct pinconf_ops bcm2835_pinconf_ops = {
|
||||
static const struct pinconf_ops bcm2835_pinconf_ops = {
|
||||
.pin_config_get = bcm2835_pinconf_get,
|
||||
.pin_config_set = bcm2835_pinconf_set,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -286,7 +286,7 @@ static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
|
|||
}
|
||||
|
||||
/* list of pinctrl callbacks for the pinctrl core */
|
||||
static struct pinctrl_ops exynos5440_pctrl_ops = {
|
||||
static const struct pinctrl_ops exynos5440_pctrl_ops = {
|
||||
.get_groups_count = exynos5440_get_group_count,
|
||||
.get_group_name = exynos5440_get_group_name,
|
||||
.get_group_pins = exynos5440_get_group_pins,
|
||||
|
|
@ -374,7 +374,7 @@ static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
|
|||
}
|
||||
|
||||
/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
|
||||
static struct pinmux_ops exynos5440_pinmux_ops = {
|
||||
static const struct pinmux_ops exynos5440_pinmux_ops = {
|
||||
.get_functions_count = exynos5440_get_functions_count,
|
||||
.get_function_name = exynos5440_pinmux_get_fname,
|
||||
.get_function_groups = exynos5440_pinmux_get_groups,
|
||||
|
|
@ -523,7 +523,7 @@ static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev,
|
|||
}
|
||||
|
||||
/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
|
||||
static struct pinconf_ops exynos5440_pinconf_ops = {
|
||||
static const struct pinconf_ops exynos5440_pinconf_ops = {
|
||||
.pin_config_get = exynos5440_pinconf_get,
|
||||
.pin_config_set = exynos5440_pinconf_set,
|
||||
.pin_config_group_get = exynos5440_pinconf_group_get,
|
||||
|
|
|
|||
|
|
@ -353,7 +353,7 @@ static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
|
|||
{
|
||||
}
|
||||
|
||||
static struct pinconf_ops falcon_pinconf_ops = {
|
||||
static const struct pinconf_ops falcon_pinconf_ops = {
|
||||
.pin_config_get = falcon_pinconf_get,
|
||||
.pin_config_set = falcon_pinconf_set,
|
||||
.pin_config_group_get = falcon_pinconf_group_get,
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue