Samsung DMC driver for v5.5
Add Samsung Dynamic Memory Controller for Exynos5422 which provides scaling of frequency and voltage of memory controller and DRAM. The driver allows to reduce energy usage without performance impact. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAl2t8FkQHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD1+wZD/9O3cKcO2T5WmDw0sZt+a7LZBbm2nCCZNk1 v+aHTYbjYEfgSfPaCHbGNjC2HjHN+ThyY3f4UyPkG3WEsRvu2DTio7RjXWGNJHQg rQ4c4sZU+5if0nXjw6QG3jtOj0q77q4XYgX9hg3Xl1hab7f8MjrhxvuRGkHIumzI SRCSVi3L4K93YTKqDa/Z1xQtCOuXDtTtnAdy2iY4YY8JE9mRgHlGKlcgdWXPlXia Fo0K9nGXOsRmA25twlqnA7ZkRh18PGQMC85o8vccqt39DOyUVwylwduvSPKosWsX bn6LwpaYwAAj2nd65evRXs5W8EHx8ODGVEmELNYiVV0bLu3eaxKyynI/F5BxGuPO ZYa2+BqG7TSHIJbb/6siYKZOhf8FRKRapjWy3Rx0oMK/pr0yGjmVyQDSp2lRvYk4 lUOm3d9IV5u3YNHgdiEdsiVSGEFK2enk7C2Lq/0++FkhT4GzRkJ13kj53fJxQxN/ xAs7L8mEpSqcFJMDoUjUOYCeNmJhNjkYVDG32I/quL2wtl8GQVOgty7sRwJBTDv5 6gRCfBU2xBjSWuWCRT7O4z2bpW2V5TaqYiCNvivFbWpE/z7G1Z0z/iQalgYoVxZs ztuuizkGuKcZAl1EA8DTmA5/Hk4uo2BirOxfsRZy5CLjukbUp+lh7S0mzC0+su70 hhNtFpRWdQ== =+imO -----END PGP SIGNATURE----- Merge tag 'samsung-drivers-dmc-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers Samsung DMC driver for v5.5 Add Samsung Dynamic Memory Controller for Exynos5422 which provides scaling of frequency and voltage of memory controller and DRAM. The driver allows to reduce energy usage without performance impact. * tag 'samsung-drivers-dmc-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: memory: samsung: exynos5422-dmc: Add support for interrupt from performance counters memory: samsung: exynos5422-dmc: Fix kfree() of devm-allocated memory and missing static memory: samsung: exynos5422-dmc: Fix spelling mistake "counld" -> "could" memory: Add DMC driver for Exynos5422 memory: Extend of_memory with LPDDR3 support Link: https://lore.kernel.org/r/20191021180453.29455-3-krzk@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
2051818b34
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@ -4969,6 +4969,14 @@ F: include/linux/dma-direct.h
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F: include/linux/dma-mapping.h
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F: include/linux/dma-noncoherent.h
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DMC FREQUENCY DRIVER FOR SAMSUNG EXYNOS5422
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M: Lukasz Luba <l.luba@partner.samsung.com>
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L: linux-pm@vger.kernel.org
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L: linux-samsung-soc@vger.kernel.org
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S: Maintained
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F: drivers/memory/samsung/exynos5422-dmc.c
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F: Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
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DME1737 HARDWARE MONITOR DRIVER
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M: Juerg Haefliger <juergh@gmail.com>
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L: linux-hwmon@vger.kernel.org
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@ -29,6 +29,7 @@
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#define DDR_TYPE_LPDDR2_S4 3
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#define DDR_TYPE_LPDDR2_S2 4
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#define DDR_TYPE_LPDDR2_NVM 5
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#define DDR_TYPE_LPDDR3 6
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/* DDR IO width */
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#define DDR_IO_WIDTH_4 1
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@ -169,4 +170,64 @@ extern const struct lpddr2_timings
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lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES];
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extern const struct lpddr2_min_tck lpddr2_jedec_min_tck;
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/*
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* Structure for timings for LPDDR3 based on LPDDR2 plus additional fields.
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* All parameters are in pico seconds(ps) excluding max_freq, min_freq which
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* are in Hz.
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*/
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struct lpddr3_timings {
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u32 max_freq;
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u32 min_freq;
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u32 tRFC;
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u32 tRRD;
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u32 tRPab;
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u32 tRPpb;
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u32 tRCD;
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u32 tRC;
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u32 tRAS;
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u32 tWTR;
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u32 tWR;
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u32 tRTP;
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u32 tW2W_C2C;
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u32 tR2R_C2C;
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u32 tWL;
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u32 tDQSCK;
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u32 tRL;
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u32 tFAW;
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u32 tXSR;
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u32 tXP;
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u32 tCKE;
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u32 tCKESR;
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u32 tMRD;
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};
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/*
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* Min value for some parameters in terms of number of tCK cycles(nCK)
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* Please set to zero parameters that are not valid for a given memory
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* type
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*/
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struct lpddr3_min_tck {
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u32 tRFC;
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u32 tRRD;
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u32 tRPab;
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u32 tRPpb;
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u32 tRCD;
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u32 tRC;
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u32 tRAS;
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u32 tWTR;
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u32 tWR;
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u32 tRTP;
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u32 tW2W_C2C;
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u32 tR2R_C2C;
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u32 tWL;
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u32 tDQSCK;
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u32 tRL;
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u32 tFAW;
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u32 tXSR;
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u32 tXP;
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u32 tCKE;
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u32 tCKESR;
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u32 tMRD;
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};
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#endif /* __JEDEC_DDR_H */
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@ -3,6 +3,7 @@
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* OpenFirmware helpers for memory drivers
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*
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* Copyright (C) 2012 Texas Instruments, Inc.
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* Copyright (C) 2019 Samsung Electronics Co., Ltd.
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*/
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#include <linux/device.h>
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@ -149,3 +150,151 @@ default_timings:
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return lpddr2_jedec_timings;
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}
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EXPORT_SYMBOL(of_get_ddr_timings);
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/**
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* of_lpddr3_get_min_tck() - extract min timing values for lpddr3
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* @np: pointer to ddr device tree node
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* @device: device requesting for min timing values
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*
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* Populates the lpddr3_min_tck structure by extracting data
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* from device tree node. Returns a pointer to the populated
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* structure. If any error in populating the structure, returns NULL.
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*/
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const struct lpddr3_min_tck *of_lpddr3_get_min_tck(struct device_node *np,
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struct device *dev)
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{
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int ret = 0;
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struct lpddr3_min_tck *min;
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min = devm_kzalloc(dev, sizeof(*min), GFP_KERNEL);
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if (!min)
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goto default_min_tck;
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ret |= of_property_read_u32(np, "tRFC-min-tck", &min->tRFC);
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ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD);
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ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab);
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ret |= of_property_read_u32(np, "tRPpb-min-tck", &min->tRPpb);
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ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD);
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ret |= of_property_read_u32(np, "tRC-min-tck", &min->tRC);
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ret |= of_property_read_u32(np, "tRAS-min-tck", &min->tRAS);
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ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR);
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ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR);
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ret |= of_property_read_u32(np, "tRTP-min-tck", &min->tRTP);
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ret |= of_property_read_u32(np, "tW2W-C2C-min-tck", &min->tW2W_C2C);
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ret |= of_property_read_u32(np, "tR2R-C2C-min-tck", &min->tR2R_C2C);
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ret |= of_property_read_u32(np, "tWL-min-tck", &min->tWL);
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ret |= of_property_read_u32(np, "tDQSCK-min-tck", &min->tDQSCK);
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ret |= of_property_read_u32(np, "tRL-min-tck", &min->tRL);
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ret |= of_property_read_u32(np, "tFAW-min-tck", &min->tFAW);
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ret |= of_property_read_u32(np, "tXSR-min-tck", &min->tXSR);
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ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP);
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ret |= of_property_read_u32(np, "tCKE-min-tck", &min->tCKE);
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ret |= of_property_read_u32(np, "tCKESR-min-tck", &min->tCKESR);
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ret |= of_property_read_u32(np, "tMRD-min-tck", &min->tMRD);
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if (ret) {
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dev_warn(dev, "%s: errors while parsing min-tck values\n",
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__func__);
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devm_kfree(dev, min);
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goto default_min_tck;
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}
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return min;
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default_min_tck:
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dev_warn(dev, "%s: using default min-tck values\n", __func__);
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return NULL;
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}
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EXPORT_SYMBOL(of_lpddr3_get_min_tck);
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static int of_lpddr3_do_get_timings(struct device_node *np,
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struct lpddr3_timings *tim)
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{
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int ret;
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/* The 'reg' param required since DT has changed, used as 'max-freq' */
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ret = of_property_read_u32(np, "reg", &tim->max_freq);
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ret |= of_property_read_u32(np, "min-freq", &tim->min_freq);
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ret |= of_property_read_u32(np, "tRFC", &tim->tRFC);
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ret |= of_property_read_u32(np, "tRRD", &tim->tRRD);
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ret |= of_property_read_u32(np, "tRPab", &tim->tRPab);
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ret |= of_property_read_u32(np, "tRPpb", &tim->tRPpb);
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ret |= of_property_read_u32(np, "tRCD", &tim->tRCD);
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ret |= of_property_read_u32(np, "tRC", &tim->tRC);
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ret |= of_property_read_u32(np, "tRAS", &tim->tRAS);
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ret |= of_property_read_u32(np, "tWTR", &tim->tWTR);
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ret |= of_property_read_u32(np, "tWR", &tim->tWR);
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ret |= of_property_read_u32(np, "tRTP", &tim->tRTP);
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ret |= of_property_read_u32(np, "tW2W-C2C", &tim->tW2W_C2C);
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ret |= of_property_read_u32(np, "tR2R-C2C", &tim->tR2R_C2C);
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ret |= of_property_read_u32(np, "tFAW", &tim->tFAW);
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ret |= of_property_read_u32(np, "tXSR", &tim->tXSR);
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ret |= of_property_read_u32(np, "tXP", &tim->tXP);
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ret |= of_property_read_u32(np, "tCKE", &tim->tCKE);
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ret |= of_property_read_u32(np, "tCKESR", &tim->tCKESR);
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ret |= of_property_read_u32(np, "tMRD", &tim->tMRD);
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return ret;
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}
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/**
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* of_lpddr3_get_ddr_timings() - extracts the lpddr3 timings and updates no of
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* frequencies available.
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* @np_ddr: Pointer to ddr device tree node
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* @dev: Device requesting for ddr timings
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* @device_type: Type of ddr
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* @nr_frequencies: No of frequencies available for ddr
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* (updated by this function)
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*
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* Populates lpddr3_timings structure by extracting data from device
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* tree node. Returns pointer to populated structure. If any error
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* while populating, returns NULL.
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*/
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const struct lpddr3_timings
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*of_lpddr3_get_ddr_timings(struct device_node *np_ddr, struct device *dev,
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u32 device_type, u32 *nr_frequencies)
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{
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struct lpddr3_timings *timings = NULL;
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u32 arr_sz = 0, i = 0;
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struct device_node *np_tim;
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char *tim_compat = NULL;
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switch (device_type) {
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case DDR_TYPE_LPDDR3:
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tim_compat = "jedec,lpddr3-timings";
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break;
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default:
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dev_warn(dev, "%s: un-supported memory type\n", __func__);
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}
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for_each_child_of_node(np_ddr, np_tim)
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if (of_device_is_compatible(np_tim, tim_compat))
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arr_sz++;
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if (arr_sz)
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timings = devm_kcalloc(dev, arr_sz, sizeof(*timings),
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GFP_KERNEL);
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if (!timings)
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goto default_timings;
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for_each_child_of_node(np_ddr, np_tim) {
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if (of_device_is_compatible(np_tim, tim_compat)) {
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if (of_lpddr3_do_get_timings(np_tim, &timings[i])) {
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devm_kfree(dev, timings);
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goto default_timings;
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}
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i++;
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}
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}
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*nr_frequencies = arr_sz;
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return timings;
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default_timings:
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dev_warn(dev, "%s: failed to get timings\n", __func__);
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*nr_frequencies = 0;
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return NULL;
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}
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EXPORT_SYMBOL(of_lpddr3_get_ddr_timings);
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@ -14,6 +14,11 @@ extern const struct lpddr2_min_tck *of_get_min_tck(struct device_node *np,
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extern const struct lpddr2_timings
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*of_get_ddr_timings(struct device_node *np_ddr, struct device *dev,
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u32 device_type, u32 *nr_frequencies);
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extern const struct lpddr3_min_tck
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*of_lpddr3_get_min_tck(struct device_node *np, struct device *dev);
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extern const struct lpddr3_timings
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*of_lpddr3_get_ddr_timings(struct device_node *np_ddr,
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struct device *dev, u32 device_type, u32 *nr_frequencies);
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#else
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static inline const struct lpddr2_min_tck
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*of_get_min_tck(struct device_node *np, struct device *dev)
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@ -27,6 +32,19 @@ static inline const struct lpddr2_timings
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{
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return NULL;
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}
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static inline const struct lpddr3_min_tck
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*of_lpddr3_get_min_tck(struct device_node *np, struct device *dev)
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{
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return NULL;
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}
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static inline const struct lpddr3_timings
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*of_lpddr3_get_ddr_timings(struct device_node *np_ddr,
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struct device *dev, u32 device_type, u32 *nr_frequencies)
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{
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return NULL;
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}
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#endif /* CONFIG_OF && CONFIG_DDR */
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#endif /* __LINUX_MEMORY_OF_REG_ */
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@ -7,6 +7,19 @@ config SAMSUNG_MC
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if SAMSUNG_MC
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config EXYNOS5422_DMC
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tristate "EXYNOS5422 Dynamic Memory Controller driver"
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depends on ARCH_EXYNOS || (COMPILE_TEST && HAS_IOMEM)
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select DDR
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depends on DEVFREQ_GOV_SIMPLE_ONDEMAND
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depends on (PM_DEVFREQ && PM_DEVFREQ_EVENT)
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help
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This adds driver for Exynos5422 DMC (Dynamic Memory Controller).
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The driver provides support for Dynamic Voltage and Frequency Scaling in
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DMC and DRAM. It also supports changing timings of DRAM running with
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different frequency. The timings are calculated based on DT memory
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information.
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config EXYNOS_SROM
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bool "Exynos SROM controller driver" if COMPILE_TEST
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depends on (ARM && ARCH_EXYNOS) || (COMPILE_TEST && HAS_IOMEM)
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|
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@ -1,2 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_EXYNOS5422_DMC) += exynos5422-dmc.o
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obj-$(CONFIG_EXYNOS_SROM) += exynos-srom.o
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|
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File diff suppressed because it is too large
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