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clk: ingenic: Use readl_poll_timeout instead of custom loop
Use the readl_poll_timeout() function instead of rolling our own busy-wait loops. This makes the code simpler. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-2-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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parent
29c37341b5
commit
21534fe39c
1 changed files with 29 additions and 26 deletions
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@ -12,11 +12,14 @@
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#include <linux/clkdev.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/math64.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/time.h>
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#include "cgu.h"
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#define MHZ (1000 * 1000)
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@ -159,6 +162,16 @@ ingenic_pll_round_rate(struct clk_hw *hw, unsigned long req_rate,
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return ingenic_pll_calc(clk_info, req_rate, *prate, NULL, NULL, NULL);
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}
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static inline int ingenic_pll_check_stable(struct ingenic_cgu *cgu,
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const struct ingenic_cgu_pll_info *pll_info)
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{
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u32 ctl;
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return readl_poll_timeout(cgu->base + pll_info->reg, ctl,
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ctl & BIT(pll_info->stable_bit),
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0, 100 * USEC_PER_MSEC);
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}
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static int
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ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long parent_rate)
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@ -201,9 +214,8 @@ static int ingenic_pll_enable(struct clk_hw *hw)
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
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const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
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const unsigned int timeout = 100;
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unsigned long flags;
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unsigned int i;
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int ret;
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u32 ctl;
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spin_lock_irqsave(&cgu->lock, flags);
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@ -219,20 +231,10 @@ static int ingenic_pll_enable(struct clk_hw *hw)
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writel(ctl, cgu->base + pll_info->reg);
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/* wait for the PLL to stabilise */
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for (i = 0; i < timeout; i++) {
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ctl = readl(cgu->base + pll_info->reg);
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if (ctl & BIT(pll_info->stable_bit))
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break;
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mdelay(1);
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}
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ret = ingenic_pll_check_stable(cgu, pll_info);
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spin_unlock_irqrestore(&cgu->lock, flags);
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if (i == timeout)
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return -EBUSY;
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return 0;
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return ret;
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}
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static void ingenic_pll_disable(struct clk_hw *hw)
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@ -441,6 +443,16 @@ ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate,
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return DIV_ROUND_UP(*parent_rate, div);
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}
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static inline int ingenic_clk_check_stable(struct ingenic_cgu *cgu,
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const struct ingenic_cgu_clk_info *clk_info)
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{
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u32 reg;
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return readl_poll_timeout(cgu->base + clk_info->div.reg, reg,
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!(reg & BIT(clk_info->div.busy_bit)),
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0, 100 * USEC_PER_MSEC);
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}
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static int
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ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long parent_rate)
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@ -448,9 +460,8 @@ ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate,
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const unsigned timeout = 100;
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unsigned long rate, flags;
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unsigned int hw_div, div, i;
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unsigned int hw_div, div;
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u32 reg, mask;
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int ret = 0;
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@ -486,16 +497,8 @@ ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate,
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writel(reg, cgu->base + clk_info->div.reg);
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/* wait for the change to take effect */
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if (clk_info->div.busy_bit != -1) {
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for (i = 0; i < timeout; i++) {
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reg = readl(cgu->base + clk_info->div.reg);
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if (!(reg & BIT(clk_info->div.busy_bit)))
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break;
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mdelay(1);
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}
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if (i == timeout)
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ret = -EBUSY;
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}
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if (clk_info->div.busy_bit != -1)
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ret = ingenic_clk_check_stable(cgu, clk_info);
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spin_unlock_irqrestore(&cgu->lock, flags);
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return ret;
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