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synced 2024-08-24 01:41:39 +00:00
spi: davinci: consolidate setup of SPIFMTn in one function
Consolidate the setup of SPIFMTn register under davinci_spi_setup_transfer() simplifying the code and avoiding unnecessary reads and writes to the register. The two inline functions {set|clear}_fmt_bits() can be eliminated because of this. Signed-off-by: Brian Niebuhr <bniebuhr@efjohnson.com> Tested-By: Michael Williamson <michael.williamson@criticallink.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This commit is contained in:
parent
53a31b07c5
commit
25f33512f6
1 changed files with 49 additions and 105 deletions
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@ -52,7 +52,6 @@
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#define SPIFMT_ODD_PARITY_MASK BIT(23)
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#define SPIFMT_WDELAY_MASK 0x3f000000u
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#define SPIFMT_WDELAY_SHIFT 24
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#define SPIFMT_CHARLEN_MASK 0x0000001Fu
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#define SPIFMT_PRESCALE_SHIFT 8
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@ -212,16 +211,6 @@ static inline void clear_io_bits(void __iomem *addr, u32 bits)
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iowrite32(v, addr);
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}
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static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
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{
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set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
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}
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static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
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{
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clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
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}
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static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable)
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{
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struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
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@ -306,10 +295,14 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
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{
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struct davinci_spi *davinci_spi;
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struct davinci_spi_config *spicfg;
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u8 bits_per_word = 0;
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u32 hz = 0, prescale = 0;
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u32 hz = 0, spifmt = 0, prescale = 0;
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davinci_spi = spi_master_get_devdata(spi->master);
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spicfg = (struct davinci_spi_config *)spi->controller_data;
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if (!spicfg)
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spicfg = &davinci_spi_default_cfg;
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if (t) {
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bits_per_word = t->bits_per_word;
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@ -338,18 +331,55 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
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if (!hz)
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hz = spi->max_speed_hz;
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/* Set up SPIFMTn register, unique to this chipselect. */
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prescale = davinci_spi_get_prescale(davinci_spi, hz);
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if (prescale < 0)
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return prescale;
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clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK,
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spi->chip_select);
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set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f,
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spi->chip_select);
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spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
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clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select);
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set_fmt_bits(davinci_spi->base,
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prescale << SPIFMT_PRESCALE_SHIFT, spi->chip_select);
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if (spi->mode & SPI_LSB_FIRST)
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spifmt |= SPIFMT_SHIFTDIR_MASK;
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if (spi->mode & SPI_CPOL)
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spifmt |= SPIFMT_POLARITY_MASK;
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if (!(spi->mode & SPI_CPHA))
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spifmt |= SPIFMT_PHASE_MASK;
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/*
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* Version 1 hardware supports two basic SPI modes:
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* - Standard SPI mode uses 4 pins, with chipselect
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* - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
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* (distinct from SPI_3WIRE, with just one data wire;
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* or similar variants without MOSI or without MISO)
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*
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* Version 2 hardware supports an optional handshaking signal,
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* so it can support two more modes:
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* - 5 pin SPI variant is standard SPI plus SPI_READY
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* - 4 pin with enable is (SPI_READY | SPI_NO_CS)
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*/
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if (davinci_spi->version == SPI_VERSION_2) {
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spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
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& SPIFMT_WDELAY_MASK);
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if (spicfg->odd_parity)
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spifmt |= SPIFMT_ODD_PARITY_MASK;
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if (spicfg->parity_enable)
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spifmt |= SPIFMT_PARITYENA_MASK;
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if (spicfg->timer_disable)
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spifmt |= SPIFMT_DISTIMER_MASK;
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if (spi->mode & SPI_READY)
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spifmt |= SPIFMT_WAITENA_MASK;
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}
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iowrite32(spifmt, davinci_spi->base + SPIFMT0);
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return 0;
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}
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@ -436,12 +466,8 @@ static int davinci_spi_setup(struct spi_device *spi)
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int retval;
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struct davinci_spi *davinci_spi;
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struct davinci_spi_dma *davinci_spi_dma;
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struct davinci_spi_config *spicfg;
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davinci_spi = spi_master_get_devdata(spi->master);
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spicfg = (struct davinci_spi_config *)spi->controller_data;
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if (!spicfg)
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spicfg = &davinci_spi_default_cfg;
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/* if bits per word length is zero then set it default 8 */
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if (!spi->bits_per_word)
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@ -460,88 +486,6 @@ static int davinci_spi_setup(struct spi_device *spi)
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}
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}
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/*
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* Set up SPIFMTn register, unique to this chipselect.
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*
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* NOTE: we could do all of these with one write. Also, some
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* of the "version 2" features are found in chips that don't
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* support all of them...
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*/
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if (spi->mode & SPI_LSB_FIRST)
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set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
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spi->chip_select);
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else
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clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
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spi->chip_select);
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if (spi->mode & SPI_CPOL)
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set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
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spi->chip_select);
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else
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clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
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spi->chip_select);
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if (!(spi->mode & SPI_CPHA))
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set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
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spi->chip_select);
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else
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clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
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spi->chip_select);
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/*
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* Version 1 hardware supports two basic SPI modes:
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* - Standard SPI mode uses 4 pins, with chipselect
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* - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
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* (distinct from SPI_3WIRE, with just one data wire;
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* or similar variants without MOSI or without MISO)
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*
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* Version 2 hardware supports an optional handshaking signal,
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* so it can support two more modes:
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* - 5 pin SPI variant is standard SPI plus SPI_READY
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* - 4 pin with enable is (SPI_READY | SPI_NO_CS)
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*/
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if (davinci_spi->version == SPI_VERSION_2) {
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clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK,
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spi->chip_select);
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set_fmt_bits(davinci_spi->base,
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(spicfg->wdelay << SPIFMT_WDELAY_SHIFT) &
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SPIFMT_WDELAY_MASK, spi->chip_select);
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if (spicfg->odd_parity)
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set_fmt_bits(davinci_spi->base, SPIFMT_ODD_PARITY_MASK,
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spi->chip_select);
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else
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clear_fmt_bits(davinci_spi->base,
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SPIFMT_ODD_PARITY_MASK,
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spi->chip_select);
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if (spicfg->parity_enable)
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set_fmt_bits(davinci_spi->base, SPIFMT_PARITYENA_MASK,
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spi->chip_select);
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else
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clear_fmt_bits(davinci_spi->base, SPIFMT_PARITYENA_MASK,
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spi->chip_select);
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if (spicfg->timer_disable)
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set_fmt_bits(davinci_spi->base, SPIFMT_DISTIMER_MASK,
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spi->chip_select);
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else
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clear_fmt_bits(davinci_spi->base, SPIFMT_DISTIMER_MASK,
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spi->chip_select);
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if (spi->mode & SPI_READY)
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set_fmt_bits(davinci_spi->base,
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SPIFMT_WAITENA_MASK,
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spi->chip_select);
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else
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clear_fmt_bits(davinci_spi->base,
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SPIFMT_WAITENA_MASK,
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spi->chip_select);
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}
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retval = davinci_spi_setup_transfer(spi, NULL);
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return retval;
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