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drm/amdgpu: set snoop bit in pde/pte entries for A+A 

Page tables in vram mapping to cpu is changed from uncached to
cached in A+A, the snoop bit in VM_CONTEXTx_PAGE_TABLE_BASE_ADDR/
PDE0s/PDE1s/PDE2s/PTE.TFs has to be set so gpuvm walker snoop
page table data out of CPU cache.

Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Huang 2021-02-27 17:46:44 -05:00 committed by Alex Deucher
parent 06bfc045d5
commit 2e2f197f4c
1 changed files with 4 additions and 0 deletions
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4
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
View File

@ -1432,6 +1432,10 @@ uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
flags |= AMDGPU_PTE_SNOOPED;
}
if (mem && mem->mem_type == TTM_PL_VRAM &&
mem->bus.caching == ttm_cached)
flags |= AMDGPU_PTE_SNOOPED;
return flags;
}