drm/amdgpu: set snoop bit in pde/pte entries for A+A
Page tables in vram mapping to cpu is changed from uncached to cached in A+A, the snoop bit in VM_CONTEXTx_PAGE_TABLE_BASE_ADDR/ PDE0s/PDE1s/PDE2s/PTE.TFs has to be set so gpuvm walker snoop page table data out of CPU cache. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1432,6 +1432,10 @@ uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
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flags |= AMDGPU_PTE_SNOOPED;
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}
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if (mem && mem->mem_type == TTM_PL_VRAM &&
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mem->bus.caching == ttm_cached)
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flags |= AMDGPU_PTE_SNOOPED;
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return flags;
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}
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