mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-04 09:59:32 +00:00
Merge branch 'tegra/cleanup' into next/cleanup
This commit is contained in:
commit
2f540738f8
180 changed files with 1260 additions and 1028 deletions
|
@ -35,13 +35,6 @@ the Out-Of-Spec bit. Following table summarizes the exported sysfs files:
|
||||||
All Sysfs entries are named with their core_id (represented here by 'X').
|
All Sysfs entries are named with their core_id (represented here by 'X').
|
||||||
tempX_input - Core temperature (in millidegrees Celsius).
|
tempX_input - Core temperature (in millidegrees Celsius).
|
||||||
tempX_max - All cooling devices should be turned on (on Core2).
|
tempX_max - All cooling devices should be turned on (on Core2).
|
||||||
Initialized with IA32_THERM_INTERRUPT. When the CPU
|
|
||||||
temperature reaches this temperature, an interrupt is
|
|
||||||
generated and tempX_max_alarm is set.
|
|
||||||
tempX_max_hyst - If the CPU temperature falls below than temperature,
|
|
||||||
an interrupt is generated and tempX_max_alarm is reset.
|
|
||||||
tempX_max_alarm - Set if the temperature reaches or exceeds tempX_max.
|
|
||||||
Reset if the temperature drops to or below tempX_max_hyst.
|
|
||||||
tempX_crit - Maximum junction temperature (in millidegrees Celsius).
|
tempX_crit - Maximum junction temperature (in millidegrees Celsius).
|
||||||
tempX_crit_alarm - Set when Out-of-spec bit is set, never clears.
|
tempX_crit_alarm - Set when Out-of-spec bit is set, never clears.
|
||||||
Correct CPU operation is no longer guaranteed.
|
Correct CPU operation is no longer guaranteed.
|
||||||
|
@ -49,9 +42,10 @@ tempX_label - Contains string "Core X", where X is processor
|
||||||
number. For Package temp, this will be "Physical id Y",
|
number. For Package temp, this will be "Physical id Y",
|
||||||
where Y is the package number.
|
where Y is the package number.
|
||||||
|
|
||||||
The TjMax temperature is set to 85 degrees C if undocumented model specific
|
On CPU models which support it, TjMax is read from a model-specific register.
|
||||||
register (UMSR) 0xee has bit 30 set. If not the TjMax is 100 degrees C as
|
On other models, it is set to an arbitrary value based on weak heuristics.
|
||||||
(sometimes) documented in processor datasheet.
|
If these heuristics don't work for you, you can pass the correct TjMax value
|
||||||
|
as a module parameter (tjmax).
|
||||||
|
|
||||||
Appendix A. Known TjMax lists (TBD):
|
Appendix A. Known TjMax lists (TBD):
|
||||||
Some information comes from ark.intel.com
|
Some information comes from ark.intel.com
|
||||||
|
|
|
@ -1042,7 +1042,7 @@ conf/interface/*:
|
||||||
The functional behaviour for certain settings is different
|
The functional behaviour for certain settings is different
|
||||||
depending on whether local forwarding is enabled or not.
|
depending on whether local forwarding is enabled or not.
|
||||||
|
|
||||||
accept_ra - BOOLEAN
|
accept_ra - INTEGER
|
||||||
Accept Router Advertisements; autoconfigure using them.
|
Accept Router Advertisements; autoconfigure using them.
|
||||||
|
|
||||||
Possible values are:
|
Possible values are:
|
||||||
|
@ -1106,7 +1106,7 @@ dad_transmits - INTEGER
|
||||||
The amount of Duplicate Address Detection probes to send.
|
The amount of Duplicate Address Detection probes to send.
|
||||||
Default: 1
|
Default: 1
|
||||||
|
|
||||||
forwarding - BOOLEAN
|
forwarding - INTEGER
|
||||||
Configure interface-specific Host/Router behaviour.
|
Configure interface-specific Host/Router behaviour.
|
||||||
|
|
||||||
Note: It is recommended to have the same setting on all
|
Note: It is recommended to have the same setting on all
|
||||||
|
|
|
@ -243,7 +243,7 @@ configured. The number of entries in the global flow table is set through:
|
||||||
|
|
||||||
The number of entries in the per-queue flow table are set through:
|
The number of entries in the per-queue flow table are set through:
|
||||||
|
|
||||||
/sys/class/net/<dev>/queues/tx-<n>/rps_flow_cnt
|
/sys/class/net/<dev>/queues/rx-<n>/rps_flow_cnt
|
||||||
|
|
||||||
== Suggested Configuration
|
== Suggested Configuration
|
||||||
|
|
||||||
|
|
|
@ -123,10 +123,11 @@ be automatically shutdown if it's set to "never".
|
||||||
khugepaged runs usually at low frequency so while one may not want to
|
khugepaged runs usually at low frequency so while one may not want to
|
||||||
invoke defrag algorithms synchronously during the page faults, it
|
invoke defrag algorithms synchronously during the page faults, it
|
||||||
should be worth invoking defrag at least in khugepaged. However it's
|
should be worth invoking defrag at least in khugepaged. However it's
|
||||||
also possible to disable defrag in khugepaged:
|
also possible to disable defrag in khugepaged by writing 0 or enable
|
||||||
|
defrag in khugepaged by writing 1:
|
||||||
|
|
||||||
echo yes >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
|
echo 0 >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
|
||||||
echo no >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
|
echo 1 >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
|
||||||
|
|
||||||
You can also control how many pages khugepaged should scan at each
|
You can also control how many pages khugepaged should scan at each
|
||||||
pass:
|
pass:
|
||||||
|
|
|
@ -6374,7 +6374,6 @@ S: Supported
|
||||||
F: arch/arm/mach-tegra
|
F: arch/arm/mach-tegra
|
||||||
|
|
||||||
TEHUTI ETHERNET DRIVER
|
TEHUTI ETHERNET DRIVER
|
||||||
M: Alexander Indenbaum <baum@tehutinetworks.net>
|
|
||||||
M: Andy Gospodarek <andy@greyhouse.net>
|
M: Andy Gospodarek <andy@greyhouse.net>
|
||||||
L: netdev@vger.kernel.org
|
L: netdev@vger.kernel.org
|
||||||
S: Supported
|
S: Supported
|
||||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
||||||
VERSION = 3
|
VERSION = 3
|
||||||
PATCHLEVEL = 1
|
PATCHLEVEL = 1
|
||||||
SUBLEVEL = 0
|
SUBLEVEL = 0
|
||||||
EXTRAVERSION = -rc7
|
EXTRAVERSION = -rc9
|
||||||
NAME = "Divemaster Edition"
|
NAME = "Divemaster Edition"
|
||||||
|
|
||||||
# *DOCUMENTATION*
|
# *DOCUMENTATION*
|
||||||
|
|
|
@ -1285,6 +1285,20 @@ config ARM_ERRATA_364296
|
||||||
processor into full low interrupt latency mode. ARM11MPCore
|
processor into full low interrupt latency mode. ARM11MPCore
|
||||||
is not affected.
|
is not affected.
|
||||||
|
|
||||||
|
config ARM_ERRATA_764369
|
||||||
|
bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
|
||||||
|
depends on CPU_V7 && SMP
|
||||||
|
help
|
||||||
|
This option enables the workaround for erratum 764369
|
||||||
|
affecting Cortex-A9 MPCore with two or more processors (all
|
||||||
|
current revisions). Under certain timing circumstances, a data
|
||||||
|
cache line maintenance operation by MVA targeting an Inner
|
||||||
|
Shareable memory region may fail to proceed up to either the
|
||||||
|
Point of Coherency or to the Point of Unification of the
|
||||||
|
system. This workaround adds a DSB instruction before the
|
||||||
|
relevant cache maintenance functions and sets a specific bit
|
||||||
|
in the diagnostic control register of the SCU.
|
||||||
|
|
||||||
endmenu
|
endmenu
|
||||||
|
|
||||||
source "arch/arm/common/Kconfig"
|
source "arch/arm/common/Kconfig"
|
||||||
|
|
|
@ -25,17 +25,17 @@
|
||||||
|
|
||||||
#ifdef CONFIG_SMP
|
#ifdef CONFIG_SMP
|
||||||
|
|
||||||
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
|
#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
|
||||||
smp_mb(); \
|
smp_mb(); \
|
||||||
__asm__ __volatile__( \
|
__asm__ __volatile__( \
|
||||||
"1: ldrex %1, [%2]\n" \
|
"1: ldrex %1, [%3]\n" \
|
||||||
" " insn "\n" \
|
" " insn "\n" \
|
||||||
"2: strex %1, %0, [%2]\n" \
|
"2: strex %2, %0, [%3]\n" \
|
||||||
" teq %1, #0\n" \
|
" teq %2, #0\n" \
|
||||||
" bne 1b\n" \
|
" bne 1b\n" \
|
||||||
" mov %0, #0\n" \
|
" mov %0, #0\n" \
|
||||||
__futex_atomic_ex_table("%4") \
|
__futex_atomic_ex_table("%5") \
|
||||||
: "=&r" (ret), "=&r" (oldval) \
|
: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
|
||||||
: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
|
: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
|
||||||
: "cc", "memory")
|
: "cc", "memory")
|
||||||
|
|
||||||
|
@ -73,14 +73,14 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
|
||||||
#include <linux/preempt.h>
|
#include <linux/preempt.h>
|
||||||
#include <asm/domain.h>
|
#include <asm/domain.h>
|
||||||
|
|
||||||
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
|
#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
|
||||||
__asm__ __volatile__( \
|
__asm__ __volatile__( \
|
||||||
"1: " T(ldr) " %1, [%2]\n" \
|
"1: " T(ldr) " %1, [%3]\n" \
|
||||||
" " insn "\n" \
|
" " insn "\n" \
|
||||||
"2: " T(str) " %0, [%2]\n" \
|
"2: " T(str) " %0, [%3]\n" \
|
||||||
" mov %0, #0\n" \
|
" mov %0, #0\n" \
|
||||||
__futex_atomic_ex_table("%4") \
|
__futex_atomic_ex_table("%5") \
|
||||||
: "=&r" (ret), "=&r" (oldval) \
|
: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
|
||||||
: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
|
: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
|
||||||
: "cc", "memory")
|
: "cc", "memory")
|
||||||
|
|
||||||
|
@ -117,7 +117,7 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
|
||||||
int cmp = (encoded_op >> 24) & 15;
|
int cmp = (encoded_op >> 24) & 15;
|
||||||
int oparg = (encoded_op << 8) >> 20;
|
int oparg = (encoded_op << 8) >> 20;
|
||||||
int cmparg = (encoded_op << 20) >> 20;
|
int cmparg = (encoded_op << 20) >> 20;
|
||||||
int oldval = 0, ret;
|
int oldval = 0, ret, tmp;
|
||||||
|
|
||||||
if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
|
if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
|
||||||
oparg = 1 << oparg;
|
oparg = 1 << oparg;
|
||||||
|
@ -129,19 +129,19 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
|
||||||
|
|
||||||
switch (op) {
|
switch (op) {
|
||||||
case FUTEX_OP_SET:
|
case FUTEX_OP_SET:
|
||||||
__futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg);
|
__futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg);
|
||||||
break;
|
break;
|
||||||
case FUTEX_OP_ADD:
|
case FUTEX_OP_ADD:
|
||||||
__futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg);
|
__futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
|
||||||
break;
|
break;
|
||||||
case FUTEX_OP_OR:
|
case FUTEX_OP_OR:
|
||||||
__futex_atomic_op("orr %0, %1, %3", ret, oldval, uaddr, oparg);
|
__futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
|
||||||
break;
|
break;
|
||||||
case FUTEX_OP_ANDN:
|
case FUTEX_OP_ANDN:
|
||||||
__futex_atomic_op("and %0, %1, %3", ret, oldval, uaddr, ~oparg);
|
__futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
|
||||||
break;
|
break;
|
||||||
case FUTEX_OP_XOR:
|
case FUTEX_OP_XOR:
|
||||||
__futex_atomic_op("eor %0, %1, %3", ret, oldval, uaddr, oparg);
|
__futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
ret = -ENOSYS;
|
ret = -ENOSYS;
|
||||||
|
|
|
@ -478,8 +478,8 @@
|
||||||
/*
|
/*
|
||||||
* Unimplemented (or alternatively implemented) syscalls
|
* Unimplemented (or alternatively implemented) syscalls
|
||||||
*/
|
*/
|
||||||
#define __IGNORE_fadvise64_64 1
|
#define __IGNORE_fadvise64_64
|
||||||
#define __IGNORE_migrate_pages 1
|
#define __IGNORE_migrate_pages
|
||||||
|
|
||||||
#endif /* __KERNEL__ */
|
#endif /* __KERNEL__ */
|
||||||
#endif /* __ASM_ARM_UNISTD_H */
|
#endif /* __ASM_ARM_UNISTD_H */
|
||||||
|
|
|
@ -13,6 +13,7 @@
|
||||||
|
|
||||||
#include <asm/smp_scu.h>
|
#include <asm/smp_scu.h>
|
||||||
#include <asm/cacheflush.h>
|
#include <asm/cacheflush.h>
|
||||||
|
#include <asm/cputype.h>
|
||||||
|
|
||||||
#define SCU_CTRL 0x00
|
#define SCU_CTRL 0x00
|
||||||
#define SCU_CONFIG 0x04
|
#define SCU_CONFIG 0x04
|
||||||
|
@ -37,6 +38,15 @@ void __init scu_enable(void __iomem *scu_base)
|
||||||
{
|
{
|
||||||
u32 scu_ctrl;
|
u32 scu_ctrl;
|
||||||
|
|
||||||
|
#ifdef CONFIG_ARM_ERRATA_764369
|
||||||
|
/* Cortex-A9 only */
|
||||||
|
if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
|
||||||
|
scu_ctrl = __raw_readl(scu_base + 0x30);
|
||||||
|
if (!(scu_ctrl & 1))
|
||||||
|
__raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
|
scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
|
||||||
/* already enabled? */
|
/* already enabled? */
|
||||||
if (scu_ctrl & 1)
|
if (scu_ctrl & 1)
|
||||||
|
|
|
@ -23,8 +23,10 @@
|
||||||
|
|
||||||
#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
|
#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
|
||||||
#define ARM_EXIT_KEEP(x) x
|
#define ARM_EXIT_KEEP(x) x
|
||||||
|
#define ARM_EXIT_DISCARD(x)
|
||||||
#else
|
#else
|
||||||
#define ARM_EXIT_KEEP(x)
|
#define ARM_EXIT_KEEP(x)
|
||||||
|
#define ARM_EXIT_DISCARD(x) x
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
OUTPUT_ARCH(arm)
|
OUTPUT_ARCH(arm)
|
||||||
|
@ -39,6 +41,11 @@ jiffies = jiffies_64 + 4;
|
||||||
SECTIONS
|
SECTIONS
|
||||||
{
|
{
|
||||||
/*
|
/*
|
||||||
|
* XXX: The linker does not define how output sections are
|
||||||
|
* assigned to input sections when there are multiple statements
|
||||||
|
* matching the same input section name. There is no documented
|
||||||
|
* order of matching.
|
||||||
|
*
|
||||||
* unwind exit sections must be discarded before the rest of the
|
* unwind exit sections must be discarded before the rest of the
|
||||||
* unwind sections get included.
|
* unwind sections get included.
|
||||||
*/
|
*/
|
||||||
|
@ -47,6 +54,9 @@ SECTIONS
|
||||||
*(.ARM.extab.exit.text)
|
*(.ARM.extab.exit.text)
|
||||||
ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
|
ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
|
||||||
ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
|
ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
|
||||||
|
ARM_EXIT_DISCARD(EXIT_TEXT)
|
||||||
|
ARM_EXIT_DISCARD(EXIT_DATA)
|
||||||
|
EXIT_CALL
|
||||||
#ifndef CONFIG_HOTPLUG
|
#ifndef CONFIG_HOTPLUG
|
||||||
*(.ARM.exidx.devexit.text)
|
*(.ARM.exidx.devexit.text)
|
||||||
*(.ARM.extab.devexit.text)
|
*(.ARM.extab.devexit.text)
|
||||||
|
@ -58,6 +68,8 @@ SECTIONS
|
||||||
#ifndef CONFIG_SMP_ON_UP
|
#ifndef CONFIG_SMP_ON_UP
|
||||||
*(.alt.smp.init)
|
*(.alt.smp.init)
|
||||||
#endif
|
#endif
|
||||||
|
*(.discard)
|
||||||
|
*(.discard.*)
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_XIP_KERNEL
|
#ifdef CONFIG_XIP_KERNEL
|
||||||
|
@ -279,9 +291,6 @@ SECTIONS
|
||||||
|
|
||||||
STABS_DEBUG
|
STABS_DEBUG
|
||||||
.comment 0 : { *(.comment) }
|
.comment 0 : { *(.comment) }
|
||||||
|
|
||||||
/* Default discards */
|
|
||||||
DISCARDS
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -899,8 +899,7 @@ static struct clksrc_clk clksrcs[] = {
|
||||||
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
|
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
|
||||||
}, {
|
}, {
|
||||||
.clk = {
|
.clk = {
|
||||||
.name = "sclk_cam",
|
.name = "sclk_cam0",
|
||||||
.devname = "exynos4-fimc.0",
|
|
||||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||||
.ctrlbit = (1 << 16),
|
.ctrlbit = (1 << 16),
|
||||||
},
|
},
|
||||||
|
@ -909,8 +908,7 @@ static struct clksrc_clk clksrcs[] = {
|
||||||
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
|
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
|
||||||
}, {
|
}, {
|
||||||
.clk = {
|
.clk = {
|
||||||
.name = "sclk_cam",
|
.name = "sclk_cam1",
|
||||||
.devname = "exynos4-fimc.1",
|
|
||||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||||
.ctrlbit = (1 << 20),
|
.ctrlbit = (1 << 20),
|
||||||
},
|
},
|
||||||
|
|
|
@ -128,7 +128,7 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
|
||||||
unsigned long clkcon0;
|
unsigned long clkcon0;
|
||||||
|
|
||||||
clkcon0 = __raw_readl(S3C2443_CLKDIV0);
|
clkcon0 = __raw_readl(S3C2443_CLKDIV0);
|
||||||
clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
|
clkcon0 &= ~S3C2443_CLKDIV0_ARMDIV_MASK;
|
||||||
clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
|
clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
|
||||||
__raw_writel(clkcon0, S3C2443_CLKDIV0);
|
__raw_writel(clkcon0, S3C2443_CLKDIV0);
|
||||||
}
|
}
|
||||||
|
|
|
@ -815,8 +815,7 @@ static struct clksrc_clk clksrcs[] = {
|
||||||
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
|
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
|
||||||
}, {
|
}, {
|
||||||
.clk = {
|
.clk = {
|
||||||
.name = "sclk_cam",
|
.name = "sclk_cam0",
|
||||||
.devname = "s5pv210-fimc.0",
|
|
||||||
.enable = s5pv210_clk_mask0_ctrl,
|
.enable = s5pv210_clk_mask0_ctrl,
|
||||||
.ctrlbit = (1 << 3),
|
.ctrlbit = (1 << 3),
|
||||||
},
|
},
|
||||||
|
@ -825,8 +824,7 @@ static struct clksrc_clk clksrcs[] = {
|
||||||
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
|
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
|
||||||
}, {
|
}, {
|
||||||
.clk = {
|
.clk = {
|
||||||
.name = "sclk_cam",
|
.name = "sclk_cam1",
|
||||||
.devname = "s5pv210-fimc.1",
|
|
||||||
.enable = s5pv210_clk_mask0_ctrl,
|
.enable = s5pv210_clk_mask0_ctrl,
|
||||||
.ctrlbit = (1 << 4),
|
.ctrlbit = (1 << 4),
|
||||||
},
|
},
|
||||||
|
|
|
@ -61,7 +61,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
|
||||||
{ NULL, NULL, 0, 0},
|
{ NULL, NULL, 0, 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
void __init tegra_init_cache(void)
|
static void __init tegra_init_cache(void)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_CACHE_L2X0
|
#ifdef CONFIG_CACHE_L2X0
|
||||||
void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
|
void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
|
||||||
|
|
|
@ -57,12 +57,12 @@ static unsigned long target_cpu_speed[NUM_CPUS];
|
||||||
static DEFINE_MUTEX(tegra_cpu_lock);
|
static DEFINE_MUTEX(tegra_cpu_lock);
|
||||||
static bool is_suspended;
|
static bool is_suspended;
|
||||||
|
|
||||||
int tegra_verify_speed(struct cpufreq_policy *policy)
|
static int tegra_verify_speed(struct cpufreq_policy *policy)
|
||||||
{
|
{
|
||||||
return cpufreq_frequency_table_verify(policy, freq_table);
|
return cpufreq_frequency_table_verify(policy, freq_table);
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned int tegra_getspeed(unsigned int cpu)
|
static unsigned int tegra_getspeed(unsigned int cpu)
|
||||||
{
|
{
|
||||||
unsigned long rate;
|
unsigned long rate;
|
||||||
|
|
||||||
|
@ -130,7 +130,7 @@ static int tegra_target(struct cpufreq_policy *policy,
|
||||||
unsigned int target_freq,
|
unsigned int target_freq,
|
||||||
unsigned int relation)
|
unsigned int relation)
|
||||||
{
|
{
|
||||||
int idx;
|
unsigned int idx;
|
||||||
unsigned int freq;
|
unsigned int freq;
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
|
|
||||||
|
|
|
@ -29,7 +29,9 @@
|
||||||
#include <mach/iomap.h>
|
#include <mach/iomap.h>
|
||||||
#include <mach/dma.h>
|
#include <mach/dma.h>
|
||||||
#include <mach/usb_phy.h>
|
#include <mach/usb_phy.h>
|
||||||
|
|
||||||
#include "gpio-names.h"
|
#include "gpio-names.h"
|
||||||
|
#include "devices.h"
|
||||||
|
|
||||||
static struct resource i2c_resource1[] = {
|
static struct resource i2c_resource1[] = {
|
||||||
[0] = {
|
[0] = {
|
||||||
|
|
|
@ -105,13 +105,17 @@
|
||||||
|
|
||||||
#define NV_DMA_MAX_TRASFER_SIZE 0x10000
|
#define NV_DMA_MAX_TRASFER_SIZE 0x10000
|
||||||
|
|
||||||
const unsigned int ahb_addr_wrap_table[8] = {
|
static const unsigned int ahb_addr_wrap_table[8] = {
|
||||||
0, 32, 64, 128, 256, 512, 1024, 2048
|
0, 32, 64, 128, 256, 512, 1024, 2048
|
||||||
};
|
};
|
||||||
|
|
||||||
const unsigned int apb_addr_wrap_table[8] = {0, 1, 2, 4, 8, 16, 32, 64};
|
static const unsigned int apb_addr_wrap_table[8] = {
|
||||||
|
0, 1, 2, 4, 8, 16, 32, 64
|
||||||
|
};
|
||||||
|
|
||||||
const unsigned int bus_width_table[5] = {8, 16, 32, 64, 128};
|
static const unsigned int bus_width_table[5] = {
|
||||||
|
8, 16, 32, 64, 128
|
||||||
|
};
|
||||||
|
|
||||||
#define TEGRA_DMA_NAME_SIZE 16
|
#define TEGRA_DMA_NAME_SIZE 16
|
||||||
struct tegra_dma_channel {
|
struct tegra_dma_channel {
|
||||||
|
@ -157,7 +161,7 @@ void tegra_dma_dequeue(struct tegra_dma_channel *ch)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
void tegra_dma_stop(struct tegra_dma_channel *ch)
|
static void tegra_dma_stop(struct tegra_dma_channel *ch)
|
||||||
{
|
{
|
||||||
u32 csr;
|
u32 csr;
|
||||||
u32 status;
|
u32 status;
|
||||||
|
@ -174,7 +178,7 @@ void tegra_dma_stop(struct tegra_dma_channel *ch)
|
||||||
writel(status, ch->addr + APB_DMA_CHAN_STA);
|
writel(status, ch->addr + APB_DMA_CHAN_STA);
|
||||||
}
|
}
|
||||||
|
|
||||||
int tegra_dma_cancel(struct tegra_dma_channel *ch)
|
static int tegra_dma_cancel(struct tegra_dma_channel *ch)
|
||||||
{
|
{
|
||||||
u32 csr;
|
u32 csr;
|
||||||
unsigned long irq_flags;
|
unsigned long irq_flags;
|
||||||
|
|
|
@ -33,20 +33,26 @@
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#ifdef __ASSEMBLY__
|
||||||
|
#define IOMEM(x) (x)
|
||||||
|
#else
|
||||||
|
#define IOMEM(x) ((void __force __iomem *)(x))
|
||||||
|
#endif
|
||||||
|
|
||||||
#define IO_IRAM_PHYS 0x40000000
|
#define IO_IRAM_PHYS 0x40000000
|
||||||
#define IO_IRAM_VIRT 0xFE400000
|
#define IO_IRAM_VIRT IOMEM(0xFE400000)
|
||||||
#define IO_IRAM_SIZE SZ_256K
|
#define IO_IRAM_SIZE SZ_256K
|
||||||
|
|
||||||
#define IO_CPU_PHYS 0x50040000
|
#define IO_CPU_PHYS 0x50040000
|
||||||
#define IO_CPU_VIRT 0xFE000000
|
#define IO_CPU_VIRT IOMEM(0xFE000000)
|
||||||
#define IO_CPU_SIZE SZ_16K
|
#define IO_CPU_SIZE SZ_16K
|
||||||
|
|
||||||
#define IO_PPSB_PHYS 0x60000000
|
#define IO_PPSB_PHYS 0x60000000
|
||||||
#define IO_PPSB_VIRT 0xFE200000
|
#define IO_PPSB_VIRT IOMEM(0xFE200000)
|
||||||
#define IO_PPSB_SIZE SZ_1M
|
#define IO_PPSB_SIZE SZ_1M
|
||||||
|
|
||||||
#define IO_APB_PHYS 0x70000000
|
#define IO_APB_PHYS 0x70000000
|
||||||
#define IO_APB_VIRT 0xFE300000
|
#define IO_APB_VIRT IOMEM(0xFE300000)
|
||||||
#define IO_APB_SIZE SZ_1M
|
#define IO_APB_SIZE SZ_1M
|
||||||
|
|
||||||
#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
|
#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
|
||||||
|
@ -61,7 +67,7 @@
|
||||||
IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \
|
IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \
|
||||||
IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ? \
|
IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ? \
|
||||||
IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) : \
|
IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) : \
|
||||||
0)
|
NULL)
|
||||||
|
|
||||||
#ifndef __ASSEMBLER__
|
#ifndef __ASSEMBLER__
|
||||||
|
|
||||||
|
@ -71,7 +77,7 @@
|
||||||
void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
|
void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
|
||||||
void tegra_iounmap(volatile void __iomem *addr);
|
void tegra_iounmap(volatile void __iomem *addr);
|
||||||
|
|
||||||
#define IO_ADDRESS(n) ((void __iomem *) IO_TO_VIRT(n))
|
#define IO_ADDRESS(n) (IO_TO_VIRT(n))
|
||||||
|
|
||||||
#ifdef CONFIG_TEGRA_PCI
|
#ifdef CONFIG_TEGRA_PCI
|
||||||
extern void __iomem *tegra_pcie_io_base;
|
extern void __iomem *tegra_pcie_io_base;
|
||||||
|
|
|
@ -31,7 +31,6 @@
|
||||||
|
|
||||||
int tegra_powergate_power_on(int id);
|
int tegra_powergate_power_on(int id);
|
||||||
int tegra_powergate_power_off(int id);
|
int tegra_powergate_power_off(int id);
|
||||||
bool tegra_powergate_is_powered(int id);
|
|
||||||
int tegra_powergate_remove_clamping(int id);
|
int tegra_powergate_remove_clamping(int id);
|
||||||
|
|
||||||
/* Must be called with clk disabled, and returns with clk enabled */
|
/* Must be called with clk disabled, and returns with clk enabled */
|
||||||
|
|
|
@ -31,25 +31,25 @@
|
||||||
|
|
||||||
static struct map_desc tegra_io_desc[] __initdata = {
|
static struct map_desc tegra_io_desc[] __initdata = {
|
||||||
{
|
{
|
||||||
.virtual = IO_PPSB_VIRT,
|
.virtual = (unsigned long)IO_PPSB_VIRT,
|
||||||
.pfn = __phys_to_pfn(IO_PPSB_PHYS),
|
.pfn = __phys_to_pfn(IO_PPSB_PHYS),
|
||||||
.length = IO_PPSB_SIZE,
|
.length = IO_PPSB_SIZE,
|
||||||
.type = MT_DEVICE,
|
.type = MT_DEVICE,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.virtual = IO_APB_VIRT,
|
.virtual = (unsigned long)IO_APB_VIRT,
|
||||||
.pfn = __phys_to_pfn(IO_APB_PHYS),
|
.pfn = __phys_to_pfn(IO_APB_PHYS),
|
||||||
.length = IO_APB_SIZE,
|
.length = IO_APB_SIZE,
|
||||||
.type = MT_DEVICE,
|
.type = MT_DEVICE,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.virtual = IO_CPU_VIRT,
|
.virtual = (unsigned long)IO_CPU_VIRT,
|
||||||
.pfn = __phys_to_pfn(IO_CPU_PHYS),
|
.pfn = __phys_to_pfn(IO_CPU_PHYS),
|
||||||
.length = IO_CPU_SIZE,
|
.length = IO_CPU_SIZE,
|
||||||
.type = MT_DEVICE,
|
.type = MT_DEVICE,
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
.virtual = IO_IRAM_VIRT,
|
.virtual = (unsigned long)IO_IRAM_VIRT,
|
||||||
.pfn = __phys_to_pfn(IO_IRAM_PHYS),
|
.pfn = __phys_to_pfn(IO_IRAM_PHYS),
|
||||||
.length = IO_IRAM_SIZE,
|
.length = IO_IRAM_SIZE,
|
||||||
.type = MT_DEVICE,
|
.type = MT_DEVICE,
|
||||||
|
|
|
@ -41,6 +41,8 @@
|
||||||
#include <mach/clk.h>
|
#include <mach/clk.h>
|
||||||
#include <mach/powergate.h>
|
#include <mach/powergate.h>
|
||||||
|
|
||||||
|
#include "board.h"
|
||||||
|
|
||||||
/* register definitions */
|
/* register definitions */
|
||||||
#define AFI_OFFSET 0x3800
|
#define AFI_OFFSET 0x3800
|
||||||
#define PADS_OFFSET 0x3000
|
#define PADS_OFFSET 0x3000
|
||||||
|
@ -150,9 +152,9 @@
|
||||||
static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
|
static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
|
||||||
|
|
||||||
#define pmc_writel(value, reg) \
|
#define pmc_writel(value, reg) \
|
||||||
__raw_writel(value, (u32)reg_pmc_base + (reg))
|
__raw_writel(value, reg_pmc_base + (reg))
|
||||||
#define pmc_readl(reg) \
|
#define pmc_readl(reg) \
|
||||||
__raw_readl((u32)reg_pmc_base + (reg))
|
__raw_readl(reg_pmc_base + (reg))
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Tegra2 defines 1GB in the AXI address map for PCIe.
|
* Tegra2 defines 1GB in the AXI address map for PCIe.
|
||||||
|
@ -460,7 +462,7 @@ static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
|
||||||
struct tegra_pcie_port *pp;
|
struct tegra_pcie_port *pp;
|
||||||
|
|
||||||
if (nr >= tegra_pcie.num_ports)
|
if (nr >= tegra_pcie.num_ports)
|
||||||
return 0;
|
return NULL;
|
||||||
|
|
||||||
pp = tegra_pcie.port + nr;
|
pp = tegra_pcie.port + nr;
|
||||||
pp->root_bus_nr = sys->busnr;
|
pp->root_bus_nr = sys->busnr;
|
||||||
|
|
|
@ -89,12 +89,11 @@ int tegra_powergate_power_off(int id)
|
||||||
return tegra_powergate_set(id, false);
|
return tegra_powergate_set(id, false);
|
||||||
}
|
}
|
||||||
|
|
||||||
bool tegra_powergate_is_powered(int id)
|
static bool tegra_powergate_is_powered(int id)
|
||||||
{
|
{
|
||||||
u32 status;
|
u32 status;
|
||||||
|
|
||||||
if (id < 0 || id >= TEGRA_NUM_POWERGATE)
|
WARN_ON(id < 0 || id >= TEGRA_NUM_POWERGATE);
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
status = pmc_read(PWRGATE_STATUS) & (1 << id);
|
status = pmc_read(PWRGATE_STATUS) & (1 << id);
|
||||||
return !!status;
|
return !!status;
|
||||||
|
|
|
@ -166,13 +166,13 @@ static DEFINE_SPINLOCK(clock_register_lock);
|
||||||
static int tegra_periph_clk_enable_refcount[3 * 32];
|
static int tegra_periph_clk_enable_refcount[3 * 32];
|
||||||
|
|
||||||
#define clk_writel(value, reg) \
|
#define clk_writel(value, reg) \
|
||||||
__raw_writel(value, (u32)reg_clk_base + (reg))
|
__raw_writel(value, reg_clk_base + (reg))
|
||||||
#define clk_readl(reg) \
|
#define clk_readl(reg) \
|
||||||
__raw_readl((u32)reg_clk_base + (reg))
|
__raw_readl(reg_clk_base + (reg))
|
||||||
#define pmc_writel(value, reg) \
|
#define pmc_writel(value, reg) \
|
||||||
__raw_writel(value, (u32)reg_pmc_base + (reg))
|
__raw_writel(value, reg_pmc_base + (reg))
|
||||||
#define pmc_readl(reg) \
|
#define pmc_readl(reg) \
|
||||||
__raw_readl((u32)reg_pmc_base + (reg))
|
__raw_readl(reg_pmc_base + (reg))
|
||||||
|
|
||||||
unsigned long clk_measure_input_freq(void)
|
unsigned long clk_measure_input_freq(void)
|
||||||
{
|
{
|
||||||
|
@ -918,7 +918,7 @@ static struct clk_ops tegra_pll_div_ops = {
|
||||||
static void tegra2_periph_clk_init(struct clk *c)
|
static void tegra2_periph_clk_init(struct clk *c)
|
||||||
{
|
{
|
||||||
u32 val = clk_readl(c->reg);
|
u32 val = clk_readl(c->reg);
|
||||||
const struct clk_mux_sel *mux = 0;
|
const struct clk_mux_sel *mux = NULL;
|
||||||
const struct clk_mux_sel *sel;
|
const struct clk_mux_sel *sel;
|
||||||
if (c->flags & MUX) {
|
if (c->flags & MUX) {
|
||||||
for (sel = c->inputs; sel->input != NULL; sel++) {
|
for (sel = c->inputs; sel->input != NULL; sel++) {
|
||||||
|
@ -1459,7 +1459,7 @@ static struct clk tegra_pll_s = {
|
||||||
static struct clk_mux_sel tegra_clk_m_sel[] = {
|
static struct clk_mux_sel tegra_clk_m_sel[] = {
|
||||||
{ .input = &tegra_clk_32k, .value = 0},
|
{ .input = &tegra_clk_32k, .value = 0},
|
||||||
{ .input = &tegra_pll_s, .value = 1},
|
{ .input = &tegra_pll_s, .value = 1},
|
||||||
{ 0, 0},
|
{ NULL , 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk tegra_clk_m = {
|
static struct clk tegra_clk_m = {
|
||||||
|
@ -1861,7 +1861,7 @@ static const struct audio_sources {
|
||||||
{ .name = "ext_audio_clk1", .value = 6 },
|
{ .name = "ext_audio_clk1", .value = 6 },
|
||||||
{ .name = "ext_vimclk", .value = 7 },
|
{ .name = "ext_vimclk", .value = 7 },
|
||||||
#endif
|
#endif
|
||||||
{ 0, 0 }
|
{ NULL, 0 }
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk tegra_clk_audio = {
|
static struct clk tegra_clk_audio = {
|
||||||
|
@ -1885,7 +1885,7 @@ static struct clk tegra_clk_audio_2x = {
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
struct clk_lookup tegra_audio_clk_lookups[] = {
|
static struct clk_lookup tegra_audio_clk_lookups[] = {
|
||||||
{ .con_id = "audio", .clk = &tegra_clk_audio },
|
{ .con_id = "audio", .clk = &tegra_clk_audio },
|
||||||
{ .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
|
{ .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
|
||||||
};
|
};
|
||||||
|
@ -1926,7 +1926,7 @@ static struct clk_mux_sel mux_cclk[] = {
|
||||||
{ .input = &tegra_pll_p_out3, .value = 6},
|
{ .input = &tegra_pll_p_out3, .value = 6},
|
||||||
{ .input = &tegra_clk_d, .value = 7},
|
{ .input = &tegra_clk_d, .value = 7},
|
||||||
{ .input = &tegra_pll_x, .value = 8},
|
{ .input = &tegra_pll_x, .value = 8},
|
||||||
{ 0, 0},
|
{ NULL, 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk_mux_sel mux_sclk[] = {
|
static struct clk_mux_sel mux_sclk[] = {
|
||||||
|
@ -1938,7 +1938,7 @@ static struct clk_mux_sel mux_sclk[] = {
|
||||||
{ .input = &tegra_clk_d, .value = 5},
|
{ .input = &tegra_clk_d, .value = 5},
|
||||||
{ .input = &tegra_clk_32k, .value = 6},
|
{ .input = &tegra_clk_32k, .value = 6},
|
||||||
{ .input = &tegra_pll_m_out1, .value = 7},
|
{ .input = &tegra_pll_m_out1, .value = 7},
|
||||||
{ 0, 0},
|
{ NULL, 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk tegra_clk_cclk = {
|
static struct clk tegra_clk_cclk = {
|
||||||
|
@ -2009,7 +2009,7 @@ static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
|
||||||
{ .input = &tegra_pll_c, .value = 1},
|
{ .input = &tegra_pll_c, .value = 1},
|
||||||
{ .input = &tegra_pll_p, .value = 2},
|
{ .input = &tegra_pll_p, .value = 2},
|
||||||
{ .input = &tegra_pll_a_out0, .value = 3},
|
{ .input = &tegra_pll_a_out0, .value = 3},
|
||||||
{ 0, 0},
|
{ NULL, 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
|
static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
|
||||||
|
@ -2017,7 +2017,7 @@ static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
|
||||||
{ .input = &tegra_pll_c, .value = 1},
|
{ .input = &tegra_pll_c, .value = 1},
|
||||||
{ .input = &tegra_pll_p, .value = 2},
|
{ .input = &tegra_pll_p, .value = 2},
|
||||||
{ .input = &tegra_clk_m, .value = 3},
|
{ .input = &tegra_clk_m, .value = 3},
|
||||||
{ 0, 0},
|
{ NULL, 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
|
static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
|
||||||
|
@ -2025,7 +2025,7 @@ static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
|
||||||
{ .input = &tegra_pll_c, .value = 1},
|
{ .input = &tegra_pll_c, .value = 1},
|
||||||
{ .input = &tegra_pll_m, .value = 2},
|
{ .input = &tegra_pll_m, .value = 2},
|
||||||
{ .input = &tegra_clk_m, .value = 3},
|
{ .input = &tegra_clk_m, .value = 3},
|
||||||
{ 0, 0},
|
{ NULL, 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
|
static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
|
||||||
|
@ -2033,7 +2033,7 @@ static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
|
||||||
{.input = &tegra_clk_audio_2x, .value = 1},
|
{.input = &tegra_clk_audio_2x, .value = 1},
|
||||||
{.input = &tegra_pll_p, .value = 2},
|
{.input = &tegra_pll_p, .value = 2},
|
||||||
{.input = &tegra_clk_m, .value = 3},
|
{.input = &tegra_clk_m, .value = 3},
|
||||||
{ 0, 0},
|
{ NULL, 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
|
static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
|
||||||
|
@ -2041,7 +2041,7 @@ static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
|
||||||
{.input = &tegra_pll_d_out0, .value = 1},
|
{.input = &tegra_pll_d_out0, .value = 1},
|
||||||
{.input = &tegra_pll_c, .value = 2},
|
{.input = &tegra_pll_c, .value = 2},
|
||||||
{.input = &tegra_clk_m, .value = 3},
|
{.input = &tegra_clk_m, .value = 3},
|
||||||
{ 0, 0},
|
{ NULL, 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
|
static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
|
||||||
|
@ -2050,39 +2050,39 @@ static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
|
||||||
{.input = &tegra_clk_audio, .value = 2},
|
{.input = &tegra_clk_audio, .value = 2},
|
||||||
{.input = &tegra_clk_m, .value = 3},
|
{.input = &tegra_clk_m, .value = 3},
|
||||||
{.input = &tegra_clk_32k, .value = 4},
|
{.input = &tegra_clk_32k, .value = 4},
|
||||||
{ 0, 0},
|
{ NULL, 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
|
static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
|
||||||
{.input = &tegra_pll_p, .value = 0},
|
{.input = &tegra_pll_p, .value = 0},
|
||||||
{.input = &tegra_pll_c, .value = 1},
|
{.input = &tegra_pll_c, .value = 1},
|
||||||
{.input = &tegra_pll_m, .value = 2},
|
{.input = &tegra_pll_m, .value = 2},
|
||||||
{ 0, 0},
|
{ NULL, 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk_mux_sel mux_clk_m[] = {
|
static struct clk_mux_sel mux_clk_m[] = {
|
||||||
{ .input = &tegra_clk_m, .value = 0},
|
{ .input = &tegra_clk_m, .value = 0},
|
||||||
{ 0, 0},
|
{ NULL, 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk_mux_sel mux_pllp_out3[] = {
|
static struct clk_mux_sel mux_pllp_out3[] = {
|
||||||
{ .input = &tegra_pll_p_out3, .value = 0},
|
{ .input = &tegra_pll_p_out3, .value = 0},
|
||||||
{ 0, 0},
|
{ NULL, 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk_mux_sel mux_plld[] = {
|
static struct clk_mux_sel mux_plld[] = {
|
||||||
{ .input = &tegra_pll_d, .value = 0},
|
{ .input = &tegra_pll_d, .value = 0},
|
||||||
{ 0, 0},
|
{ NULL, 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk_mux_sel mux_clk_32k[] = {
|
static struct clk_mux_sel mux_clk_32k[] = {
|
||||||
{ .input = &tegra_clk_32k, .value = 0},
|
{ .input = &tegra_clk_32k, .value = 0},
|
||||||
{ 0, 0},
|
{ NULL, 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk_mux_sel mux_pclk[] = {
|
static struct clk_mux_sel mux_pclk[] = {
|
||||||
{ .input = &tegra_clk_pclk, .value = 0},
|
{ .input = &tegra_clk_pclk, .value = 0},
|
||||||
{ 0, 0},
|
{ NULL, 0},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk tegra_clk_emc = {
|
static struct clk tegra_clk_emc = {
|
||||||
|
@ -2125,7 +2125,7 @@ static struct clk tegra_clk_emc = {
|
||||||
.parent = _parent, \
|
.parent = _parent, \
|
||||||
}
|
}
|
||||||
|
|
||||||
struct clk tegra_list_clks[] = {
|
static struct clk tegra_list_clks[] = {
|
||||||
PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 108000000, mux_pclk, 0),
|
PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 108000000, mux_pclk, 0),
|
||||||
PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
|
PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
|
||||||
PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
|
PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
|
||||||
|
@ -2221,7 +2221,7 @@ struct clk tegra_list_clks[] = {
|
||||||
* configuration. List those here to register them twice in the clock lookup
|
* configuration. List those here to register them twice in the clock lookup
|
||||||
* table under two names.
|
* table under two names.
|
||||||
*/
|
*/
|
||||||
struct clk_duplicate tegra_clk_duplicates[] = {
|
static struct clk_duplicate tegra_clk_duplicates[] = {
|
||||||
CLK_DUPLICATE("uarta", "tegra_uart.0", NULL),
|
CLK_DUPLICATE("uarta", "tegra_uart.0", NULL),
|
||||||
CLK_DUPLICATE("uartb", "tegra_uart.1", NULL),
|
CLK_DUPLICATE("uartb", "tegra_uart.1", NULL),
|
||||||
CLK_DUPLICATE("uartc", "tegra_uart.2", NULL),
|
CLK_DUPLICATE("uartc", "tegra_uart.2", NULL),
|
||||||
|
@ -2252,7 +2252,7 @@ struct clk_duplicate tegra_clk_duplicates[] = {
|
||||||
.clk = ck, \
|
.clk = ck, \
|
||||||
}
|
}
|
||||||
|
|
||||||
struct clk *tegra_ptr_clks[] = {
|
static struct clk *tegra_ptr_clks[] = {
|
||||||
&tegra_clk_32k,
|
&tegra_clk_32k,
|
||||||
&tegra_pll_s,
|
&tegra_pll_s,
|
||||||
&tegra_clk_m,
|
&tegra_clk_m,
|
||||||
|
|
|
@ -62,9 +62,9 @@ static struct timespec persistent_ts;
|
||||||
static u64 persistent_ms, last_persistent_ms;
|
static u64 persistent_ms, last_persistent_ms;
|
||||||
|
|
||||||
#define timer_writel(value, reg) \
|
#define timer_writel(value, reg) \
|
||||||
__raw_writel(value, (u32)timer_reg_base + (reg))
|
__raw_writel(value, timer_reg_base + (reg))
|
||||||
#define timer_readl(reg) \
|
#define timer_readl(reg) \
|
||||||
__raw_readl((u32)timer_reg_base + (reg))
|
__raw_readl(timer_reg_base + (reg))
|
||||||
|
|
||||||
static int tegra_timer_set_next_event(unsigned long cycles,
|
static int tegra_timer_set_next_event(unsigned long cycles,
|
||||||
struct clock_event_device *evt)
|
struct clock_event_device *evt)
|
||||||
|
@ -133,7 +133,7 @@ static void notrace tegra_update_sched_clock(void)
|
||||||
* tegra_rtc driver could be executing to avoid race conditions
|
* tegra_rtc driver could be executing to avoid race conditions
|
||||||
* on the RTC shadow register
|
* on the RTC shadow register
|
||||||
*/
|
*/
|
||||||
u64 tegra_rtc_read_ms(void)
|
static u64 tegra_rtc_read_ms(void)
|
||||||
{
|
{
|
||||||
u32 ms = readl(rtc_base + RTC_MILLISECONDS);
|
u32 ms = readl(rtc_base + RTC_MILLISECONDS);
|
||||||
u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
|
u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
|
||||||
|
|
|
@ -174,6 +174,10 @@ ENTRY(v7_coherent_user_range)
|
||||||
dcache_line_size r2, r3
|
dcache_line_size r2, r3
|
||||||
sub r3, r2, #1
|
sub r3, r2, #1
|
||||||
bic r12, r0, r3
|
bic r12, r0, r3
|
||||||
|
#ifdef CONFIG_ARM_ERRATA_764369
|
||||||
|
ALT_SMP(W(dsb))
|
||||||
|
ALT_UP(W(nop))
|
||||||
|
#endif
|
||||||
1:
|
1:
|
||||||
USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification
|
USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification
|
||||||
add r12, r12, r2
|
add r12, r12, r2
|
||||||
|
@ -223,6 +227,10 @@ ENTRY(v7_flush_kern_dcache_area)
|
||||||
add r1, r0, r1
|
add r1, r0, r1
|
||||||
sub r3, r2, #1
|
sub r3, r2, #1
|
||||||
bic r0, r0, r3
|
bic r0, r0, r3
|
||||||
|
#ifdef CONFIG_ARM_ERRATA_764369
|
||||||
|
ALT_SMP(W(dsb))
|
||||||
|
ALT_UP(W(nop))
|
||||||
|
#endif
|
||||||
1:
|
1:
|
||||||
mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
|
mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
|
||||||
add r0, r0, r2
|
add r0, r0, r2
|
||||||
|
@ -247,6 +255,10 @@ v7_dma_inv_range:
|
||||||
sub r3, r2, #1
|
sub r3, r2, #1
|
||||||
tst r0, r3
|
tst r0, r3
|
||||||
bic r0, r0, r3
|
bic r0, r0, r3
|
||||||
|
#ifdef CONFIG_ARM_ERRATA_764369
|
||||||
|
ALT_SMP(W(dsb))
|
||||||
|
ALT_UP(W(nop))
|
||||||
|
#endif
|
||||||
mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
|
mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
|
||||||
|
|
||||||
tst r1, r3
|
tst r1, r3
|
||||||
|
@ -270,6 +282,10 @@ v7_dma_clean_range:
|
||||||
dcache_line_size r2, r3
|
dcache_line_size r2, r3
|
||||||
sub r3, r2, #1
|
sub r3, r2, #1
|
||||||
bic r0, r0, r3
|
bic r0, r0, r3
|
||||||
|
#ifdef CONFIG_ARM_ERRATA_764369
|
||||||
|
ALT_SMP(W(dsb))
|
||||||
|
ALT_UP(W(nop))
|
||||||
|
#endif
|
||||||
1:
|
1:
|
||||||
mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
|
mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
|
||||||
add r0, r0, r2
|
add r0, r0, r2
|
||||||
|
@ -288,6 +304,10 @@ ENTRY(v7_dma_flush_range)
|
||||||
dcache_line_size r2, r3
|
dcache_line_size r2, r3
|
||||||
sub r3, r2, #1
|
sub r3, r2, #1
|
||||||
bic r0, r0, r3
|
bic r0, r0, r3
|
||||||
|
#ifdef CONFIG_ARM_ERRATA_764369
|
||||||
|
ALT_SMP(W(dsb))
|
||||||
|
ALT_UP(W(nop))
|
||||||
|
#endif
|
||||||
1:
|
1:
|
||||||
mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
|
mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
|
||||||
add r0, r0, r2
|
add r0, r0, r2
|
||||||
|
|
|
@ -347,6 +347,8 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
|
||||||
|
|
||||||
if (addr)
|
if (addr)
|
||||||
*handle = pfn_to_dma(dev, page_to_pfn(page));
|
*handle = pfn_to_dma(dev, page_to_pfn(page));
|
||||||
|
else
|
||||||
|
__dma_free_buffer(page, size);
|
||||||
|
|
||||||
return addr;
|
return addr;
|
||||||
}
|
}
|
||||||
|
|
|
@ -114,17 +114,18 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
|
||||||
{
|
{
|
||||||
static int used_gpioint_groups = 0;
|
static int used_gpioint_groups = 0;
|
||||||
int group = chip->group;
|
int group = chip->group;
|
||||||
struct s5p_gpioint_bank *bank = NULL;
|
struct s5p_gpioint_bank *b, *bank = NULL;
|
||||||
struct irq_chip_generic *gc;
|
struct irq_chip_generic *gc;
|
||||||
struct irq_chip_type *ct;
|
struct irq_chip_type *ct;
|
||||||
|
|
||||||
if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
|
if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
|
|
||||||
list_for_each_entry(bank, &banks, list) {
|
list_for_each_entry(b, &banks, list) {
|
||||||
if (group >= bank->start &&
|
if (group >= b->start && group < b->start + b->nr_groups) {
|
||||||
group < bank->start + bank->nr_groups)
|
bank = b;
|
||||||
break;
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
if (!bank)
|
if (!bank)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
|
@ -561,6 +561,20 @@ static struct pci_ops u4_pcie_pci_ops =
|
||||||
.write = u4_pcie_write_config,
|
.write = u4_pcie_write_config,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static void __devinit pmac_pci_fixup_u4_of_node(struct pci_dev *dev)
|
||||||
|
{
|
||||||
|
/* Apple's device-tree "hides" the root complex virtual P2P bridge
|
||||||
|
* on U4. However, Linux sees it, causing the PCI <-> OF matching
|
||||||
|
* code to fail to properly match devices below it. This works around
|
||||||
|
* it by setting the node of the bridge to point to the PHB node,
|
||||||
|
* which is not entirely correct but fixes the matching code and
|
||||||
|
* doesn't break anything else. It's also the simplest possible fix.
|
||||||
|
*/
|
||||||
|
if (dev->dev.of_node == NULL)
|
||||||
|
dev->dev.of_node = pcibios_get_phb_of_node(dev->bus);
|
||||||
|
}
|
||||||
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, 0x5b, pmac_pci_fixup_u4_of_node);
|
||||||
|
|
||||||
#endif /* CONFIG_PPC64 */
|
#endif /* CONFIG_PPC64 */
|
||||||
|
|
||||||
#ifdef CONFIG_PPC32
|
#ifdef CONFIG_PPC32
|
||||||
|
|
|
@ -188,7 +188,8 @@ extern char elf_platform[];
|
||||||
#define SET_PERSONALITY(ex) \
|
#define SET_PERSONALITY(ex) \
|
||||||
do { \
|
do { \
|
||||||
if (personality(current->personality) != PER_LINUX32) \
|
if (personality(current->personality) != PER_LINUX32) \
|
||||||
set_personality(PER_LINUX); \
|
set_personality(PER_LINUX | \
|
||||||
|
(current->personality & ~PER_MASK)); \
|
||||||
if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
|
if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
|
||||||
set_thread_flag(TIF_31BIT); \
|
set_thread_flag(TIF_31BIT); \
|
||||||
else \
|
else \
|
||||||
|
|
|
@ -658,12 +658,14 @@ static inline void pgste_set_pte(pte_t *ptep, pgste_t pgste)
|
||||||
* struct gmap_struct - guest address space
|
* struct gmap_struct - guest address space
|
||||||
* @mm: pointer to the parent mm_struct
|
* @mm: pointer to the parent mm_struct
|
||||||
* @table: pointer to the page directory
|
* @table: pointer to the page directory
|
||||||
|
* @asce: address space control element for gmap page table
|
||||||
* @crst_list: list of all crst tables used in the guest address space
|
* @crst_list: list of all crst tables used in the guest address space
|
||||||
*/
|
*/
|
||||||
struct gmap {
|
struct gmap {
|
||||||
struct list_head list;
|
struct list_head list;
|
||||||
struct mm_struct *mm;
|
struct mm_struct *mm;
|
||||||
unsigned long *table;
|
unsigned long *table;
|
||||||
|
unsigned long asce;
|
||||||
struct list_head crst_list;
|
struct list_head crst_list;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -10,6 +10,7 @@
|
||||||
#include <linux/sched.h>
|
#include <linux/sched.h>
|
||||||
#include <asm/vdso.h>
|
#include <asm/vdso.h>
|
||||||
#include <asm/sigp.h>
|
#include <asm/sigp.h>
|
||||||
|
#include <asm/pgtable.h>
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Make sure that the compiler is new enough. We want a compiler that
|
* Make sure that the compiler is new enough. We want a compiler that
|
||||||
|
@ -126,6 +127,7 @@ int main(void)
|
||||||
DEFINE(__LC_KERNEL_STACK, offsetof(struct _lowcore, kernel_stack));
|
DEFINE(__LC_KERNEL_STACK, offsetof(struct _lowcore, kernel_stack));
|
||||||
DEFINE(__LC_ASYNC_STACK, offsetof(struct _lowcore, async_stack));
|
DEFINE(__LC_ASYNC_STACK, offsetof(struct _lowcore, async_stack));
|
||||||
DEFINE(__LC_PANIC_STACK, offsetof(struct _lowcore, panic_stack));
|
DEFINE(__LC_PANIC_STACK, offsetof(struct _lowcore, panic_stack));
|
||||||
|
DEFINE(__LC_USER_ASCE, offsetof(struct _lowcore, user_asce));
|
||||||
DEFINE(__LC_INT_CLOCK, offsetof(struct _lowcore, int_clock));
|
DEFINE(__LC_INT_CLOCK, offsetof(struct _lowcore, int_clock));
|
||||||
DEFINE(__LC_MCCK_CLOCK, offsetof(struct _lowcore, mcck_clock));
|
DEFINE(__LC_MCCK_CLOCK, offsetof(struct _lowcore, mcck_clock));
|
||||||
DEFINE(__LC_MACHINE_FLAGS, offsetof(struct _lowcore, machine_flags));
|
DEFINE(__LC_MACHINE_FLAGS, offsetof(struct _lowcore, machine_flags));
|
||||||
|
@ -151,6 +153,7 @@ int main(void)
|
||||||
DEFINE(__LC_VDSO_PER_CPU, offsetof(struct _lowcore, vdso_per_cpu_data));
|
DEFINE(__LC_VDSO_PER_CPU, offsetof(struct _lowcore, vdso_per_cpu_data));
|
||||||
DEFINE(__LC_GMAP, offsetof(struct _lowcore, gmap));
|
DEFINE(__LC_GMAP, offsetof(struct _lowcore, gmap));
|
||||||
DEFINE(__LC_CMF_HPP, offsetof(struct _lowcore, cmf_hpp));
|
DEFINE(__LC_CMF_HPP, offsetof(struct _lowcore, cmf_hpp));
|
||||||
|
DEFINE(__GMAP_ASCE, offsetof(struct gmap, asce));
|
||||||
#endif /* CONFIG_32BIT */
|
#endif /* CONFIG_32BIT */
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
@ -1076,6 +1076,11 @@ sie_loop:
|
||||||
lg %r14,__LC_THREAD_INFO # pointer thread_info struct
|
lg %r14,__LC_THREAD_INFO # pointer thread_info struct
|
||||||
tm __TI_flags+7(%r14),_TIF_EXIT_SIE
|
tm __TI_flags+7(%r14),_TIF_EXIT_SIE
|
||||||
jnz sie_exit
|
jnz sie_exit
|
||||||
|
lg %r14,__LC_GMAP # get gmap pointer
|
||||||
|
ltgr %r14,%r14
|
||||||
|
jz sie_gmap
|
||||||
|
lctlg %c1,%c1,__GMAP_ASCE(%r14) # load primary asce
|
||||||
|
sie_gmap:
|
||||||
lg %r14,__SF_EMPTY(%r15) # get control block pointer
|
lg %r14,__SF_EMPTY(%r15) # get control block pointer
|
||||||
SPP __SF_EMPTY(%r15) # set guest id
|
SPP __SF_EMPTY(%r15) # set guest id
|
||||||
sie 0(%r14)
|
sie 0(%r14)
|
||||||
|
@ -1083,6 +1088,7 @@ sie_done:
|
||||||
SPP __LC_CMF_HPP # set host id
|
SPP __LC_CMF_HPP # set host id
|
||||||
lg %r14,__LC_THREAD_INFO # pointer thread_info struct
|
lg %r14,__LC_THREAD_INFO # pointer thread_info struct
|
||||||
sie_exit:
|
sie_exit:
|
||||||
|
lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
|
||||||
ni __TI_flags+6(%r14),255-(_TIF_SIE>>8)
|
ni __TI_flags+6(%r14),255-(_TIF_SIE>>8)
|
||||||
lg %r14,__SF_EMPTY+8(%r15) # load guest register save area
|
lg %r14,__SF_EMPTY+8(%r15) # load guest register save area
|
||||||
stmg %r0,%r13,0(%r14) # save guest gprs 0-13
|
stmg %r0,%r13,0(%r14) # save guest gprs 0-13
|
||||||
|
|
|
@ -123,6 +123,7 @@ int kvm_dev_ioctl_check_extension(long ext)
|
||||||
|
|
||||||
switch (ext) {
|
switch (ext) {
|
||||||
case KVM_CAP_S390_PSW:
|
case KVM_CAP_S390_PSW:
|
||||||
|
case KVM_CAP_S390_GMAP:
|
||||||
r = 1;
|
r = 1;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
|
@ -263,10 +264,12 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
|
||||||
vcpu->arch.guest_fpregs.fpc &= FPC_VALID_MASK;
|
vcpu->arch.guest_fpregs.fpc &= FPC_VALID_MASK;
|
||||||
restore_fp_regs(&vcpu->arch.guest_fpregs);
|
restore_fp_regs(&vcpu->arch.guest_fpregs);
|
||||||
restore_access_regs(vcpu->arch.guest_acrs);
|
restore_access_regs(vcpu->arch.guest_acrs);
|
||||||
|
gmap_enable(vcpu->arch.gmap);
|
||||||
}
|
}
|
||||||
|
|
||||||
void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
|
void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
|
||||||
{
|
{
|
||||||
|
gmap_disable(vcpu->arch.gmap);
|
||||||
save_fp_regs(&vcpu->arch.guest_fpregs);
|
save_fp_regs(&vcpu->arch.guest_fpregs);
|
||||||
save_access_regs(vcpu->arch.guest_acrs);
|
save_access_regs(vcpu->arch.guest_acrs);
|
||||||
restore_fp_regs(&vcpu->arch.host_fpregs);
|
restore_fp_regs(&vcpu->arch.host_fpregs);
|
||||||
|
@ -461,7 +464,6 @@ static void __vcpu_run(struct kvm_vcpu *vcpu)
|
||||||
local_irq_disable();
|
local_irq_disable();
|
||||||
kvm_guest_enter();
|
kvm_guest_enter();
|
||||||
local_irq_enable();
|
local_irq_enable();
|
||||||
gmap_enable(vcpu->arch.gmap);
|
|
||||||
VCPU_EVENT(vcpu, 6, "entering sie flags %x",
|
VCPU_EVENT(vcpu, 6, "entering sie flags %x",
|
||||||
atomic_read(&vcpu->arch.sie_block->cpuflags));
|
atomic_read(&vcpu->arch.sie_block->cpuflags));
|
||||||
if (sie64a(vcpu->arch.sie_block, vcpu->arch.guest_gprs)) {
|
if (sie64a(vcpu->arch.sie_block, vcpu->arch.guest_gprs)) {
|
||||||
|
@ -470,7 +472,6 @@ static void __vcpu_run(struct kvm_vcpu *vcpu)
|
||||||
}
|
}
|
||||||
VCPU_EVENT(vcpu, 6, "exit sie icptcode %d",
|
VCPU_EVENT(vcpu, 6, "exit sie icptcode %d",
|
||||||
vcpu->arch.sie_block->icptcode);
|
vcpu->arch.sie_block->icptcode);
|
||||||
gmap_disable(vcpu->arch.gmap);
|
|
||||||
local_irq_disable();
|
local_irq_disable();
|
||||||
kvm_guest_exit();
|
kvm_guest_exit();
|
||||||
local_irq_enable();
|
local_irq_enable();
|
||||||
|
|
|
@ -160,6 +160,8 @@ struct gmap *gmap_alloc(struct mm_struct *mm)
|
||||||
table = (unsigned long *) page_to_phys(page);
|
table = (unsigned long *) page_to_phys(page);
|
||||||
crst_table_init(table, _REGION1_ENTRY_EMPTY);
|
crst_table_init(table, _REGION1_ENTRY_EMPTY);
|
||||||
gmap->table = table;
|
gmap->table = table;
|
||||||
|
gmap->asce = _ASCE_TYPE_REGION1 | _ASCE_TABLE_LENGTH |
|
||||||
|
_ASCE_USER_BITS | __pa(table);
|
||||||
list_add(&gmap->list, &mm->context.gmap_list);
|
list_add(&gmap->list, &mm->context.gmap_list);
|
||||||
return gmap;
|
return gmap;
|
||||||
|
|
||||||
|
@ -240,10 +242,6 @@ EXPORT_SYMBOL_GPL(gmap_free);
|
||||||
*/
|
*/
|
||||||
void gmap_enable(struct gmap *gmap)
|
void gmap_enable(struct gmap *gmap)
|
||||||
{
|
{
|
||||||
/* Load primary space page table origin. */
|
|
||||||
S390_lowcore.user_asce = _ASCE_TYPE_REGION1 | _ASCE_TABLE_LENGTH |
|
|
||||||
_ASCE_USER_BITS | __pa(gmap->table);
|
|
||||||
asm volatile("lctlg 1,1,%0\n" : : "m" (S390_lowcore.user_asce) );
|
|
||||||
S390_lowcore.gmap = (unsigned long) gmap;
|
S390_lowcore.gmap = (unsigned long) gmap;
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL_GPL(gmap_enable);
|
EXPORT_SYMBOL_GPL(gmap_enable);
|
||||||
|
@ -254,10 +252,6 @@ EXPORT_SYMBOL_GPL(gmap_enable);
|
||||||
*/
|
*/
|
||||||
void gmap_disable(struct gmap *gmap)
|
void gmap_disable(struct gmap *gmap)
|
||||||
{
|
{
|
||||||
/* Load primary space page table origin. */
|
|
||||||
S390_lowcore.user_asce =
|
|
||||||
gmap->mm->context.asce_bits | __pa(gmap->mm->pgd);
|
|
||||||
asm volatile("lctlg 1,1,%0\n" : : "m" (S390_lowcore.user_asce) );
|
|
||||||
S390_lowcore.gmap = 0UL;
|
S390_lowcore.gmap = 0UL;
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL_GPL(gmap_disable);
|
EXPORT_SYMBOL_GPL(gmap_disable);
|
||||||
|
@ -309,15 +303,15 @@ int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len)
|
||||||
/* Walk the guest addr space page table */
|
/* Walk the guest addr space page table */
|
||||||
table = gmap->table + (((to + off) >> 53) & 0x7ff);
|
table = gmap->table + (((to + off) >> 53) & 0x7ff);
|
||||||
if (*table & _REGION_ENTRY_INV)
|
if (*table & _REGION_ENTRY_INV)
|
||||||
return 0;
|
goto out;
|
||||||
table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
|
table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
|
||||||
table = table + (((to + off) >> 42) & 0x7ff);
|
table = table + (((to + off) >> 42) & 0x7ff);
|
||||||
if (*table & _REGION_ENTRY_INV)
|
if (*table & _REGION_ENTRY_INV)
|
||||||
return 0;
|
goto out;
|
||||||
table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
|
table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
|
||||||
table = table + (((to + off) >> 31) & 0x7ff);
|
table = table + (((to + off) >> 31) & 0x7ff);
|
||||||
if (*table & _REGION_ENTRY_INV)
|
if (*table & _REGION_ENTRY_INV)
|
||||||
return 0;
|
goto out;
|
||||||
table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
|
table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
|
||||||
table = table + (((to + off) >> 20) & 0x7ff);
|
table = table + (((to + off) >> 20) & 0x7ff);
|
||||||
|
|
||||||
|
@ -325,6 +319,7 @@ int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len)
|
||||||
flush |= gmap_unlink_segment(gmap, table);
|
flush |= gmap_unlink_segment(gmap, table);
|
||||||
*table = _SEGMENT_ENTRY_INV;
|
*table = _SEGMENT_ENTRY_INV;
|
||||||
}
|
}
|
||||||
|
out:
|
||||||
up_read(&gmap->mm->mmap_sem);
|
up_read(&gmap->mm->mmap_sem);
|
||||||
if (flush)
|
if (flush)
|
||||||
gmap_flush_tlb(gmap);
|
gmap_flush_tlb(gmap);
|
||||||
|
|
|
@ -43,6 +43,8 @@
|
||||||
#define SUN4V_CHIP_NIAGARA1 0x01
|
#define SUN4V_CHIP_NIAGARA1 0x01
|
||||||
#define SUN4V_CHIP_NIAGARA2 0x02
|
#define SUN4V_CHIP_NIAGARA2 0x02
|
||||||
#define SUN4V_CHIP_NIAGARA3 0x03
|
#define SUN4V_CHIP_NIAGARA3 0x03
|
||||||
|
#define SUN4V_CHIP_NIAGARA4 0x04
|
||||||
|
#define SUN4V_CHIP_NIAGARA5 0x05
|
||||||
#define SUN4V_CHIP_UNKNOWN 0xff
|
#define SUN4V_CHIP_UNKNOWN 0xff
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
#ifndef __ASSEMBLY__
|
||||||
|
|
|
@ -66,6 +66,8 @@ static struct xor_block_template xor_block_niagara = {
|
||||||
((tlb_type == hypervisor && \
|
((tlb_type == hypervisor && \
|
||||||
(sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \
|
(sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \
|
||||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || \
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || \
|
||||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA3)) ? \
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || \
|
||||||
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || \
|
||||||
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)) ? \
|
||||||
&xor_block_niagara : \
|
&xor_block_niagara : \
|
||||||
&xor_block_VIS)
|
&xor_block_VIS)
|
||||||
|
|
|
@ -481,6 +481,18 @@ static void __init sun4v_cpu_probe(void)
|
||||||
sparc_pmu_type = "niagara3";
|
sparc_pmu_type = "niagara3";
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
case SUN4V_CHIP_NIAGARA4:
|
||||||
|
sparc_cpu_type = "UltraSparc T4 (Niagara4)";
|
||||||
|
sparc_fpu_type = "UltraSparc T4 integrated FPU";
|
||||||
|
sparc_pmu_type = "niagara4";
|
||||||
|
break;
|
||||||
|
|
||||||
|
case SUN4V_CHIP_NIAGARA5:
|
||||||
|
sparc_cpu_type = "UltraSparc T5 (Niagara5)";
|
||||||
|
sparc_fpu_type = "UltraSparc T5 integrated FPU";
|
||||||
|
sparc_pmu_type = "niagara5";
|
||||||
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
|
printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
|
||||||
prom_cpu_compatible);
|
prom_cpu_compatible);
|
||||||
|
|
|
@ -325,6 +325,8 @@ static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index)
|
||||||
case SUN4V_CHIP_NIAGARA1:
|
case SUN4V_CHIP_NIAGARA1:
|
||||||
case SUN4V_CHIP_NIAGARA2:
|
case SUN4V_CHIP_NIAGARA2:
|
||||||
case SUN4V_CHIP_NIAGARA3:
|
case SUN4V_CHIP_NIAGARA3:
|
||||||
|
case SUN4V_CHIP_NIAGARA4:
|
||||||
|
case SUN4V_CHIP_NIAGARA5:
|
||||||
rover_inc_table = niagara_iterate_method;
|
rover_inc_table = niagara_iterate_method;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
|
|
|
@ -133,7 +133,7 @@ prom_sun4v_name:
|
||||||
prom_niagara_prefix:
|
prom_niagara_prefix:
|
||||||
.asciz "SUNW,UltraSPARC-T"
|
.asciz "SUNW,UltraSPARC-T"
|
||||||
prom_sparc_prefix:
|
prom_sparc_prefix:
|
||||||
.asciz "SPARC-T"
|
.asciz "SPARC-"
|
||||||
.align 4
|
.align 4
|
||||||
prom_root_compatible:
|
prom_root_compatible:
|
||||||
.skip 64
|
.skip 64
|
||||||
|
@ -396,7 +396,7 @@ sun4v_chip_type:
|
||||||
or %g1, %lo(prom_cpu_compatible), %g1
|
or %g1, %lo(prom_cpu_compatible), %g1
|
||||||
sethi %hi(prom_sparc_prefix), %g7
|
sethi %hi(prom_sparc_prefix), %g7
|
||||||
or %g7, %lo(prom_sparc_prefix), %g7
|
or %g7, %lo(prom_sparc_prefix), %g7
|
||||||
mov 7, %g3
|
mov 6, %g3
|
||||||
90: ldub [%g7], %g2
|
90: ldub [%g7], %g2
|
||||||
ldub [%g1], %g4
|
ldub [%g1], %g4
|
||||||
cmp %g2, %g4
|
cmp %g2, %g4
|
||||||
|
@ -408,10 +408,23 @@ sun4v_chip_type:
|
||||||
|
|
||||||
sethi %hi(prom_cpu_compatible), %g1
|
sethi %hi(prom_cpu_compatible), %g1
|
||||||
or %g1, %lo(prom_cpu_compatible), %g1
|
or %g1, %lo(prom_cpu_compatible), %g1
|
||||||
ldub [%g1 + 7], %g2
|
ldub [%g1 + 6], %g2
|
||||||
|
cmp %g2, 'T'
|
||||||
|
be,pt %xcc, 70f
|
||||||
|
cmp %g2, 'M'
|
||||||
|
bne,pn %xcc, 4f
|
||||||
|
nop
|
||||||
|
|
||||||
|
70: ldub [%g1 + 7], %g2
|
||||||
cmp %g2, '3'
|
cmp %g2, '3'
|
||||||
be,pt %xcc, 5f
|
be,pt %xcc, 5f
|
||||||
mov SUN4V_CHIP_NIAGARA3, %g4
|
mov SUN4V_CHIP_NIAGARA3, %g4
|
||||||
|
cmp %g2, '4'
|
||||||
|
be,pt %xcc, 5f
|
||||||
|
mov SUN4V_CHIP_NIAGARA4, %g4
|
||||||
|
cmp %g2, '5'
|
||||||
|
be,pt %xcc, 5f
|
||||||
|
mov SUN4V_CHIP_NIAGARA5, %g4
|
||||||
ba,pt %xcc, 4f
|
ba,pt %xcc, 4f
|
||||||
nop
|
nop
|
||||||
|
|
||||||
|
@ -543,6 +556,12 @@ niagara_tlb_fixup:
|
||||||
be,pt %xcc, niagara2_patch
|
be,pt %xcc, niagara2_patch
|
||||||
nop
|
nop
|
||||||
cmp %g1, SUN4V_CHIP_NIAGARA3
|
cmp %g1, SUN4V_CHIP_NIAGARA3
|
||||||
|
be,pt %xcc, niagara2_patch
|
||||||
|
nop
|
||||||
|
cmp %g1, SUN4V_CHIP_NIAGARA4
|
||||||
|
be,pt %xcc, niagara2_patch
|
||||||
|
nop
|
||||||
|
cmp %g1, SUN4V_CHIP_NIAGARA5
|
||||||
be,pt %xcc, niagara2_patch
|
be,pt %xcc, niagara2_patch
|
||||||
nop
|
nop
|
||||||
|
|
||||||
|
|
|
@ -380,8 +380,7 @@ void flush_thread(void)
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Now, this task is no longer a kernel thread. */
|
/* This task is no longer a kernel thread. */
|
||||||
current->thread.current_ds = USER_DS;
|
|
||||||
if (current->thread.flags & SPARC_FLAG_KTHREAD) {
|
if (current->thread.flags & SPARC_FLAG_KTHREAD) {
|
||||||
current->thread.flags &= ~SPARC_FLAG_KTHREAD;
|
current->thread.flags &= ~SPARC_FLAG_KTHREAD;
|
||||||
|
|
||||||
|
|
|
@ -368,9 +368,6 @@ void flush_thread(void)
|
||||||
|
|
||||||
/* Clear FPU register state. */
|
/* Clear FPU register state. */
|
||||||
t->fpsaved[0] = 0;
|
t->fpsaved[0] = 0;
|
||||||
|
|
||||||
if (get_thread_current_ds() != ASI_AIUS)
|
|
||||||
set_fs(USER_DS);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* It's a bit more tricky when 64-bit tasks are involved... */
|
/* It's a bit more tricky when 64-bit tasks are involved... */
|
||||||
|
|
|
@ -137,7 +137,7 @@ static void __init process_switch(char c)
|
||||||
prom_halt();
|
prom_halt();
|
||||||
break;
|
break;
|
||||||
case 'p':
|
case 'p':
|
||||||
/* Just ignore, this behavior is now the default. */
|
prom_early_console.flags &= ~CON_BOOT;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
printk("Unknown boot switch (-%c)\n", c);
|
printk("Unknown boot switch (-%c)\n", c);
|
||||||
|
|
|
@ -106,7 +106,7 @@ static void __init process_switch(char c)
|
||||||
prom_halt();
|
prom_halt();
|
||||||
break;
|
break;
|
||||||
case 'p':
|
case 'p':
|
||||||
/* Just ignore, this behavior is now the default. */
|
prom_early_console.flags &= ~CON_BOOT;
|
||||||
break;
|
break;
|
||||||
case 'P':
|
case 'P':
|
||||||
/* Force UltraSPARC-III P-Cache on. */
|
/* Force UltraSPARC-III P-Cache on. */
|
||||||
|
@ -425,10 +425,14 @@ static void __init init_sparc64_elf_hwcap(void)
|
||||||
else if (tlb_type == hypervisor) {
|
else if (tlb_type == hypervisor) {
|
||||||
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
|
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
|
||||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
|
||||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
|
||||||
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
|
||||||
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
|
||||||
cap |= HWCAP_SPARC_BLKINIT;
|
cap |= HWCAP_SPARC_BLKINIT;
|
||||||
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
|
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
|
||||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
|
||||||
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
|
||||||
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
|
||||||
cap |= HWCAP_SPARC_N2;
|
cap |= HWCAP_SPARC_N2;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -452,11 +456,15 @@ static void __init init_sparc64_elf_hwcap(void)
|
||||||
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
|
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
|
||||||
cap |= AV_SPARC_ASI_BLK_INIT;
|
cap |= AV_SPARC_ASI_BLK_INIT;
|
||||||
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
|
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
|
||||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
|
||||||
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
|
||||||
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
|
||||||
cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
|
cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
|
||||||
AV_SPARC_ASI_BLK_INIT |
|
AV_SPARC_ASI_BLK_INIT |
|
||||||
AV_SPARC_POPC);
|
AV_SPARC_POPC);
|
||||||
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
|
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
|
||||||
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
|
||||||
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
|
||||||
cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
|
cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
|
||||||
AV_SPARC_FMAF);
|
AV_SPARC_FMAF);
|
||||||
}
|
}
|
||||||
|
|
|
@ -511,6 +511,11 @@ static void __init read_obp_translations(void)
|
||||||
for (i = 0; i < prom_trans_ents; i++)
|
for (i = 0; i < prom_trans_ents; i++)
|
||||||
prom_trans[i].data &= ~0x0003fe0000000000UL;
|
prom_trans[i].data &= ~0x0003fe0000000000UL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* Force execute bit on. */
|
||||||
|
for (i = 0; i < prom_trans_ents; i++)
|
||||||
|
prom_trans[i].data |= (tlb_type == hypervisor ?
|
||||||
|
_PAGE_EXEC_4V : _PAGE_EXEC_4U);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void __init hypervisor_tlb_lock(unsigned long vaddr,
|
static void __init hypervisor_tlb_lock(unsigned long vaddr,
|
||||||
|
|
|
@ -42,8 +42,11 @@ int mach_set_rtc_mmss(unsigned long nowtime)
|
||||||
{
|
{
|
||||||
int real_seconds, real_minutes, cmos_minutes;
|
int real_seconds, real_minutes, cmos_minutes;
|
||||||
unsigned char save_control, save_freq_select;
|
unsigned char save_control, save_freq_select;
|
||||||
|
unsigned long flags;
|
||||||
int retval = 0;
|
int retval = 0;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&rtc_lock, flags);
|
||||||
|
|
||||||
/* tell the clock it's being set */
|
/* tell the clock it's being set */
|
||||||
save_control = CMOS_READ(RTC_CONTROL);
|
save_control = CMOS_READ(RTC_CONTROL);
|
||||||
CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
|
CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
|
||||||
|
@ -93,12 +96,17 @@ int mach_set_rtc_mmss(unsigned long nowtime)
|
||||||
CMOS_WRITE(save_control, RTC_CONTROL);
|
CMOS_WRITE(save_control, RTC_CONTROL);
|
||||||
CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
|
CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
|
||||||
|
|
||||||
|
spin_unlock_irqrestore(&rtc_lock, flags);
|
||||||
|
|
||||||
return retval;
|
return retval;
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned long mach_get_cmos_time(void)
|
unsigned long mach_get_cmos_time(void)
|
||||||
{
|
{
|
||||||
unsigned int status, year, mon, day, hour, min, sec, century = 0;
|
unsigned int status, year, mon, day, hour, min, sec, century = 0;
|
||||||
|
unsigned long flags;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&rtc_lock, flags);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* If UIP is clear, then we have >= 244 microseconds before
|
* If UIP is clear, then we have >= 244 microseconds before
|
||||||
|
@ -125,6 +133,8 @@ unsigned long mach_get_cmos_time(void)
|
||||||
status = CMOS_READ(RTC_CONTROL);
|
status = CMOS_READ(RTC_CONTROL);
|
||||||
WARN_ON_ONCE(RTC_ALWAYS_BCD && (status & RTC_DM_BINARY));
|
WARN_ON_ONCE(RTC_ALWAYS_BCD && (status & RTC_DM_BINARY));
|
||||||
|
|
||||||
|
spin_unlock_irqrestore(&rtc_lock, flags);
|
||||||
|
|
||||||
if (RTC_ALWAYS_BCD || !(status & RTC_DM_BINARY)) {
|
if (RTC_ALWAYS_BCD || !(status & RTC_DM_BINARY)) {
|
||||||
sec = bcd2bin(sec);
|
sec = bcd2bin(sec);
|
||||||
min = bcd2bin(min);
|
min = bcd2bin(min);
|
||||||
|
@ -169,24 +179,15 @@ EXPORT_SYMBOL(rtc_cmos_write);
|
||||||
|
|
||||||
int update_persistent_clock(struct timespec now)
|
int update_persistent_clock(struct timespec now)
|
||||||
{
|
{
|
||||||
unsigned long flags;
|
return x86_platform.set_wallclock(now.tv_sec);
|
||||||
int retval;
|
|
||||||
|
|
||||||
spin_lock_irqsave(&rtc_lock, flags);
|
|
||||||
retval = x86_platform.set_wallclock(now.tv_sec);
|
|
||||||
spin_unlock_irqrestore(&rtc_lock, flags);
|
|
||||||
|
|
||||||
return retval;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* not static: needed by APM */
|
/* not static: needed by APM */
|
||||||
void read_persistent_clock(struct timespec *ts)
|
void read_persistent_clock(struct timespec *ts)
|
||||||
{
|
{
|
||||||
unsigned long retval, flags;
|
unsigned long retval;
|
||||||
|
|
||||||
spin_lock_irqsave(&rtc_lock, flags);
|
|
||||||
retval = x86_platform.get_wallclock();
|
retval = x86_platform.get_wallclock();
|
||||||
spin_unlock_irqrestore(&rtc_lock, flags);
|
|
||||||
|
|
||||||
ts->tv_sec = retval;
|
ts->tv_sec = retval;
|
||||||
ts->tv_nsec = 0;
|
ts->tv_nsec = 0;
|
||||||
|
|
|
@ -3603,7 +3603,7 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
|
||||||
break;
|
break;
|
||||||
case Src2CL:
|
case Src2CL:
|
||||||
ctxt->src2.bytes = 1;
|
ctxt->src2.bytes = 1;
|
||||||
ctxt->src2.val = ctxt->regs[VCPU_REGS_RCX] & 0x8;
|
ctxt->src2.val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
|
||||||
break;
|
break;
|
||||||
case Src2ImmByte:
|
case Src2ImmByte:
|
||||||
rc = decode_imm(ctxt, &ctxt->src2, 1, true);
|
rc = decode_imm(ctxt, &ctxt->src2, 1, true);
|
||||||
|
|
|
@ -400,7 +400,8 @@ static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
|
||||||
|
|
||||||
/* xchg acts as a barrier before the setting of the high bits */
|
/* xchg acts as a barrier before the setting of the high bits */
|
||||||
orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
|
orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
|
||||||
orig.spte_high = ssptep->spte_high = sspte.spte_high;
|
orig.spte_high = ssptep->spte_high;
|
||||||
|
ssptep->spte_high = sspte.spte_high;
|
||||||
count_spte_clear(sptep, spte);
|
count_spte_clear(sptep, spte);
|
||||||
|
|
||||||
return orig.spte;
|
return orig.spte;
|
||||||
|
|
|
@ -58,8 +58,11 @@ EXPORT_SYMBOL_GPL(vrtc_cmos_write);
|
||||||
unsigned long vrtc_get_time(void)
|
unsigned long vrtc_get_time(void)
|
||||||
{
|
{
|
||||||
u8 sec, min, hour, mday, mon;
|
u8 sec, min, hour, mday, mon;
|
||||||
|
unsigned long flags;
|
||||||
u32 year;
|
u32 year;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&rtc_lock, flags);
|
||||||
|
|
||||||
while ((vrtc_cmos_read(RTC_FREQ_SELECT) & RTC_UIP))
|
while ((vrtc_cmos_read(RTC_FREQ_SELECT) & RTC_UIP))
|
||||||
cpu_relax();
|
cpu_relax();
|
||||||
|
|
||||||
|
@ -70,6 +73,8 @@ unsigned long vrtc_get_time(void)
|
||||||
mon = vrtc_cmos_read(RTC_MONTH);
|
mon = vrtc_cmos_read(RTC_MONTH);
|
||||||
year = vrtc_cmos_read(RTC_YEAR);
|
year = vrtc_cmos_read(RTC_YEAR);
|
||||||
|
|
||||||
|
spin_unlock_irqrestore(&rtc_lock, flags);
|
||||||
|
|
||||||
/* vRTC YEAR reg contains the offset to 1960 */
|
/* vRTC YEAR reg contains the offset to 1960 */
|
||||||
year += 1960;
|
year += 1960;
|
||||||
|
|
||||||
|
@ -83,8 +88,10 @@ unsigned long vrtc_get_time(void)
|
||||||
int vrtc_set_mmss(unsigned long nowtime)
|
int vrtc_set_mmss(unsigned long nowtime)
|
||||||
{
|
{
|
||||||
int real_sec, real_min;
|
int real_sec, real_min;
|
||||||
|
unsigned long flags;
|
||||||
int vrtc_min;
|
int vrtc_min;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&rtc_lock, flags);
|
||||||
vrtc_min = vrtc_cmos_read(RTC_MINUTES);
|
vrtc_min = vrtc_cmos_read(RTC_MINUTES);
|
||||||
|
|
||||||
real_sec = nowtime % 60;
|
real_sec = nowtime % 60;
|
||||||
|
@ -95,6 +102,8 @@ int vrtc_set_mmss(unsigned long nowtime)
|
||||||
|
|
||||||
vrtc_cmos_write(real_sec, RTC_SECONDS);
|
vrtc_cmos_write(real_sec, RTC_SECONDS);
|
||||||
vrtc_cmos_write(real_min, RTC_MINUTES);
|
vrtc_cmos_write(real_min, RTC_MINUTES);
|
||||||
|
spin_unlock_irqrestore(&rtc_lock, flags);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -348,9 +348,10 @@ void blk_put_queue(struct request_queue *q)
|
||||||
EXPORT_SYMBOL(blk_put_queue);
|
EXPORT_SYMBOL(blk_put_queue);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Note: If a driver supplied the queue lock, it should not zap that lock
|
* Note: If a driver supplied the queue lock, it is disconnected
|
||||||
* unexpectedly as some queue cleanup components like elevator_exit() and
|
* by this function. The actual state of the lock doesn't matter
|
||||||
* blk_throtl_exit() need queue lock.
|
* here as the request_queue isn't accessible after this point
|
||||||
|
* (QUEUE_FLAG_DEAD is set) and no other requests will be queued.
|
||||||
*/
|
*/
|
||||||
void blk_cleanup_queue(struct request_queue *q)
|
void blk_cleanup_queue(struct request_queue *q)
|
||||||
{
|
{
|
||||||
|
@ -367,10 +368,8 @@ void blk_cleanup_queue(struct request_queue *q)
|
||||||
queue_flag_set_unlocked(QUEUE_FLAG_DEAD, q);
|
queue_flag_set_unlocked(QUEUE_FLAG_DEAD, q);
|
||||||
mutex_unlock(&q->sysfs_lock);
|
mutex_unlock(&q->sysfs_lock);
|
||||||
|
|
||||||
if (q->elevator)
|
if (q->queue_lock != &q->__queue_lock)
|
||||||
elevator_exit(q->elevator);
|
q->queue_lock = &q->__queue_lock;
|
||||||
|
|
||||||
blk_throtl_exit(q);
|
|
||||||
|
|
||||||
blk_put_queue(q);
|
blk_put_queue(q);
|
||||||
}
|
}
|
||||||
|
|
|
@ -479,6 +479,11 @@ static void blk_release_queue(struct kobject *kobj)
|
||||||
|
|
||||||
blk_sync_queue(q);
|
blk_sync_queue(q);
|
||||||
|
|
||||||
|
if (q->elevator)
|
||||||
|
elevator_exit(q->elevator);
|
||||||
|
|
||||||
|
blk_throtl_exit(q);
|
||||||
|
|
||||||
if (rl->rq_pool)
|
if (rl->rq_pool)
|
||||||
mempool_destroy(rl->rq_pool);
|
mempool_destroy(rl->rq_pool);
|
||||||
|
|
||||||
|
|
|
@ -41,6 +41,22 @@ static struct pm_clk_data *__to_pcd(struct device *dev)
|
||||||
return dev ? dev->power.subsys_data : NULL;
|
return dev ? dev->power.subsys_data : NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* pm_clk_acquire - Acquire a device clock.
|
||||||
|
* @dev: Device whose clock is to be acquired.
|
||||||
|
* @ce: PM clock entry corresponding to the clock.
|
||||||
|
*/
|
||||||
|
static void pm_clk_acquire(struct device *dev, struct pm_clock_entry *ce)
|
||||||
|
{
|
||||||
|
ce->clk = clk_get(dev, ce->con_id);
|
||||||
|
if (IS_ERR(ce->clk)) {
|
||||||
|
ce->status = PCE_STATUS_ERROR;
|
||||||
|
} else {
|
||||||
|
ce->status = PCE_STATUS_ACQUIRED;
|
||||||
|
dev_dbg(dev, "Clock %s managed by runtime PM.\n", ce->con_id);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* pm_clk_add - Start using a device clock for power management.
|
* pm_clk_add - Start using a device clock for power management.
|
||||||
* @dev: Device whose clock is going to be used for power management.
|
* @dev: Device whose clock is going to be used for power management.
|
||||||
|
@ -73,6 +89,8 @@ int pm_clk_add(struct device *dev, const char *con_id)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
pm_clk_acquire(dev, ce);
|
||||||
|
|
||||||
spin_lock_irq(&pcd->lock);
|
spin_lock_irq(&pcd->lock);
|
||||||
list_add_tail(&ce->node, &pcd->clock_list);
|
list_add_tail(&ce->node, &pcd->clock_list);
|
||||||
spin_unlock_irq(&pcd->lock);
|
spin_unlock_irq(&pcd->lock);
|
||||||
|
@ -82,17 +100,12 @@ int pm_clk_add(struct device *dev, const char *con_id)
|
||||||
/**
|
/**
|
||||||
* __pm_clk_remove - Destroy PM clock entry.
|
* __pm_clk_remove - Destroy PM clock entry.
|
||||||
* @ce: PM clock entry to destroy.
|
* @ce: PM clock entry to destroy.
|
||||||
*
|
|
||||||
* This routine must be called under the spinlock protecting the PM list of
|
|
||||||
* clocks corresponding the the @ce's device.
|
|
||||||
*/
|
*/
|
||||||
static void __pm_clk_remove(struct pm_clock_entry *ce)
|
static void __pm_clk_remove(struct pm_clock_entry *ce)
|
||||||
{
|
{
|
||||||
if (!ce)
|
if (!ce)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
list_del(&ce->node);
|
|
||||||
|
|
||||||
if (ce->status < PCE_STATUS_ERROR) {
|
if (ce->status < PCE_STATUS_ERROR) {
|
||||||
if (ce->status == PCE_STATUS_ENABLED)
|
if (ce->status == PCE_STATUS_ENABLED)
|
||||||
clk_disable(ce->clk);
|
clk_disable(ce->clk);
|
||||||
|
@ -126,18 +139,22 @@ void pm_clk_remove(struct device *dev, const char *con_id)
|
||||||
spin_lock_irq(&pcd->lock);
|
spin_lock_irq(&pcd->lock);
|
||||||
|
|
||||||
list_for_each_entry(ce, &pcd->clock_list, node) {
|
list_for_each_entry(ce, &pcd->clock_list, node) {
|
||||||
if (!con_id && !ce->con_id) {
|
if (!con_id && !ce->con_id)
|
||||||
__pm_clk_remove(ce);
|
goto remove;
|
||||||
break;
|
else if (!con_id || !ce->con_id)
|
||||||
} else if (!con_id || !ce->con_id) {
|
|
||||||
continue;
|
continue;
|
||||||
} else if (!strcmp(con_id, ce->con_id)) {
|
else if (!strcmp(con_id, ce->con_id))
|
||||||
__pm_clk_remove(ce);
|
goto remove;
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
spin_unlock_irq(&pcd->lock);
|
spin_unlock_irq(&pcd->lock);
|
||||||
|
return;
|
||||||
|
|
||||||
|
remove:
|
||||||
|
list_del(&ce->node);
|
||||||
|
spin_unlock_irq(&pcd->lock);
|
||||||
|
|
||||||
|
__pm_clk_remove(ce);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -175,43 +192,33 @@ void pm_clk_destroy(struct device *dev)
|
||||||
{
|
{
|
||||||
struct pm_clk_data *pcd = __to_pcd(dev);
|
struct pm_clk_data *pcd = __to_pcd(dev);
|
||||||
struct pm_clock_entry *ce, *c;
|
struct pm_clock_entry *ce, *c;
|
||||||
|
struct list_head list;
|
||||||
|
|
||||||
if (!pcd)
|
if (!pcd)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
dev->power.subsys_data = NULL;
|
dev->power.subsys_data = NULL;
|
||||||
|
INIT_LIST_HEAD(&list);
|
||||||
|
|
||||||
spin_lock_irq(&pcd->lock);
|
spin_lock_irq(&pcd->lock);
|
||||||
|
|
||||||
list_for_each_entry_safe_reverse(ce, c, &pcd->clock_list, node)
|
list_for_each_entry_safe_reverse(ce, c, &pcd->clock_list, node)
|
||||||
__pm_clk_remove(ce);
|
list_move(&ce->node, &list);
|
||||||
|
|
||||||
spin_unlock_irq(&pcd->lock);
|
spin_unlock_irq(&pcd->lock);
|
||||||
|
|
||||||
kfree(pcd);
|
kfree(pcd);
|
||||||
|
|
||||||
|
list_for_each_entry_safe_reverse(ce, c, &list, node) {
|
||||||
|
list_del(&ce->node);
|
||||||
|
__pm_clk_remove(ce);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* CONFIG_PM */
|
#endif /* CONFIG_PM */
|
||||||
|
|
||||||
#ifdef CONFIG_PM_RUNTIME
|
#ifdef CONFIG_PM_RUNTIME
|
||||||
|
|
||||||
/**
|
|
||||||
* pm_clk_acquire - Acquire a device clock.
|
|
||||||
* @dev: Device whose clock is to be acquired.
|
|
||||||
* @con_id: Connection ID of the clock.
|
|
||||||
*/
|
|
||||||
static void pm_clk_acquire(struct device *dev,
|
|
||||||
struct pm_clock_entry *ce)
|
|
||||||
{
|
|
||||||
ce->clk = clk_get(dev, ce->con_id);
|
|
||||||
if (IS_ERR(ce->clk)) {
|
|
||||||
ce->status = PCE_STATUS_ERROR;
|
|
||||||
} else {
|
|
||||||
ce->status = PCE_STATUS_ACQUIRED;
|
|
||||||
dev_dbg(dev, "Clock %s managed by runtime PM.\n", ce->con_id);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* pm_clk_suspend - Disable clocks in a device's PM clock list.
|
* pm_clk_suspend - Disable clocks in a device's PM clock list.
|
||||||
* @dev: Device to disable the clocks for.
|
* @dev: Device to disable the clocks for.
|
||||||
|
@ -230,9 +237,6 @@ int pm_clk_suspend(struct device *dev)
|
||||||
spin_lock_irqsave(&pcd->lock, flags);
|
spin_lock_irqsave(&pcd->lock, flags);
|
||||||
|
|
||||||
list_for_each_entry_reverse(ce, &pcd->clock_list, node) {
|
list_for_each_entry_reverse(ce, &pcd->clock_list, node) {
|
||||||
if (ce->status == PCE_STATUS_NONE)
|
|
||||||
pm_clk_acquire(dev, ce);
|
|
||||||
|
|
||||||
if (ce->status < PCE_STATUS_ERROR) {
|
if (ce->status < PCE_STATUS_ERROR) {
|
||||||
clk_disable(ce->clk);
|
clk_disable(ce->clk);
|
||||||
ce->status = PCE_STATUS_ACQUIRED;
|
ce->status = PCE_STATUS_ACQUIRED;
|
||||||
|
@ -262,9 +266,6 @@ int pm_clk_resume(struct device *dev)
|
||||||
spin_lock_irqsave(&pcd->lock, flags);
|
spin_lock_irqsave(&pcd->lock, flags);
|
||||||
|
|
||||||
list_for_each_entry(ce, &pcd->clock_list, node) {
|
list_for_each_entry(ce, &pcd->clock_list, node) {
|
||||||
if (ce->status == PCE_STATUS_NONE)
|
|
||||||
pm_clk_acquire(dev, ce);
|
|
||||||
|
|
||||||
if (ce->status < PCE_STATUS_ERROR) {
|
if (ce->status < PCE_STATUS_ERROR) {
|
||||||
clk_enable(ce->clk);
|
clk_enable(ce->clk);
|
||||||
ce->status = PCE_STATUS_ENABLED;
|
ce->status = PCE_STATUS_ENABLED;
|
||||||
|
|
|
@ -43,6 +43,7 @@ config TCG_NSC
|
||||||
|
|
||||||
config TCG_ATMEL
|
config TCG_ATMEL
|
||||||
tristate "Atmel TPM Interface"
|
tristate "Atmel TPM Interface"
|
||||||
|
depends on PPC64 || HAS_IOPORT
|
||||||
---help---
|
---help---
|
||||||
If you have a TPM security chip from Atmel say Yes and it
|
If you have a TPM security chip from Atmel say Yes and it
|
||||||
will be accessible from within Linux. To compile this driver
|
will be accessible from within Linux. To compile this driver
|
||||||
|
|
|
@ -383,6 +383,9 @@ static ssize_t tpm_transmit(struct tpm_chip *chip, const char *buf,
|
||||||
u32 count, ordinal;
|
u32 count, ordinal;
|
||||||
unsigned long stop;
|
unsigned long stop;
|
||||||
|
|
||||||
|
if (bufsiz > TPM_BUFSIZE)
|
||||||
|
bufsiz = TPM_BUFSIZE;
|
||||||
|
|
||||||
count = be32_to_cpu(*((__be32 *) (buf + 2)));
|
count = be32_to_cpu(*((__be32 *) (buf + 2)));
|
||||||
ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
|
ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
|
||||||
if (count == 0)
|
if (count == 0)
|
||||||
|
@ -1102,6 +1105,7 @@ ssize_t tpm_read(struct file *file, char __user *buf,
|
||||||
{
|
{
|
||||||
struct tpm_chip *chip = file->private_data;
|
struct tpm_chip *chip = file->private_data;
|
||||||
ssize_t ret_size;
|
ssize_t ret_size;
|
||||||
|
int rc;
|
||||||
|
|
||||||
del_singleshot_timer_sync(&chip->user_read_timer);
|
del_singleshot_timer_sync(&chip->user_read_timer);
|
||||||
flush_work_sync(&chip->work);
|
flush_work_sync(&chip->work);
|
||||||
|
@ -1112,8 +1116,11 @@ ssize_t tpm_read(struct file *file, char __user *buf,
|
||||||
ret_size = size;
|
ret_size = size;
|
||||||
|
|
||||||
mutex_lock(&chip->buffer_mutex);
|
mutex_lock(&chip->buffer_mutex);
|
||||||
if (copy_to_user(buf, chip->data_buffer, ret_size))
|
rc = copy_to_user(buf, chip->data_buffer, ret_size);
|
||||||
|
memset(chip->data_buffer, 0, ret_size);
|
||||||
|
if (rc)
|
||||||
ret_size = -EFAULT;
|
ret_size = -EFAULT;
|
||||||
|
|
||||||
mutex_unlock(&chip->buffer_mutex);
|
mutex_unlock(&chip->buffer_mutex);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -396,8 +396,6 @@ static void __exit cleanup_nsc(void)
|
||||||
if (pdev) {
|
if (pdev) {
|
||||||
tpm_nsc_remove(&pdev->dev);
|
tpm_nsc_remove(&pdev->dev);
|
||||||
platform_device_unregister(pdev);
|
platform_device_unregister(pdev);
|
||||||
kfree(pdev);
|
|
||||||
pdev = NULL;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
platform_driver_unregister(&nsc_drv);
|
platform_driver_unregister(&nsc_drv);
|
||||||
|
|
|
@ -67,11 +67,11 @@ module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
|
||||||
MODULE_PARM_DESC(i915_enable_rc6,
|
MODULE_PARM_DESC(i915_enable_rc6,
|
||||||
"Enable power-saving render C-state 6 (default: true)");
|
"Enable power-saving render C-state 6 (default: true)");
|
||||||
|
|
||||||
unsigned int i915_enable_fbc __read_mostly = 1;
|
unsigned int i915_enable_fbc __read_mostly = -1;
|
||||||
module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
|
module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
|
||||||
MODULE_PARM_DESC(i915_enable_fbc,
|
MODULE_PARM_DESC(i915_enable_fbc,
|
||||||
"Enable frame buffer compression for power savings "
|
"Enable frame buffer compression for power savings "
|
||||||
"(default: false)");
|
"(default: -1 (use per-chip default))");
|
||||||
|
|
||||||
unsigned int i915_lvds_downclock __read_mostly = 0;
|
unsigned int i915_lvds_downclock __read_mostly = 0;
|
||||||
module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
|
module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
|
||||||
|
|
|
@ -1799,6 +1799,7 @@ static void intel_update_fbc(struct drm_device *dev)
|
||||||
struct drm_framebuffer *fb;
|
struct drm_framebuffer *fb;
|
||||||
struct intel_framebuffer *intel_fb;
|
struct intel_framebuffer *intel_fb;
|
||||||
struct drm_i915_gem_object *obj;
|
struct drm_i915_gem_object *obj;
|
||||||
|
int enable_fbc;
|
||||||
|
|
||||||
DRM_DEBUG_KMS("\n");
|
DRM_DEBUG_KMS("\n");
|
||||||
|
|
||||||
|
@ -1839,8 +1840,15 @@ static void intel_update_fbc(struct drm_device *dev)
|
||||||
intel_fb = to_intel_framebuffer(fb);
|
intel_fb = to_intel_framebuffer(fb);
|
||||||
obj = intel_fb->obj;
|
obj = intel_fb->obj;
|
||||||
|
|
||||||
if (!i915_enable_fbc) {
|
enable_fbc = i915_enable_fbc;
|
||||||
DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
|
if (enable_fbc < 0) {
|
||||||
|
DRM_DEBUG_KMS("fbc set to per-chip default\n");
|
||||||
|
enable_fbc = 1;
|
||||||
|
if (INTEL_INFO(dev)->gen <= 5)
|
||||||
|
enable_fbc = 0;
|
||||||
|
}
|
||||||
|
if (!enable_fbc) {
|
||||||
|
DRM_DEBUG_KMS("fbc disabled per module param\n");
|
||||||
dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
|
dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
|
||||||
goto out_disable;
|
goto out_disable;
|
||||||
}
|
}
|
||||||
|
@ -4687,13 +4695,13 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
|
||||||
bpc = 6; /* min is 18bpp */
|
bpc = 6; /* min is 18bpp */
|
||||||
break;
|
break;
|
||||||
case 24:
|
case 24:
|
||||||
bpc = min((unsigned int)8, display_bpc);
|
bpc = 8;
|
||||||
break;
|
break;
|
||||||
case 30:
|
case 30:
|
||||||
bpc = min((unsigned int)10, display_bpc);
|
bpc = 10;
|
||||||
break;
|
break;
|
||||||
case 48:
|
case 48:
|
||||||
bpc = min((unsigned int)12, display_bpc);
|
bpc = 12;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
DRM_DEBUG("unsupported depth, assuming 24 bits\n");
|
DRM_DEBUG("unsupported depth, assuming 24 bits\n");
|
||||||
|
@ -4701,10 +4709,12 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
display_bpc = min(display_bpc, bpc);
|
||||||
|
|
||||||
DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
|
DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
|
||||||
bpc, display_bpc);
|
bpc, display_bpc);
|
||||||
|
|
||||||
*pipe_bpp = bpc * 3;
|
*pipe_bpp = display_bpc * 3;
|
||||||
|
|
||||||
return display_bpc != bpc;
|
return display_bpc != bpc;
|
||||||
}
|
}
|
||||||
|
|
|
@ -337,9 +337,6 @@ extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
|
||||||
struct drm_connector *connector,
|
struct drm_connector *connector,
|
||||||
struct intel_load_detect_pipe *old);
|
struct intel_load_detect_pipe *old);
|
||||||
|
|
||||||
extern struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB);
|
|
||||||
extern int intel_sdvo_supports_hotplug(struct drm_connector *connector);
|
|
||||||
extern void intel_sdvo_set_hotplug(struct drm_connector *connector, int enable);
|
|
||||||
extern void intelfb_restore(void);
|
extern void intelfb_restore(void);
|
||||||
extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
|
extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
|
||||||
u16 blue, int regno);
|
u16 blue, int regno);
|
||||||
|
|
|
@ -92,6 +92,11 @@ struct intel_sdvo {
|
||||||
*/
|
*/
|
||||||
uint16_t attached_output;
|
uint16_t attached_output;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Hotplug activation bits for this device
|
||||||
|
*/
|
||||||
|
uint8_t hotplug_active[2];
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* This is used to select the color range of RBG outputs in HDMI mode.
|
* This is used to select the color range of RBG outputs in HDMI mode.
|
||||||
* It is only valid when using TMDS encoding and 8 bit per color mode.
|
* It is only valid when using TMDS encoding and 8 bit per color mode.
|
||||||
|
@ -1208,74 +1213,20 @@ static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct in
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* No use! */
|
static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
|
||||||
#if 0
|
|
||||||
struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
|
|
||||||
{
|
|
||||||
struct drm_connector *connector = NULL;
|
|
||||||
struct intel_sdvo *iout = NULL;
|
|
||||||
struct intel_sdvo *sdvo;
|
|
||||||
|
|
||||||
/* find the sdvo connector */
|
|
||||||
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
|
|
||||||
iout = to_intel_sdvo(connector);
|
|
||||||
|
|
||||||
if (iout->type != INTEL_OUTPUT_SDVO)
|
|
||||||
continue;
|
|
||||||
|
|
||||||
sdvo = iout->dev_priv;
|
|
||||||
|
|
||||||
if (sdvo->sdvo_reg == SDVOB && sdvoB)
|
|
||||||
return connector;
|
|
||||||
|
|
||||||
if (sdvo->sdvo_reg == SDVOC && !sdvoB)
|
|
||||||
return connector;
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
int intel_sdvo_supports_hotplug(struct drm_connector *connector)
|
|
||||||
{
|
{
|
||||||
u8 response[2];
|
u8 response[2];
|
||||||
u8 status;
|
|
||||||
struct intel_sdvo *intel_sdvo;
|
|
||||||
DRM_DEBUG_KMS("\n");
|
|
||||||
|
|
||||||
if (!connector)
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
intel_sdvo = to_intel_sdvo(connector);
|
|
||||||
|
|
||||||
return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
|
return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
|
||||||
&response, 2) && response[0];
|
&response, 2) && response[0];
|
||||||
}
|
}
|
||||||
|
|
||||||
void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
|
static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
|
||||||
{
|
{
|
||||||
u8 response[2];
|
struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
|
||||||
u8 status;
|
|
||||||
struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
|
|
||||||
|
|
||||||
intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
|
intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
|
||||||
intel_sdvo_read_response(intel_sdvo, &response, 2);
|
|
||||||
|
|
||||||
if (on) {
|
|
||||||
intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
|
|
||||||
status = intel_sdvo_read_response(intel_sdvo, &response, 2);
|
|
||||||
|
|
||||||
intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
|
|
||||||
} else {
|
|
||||||
response[0] = 0;
|
|
||||||
response[1] = 0;
|
|
||||||
intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
|
|
||||||
}
|
|
||||||
|
|
||||||
intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
|
|
||||||
intel_sdvo_read_response(intel_sdvo, &response, 2);
|
|
||||||
}
|
}
|
||||||
#endif
|
|
||||||
|
|
||||||
static bool
|
static bool
|
||||||
intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
|
intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
|
||||||
|
@ -2045,6 +1996,7 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
|
||||||
{
|
{
|
||||||
struct drm_encoder *encoder = &intel_sdvo->base.base;
|
struct drm_encoder *encoder = &intel_sdvo->base.base;
|
||||||
struct drm_connector *connector;
|
struct drm_connector *connector;
|
||||||
|
struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
|
||||||
struct intel_connector *intel_connector;
|
struct intel_connector *intel_connector;
|
||||||
struct intel_sdvo_connector *intel_sdvo_connector;
|
struct intel_sdvo_connector *intel_sdvo_connector;
|
||||||
|
|
||||||
|
@ -2062,7 +2014,17 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
|
||||||
|
|
||||||
intel_connector = &intel_sdvo_connector->base;
|
intel_connector = &intel_sdvo_connector->base;
|
||||||
connector = &intel_connector->base;
|
connector = &intel_connector->base;
|
||||||
connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
|
if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
|
||||||
|
connector->polled = DRM_CONNECTOR_POLL_HPD;
|
||||||
|
intel_sdvo->hotplug_active[0] |= 1 << device;
|
||||||
|
/* Some SDVO devices have one-shot hotplug interrupts.
|
||||||
|
* Ensure that they get re-enabled when an interrupt happens.
|
||||||
|
*/
|
||||||
|
intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
|
||||||
|
intel_sdvo_enable_hotplug(intel_encoder);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
|
||||||
encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
|
encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
|
||||||
connector->connector_type = DRM_MODE_CONNECTOR_DVID;
|
connector->connector_type = DRM_MODE_CONNECTOR_DVID;
|
||||||
|
|
||||||
|
@ -2569,6 +2531,14 @@ bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
|
||||||
if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
|
if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
|
||||||
goto err;
|
goto err;
|
||||||
|
|
||||||
|
/* Set up hotplug command - note paranoia about contents of reply.
|
||||||
|
* We assume that the hardware is in a sane state, and only touch
|
||||||
|
* the bits we think we understand.
|
||||||
|
*/
|
||||||
|
intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
|
||||||
|
&intel_sdvo->hotplug_active, 2);
|
||||||
|
intel_sdvo->hotplug_active[0] &= ~0x3;
|
||||||
|
|
||||||
if (intel_sdvo_output_setup(intel_sdvo,
|
if (intel_sdvo_output_setup(intel_sdvo,
|
||||||
intel_sdvo->caps.output_flags) != true) {
|
intel_sdvo->caps.output_flags) != true) {
|
||||||
DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
|
DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
|
||||||
|
|
|
@ -115,6 +115,7 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
|
||||||
u8 msg[20];
|
u8 msg[20];
|
||||||
int msg_bytes = send_bytes + 4;
|
int msg_bytes = send_bytes + 4;
|
||||||
u8 ack;
|
u8 ack;
|
||||||
|
unsigned retry;
|
||||||
|
|
||||||
if (send_bytes > 16)
|
if (send_bytes > 16)
|
||||||
return -1;
|
return -1;
|
||||||
|
@ -125,20 +126,20 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
|
||||||
msg[3] = (msg_bytes << 4) | (send_bytes - 1);
|
msg[3] = (msg_bytes << 4) | (send_bytes - 1);
|
||||||
memcpy(&msg[4], send, send_bytes);
|
memcpy(&msg[4], send, send_bytes);
|
||||||
|
|
||||||
while (1) {
|
for (retry = 0; retry < 4; retry++) {
|
||||||
ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
|
ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
|
||||||
msg, msg_bytes, NULL, 0, delay, &ack);
|
msg, msg_bytes, NULL, 0, delay, &ack);
|
||||||
if (ret < 0)
|
if (ret < 0)
|
||||||
return ret;
|
return ret;
|
||||||
if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
|
if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
|
||||||
break;
|
return send_bytes;
|
||||||
else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
|
else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
|
||||||
udelay(400);
|
udelay(400);
|
||||||
else
|
else
|
||||||
return -EIO;
|
return -EIO;
|
||||||
}
|
}
|
||||||
|
|
||||||
return send_bytes;
|
return -EIO;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
|
static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
|
||||||
|
@ -149,26 +150,29 @@ static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
|
||||||
int msg_bytes = 4;
|
int msg_bytes = 4;
|
||||||
u8 ack;
|
u8 ack;
|
||||||
int ret;
|
int ret;
|
||||||
|
unsigned retry;
|
||||||
|
|
||||||
msg[0] = address;
|
msg[0] = address;
|
||||||
msg[1] = address >> 8;
|
msg[1] = address >> 8;
|
||||||
msg[2] = AUX_NATIVE_READ << 4;
|
msg[2] = AUX_NATIVE_READ << 4;
|
||||||
msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
|
msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
|
||||||
|
|
||||||
while (1) {
|
for (retry = 0; retry < 4; retry++) {
|
||||||
ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
|
ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
|
||||||
msg, msg_bytes, recv, recv_bytes, delay, &ack);
|
msg, msg_bytes, recv, recv_bytes, delay, &ack);
|
||||||
if (ret == 0)
|
|
||||||
return -EPROTO;
|
|
||||||
if (ret < 0)
|
if (ret < 0)
|
||||||
return ret;
|
return ret;
|
||||||
if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
|
if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
|
||||||
return ret;
|
return ret;
|
||||||
else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
|
else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
|
||||||
udelay(400);
|
udelay(400);
|
||||||
|
else if (ret == 0)
|
||||||
|
return -EPROTO;
|
||||||
else
|
else
|
||||||
return -EIO;
|
return -EIO;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
return -EIO;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
|
static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
|
||||||
|
|
|
@ -1590,48 +1590,6 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
|
||||||
return backend_map;
|
return backend_map;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void evergreen_program_channel_remap(struct radeon_device *rdev)
|
|
||||||
{
|
|
||||||
u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
|
|
||||||
|
|
||||||
tmp = RREG32(MC_SHARED_CHMAP);
|
|
||||||
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
|
|
||||||
case 0:
|
|
||||||
case 1:
|
|
||||||
case 2:
|
|
||||||
case 3:
|
|
||||||
default:
|
|
||||||
/* default mapping */
|
|
||||||
mc_shared_chremap = 0x00fac688;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
switch (rdev->family) {
|
|
||||||
case CHIP_HEMLOCK:
|
|
||||||
case CHIP_CYPRESS:
|
|
||||||
case CHIP_BARTS:
|
|
||||||
tcp_chan_steer_lo = 0x54763210;
|
|
||||||
tcp_chan_steer_hi = 0x0000ba98;
|
|
||||||
break;
|
|
||||||
case CHIP_JUNIPER:
|
|
||||||
case CHIP_REDWOOD:
|
|
||||||
case CHIP_CEDAR:
|
|
||||||
case CHIP_PALM:
|
|
||||||
case CHIP_SUMO:
|
|
||||||
case CHIP_SUMO2:
|
|
||||||
case CHIP_TURKS:
|
|
||||||
case CHIP_CAICOS:
|
|
||||||
default:
|
|
||||||
tcp_chan_steer_lo = 0x76543210;
|
|
||||||
tcp_chan_steer_hi = 0x0000ba98;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
|
|
||||||
WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
|
|
||||||
WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void evergreen_gpu_init(struct radeon_device *rdev)
|
static void evergreen_gpu_init(struct radeon_device *rdev)
|
||||||
{
|
{
|
||||||
u32 cc_rb_backend_disable = 0;
|
u32 cc_rb_backend_disable = 0;
|
||||||
|
@ -2078,8 +2036,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
|
||||||
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
|
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
|
||||||
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
|
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
|
||||||
|
|
||||||
evergreen_program_channel_remap(rdev);
|
|
||||||
|
|
||||||
num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
|
num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
|
||||||
grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
|
grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
|
||||||
|
|
||||||
|
|
|
@ -569,36 +569,6 @@ static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
|
||||||
return backend_map;
|
return backend_map;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void cayman_program_channel_remap(struct radeon_device *rdev)
|
|
||||||
{
|
|
||||||
u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
|
|
||||||
|
|
||||||
tmp = RREG32(MC_SHARED_CHMAP);
|
|
||||||
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
|
|
||||||
case 0:
|
|
||||||
case 1:
|
|
||||||
case 2:
|
|
||||||
case 3:
|
|
||||||
default:
|
|
||||||
/* default mapping */
|
|
||||||
mc_shared_chremap = 0x00fac688;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
switch (rdev->family) {
|
|
||||||
case CHIP_CAYMAN:
|
|
||||||
default:
|
|
||||||
//tcp_chan_steer_lo = 0x54763210
|
|
||||||
tcp_chan_steer_lo = 0x76543210;
|
|
||||||
tcp_chan_steer_hi = 0x0000ba98;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
|
|
||||||
WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
|
|
||||||
WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
|
|
||||||
}
|
|
||||||
|
|
||||||
static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
|
static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
|
||||||
u32 disable_mask_per_se,
|
u32 disable_mask_per_se,
|
||||||
u32 max_disable_mask_per_se,
|
u32 max_disable_mask_per_se,
|
||||||
|
@ -842,8 +812,6 @@ static void cayman_gpu_init(struct radeon_device *rdev)
|
||||||
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
|
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
|
||||||
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
|
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
|
||||||
|
|
||||||
cayman_program_channel_remap(rdev);
|
|
||||||
|
|
||||||
/* primary versions */
|
/* primary versions */
|
||||||
WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
|
WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
|
||||||
WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
|
WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
|
||||||
|
|
|
@ -773,8 +773,8 @@ int r100_copy_blit(struct radeon_device *rdev,
|
||||||
radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
|
radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
|
||||||
radeon_ring_write(rdev, 0);
|
radeon_ring_write(rdev, 0);
|
||||||
radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
|
radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
|
||||||
radeon_ring_write(rdev, cur_pages);
|
radeon_ring_write(rdev, num_gpu_pages);
|
||||||
radeon_ring_write(rdev, cur_pages);
|
radeon_ring_write(rdev, num_gpu_pages);
|
||||||
radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
|
radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
|
||||||
}
|
}
|
||||||
radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
|
radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
|
||||||
|
|
|
@ -68,11 +68,11 @@ void radeon_connector_hotplug(struct drm_connector *connector)
|
||||||
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
|
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
|
||||||
int saved_dpms = connector->dpms;
|
int saved_dpms = connector->dpms;
|
||||||
|
|
||||||
if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd) &&
|
/* Only turn off the display it it's physically disconnected */
|
||||||
radeon_dp_needs_link_train(radeon_connector))
|
if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
|
||||||
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
|
|
||||||
else
|
|
||||||
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
|
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
|
||||||
|
else if (radeon_dp_needs_link_train(radeon_connector))
|
||||||
|
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
|
||||||
connector->dpms = saved_dpms;
|
connector->dpms = saved_dpms;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -208,24 +208,26 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
|
||||||
int xorigin = 0, yorigin = 0;
|
int xorigin = 0, yorigin = 0;
|
||||||
int w = radeon_crtc->cursor_width;
|
int w = radeon_crtc->cursor_width;
|
||||||
|
|
||||||
if (x < 0)
|
if (ASIC_IS_AVIVO(rdev)) {
|
||||||
xorigin = -x + 1;
|
/* avivo cursor are offset into the total surface */
|
||||||
if (y < 0)
|
x += crtc->x;
|
||||||
yorigin = -y + 1;
|
y += crtc->y;
|
||||||
if (xorigin >= CURSOR_WIDTH)
|
}
|
||||||
xorigin = CURSOR_WIDTH - 1;
|
DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
|
||||||
if (yorigin >= CURSOR_HEIGHT)
|
|
||||||
yorigin = CURSOR_HEIGHT - 1;
|
if (x < 0) {
|
||||||
|
xorigin = min(-x, CURSOR_WIDTH - 1);
|
||||||
|
x = 0;
|
||||||
|
}
|
||||||
|
if (y < 0) {
|
||||||
|
yorigin = min(-y, CURSOR_HEIGHT - 1);
|
||||||
|
y = 0;
|
||||||
|
}
|
||||||
|
|
||||||
if (ASIC_IS_AVIVO(rdev)) {
|
if (ASIC_IS_AVIVO(rdev)) {
|
||||||
int i = 0;
|
int i = 0;
|
||||||
struct drm_crtc *crtc_p;
|
struct drm_crtc *crtc_p;
|
||||||
|
|
||||||
/* avivo cursor are offset into the total surface */
|
|
||||||
x += crtc->x;
|
|
||||||
y += crtc->y;
|
|
||||||
DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
|
|
||||||
|
|
||||||
/* avivo cursor image can't end on 128 pixel boundary or
|
/* avivo cursor image can't end on 128 pixel boundary or
|
||||||
* go past the end of the frame if both crtcs are enabled
|
* go past the end of the frame if both crtcs are enabled
|
||||||
*/
|
*/
|
||||||
|
@ -253,16 +255,12 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
|
||||||
|
|
||||||
radeon_lock_cursor(crtc, true);
|
radeon_lock_cursor(crtc, true);
|
||||||
if (ASIC_IS_DCE4(rdev)) {
|
if (ASIC_IS_DCE4(rdev)) {
|
||||||
WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset,
|
WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
|
||||||
((xorigin ? 0 : x) << 16) |
|
|
||||||
(yorigin ? 0 : y));
|
|
||||||
WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
|
WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
|
||||||
WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
|
WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
|
||||||
((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
|
((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
|
||||||
} else if (ASIC_IS_AVIVO(rdev)) {
|
} else if (ASIC_IS_AVIVO(rdev)) {
|
||||||
WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,
|
WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
|
||||||
((xorigin ? 0 : x) << 16) |
|
|
||||||
(yorigin ? 0 : y));
|
|
||||||
WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
|
WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
|
||||||
WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
|
WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
|
||||||
((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
|
((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
|
||||||
|
@ -276,8 +274,8 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
|
||||||
| yorigin));
|
| yorigin));
|
||||||
WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
|
WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
|
||||||
(RADEON_CUR_LOCK
|
(RADEON_CUR_LOCK
|
||||||
| ((xorigin ? 0 : x) << 16)
|
| (x << 16)
|
||||||
| (yorigin ? 0 : y)));
|
| y));
|
||||||
/* offset is from DISP(2)_BASE_ADDRESS */
|
/* offset is from DISP(2)_BASE_ADDRESS */
|
||||||
WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
|
WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
|
||||||
(yorigin * 256)));
|
(yorigin * 256)));
|
||||||
|
|
|
@ -1507,7 +1507,14 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
|
||||||
switch (mode) {
|
switch (mode) {
|
||||||
case DRM_MODE_DPMS_ON:
|
case DRM_MODE_DPMS_ON:
|
||||||
args.ucAction = ATOM_ENABLE;
|
args.ucAction = ATOM_ENABLE;
|
||||||
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
|
/* workaround for DVOOutputControl on some RS690 systems */
|
||||||
|
if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
|
||||||
|
u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
|
||||||
|
WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
|
||||||
|
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
|
||||||
|
WREG32(RADEON_BIOS_3_SCRATCH, reg);
|
||||||
|
} else
|
||||||
|
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
|
||||||
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
|
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
|
||||||
args.ucAction = ATOM_LCD_BLON;
|
args.ucAction = ATOM_LCD_BLON;
|
||||||
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
|
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
|
||||||
|
|
|
@ -536,55 +536,6 @@ static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
|
||||||
return backend_map;
|
return backend_map;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void rv770_program_channel_remap(struct radeon_device *rdev)
|
|
||||||
{
|
|
||||||
u32 tcp_chan_steer, mc_shared_chremap, tmp;
|
|
||||||
bool force_no_swizzle;
|
|
||||||
|
|
||||||
switch (rdev->family) {
|
|
||||||
case CHIP_RV770:
|
|
||||||
case CHIP_RV730:
|
|
||||||
force_no_swizzle = false;
|
|
||||||
break;
|
|
||||||
case CHIP_RV710:
|
|
||||||
case CHIP_RV740:
|
|
||||||
default:
|
|
||||||
force_no_swizzle = true;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
tmp = RREG32(MC_SHARED_CHMAP);
|
|
||||||
switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
|
|
||||||
case 0:
|
|
||||||
case 1:
|
|
||||||
default:
|
|
||||||
/* default mapping */
|
|
||||||
mc_shared_chremap = 0x00fac688;
|
|
||||||
break;
|
|
||||||
case 2:
|
|
||||||
case 3:
|
|
||||||
if (force_no_swizzle)
|
|
||||||
mc_shared_chremap = 0x00fac688;
|
|
||||||
else
|
|
||||||
mc_shared_chremap = 0x00bbc298;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (rdev->family == CHIP_RV740)
|
|
||||||
tcp_chan_steer = 0x00ef2a60;
|
|
||||||
else
|
|
||||||
tcp_chan_steer = 0x00fac688;
|
|
||||||
|
|
||||||
/* RV770 CE has special chremap setup */
|
|
||||||
if (rdev->pdev->device == 0x944e) {
|
|
||||||
tcp_chan_steer = 0x00b08b08;
|
|
||||||
mc_shared_chremap = 0x00b08b08;
|
|
||||||
}
|
|
||||||
|
|
||||||
WREG32(TCP_CHAN_STEER, tcp_chan_steer);
|
|
||||||
WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void rv770_gpu_init(struct radeon_device *rdev)
|
static void rv770_gpu_init(struct radeon_device *rdev)
|
||||||
{
|
{
|
||||||
int i, j, num_qd_pipes;
|
int i, j, num_qd_pipes;
|
||||||
|
@ -785,8 +736,6 @@ static void rv770_gpu_init(struct radeon_device *rdev)
|
||||||
WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
|
WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
|
||||||
WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
|
WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
|
||||||
|
|
||||||
rv770_program_channel_remap(rdev);
|
|
||||||
|
|
||||||
WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
|
WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
|
||||||
WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
|
WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
|
||||||
WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
|
WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
|
||||||
|
|
|
@ -36,17 +36,25 @@
|
||||||
#include <linux/cpu.h>
|
#include <linux/cpu.h>
|
||||||
#include <linux/pci.h>
|
#include <linux/pci.h>
|
||||||
#include <linux/smp.h>
|
#include <linux/smp.h>
|
||||||
|
#include <linux/moduleparam.h>
|
||||||
#include <asm/msr.h>
|
#include <asm/msr.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
|
|
||||||
#define DRVNAME "coretemp"
|
#define DRVNAME "coretemp"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* force_tjmax only matters when TjMax can't be read from the CPU itself.
|
||||||
|
* When set, it replaces the driver's suboptimal heuristic.
|
||||||
|
*/
|
||||||
|
static int force_tjmax;
|
||||||
|
module_param_named(tjmax, force_tjmax, int, 0444);
|
||||||
|
MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius");
|
||||||
|
|
||||||
#define BASE_SYSFS_ATTR_NO 2 /* Sysfs Base attr no for coretemp */
|
#define BASE_SYSFS_ATTR_NO 2 /* Sysfs Base attr no for coretemp */
|
||||||
#define NUM_REAL_CORES 16 /* Number of Real cores per cpu */
|
#define NUM_REAL_CORES 16 /* Number of Real cores per cpu */
|
||||||
#define CORETEMP_NAME_LENGTH 17 /* String Length of attrs */
|
#define CORETEMP_NAME_LENGTH 17 /* String Length of attrs */
|
||||||
#define MAX_CORE_ATTRS 4 /* Maximum no of basic attrs */
|
#define MAX_CORE_ATTRS 4 /* Maximum no of basic attrs */
|
||||||
#define MAX_THRESH_ATTRS 3 /* Maximum no of Threshold attrs */
|
#define TOTAL_ATTRS (MAX_CORE_ATTRS + 1)
|
||||||
#define TOTAL_ATTRS (MAX_CORE_ATTRS + MAX_THRESH_ATTRS)
|
|
||||||
#define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO)
|
#define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO)
|
||||||
|
|
||||||
#ifdef CONFIG_SMP
|
#ifdef CONFIG_SMP
|
||||||
|
@ -69,8 +77,6 @@
|
||||||
* This value is passed as "id" field to rdmsr/wrmsr functions.
|
* This value is passed as "id" field to rdmsr/wrmsr functions.
|
||||||
* @status_reg: One of IA32_THERM_STATUS or IA32_PACKAGE_THERM_STATUS,
|
* @status_reg: One of IA32_THERM_STATUS or IA32_PACKAGE_THERM_STATUS,
|
||||||
* from where the temperature values should be read.
|
* from where the temperature values should be read.
|
||||||
* @intrpt_reg: One of IA32_THERM_INTERRUPT or IA32_PACKAGE_THERM_INTERRUPT,
|
|
||||||
* from where the thresholds are read.
|
|
||||||
* @attr_size: Total number of pre-core attrs displayed in the sysfs.
|
* @attr_size: Total number of pre-core attrs displayed in the sysfs.
|
||||||
* @is_pkg_data: If this is 1, the temp_data holds pkgtemp data.
|
* @is_pkg_data: If this is 1, the temp_data holds pkgtemp data.
|
||||||
* Otherwise, temp_data holds coretemp data.
|
* Otherwise, temp_data holds coretemp data.
|
||||||
|
@ -79,13 +85,11 @@
|
||||||
struct temp_data {
|
struct temp_data {
|
||||||
int temp;
|
int temp;
|
||||||
int ttarget;
|
int ttarget;
|
||||||
int tmin;
|
|
||||||
int tjmax;
|
int tjmax;
|
||||||
unsigned long last_updated;
|
unsigned long last_updated;
|
||||||
unsigned int cpu;
|
unsigned int cpu;
|
||||||
u32 cpu_core_id;
|
u32 cpu_core_id;
|
||||||
u32 status_reg;
|
u32 status_reg;
|
||||||
u32 intrpt_reg;
|
|
||||||
int attr_size;
|
int attr_size;
|
||||||
bool is_pkg_data;
|
bool is_pkg_data;
|
||||||
bool valid;
|
bool valid;
|
||||||
|
@ -143,19 +147,6 @@ static ssize_t show_crit_alarm(struct device *dev,
|
||||||
return sprintf(buf, "%d\n", (eax >> 5) & 1);
|
return sprintf(buf, "%d\n", (eax >> 5) & 1);
|
||||||
}
|
}
|
||||||
|
|
||||||
static ssize_t show_max_alarm(struct device *dev,
|
|
||||||
struct device_attribute *devattr, char *buf)
|
|
||||||
{
|
|
||||||
u32 eax, edx;
|
|
||||||
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
|
|
||||||
struct platform_data *pdata = dev_get_drvdata(dev);
|
|
||||||
struct temp_data *tdata = pdata->core_data[attr->index];
|
|
||||||
|
|
||||||
rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx);
|
|
||||||
|
|
||||||
return sprintf(buf, "%d\n", !!(eax & THERM_STATUS_THRESHOLD1));
|
|
||||||
}
|
|
||||||
|
|
||||||
static ssize_t show_tjmax(struct device *dev,
|
static ssize_t show_tjmax(struct device *dev,
|
||||||
struct device_attribute *devattr, char *buf)
|
struct device_attribute *devattr, char *buf)
|
||||||
{
|
{
|
||||||
|
@ -174,83 +165,6 @@ static ssize_t show_ttarget(struct device *dev,
|
||||||
return sprintf(buf, "%d\n", pdata->core_data[attr->index]->ttarget);
|
return sprintf(buf, "%d\n", pdata->core_data[attr->index]->ttarget);
|
||||||
}
|
}
|
||||||
|
|
||||||
static ssize_t store_ttarget(struct device *dev,
|
|
||||||
struct device_attribute *devattr,
|
|
||||||
const char *buf, size_t count)
|
|
||||||
{
|
|
||||||
struct platform_data *pdata = dev_get_drvdata(dev);
|
|
||||||
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
|
|
||||||
struct temp_data *tdata = pdata->core_data[attr->index];
|
|
||||||
u32 eax, edx;
|
|
||||||
unsigned long val;
|
|
||||||
int diff;
|
|
||||||
|
|
||||||
if (strict_strtoul(buf, 10, &val))
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* THERM_MASK_THRESHOLD1 is 7 bits wide. Values are entered in terms
|
|
||||||
* of milli degree celsius. Hence don't accept val > (127 * 1000)
|
|
||||||
*/
|
|
||||||
if (val > tdata->tjmax || val > 127000)
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
diff = (tdata->tjmax - val) / 1000;
|
|
||||||
|
|
||||||
mutex_lock(&tdata->update_lock);
|
|
||||||
rdmsr_on_cpu(tdata->cpu, tdata->intrpt_reg, &eax, &edx);
|
|
||||||
eax = (eax & ~THERM_MASK_THRESHOLD1) |
|
|
||||||
(diff << THERM_SHIFT_THRESHOLD1);
|
|
||||||
wrmsr_on_cpu(tdata->cpu, tdata->intrpt_reg, eax, edx);
|
|
||||||
tdata->ttarget = val;
|
|
||||||
mutex_unlock(&tdata->update_lock);
|
|
||||||
|
|
||||||
return count;
|
|
||||||
}
|
|
||||||
|
|
||||||
static ssize_t show_tmin(struct device *dev,
|
|
||||||
struct device_attribute *devattr, char *buf)
|
|
||||||
{
|
|
||||||
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
|
|
||||||
struct platform_data *pdata = dev_get_drvdata(dev);
|
|
||||||
|
|
||||||
return sprintf(buf, "%d\n", pdata->core_data[attr->index]->tmin);
|
|
||||||
}
|
|
||||||
|
|
||||||
static ssize_t store_tmin(struct device *dev,
|
|
||||||
struct device_attribute *devattr,
|
|
||||||
const char *buf, size_t count)
|
|
||||||
{
|
|
||||||
struct platform_data *pdata = dev_get_drvdata(dev);
|
|
||||||
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
|
|
||||||
struct temp_data *tdata = pdata->core_data[attr->index];
|
|
||||||
u32 eax, edx;
|
|
||||||
unsigned long val;
|
|
||||||
int diff;
|
|
||||||
|
|
||||||
if (strict_strtoul(buf, 10, &val))
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* THERM_MASK_THRESHOLD0 is 7 bits wide. Values are entered in terms
|
|
||||||
* of milli degree celsius. Hence don't accept val > (127 * 1000)
|
|
||||||
*/
|
|
||||||
if (val > tdata->tjmax || val > 127000)
|
|
||||||
return -EINVAL;
|
|
||||||
|
|
||||||
diff = (tdata->tjmax - val) / 1000;
|
|
||||||
|
|
||||||
mutex_lock(&tdata->update_lock);
|
|
||||||
rdmsr_on_cpu(tdata->cpu, tdata->intrpt_reg, &eax, &edx);
|
|
||||||
eax = (eax & ~THERM_MASK_THRESHOLD0) |
|
|
||||||
(diff << THERM_SHIFT_THRESHOLD0);
|
|
||||||
wrmsr_on_cpu(tdata->cpu, tdata->intrpt_reg, eax, edx);
|
|
||||||
tdata->tmin = val;
|
|
||||||
mutex_unlock(&tdata->update_lock);
|
|
||||||
|
|
||||||
return count;
|
|
||||||
}
|
|
||||||
|
|
||||||
static ssize_t show_temp(struct device *dev,
|
static ssize_t show_temp(struct device *dev,
|
||||||
struct device_attribute *devattr, char *buf)
|
struct device_attribute *devattr, char *buf)
|
||||||
{
|
{
|
||||||
|
@ -374,7 +288,6 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
|
||||||
|
|
||||||
static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
|
static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
|
||||||
{
|
{
|
||||||
/* The 100C is default for both mobile and non mobile CPUs */
|
|
||||||
int err;
|
int err;
|
||||||
u32 eax, edx;
|
u32 eax, edx;
|
||||||
u32 val;
|
u32 val;
|
||||||
|
@ -385,7 +298,8 @@ static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
|
||||||
*/
|
*/
|
||||||
err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
|
err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
|
||||||
if (err) {
|
if (err) {
|
||||||
dev_warn(dev, "Unable to read TjMax from CPU.\n");
|
if (c->x86_model > 0xe && c->x86_model != 0x1c)
|
||||||
|
dev_warn(dev, "Unable to read TjMax from CPU %u\n", id);
|
||||||
} else {
|
} else {
|
||||||
val = (eax >> 16) & 0xff;
|
val = (eax >> 16) & 0xff;
|
||||||
/*
|
/*
|
||||||
|
@ -393,11 +307,17 @@ static int get_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
|
||||||
* will be used
|
* will be used
|
||||||
*/
|
*/
|
||||||
if (val) {
|
if (val) {
|
||||||
dev_info(dev, "TjMax is %d C.\n", val);
|
dev_dbg(dev, "TjMax is %d degrees C\n", val);
|
||||||
return val * 1000;
|
return val * 1000;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (force_tjmax) {
|
||||||
|
dev_notice(dev, "TjMax forced to %d degrees C by user\n",
|
||||||
|
force_tjmax);
|
||||||
|
return force_tjmax * 1000;
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* An assumption is made for early CPUs and unreadable MSR.
|
* An assumption is made for early CPUs and unreadable MSR.
|
||||||
* NOTE: the calculated value may not be correct.
|
* NOTE: the calculated value may not be correct.
|
||||||
|
@ -414,21 +334,6 @@ static void __devinit get_ucode_rev_on_cpu(void *edx)
|
||||||
rdmsr(MSR_IA32_UCODE_REV, eax, *(u32 *)edx);
|
rdmsr(MSR_IA32_UCODE_REV, eax, *(u32 *)edx);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int get_pkg_tjmax(unsigned int cpu, struct device *dev)
|
|
||||||
{
|
|
||||||
int err;
|
|
||||||
u32 eax, edx, val;
|
|
||||||
|
|
||||||
err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
|
|
||||||
if (!err) {
|
|
||||||
val = (eax >> 16) & 0xff;
|
|
||||||
if (val)
|
|
||||||
return val * 1000;
|
|
||||||
}
|
|
||||||
dev_warn(dev, "Unable to read Pkg-TjMax from CPU:%u\n", cpu);
|
|
||||||
return 100000; /* Default TjMax: 100 degree celsius */
|
|
||||||
}
|
|
||||||
|
|
||||||
static int create_name_attr(struct platform_data *pdata, struct device *dev)
|
static int create_name_attr(struct platform_data *pdata, struct device *dev)
|
||||||
{
|
{
|
||||||
sysfs_attr_init(&pdata->name_attr.attr);
|
sysfs_attr_init(&pdata->name_attr.attr);
|
||||||
|
@ -442,19 +347,14 @@ static int create_core_attrs(struct temp_data *tdata, struct device *dev,
|
||||||
int attr_no)
|
int attr_no)
|
||||||
{
|
{
|
||||||
int err, i;
|
int err, i;
|
||||||
static ssize_t (*rd_ptr[TOTAL_ATTRS]) (struct device *dev,
|
static ssize_t (*const rd_ptr[TOTAL_ATTRS]) (struct device *dev,
|
||||||
struct device_attribute *devattr, char *buf) = {
|
struct device_attribute *devattr, char *buf) = {
|
||||||
show_label, show_crit_alarm, show_temp, show_tjmax,
|
show_label, show_crit_alarm, show_temp, show_tjmax,
|
||||||
show_max_alarm, show_ttarget, show_tmin };
|
show_ttarget };
|
||||||
static ssize_t (*rw_ptr[TOTAL_ATTRS]) (struct device *dev,
|
static const char *const names[TOTAL_ATTRS] = {
|
||||||
struct device_attribute *devattr, const char *buf,
|
|
||||||
size_t count) = { NULL, NULL, NULL, NULL, NULL,
|
|
||||||
store_ttarget, store_tmin };
|
|
||||||
static const char *names[TOTAL_ATTRS] = {
|
|
||||||
"temp%d_label", "temp%d_crit_alarm",
|
"temp%d_label", "temp%d_crit_alarm",
|
||||||
"temp%d_input", "temp%d_crit",
|
"temp%d_input", "temp%d_crit",
|
||||||
"temp%d_max_alarm", "temp%d_max",
|
"temp%d_max" };
|
||||||
"temp%d_max_hyst" };
|
|
||||||
|
|
||||||
for (i = 0; i < tdata->attr_size; i++) {
|
for (i = 0; i < tdata->attr_size; i++) {
|
||||||
snprintf(tdata->attr_name[i], CORETEMP_NAME_LENGTH, names[i],
|
snprintf(tdata->attr_name[i], CORETEMP_NAME_LENGTH, names[i],
|
||||||
|
@ -462,10 +362,6 @@ static int create_core_attrs(struct temp_data *tdata, struct device *dev,
|
||||||
sysfs_attr_init(&tdata->sd_attrs[i].dev_attr.attr);
|
sysfs_attr_init(&tdata->sd_attrs[i].dev_attr.attr);
|
||||||
tdata->sd_attrs[i].dev_attr.attr.name = tdata->attr_name[i];
|
tdata->sd_attrs[i].dev_attr.attr.name = tdata->attr_name[i];
|
||||||
tdata->sd_attrs[i].dev_attr.attr.mode = S_IRUGO;
|
tdata->sd_attrs[i].dev_attr.attr.mode = S_IRUGO;
|
||||||
if (rw_ptr[i]) {
|
|
||||||
tdata->sd_attrs[i].dev_attr.attr.mode |= S_IWUSR;
|
|
||||||
tdata->sd_attrs[i].dev_attr.store = rw_ptr[i];
|
|
||||||
}
|
|
||||||
tdata->sd_attrs[i].dev_attr.show = rd_ptr[i];
|
tdata->sd_attrs[i].dev_attr.show = rd_ptr[i];
|
||||||
tdata->sd_attrs[i].index = attr_no;
|
tdata->sd_attrs[i].index = attr_no;
|
||||||
err = device_create_file(dev, &tdata->sd_attrs[i].dev_attr);
|
err = device_create_file(dev, &tdata->sd_attrs[i].dev_attr);
|
||||||
|
@ -481,9 +377,9 @@ static int create_core_attrs(struct temp_data *tdata, struct device *dev,
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
static int __devinit chk_ucode_version(struct platform_device *pdev)
|
static int __cpuinit chk_ucode_version(unsigned int cpu)
|
||||||
{
|
{
|
||||||
struct cpuinfo_x86 *c = &cpu_data(pdev->id);
|
struct cpuinfo_x86 *c = &cpu_data(cpu);
|
||||||
int err;
|
int err;
|
||||||
u32 edx;
|
u32 edx;
|
||||||
|
|
||||||
|
@ -494,17 +390,15 @@ static int __devinit chk_ucode_version(struct platform_device *pdev)
|
||||||
*/
|
*/
|
||||||
if (c->x86_model == 0xe && c->x86_mask < 0xc) {
|
if (c->x86_model == 0xe && c->x86_mask < 0xc) {
|
||||||
/* check for microcode update */
|
/* check for microcode update */
|
||||||
err = smp_call_function_single(pdev->id, get_ucode_rev_on_cpu,
|
err = smp_call_function_single(cpu, get_ucode_rev_on_cpu,
|
||||||
&edx, 1);
|
&edx, 1);
|
||||||
if (err) {
|
if (err) {
|
||||||
dev_err(&pdev->dev,
|
pr_err("Cannot determine microcode revision of "
|
||||||
"Cannot determine microcode revision of "
|
"CPU#%u (%d)!\n", cpu, err);
|
||||||
"CPU#%u (%d)!\n", pdev->id, err);
|
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
} else if (edx < 0x39) {
|
} else if (edx < 0x39) {
|
||||||
dev_err(&pdev->dev,
|
pr_err("Errata AE18 not fixed, update BIOS or "
|
||||||
"Errata AE18 not fixed, update BIOS or "
|
"microcode of the CPU!\n");
|
||||||
"microcode of the CPU!\n");
|
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -538,8 +432,6 @@ static struct temp_data *init_temp_data(unsigned int cpu, int pkg_flag)
|
||||||
|
|
||||||
tdata->status_reg = pkg_flag ? MSR_IA32_PACKAGE_THERM_STATUS :
|
tdata->status_reg = pkg_flag ? MSR_IA32_PACKAGE_THERM_STATUS :
|
||||||
MSR_IA32_THERM_STATUS;
|
MSR_IA32_THERM_STATUS;
|
||||||
tdata->intrpt_reg = pkg_flag ? MSR_IA32_PACKAGE_THERM_INTERRUPT :
|
|
||||||
MSR_IA32_THERM_INTERRUPT;
|
|
||||||
tdata->is_pkg_data = pkg_flag;
|
tdata->is_pkg_data = pkg_flag;
|
||||||
tdata->cpu = cpu;
|
tdata->cpu = cpu;
|
||||||
tdata->cpu_core_id = TO_CORE_ID(cpu);
|
tdata->cpu_core_id = TO_CORE_ID(cpu);
|
||||||
|
@ -548,11 +440,11 @@ static struct temp_data *init_temp_data(unsigned int cpu, int pkg_flag)
|
||||||
return tdata;
|
return tdata;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int create_core_data(struct platform_data *pdata,
|
static int create_core_data(struct platform_device *pdev,
|
||||||
struct platform_device *pdev,
|
|
||||||
unsigned int cpu, int pkg_flag)
|
unsigned int cpu, int pkg_flag)
|
||||||
{
|
{
|
||||||
struct temp_data *tdata;
|
struct temp_data *tdata;
|
||||||
|
struct platform_data *pdata = platform_get_drvdata(pdev);
|
||||||
struct cpuinfo_x86 *c = &cpu_data(cpu);
|
struct cpuinfo_x86 *c = &cpu_data(cpu);
|
||||||
u32 eax, edx;
|
u32 eax, edx;
|
||||||
int err, attr_no;
|
int err, attr_no;
|
||||||
|
@ -588,25 +480,21 @@ static int create_core_data(struct platform_data *pdata,
|
||||||
goto exit_free;
|
goto exit_free;
|
||||||
|
|
||||||
/* We can access status register. Get Critical Temperature */
|
/* We can access status register. Get Critical Temperature */
|
||||||
if (pkg_flag)
|
tdata->tjmax = get_tjmax(c, cpu, &pdev->dev);
|
||||||
tdata->tjmax = get_pkg_tjmax(pdev->id, &pdev->dev);
|
|
||||||
else
|
|
||||||
tdata->tjmax = get_tjmax(c, cpu, &pdev->dev);
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Test if we can access the intrpt register. If so, increase the
|
* Read the still undocumented bits 8:15 of IA32_TEMPERATURE_TARGET.
|
||||||
* 'size' enough to have ttarget/tmin/max_alarm interfaces.
|
* The target temperature is available on older CPUs but not in this
|
||||||
* Initialize ttarget with bits 16:22 of MSR_IA32_THERM_INTERRUPT
|
* register. Atoms don't have the register at all.
|
||||||
*/
|
*/
|
||||||
err = rdmsr_safe_on_cpu(cpu, tdata->intrpt_reg, &eax, &edx);
|
if (c->x86_model > 0xe && c->x86_model != 0x1c) {
|
||||||
if (!err) {
|
err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET,
|
||||||
tdata->attr_size += MAX_THRESH_ATTRS;
|
&eax, &edx);
|
||||||
tdata->tmin = tdata->tjmax -
|
if (!err) {
|
||||||
((eax & THERM_MASK_THRESHOLD0) >>
|
tdata->ttarget
|
||||||
THERM_SHIFT_THRESHOLD0) * 1000;
|
= tdata->tjmax - ((eax >> 8) & 0xff) * 1000;
|
||||||
tdata->ttarget = tdata->tjmax -
|
tdata->attr_size++;
|
||||||
((eax & THERM_MASK_THRESHOLD1) >>
|
}
|
||||||
THERM_SHIFT_THRESHOLD1) * 1000;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
pdata->core_data[attr_no] = tdata;
|
pdata->core_data[attr_no] = tdata;
|
||||||
|
@ -618,22 +506,20 @@ static int create_core_data(struct platform_data *pdata,
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
exit_free:
|
exit_free:
|
||||||
|
pdata->core_data[attr_no] = NULL;
|
||||||
kfree(tdata);
|
kfree(tdata);
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void coretemp_add_core(unsigned int cpu, int pkg_flag)
|
static void coretemp_add_core(unsigned int cpu, int pkg_flag)
|
||||||
{
|
{
|
||||||
struct platform_data *pdata;
|
|
||||||
struct platform_device *pdev = coretemp_get_pdev(cpu);
|
struct platform_device *pdev = coretemp_get_pdev(cpu);
|
||||||
int err;
|
int err;
|
||||||
|
|
||||||
if (!pdev)
|
if (!pdev)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
pdata = platform_get_drvdata(pdev);
|
err = create_core_data(pdev, cpu, pkg_flag);
|
||||||
|
|
||||||
err = create_core_data(pdata, pdev, cpu, pkg_flag);
|
|
||||||
if (err)
|
if (err)
|
||||||
dev_err(&pdev->dev, "Adding Core %u failed\n", cpu);
|
dev_err(&pdev->dev, "Adding Core %u failed\n", cpu);
|
||||||
}
|
}
|
||||||
|
@ -657,11 +543,6 @@ static int __devinit coretemp_probe(struct platform_device *pdev)
|
||||||
struct platform_data *pdata;
|
struct platform_data *pdata;
|
||||||
int err;
|
int err;
|
||||||
|
|
||||||
/* Check the microcode version of the CPU */
|
|
||||||
err = chk_ucode_version(pdev);
|
|
||||||
if (err)
|
|
||||||
return err;
|
|
||||||
|
|
||||||
/* Initialize the per-package data structures */
|
/* Initialize the per-package data structures */
|
||||||
pdata = kzalloc(sizeof(struct platform_data), GFP_KERNEL);
|
pdata = kzalloc(sizeof(struct platform_data), GFP_KERNEL);
|
||||||
if (!pdata)
|
if (!pdata)
|
||||||
|
@ -671,7 +552,7 @@ static int __devinit coretemp_probe(struct platform_device *pdev)
|
||||||
if (err)
|
if (err)
|
||||||
goto exit_free;
|
goto exit_free;
|
||||||
|
|
||||||
pdata->phys_proc_id = TO_PHYS_ID(pdev->id);
|
pdata->phys_proc_id = pdev->id;
|
||||||
platform_set_drvdata(pdev, pdata);
|
platform_set_drvdata(pdev, pdata);
|
||||||
|
|
||||||
pdata->hwmon_dev = hwmon_device_register(&pdev->dev);
|
pdata->hwmon_dev = hwmon_device_register(&pdev->dev);
|
||||||
|
@ -723,7 +604,7 @@ static int __cpuinit coretemp_device_add(unsigned int cpu)
|
||||||
|
|
||||||
mutex_lock(&pdev_list_mutex);
|
mutex_lock(&pdev_list_mutex);
|
||||||
|
|
||||||
pdev = platform_device_alloc(DRVNAME, cpu);
|
pdev = platform_device_alloc(DRVNAME, TO_PHYS_ID(cpu));
|
||||||
if (!pdev) {
|
if (!pdev) {
|
||||||
err = -ENOMEM;
|
err = -ENOMEM;
|
||||||
pr_err("Device allocation failed\n");
|
pr_err("Device allocation failed\n");
|
||||||
|
@ -743,7 +624,7 @@ static int __cpuinit coretemp_device_add(unsigned int cpu)
|
||||||
}
|
}
|
||||||
|
|
||||||
pdev_entry->pdev = pdev;
|
pdev_entry->pdev = pdev;
|
||||||
pdev_entry->phys_proc_id = TO_PHYS_ID(cpu);
|
pdev_entry->phys_proc_id = pdev->id;
|
||||||
|
|
||||||
list_add_tail(&pdev_entry->list, &pdev_list);
|
list_add_tail(&pdev_entry->list, &pdev_list);
|
||||||
mutex_unlock(&pdev_list_mutex);
|
mutex_unlock(&pdev_list_mutex);
|
||||||
|
@ -804,6 +685,10 @@ static void __cpuinit get_core_online(unsigned int cpu)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
if (!pdev) {
|
if (!pdev) {
|
||||||
|
/* Check the microcode version of the CPU */
|
||||||
|
if (chk_ucode_version(cpu))
|
||||||
|
return;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Alright, we have DTS support.
|
* Alright, we have DTS support.
|
||||||
* We are bringing the _first_ core in this pkg
|
* We are bringing the _first_ core in this pkg
|
||||||
|
|
|
@ -72,7 +72,7 @@ struct ds620_data {
|
||||||
char valid; /* !=0 if following fields are valid */
|
char valid; /* !=0 if following fields are valid */
|
||||||
unsigned long last_updated; /* In jiffies */
|
unsigned long last_updated; /* In jiffies */
|
||||||
|
|
||||||
u16 temp[3]; /* Register values, word */
|
s16 temp[3]; /* Register values, word */
|
||||||
};
|
};
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -329,8 +329,8 @@ static int w83791d_detect(struct i2c_client *client,
|
||||||
struct i2c_board_info *info);
|
struct i2c_board_info *info);
|
||||||
static int w83791d_remove(struct i2c_client *client);
|
static int w83791d_remove(struct i2c_client *client);
|
||||||
|
|
||||||
static int w83791d_read(struct i2c_client *client, u8 register);
|
static int w83791d_read(struct i2c_client *client, u8 reg);
|
||||||
static int w83791d_write(struct i2c_client *client, u8 register, u8 value);
|
static int w83791d_write(struct i2c_client *client, u8 reg, u8 value);
|
||||||
static struct w83791d_data *w83791d_update_device(struct device *dev);
|
static struct w83791d_data *w83791d_update_device(struct device *dev);
|
||||||
|
|
||||||
#ifdef DEBUG
|
#ifdef DEBUG
|
||||||
|
|
|
@ -435,7 +435,12 @@ static int idedisk_prep_fn(struct request_queue *q, struct request *rq)
|
||||||
if (!(rq->cmd_flags & REQ_FLUSH))
|
if (!(rq->cmd_flags & REQ_FLUSH))
|
||||||
return BLKPREP_OK;
|
return BLKPREP_OK;
|
||||||
|
|
||||||
cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
|
if (rq->special) {
|
||||||
|
cmd = rq->special;
|
||||||
|
memset(cmd, 0, sizeof(*cmd));
|
||||||
|
} else {
|
||||||
|
cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
|
||||||
|
}
|
||||||
|
|
||||||
/* FIXME: map struct ide_taskfile on rq->cmd[] */
|
/* FIXME: map struct ide_taskfile on rq->cmd[] */
|
||||||
BUG_ON(cmd == NULL);
|
BUG_ON(cmd == NULL);
|
||||||
|
|
|
@ -287,7 +287,7 @@ void __free_ep(struct kref *kref)
|
||||||
if (test_bit(RELEASE_RESOURCES, &ep->com.flags)) {
|
if (test_bit(RELEASE_RESOURCES, &ep->com.flags)) {
|
||||||
cxgb3_remove_tid(ep->com.tdev, (void *)ep, ep->hwtid);
|
cxgb3_remove_tid(ep->com.tdev, (void *)ep, ep->hwtid);
|
||||||
dst_release(ep->dst);
|
dst_release(ep->dst);
|
||||||
l2t_release(L2DATA(ep->com.tdev), ep->l2t);
|
l2t_release(ep->com.tdev, ep->l2t);
|
||||||
}
|
}
|
||||||
kfree(ep);
|
kfree(ep);
|
||||||
}
|
}
|
||||||
|
@ -1178,7 +1178,7 @@ static int act_open_rpl(struct t3cdev *tdev, struct sk_buff *skb, void *ctx)
|
||||||
release_tid(ep->com.tdev, GET_TID(rpl), NULL);
|
release_tid(ep->com.tdev, GET_TID(rpl), NULL);
|
||||||
cxgb3_free_atid(ep->com.tdev, ep->atid);
|
cxgb3_free_atid(ep->com.tdev, ep->atid);
|
||||||
dst_release(ep->dst);
|
dst_release(ep->dst);
|
||||||
l2t_release(L2DATA(ep->com.tdev), ep->l2t);
|
l2t_release(ep->com.tdev, ep->l2t);
|
||||||
put_ep(&ep->com);
|
put_ep(&ep->com);
|
||||||
return CPL_RET_BUF_DONE;
|
return CPL_RET_BUF_DONE;
|
||||||
}
|
}
|
||||||
|
@ -1377,7 +1377,7 @@ static int pass_accept_req(struct t3cdev *tdev, struct sk_buff *skb, void *ctx)
|
||||||
if (!child_ep) {
|
if (!child_ep) {
|
||||||
printk(KERN_ERR MOD "%s - failed to allocate ep entry!\n",
|
printk(KERN_ERR MOD "%s - failed to allocate ep entry!\n",
|
||||||
__func__);
|
__func__);
|
||||||
l2t_release(L2DATA(tdev), l2t);
|
l2t_release(tdev, l2t);
|
||||||
dst_release(dst);
|
dst_release(dst);
|
||||||
goto reject;
|
goto reject;
|
||||||
}
|
}
|
||||||
|
@ -1956,7 +1956,7 @@ int iwch_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
|
||||||
if (!err)
|
if (!err)
|
||||||
goto out;
|
goto out;
|
||||||
|
|
||||||
l2t_release(L2DATA(h->rdev.t3cdev_p), ep->l2t);
|
l2t_release(h->rdev.t3cdev_p, ep->l2t);
|
||||||
fail4:
|
fail4:
|
||||||
dst_release(ep->dst);
|
dst_release(ep->dst);
|
||||||
fail3:
|
fail3:
|
||||||
|
@ -2127,7 +2127,7 @@ int iwch_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
|
||||||
PDBG("%s ep %p redirect to dst %p l2t %p\n", __func__, ep, new,
|
PDBG("%s ep %p redirect to dst %p l2t %p\n", __func__, ep, new,
|
||||||
l2t);
|
l2t);
|
||||||
dst_hold(new);
|
dst_hold(new);
|
||||||
l2t_release(L2DATA(ep->com.tdev), ep->l2t);
|
l2t_release(ep->com.tdev, ep->l2t);
|
||||||
ep->l2t = l2t;
|
ep->l2t = l2t;
|
||||||
dst_release(old);
|
dst_release(old);
|
||||||
ep->dst = new;
|
ep->dst = new;
|
||||||
|
|
|
@ -2194,19 +2194,6 @@ static int __init omap_vout_probe(struct platform_device *pdev)
|
||||||
"'%s' Display already enabled\n",
|
"'%s' Display already enabled\n",
|
||||||
def_display->name);
|
def_display->name);
|
||||||
}
|
}
|
||||||
/* set the update mode */
|
|
||||||
if (def_display->caps &
|
|
||||||
OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
|
|
||||||
if (dssdrv->enable_te)
|
|
||||||
dssdrv->enable_te(def_display, 0);
|
|
||||||
if (dssdrv->set_update_mode)
|
|
||||||
dssdrv->set_update_mode(def_display,
|
|
||||||
OMAP_DSS_UPDATE_MANUAL);
|
|
||||||
} else {
|
|
||||||
if (dssdrv->set_update_mode)
|
|
||||||
dssdrv->set_update_mode(def_display,
|
|
||||||
OMAP_DSS_UPDATE_AUTO);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -31,6 +31,7 @@
|
||||||
#include <linux/dma-mapping.h>
|
#include <linux/dma-mapping.h>
|
||||||
#include <linux/mm.h>
|
#include <linux/mm.h>
|
||||||
#include <linux/sched.h>
|
#include <linux/sched.h>
|
||||||
|
#include <linux/slab.h>
|
||||||
#include <media/v4l2-event.h>
|
#include <media/v4l2-event.h>
|
||||||
|
|
||||||
#include "isp.h"
|
#include "isp.h"
|
||||||
|
|
|
@ -1961,7 +1961,7 @@ static int __uvc_resume(struct usb_interface *intf, int reset)
|
||||||
|
|
||||||
list_for_each_entry(stream, &dev->streams, list) {
|
list_for_each_entry(stream, &dev->streams, list) {
|
||||||
if (stream->intf == intf)
|
if (stream->intf == intf)
|
||||||
return uvc_video_resume(stream);
|
return uvc_video_resume(stream, reset);
|
||||||
}
|
}
|
||||||
|
|
||||||
uvc_trace(UVC_TRACE_SUSPEND, "Resume: video streaming USB interface "
|
uvc_trace(UVC_TRACE_SUSPEND, "Resume: video streaming USB interface "
|
||||||
|
|
|
@ -49,7 +49,7 @@ static int uvc_mc_register_entity(struct uvc_video_chain *chain,
|
||||||
if (remote == NULL)
|
if (remote == NULL)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
source = (UVC_ENTITY_TYPE(remote) != UVC_TT_STREAMING)
|
source = (UVC_ENTITY_TYPE(remote) == UVC_TT_STREAMING)
|
||||||
? (remote->vdev ? &remote->vdev->entity : NULL)
|
? (remote->vdev ? &remote->vdev->entity : NULL)
|
||||||
: &remote->subdev.entity;
|
: &remote->subdev.entity;
|
||||||
if (source == NULL)
|
if (source == NULL)
|
||||||
|
|
|
@ -1104,10 +1104,18 @@ int uvc_video_suspend(struct uvc_streaming *stream)
|
||||||
* buffers, making sure userspace applications are notified of the problem
|
* buffers, making sure userspace applications are notified of the problem
|
||||||
* instead of waiting forever.
|
* instead of waiting forever.
|
||||||
*/
|
*/
|
||||||
int uvc_video_resume(struct uvc_streaming *stream)
|
int uvc_video_resume(struct uvc_streaming *stream, int reset)
|
||||||
{
|
{
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
|
/* If the bus has been reset on resume, set the alternate setting to 0.
|
||||||
|
* This should be the default value, but some devices crash or otherwise
|
||||||
|
* misbehave if they don't receive a SET_INTERFACE request before any
|
||||||
|
* other video control request.
|
||||||
|
*/
|
||||||
|
if (reset)
|
||||||
|
usb_set_interface(stream->dev->udev, stream->intfnum, 0);
|
||||||
|
|
||||||
stream->frozen = 0;
|
stream->frozen = 0;
|
||||||
|
|
||||||
ret = uvc_commit_video(stream, &stream->ctrl);
|
ret = uvc_commit_video(stream, &stream->ctrl);
|
||||||
|
|
|
@ -638,7 +638,7 @@ extern void uvc_mc_cleanup_entity(struct uvc_entity *entity);
|
||||||
/* Video */
|
/* Video */
|
||||||
extern int uvc_video_init(struct uvc_streaming *stream);
|
extern int uvc_video_init(struct uvc_streaming *stream);
|
||||||
extern int uvc_video_suspend(struct uvc_streaming *stream);
|
extern int uvc_video_suspend(struct uvc_streaming *stream);
|
||||||
extern int uvc_video_resume(struct uvc_streaming *stream);
|
extern int uvc_video_resume(struct uvc_streaming *stream, int reset);
|
||||||
extern int uvc_video_enable(struct uvc_streaming *stream, int enable);
|
extern int uvc_video_enable(struct uvc_streaming *stream, int enable);
|
||||||
extern int uvc_probe_video(struct uvc_streaming *stream,
|
extern int uvc_probe_video(struct uvc_streaming *stream,
|
||||||
struct uvc_streaming_control *probe);
|
struct uvc_streaming_control *probe);
|
||||||
|
|
|
@ -173,6 +173,17 @@ static void v4l2_device_release(struct device *cd)
|
||||||
media_device_unregister_entity(&vdev->entity);
|
media_device_unregister_entity(&vdev->entity);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/* Do not call v4l2_device_put if there is no release callback set.
|
||||||
|
* Drivers that have no v4l2_device release callback might free the
|
||||||
|
* v4l2_dev instance in the video_device release callback below, so we
|
||||||
|
* must perform this check here.
|
||||||
|
*
|
||||||
|
* TODO: In the long run all drivers that use v4l2_device should use the
|
||||||
|
* v4l2_device release callback. This check will then be unnecessary.
|
||||||
|
*/
|
||||||
|
if (v4l2_dev->release == NULL)
|
||||||
|
v4l2_dev = NULL;
|
||||||
|
|
||||||
/* Release video_device and perform other
|
/* Release video_device and perform other
|
||||||
cleanups as needed. */
|
cleanups as needed. */
|
||||||
vdev->release(vdev);
|
vdev->release(vdev);
|
||||||
|
|
|
@ -38,6 +38,7 @@ int v4l2_device_register(struct device *dev, struct v4l2_device *v4l2_dev)
|
||||||
mutex_init(&v4l2_dev->ioctl_lock);
|
mutex_init(&v4l2_dev->ioctl_lock);
|
||||||
v4l2_prio_init(&v4l2_dev->prio);
|
v4l2_prio_init(&v4l2_dev->prio);
|
||||||
kref_init(&v4l2_dev->ref);
|
kref_init(&v4l2_dev->ref);
|
||||||
|
get_device(dev);
|
||||||
v4l2_dev->dev = dev;
|
v4l2_dev->dev = dev;
|
||||||
if (dev == NULL) {
|
if (dev == NULL) {
|
||||||
/* If dev == NULL, then name must be filled in by the caller */
|
/* If dev == NULL, then name must be filled in by the caller */
|
||||||
|
@ -93,6 +94,7 @@ void v4l2_device_disconnect(struct v4l2_device *v4l2_dev)
|
||||||
|
|
||||||
if (dev_get_drvdata(v4l2_dev->dev) == v4l2_dev)
|
if (dev_get_drvdata(v4l2_dev->dev) == v4l2_dev)
|
||||||
dev_set_drvdata(v4l2_dev->dev, NULL);
|
dev_set_drvdata(v4l2_dev->dev, NULL);
|
||||||
|
put_device(v4l2_dev->dev);
|
||||||
v4l2_dev->dev = NULL;
|
v4l2_dev->dev = NULL;
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL_GPL(v4l2_device_disconnect);
|
EXPORT_SYMBOL_GPL(v4l2_device_disconnect);
|
||||||
|
|
|
@ -273,7 +273,7 @@ static int __devinit jz4740_adc_probe(struct platform_device *pdev)
|
||||||
ct->regs.ack = JZ_REG_ADC_STATUS;
|
ct->regs.ack = JZ_REG_ADC_STATUS;
|
||||||
ct->chip.irq_mask = irq_gc_mask_set_bit;
|
ct->chip.irq_mask = irq_gc_mask_set_bit;
|
||||||
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
|
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
|
||||||
ct->chip.irq_ack = irq_gc_ack;
|
ct->chip.irq_ack = irq_gc_ack_set_bit;
|
||||||
|
|
||||||
irq_setup_generic_chip(gc, IRQ_MSK(5), 0, 0, IRQ_NOPROBE | IRQ_LEVEL);
|
irq_setup_generic_chip(gc, IRQ_MSK(5), 0, 0, IRQ_NOPROBE | IRQ_LEVEL);
|
||||||
|
|
||||||
|
|
|
@ -375,12 +375,14 @@ void lis3lv02d_poweron(struct lis3lv02d *lis3)
|
||||||
* both have been read. So the value read will always be correct.
|
* both have been read. So the value read will always be correct.
|
||||||
* Set BOOT bit to refresh factory tuning values.
|
* Set BOOT bit to refresh factory tuning values.
|
||||||
*/
|
*/
|
||||||
lis3->read(lis3, CTRL_REG2, ®);
|
if (lis3->pdata) {
|
||||||
if (lis3->whoami == WAI_12B)
|
lis3->read(lis3, CTRL_REG2, ®);
|
||||||
reg |= CTRL2_BDU | CTRL2_BOOT;
|
if (lis3->whoami == WAI_12B)
|
||||||
else
|
reg |= CTRL2_BDU | CTRL2_BOOT;
|
||||||
reg |= CTRL2_BOOT_8B;
|
else
|
||||||
lis3->write(lis3, CTRL_REG2, reg);
|
reg |= CTRL2_BOOT_8B;
|
||||||
|
lis3->write(lis3, CTRL_REG2, reg);
|
||||||
|
}
|
||||||
|
|
||||||
/* LIS3 power on delay is quite long */
|
/* LIS3 power on delay is quite long */
|
||||||
msleep(lis3->pwron_delay / lis3lv02d_get_odr());
|
msleep(lis3->pwron_delay / lis3lv02d_get_odr());
|
||||||
|
|
|
@ -2120,6 +2120,7 @@ static u8 bnx2x_dcbnl_get_cap(struct net_device *netdev, int capid, u8 *cap)
|
||||||
break;
|
break;
|
||||||
case DCB_CAP_ATTR_DCBX:
|
case DCB_CAP_ATTR_DCBX:
|
||||||
*cap = BNX2X_DCBX_CAPS;
|
*cap = BNX2X_DCBX_CAPS;
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
rval = -EINVAL;
|
rval = -EINVAL;
|
||||||
break;
|
break;
|
||||||
|
|
|
@ -4943,7 +4943,7 @@ static void bnx2x_init_def_sb(struct bnx2x *bp)
|
||||||
int igu_seg_id;
|
int igu_seg_id;
|
||||||
int port = BP_PORT(bp);
|
int port = BP_PORT(bp);
|
||||||
int func = BP_FUNC(bp);
|
int func = BP_FUNC(bp);
|
||||||
int reg_offset;
|
int reg_offset, reg_offset_en5;
|
||||||
u64 section;
|
u64 section;
|
||||||
int index;
|
int index;
|
||||||
struct hc_sp_status_block_data sp_sb_data;
|
struct hc_sp_status_block_data sp_sb_data;
|
||||||
|
@ -4966,6 +4966,8 @@ static void bnx2x_init_def_sb(struct bnx2x *bp)
|
||||||
|
|
||||||
reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
|
reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
|
||||||
MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
|
MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
|
||||||
|
reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
|
||||||
|
MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
|
||||||
for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
|
for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
|
||||||
int sindex;
|
int sindex;
|
||||||
/* take care of sig[0]..sig[4] */
|
/* take care of sig[0]..sig[4] */
|
||||||
|
@ -4980,7 +4982,7 @@ static void bnx2x_init_def_sb(struct bnx2x *bp)
|
||||||
* and not 16 between the different groups
|
* and not 16 between the different groups
|
||||||
*/
|
*/
|
||||||
bp->attn_group[index].sig[4] = REG_RD(bp,
|
bp->attn_group[index].sig[4] = REG_RD(bp,
|
||||||
reg_offset + 0x10 + 0x4*index);
|
reg_offset_en5 + 0x4*index);
|
||||||
else
|
else
|
||||||
bp->attn_group[index].sig[4] = 0;
|
bp->attn_group[index].sig[4] = 0;
|
||||||
}
|
}
|
||||||
|
@ -7625,8 +7627,11 @@ u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
|
||||||
u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
|
u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
|
||||||
u8 *mac_addr = bp->dev->dev_addr;
|
u8 *mac_addr = bp->dev->dev_addr;
|
||||||
u32 val;
|
u32 val;
|
||||||
|
u16 pmc;
|
||||||
|
|
||||||
/* The mac address is written to entries 1-4 to
|
/* The mac address is written to entries 1-4 to
|
||||||
preserve entry 0 which is used by the PMF */
|
* preserve entry 0 which is used by the PMF
|
||||||
|
*/
|
||||||
u8 entry = (BP_VN(bp) + 1)*8;
|
u8 entry = (BP_VN(bp) + 1)*8;
|
||||||
|
|
||||||
val = (mac_addr[0] << 8) | mac_addr[1];
|
val = (mac_addr[0] << 8) | mac_addr[1];
|
||||||
|
@ -7636,6 +7641,11 @@ u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
|
||||||
(mac_addr[4] << 8) | mac_addr[5];
|
(mac_addr[4] << 8) | mac_addr[5];
|
||||||
EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
|
EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
|
||||||
|
|
||||||
|
/* Enable the PME and clear the status */
|
||||||
|
pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
|
||||||
|
pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
|
||||||
|
pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
|
||||||
|
|
||||||
reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
|
reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
|
||||||
|
|
||||||
} else
|
} else
|
||||||
|
|
|
@ -1384,6 +1384,18 @@
|
||||||
Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
|
Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
|
||||||
#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
|
#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
|
||||||
#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
|
#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
|
||||||
|
/* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped
|
||||||
|
* as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
|
||||||
|
* attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
|
||||||
|
* mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
|
||||||
|
* parity; [31-10] Reserved; */
|
||||||
|
#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688
|
||||||
|
/* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped
|
||||||
|
* as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
|
||||||
|
* attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
|
||||||
|
* mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
|
||||||
|
* parity; [31-10] Reserved; */
|
||||||
|
#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0
|
||||||
/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
|
/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
|
||||||
128 bit vector */
|
128 bit vector */
|
||||||
#define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
|
#define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
|
||||||
|
|
|
@ -2168,7 +2168,8 @@ void bond_3ad_state_machine_handler(struct work_struct *work)
|
||||||
}
|
}
|
||||||
|
|
||||||
re_arm:
|
re_arm:
|
||||||
queue_delayed_work(bond->wq, &bond->ad_work, ad_delta_in_ticks);
|
if (!bond->kill_timers)
|
||||||
|
queue_delayed_work(bond->wq, &bond->ad_work, ad_delta_in_ticks);
|
||||||
out:
|
out:
|
||||||
read_unlock(&bond->lock);
|
read_unlock(&bond->lock);
|
||||||
}
|
}
|
||||||
|
|
|
@ -1440,7 +1440,8 @@ void bond_alb_monitor(struct work_struct *work)
|
||||||
}
|
}
|
||||||
|
|
||||||
re_arm:
|
re_arm:
|
||||||
queue_delayed_work(bond->wq, &bond->alb_work, alb_delta_in_ticks);
|
if (!bond->kill_timers)
|
||||||
|
queue_delayed_work(bond->wq, &bond->alb_work, alb_delta_in_ticks);
|
||||||
out:
|
out:
|
||||||
read_unlock(&bond->lock);
|
read_unlock(&bond->lock);
|
||||||
}
|
}
|
||||||
|
|
|
@ -777,6 +777,9 @@ static void bond_resend_igmp_join_requests(struct bonding *bond)
|
||||||
|
|
||||||
read_lock(&bond->lock);
|
read_lock(&bond->lock);
|
||||||
|
|
||||||
|
if (bond->kill_timers)
|
||||||
|
goto out;
|
||||||
|
|
||||||
/* rejoin all groups on bond device */
|
/* rejoin all groups on bond device */
|
||||||
__bond_resend_igmp_join_requests(bond->dev);
|
__bond_resend_igmp_join_requests(bond->dev);
|
||||||
|
|
||||||
|
@ -790,9 +793,9 @@ static void bond_resend_igmp_join_requests(struct bonding *bond)
|
||||||
__bond_resend_igmp_join_requests(vlan_dev);
|
__bond_resend_igmp_join_requests(vlan_dev);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (--bond->igmp_retrans > 0)
|
if ((--bond->igmp_retrans > 0) && !bond->kill_timers)
|
||||||
queue_delayed_work(bond->wq, &bond->mcast_work, HZ/5);
|
queue_delayed_work(bond->wq, &bond->mcast_work, HZ/5);
|
||||||
|
out:
|
||||||
read_unlock(&bond->lock);
|
read_unlock(&bond->lock);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -2538,7 +2541,7 @@ void bond_mii_monitor(struct work_struct *work)
|
||||||
}
|
}
|
||||||
|
|
||||||
re_arm:
|
re_arm:
|
||||||
if (bond->params.miimon)
|
if (bond->params.miimon && !bond->kill_timers)
|
||||||
queue_delayed_work(bond->wq, &bond->mii_work,
|
queue_delayed_work(bond->wq, &bond->mii_work,
|
||||||
msecs_to_jiffies(bond->params.miimon));
|
msecs_to_jiffies(bond->params.miimon));
|
||||||
out:
|
out:
|
||||||
|
@ -2886,7 +2889,7 @@ void bond_loadbalance_arp_mon(struct work_struct *work)
|
||||||
}
|
}
|
||||||
|
|
||||||
re_arm:
|
re_arm:
|
||||||
if (bond->params.arp_interval)
|
if (bond->params.arp_interval && !bond->kill_timers)
|
||||||
queue_delayed_work(bond->wq, &bond->arp_work, delta_in_ticks);
|
queue_delayed_work(bond->wq, &bond->arp_work, delta_in_ticks);
|
||||||
out:
|
out:
|
||||||
read_unlock(&bond->lock);
|
read_unlock(&bond->lock);
|
||||||
|
@ -3154,7 +3157,7 @@ void bond_activebackup_arp_mon(struct work_struct *work)
|
||||||
bond_ab_arp_probe(bond);
|
bond_ab_arp_probe(bond);
|
||||||
|
|
||||||
re_arm:
|
re_arm:
|
||||||
if (bond->params.arp_interval)
|
if (bond->params.arp_interval && !bond->kill_timers)
|
||||||
queue_delayed_work(bond->wq, &bond->arp_work, delta_in_ticks);
|
queue_delayed_work(bond->wq, &bond->arp_work, delta_in_ticks);
|
||||||
out:
|
out:
|
||||||
read_unlock(&bond->lock);
|
read_unlock(&bond->lock);
|
||||||
|
|
|
@ -1146,12 +1146,14 @@ static void cxgb_redirect(struct dst_entry *old, struct dst_entry *new)
|
||||||
if (te && te->ctx && te->client && te->client->redirect) {
|
if (te && te->ctx && te->client && te->client->redirect) {
|
||||||
update_tcb = te->client->redirect(te->ctx, old, new, e);
|
update_tcb = te->client->redirect(te->ctx, old, new, e);
|
||||||
if (update_tcb) {
|
if (update_tcb) {
|
||||||
|
rcu_read_lock();
|
||||||
l2t_hold(L2DATA(tdev), e);
|
l2t_hold(L2DATA(tdev), e);
|
||||||
|
rcu_read_unlock();
|
||||||
set_l2t_ix(tdev, tid, e);
|
set_l2t_ix(tdev, tid, e);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
l2t_release(L2DATA(tdev), e);
|
l2t_release(tdev, e);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -1264,7 +1266,7 @@ int cxgb3_offload_activate(struct adapter *adapter)
|
||||||
goto out_free;
|
goto out_free;
|
||||||
|
|
||||||
err = -ENOMEM;
|
err = -ENOMEM;
|
||||||
L2DATA(dev) = t3_init_l2t(l2t_capacity);
|
RCU_INIT_POINTER(dev->l2opt, t3_init_l2t(l2t_capacity));
|
||||||
if (!L2DATA(dev))
|
if (!L2DATA(dev))
|
||||||
goto out_free;
|
goto out_free;
|
||||||
|
|
||||||
|
@ -1298,16 +1300,24 @@ int cxgb3_offload_activate(struct adapter *adapter)
|
||||||
|
|
||||||
out_free_l2t:
|
out_free_l2t:
|
||||||
t3_free_l2t(L2DATA(dev));
|
t3_free_l2t(L2DATA(dev));
|
||||||
L2DATA(dev) = NULL;
|
rcu_assign_pointer(dev->l2opt, NULL);
|
||||||
out_free:
|
out_free:
|
||||||
kfree(t);
|
kfree(t);
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void clean_l2_data(struct rcu_head *head)
|
||||||
|
{
|
||||||
|
struct l2t_data *d = container_of(head, struct l2t_data, rcu_head);
|
||||||
|
t3_free_l2t(d);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
void cxgb3_offload_deactivate(struct adapter *adapter)
|
void cxgb3_offload_deactivate(struct adapter *adapter)
|
||||||
{
|
{
|
||||||
struct t3cdev *tdev = &adapter->tdev;
|
struct t3cdev *tdev = &adapter->tdev;
|
||||||
struct t3c_data *t = T3C_DATA(tdev);
|
struct t3c_data *t = T3C_DATA(tdev);
|
||||||
|
struct l2t_data *d;
|
||||||
|
|
||||||
remove_adapter(adapter);
|
remove_adapter(adapter);
|
||||||
if (list_empty(&adapter_list))
|
if (list_empty(&adapter_list))
|
||||||
|
@ -1315,8 +1325,11 @@ void cxgb3_offload_deactivate(struct adapter *adapter)
|
||||||
|
|
||||||
free_tid_maps(&t->tid_maps);
|
free_tid_maps(&t->tid_maps);
|
||||||
T3C_DATA(tdev) = NULL;
|
T3C_DATA(tdev) = NULL;
|
||||||
t3_free_l2t(L2DATA(tdev));
|
rcu_read_lock();
|
||||||
L2DATA(tdev) = NULL;
|
d = L2DATA(tdev);
|
||||||
|
rcu_read_unlock();
|
||||||
|
rcu_assign_pointer(tdev->l2opt, NULL);
|
||||||
|
call_rcu(&d->rcu_head, clean_l2_data);
|
||||||
if (t->nofail_skb)
|
if (t->nofail_skb)
|
||||||
kfree_skb(t->nofail_skb);
|
kfree_skb(t->nofail_skb);
|
||||||
kfree(t);
|
kfree(t);
|
||||||
|
|
|
@ -300,14 +300,21 @@ static inline void reuse_entry(struct l2t_entry *e, struct neighbour *neigh)
|
||||||
struct l2t_entry *t3_l2t_get(struct t3cdev *cdev, struct neighbour *neigh,
|
struct l2t_entry *t3_l2t_get(struct t3cdev *cdev, struct neighbour *neigh,
|
||||||
struct net_device *dev)
|
struct net_device *dev)
|
||||||
{
|
{
|
||||||
struct l2t_entry *e;
|
struct l2t_entry *e = NULL;
|
||||||
struct l2t_data *d = L2DATA(cdev);
|
struct l2t_data *d;
|
||||||
|
int hash;
|
||||||
u32 addr = *(u32 *) neigh->primary_key;
|
u32 addr = *(u32 *) neigh->primary_key;
|
||||||
int ifidx = neigh->dev->ifindex;
|
int ifidx = neigh->dev->ifindex;
|
||||||
int hash = arp_hash(addr, ifidx, d);
|
|
||||||
struct port_info *p = netdev_priv(dev);
|
struct port_info *p = netdev_priv(dev);
|
||||||
int smt_idx = p->port_id;
|
int smt_idx = p->port_id;
|
||||||
|
|
||||||
|
rcu_read_lock();
|
||||||
|
d = L2DATA(cdev);
|
||||||
|
if (!d)
|
||||||
|
goto done_rcu;
|
||||||
|
|
||||||
|
hash = arp_hash(addr, ifidx, d);
|
||||||
|
|
||||||
write_lock_bh(&d->lock);
|
write_lock_bh(&d->lock);
|
||||||
for (e = d->l2tab[hash].first; e; e = e->next)
|
for (e = d->l2tab[hash].first; e; e = e->next)
|
||||||
if (e->addr == addr && e->ifindex == ifidx &&
|
if (e->addr == addr && e->ifindex == ifidx &&
|
||||||
|
@ -338,6 +345,8 @@ struct l2t_entry *t3_l2t_get(struct t3cdev *cdev, struct neighbour *neigh,
|
||||||
}
|
}
|
||||||
done:
|
done:
|
||||||
write_unlock_bh(&d->lock);
|
write_unlock_bh(&d->lock);
|
||||||
|
done_rcu:
|
||||||
|
rcu_read_unlock();
|
||||||
return e;
|
return e;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -76,6 +76,7 @@ struct l2t_data {
|
||||||
atomic_t nfree; /* number of free entries */
|
atomic_t nfree; /* number of free entries */
|
||||||
rwlock_t lock;
|
rwlock_t lock;
|
||||||
struct l2t_entry l2tab[0];
|
struct l2t_entry l2tab[0];
|
||||||
|
struct rcu_head rcu_head; /* to handle rcu cleanup */
|
||||||
};
|
};
|
||||||
|
|
||||||
typedef void (*arp_failure_handler_func)(struct t3cdev * dev,
|
typedef void (*arp_failure_handler_func)(struct t3cdev * dev,
|
||||||
|
@ -99,7 +100,7 @@ static inline void set_arp_failure_handler(struct sk_buff *skb,
|
||||||
/*
|
/*
|
||||||
* Getting to the L2 data from an offload device.
|
* Getting to the L2 data from an offload device.
|
||||||
*/
|
*/
|
||||||
#define L2DATA(dev) ((dev)->l2opt)
|
#define L2DATA(cdev) (rcu_dereference((cdev)->l2opt))
|
||||||
|
|
||||||
#define W_TCB_L2T_IX 0
|
#define W_TCB_L2T_IX 0
|
||||||
#define S_TCB_L2T_IX 7
|
#define S_TCB_L2T_IX 7
|
||||||
|
@ -126,15 +127,22 @@ static inline int l2t_send(struct t3cdev *dev, struct sk_buff *skb,
|
||||||
return t3_l2t_send_slow(dev, skb, e);
|
return t3_l2t_send_slow(dev, skb, e);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void l2t_release(struct l2t_data *d, struct l2t_entry *e)
|
static inline void l2t_release(struct t3cdev *t, struct l2t_entry *e)
|
||||||
{
|
{
|
||||||
if (atomic_dec_and_test(&e->refcnt))
|
struct l2t_data *d;
|
||||||
|
|
||||||
|
rcu_read_lock();
|
||||||
|
d = L2DATA(t);
|
||||||
|
|
||||||
|
if (atomic_dec_and_test(&e->refcnt) && d)
|
||||||
t3_l2e_free(d, e);
|
t3_l2e_free(d, e);
|
||||||
|
|
||||||
|
rcu_read_unlock();
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void l2t_hold(struct l2t_data *d, struct l2t_entry *e)
|
static inline void l2t_hold(struct l2t_data *d, struct l2t_entry *e)
|
||||||
{
|
{
|
||||||
if (atomic_add_return(1, &e->refcnt) == 1) /* 0 -> 1 transition */
|
if (d && atomic_add_return(1, &e->refcnt) == 1) /* 0 -> 1 transition */
|
||||||
atomic_dec(&d->nfree);
|
atomic_dec(&d->nfree);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -3712,6 +3712,9 @@ static int __devinit init_one(struct pci_dev *pdev,
|
||||||
setup_debugfs(adapter);
|
setup_debugfs(adapter);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* PCIe EEH recovery on powerpc platforms needs fundamental reset */
|
||||||
|
pdev->needs_freset = 1;
|
||||||
|
|
||||||
if (is_offload(adapter))
|
if (is_offload(adapter))
|
||||||
attach_ulds(adapter);
|
attach_ulds(adapter);
|
||||||
|
|
||||||
|
|
|
@ -636,8 +636,8 @@ static int ibmveth_open(struct net_device *netdev)
|
||||||
netdev_err(netdev, "unable to request irq 0x%x, rc %d\n",
|
netdev_err(netdev, "unable to request irq 0x%x, rc %d\n",
|
||||||
netdev->irq, rc);
|
netdev->irq, rc);
|
||||||
do {
|
do {
|
||||||
rc = h_free_logical_lan(adapter->vdev->unit_address);
|
lpar_rc = h_free_logical_lan(adapter->vdev->unit_address);
|
||||||
} while (H_IS_LONG_BUSY(rc) || (rc == H_BUSY));
|
} while (H_IS_LONG_BUSY(lpar_rc) || (lpar_rc == H_BUSY));
|
||||||
|
|
||||||
goto err_out;
|
goto err_out;
|
||||||
}
|
}
|
||||||
|
|
|
@ -1199,6 +1199,8 @@ static irqreturn_t pch_gbe_intr(int irq, void *data)
|
||||||
iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
|
iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
|
||||||
&hw->reg->INT_EN);
|
&hw->reg->INT_EN);
|
||||||
pch_gbe_stop_receive(adapter);
|
pch_gbe_stop_receive(adapter);
|
||||||
|
int_st |= ioread32(&hw->reg->INT_ST);
|
||||||
|
int_st = int_st & ioread32(&hw->reg->INT_EN);
|
||||||
}
|
}
|
||||||
if (int_st & PCH_GBE_INT_RX_DMA_ERR)
|
if (int_st & PCH_GBE_INT_RX_DMA_ERR)
|
||||||
adapter->stats.intr_rx_dma_err_count++;
|
adapter->stats.intr_rx_dma_err_count++;
|
||||||
|
@ -1218,14 +1220,11 @@ static irqreturn_t pch_gbe_intr(int irq, void *data)
|
||||||
/* Set Pause packet */
|
/* Set Pause packet */
|
||||||
pch_gbe_mac_set_pause_packet(hw);
|
pch_gbe_mac_set_pause_packet(hw);
|
||||||
}
|
}
|
||||||
if ((int_en & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))
|
|
||||||
== 0) {
|
|
||||||
return IRQ_HANDLED;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* When request status is Receive interruption */
|
/* When request status is Receive interruption */
|
||||||
if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT))) {
|
if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) ||
|
||||||
|
(adapter->rx_stop_flag == true)) {
|
||||||
if (likely(napi_schedule_prep(&adapter->napi))) {
|
if (likely(napi_schedule_prep(&adapter->napi))) {
|
||||||
/* Enable only Rx Descriptor empty */
|
/* Enable only Rx Descriptor empty */
|
||||||
atomic_inc(&adapter->irq_sem);
|
atomic_inc(&adapter->irq_sem);
|
||||||
|
@ -1385,7 +1384,7 @@ pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
|
||||||
struct sk_buff *skb;
|
struct sk_buff *skb;
|
||||||
unsigned int i;
|
unsigned int i;
|
||||||
unsigned int cleaned_count = 0;
|
unsigned int cleaned_count = 0;
|
||||||
bool cleaned = false;
|
bool cleaned = true;
|
||||||
|
|
||||||
pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
|
pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
|
||||||
|
|
||||||
|
@ -1396,7 +1395,6 @@ pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
|
||||||
|
|
||||||
while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
|
while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
|
||||||
pr_debug("gbec_status:0x%04x\n", tx_desc->gbec_status);
|
pr_debug("gbec_status:0x%04x\n", tx_desc->gbec_status);
|
||||||
cleaned = true;
|
|
||||||
buffer_info = &tx_ring->buffer_info[i];
|
buffer_info = &tx_ring->buffer_info[i];
|
||||||
skb = buffer_info->skb;
|
skb = buffer_info->skb;
|
||||||
|
|
||||||
|
@ -1439,8 +1437,10 @@ pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
|
||||||
tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
|
tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
|
||||||
|
|
||||||
/* weight of a sort for tx, to avoid endless transmit cleanup */
|
/* weight of a sort for tx, to avoid endless transmit cleanup */
|
||||||
if (cleaned_count++ == PCH_GBE_TX_WEIGHT)
|
if (cleaned_count++ == PCH_GBE_TX_WEIGHT) {
|
||||||
|
cleaned = false;
|
||||||
break;
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
pr_debug("called pch_gbe_unmap_and_free_tx_resource() %d count\n",
|
pr_debug("called pch_gbe_unmap_and_free_tx_resource() %d count\n",
|
||||||
cleaned_count);
|
cleaned_count);
|
||||||
|
@ -2168,7 +2168,6 @@ static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
|
||||||
{
|
{
|
||||||
struct pch_gbe_adapter *adapter =
|
struct pch_gbe_adapter *adapter =
|
||||||
container_of(napi, struct pch_gbe_adapter, napi);
|
container_of(napi, struct pch_gbe_adapter, napi);
|
||||||
struct net_device *netdev = adapter->netdev;
|
|
||||||
int work_done = 0;
|
int work_done = 0;
|
||||||
bool poll_end_flag = false;
|
bool poll_end_flag = false;
|
||||||
bool cleaned = false;
|
bool cleaned = false;
|
||||||
|
@ -2176,33 +2175,32 @@ static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
|
||||||
|
|
||||||
pr_debug("budget : %d\n", budget);
|
pr_debug("budget : %d\n", budget);
|
||||||
|
|
||||||
/* Keep link state information with original netdev */
|
pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
|
||||||
if (!netif_carrier_ok(netdev)) {
|
cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
|
||||||
|
|
||||||
|
if (!cleaned)
|
||||||
|
work_done = budget;
|
||||||
|
/* If no Tx and not enough Rx work done,
|
||||||
|
* exit the polling mode
|
||||||
|
*/
|
||||||
|
if (work_done < budget)
|
||||||
poll_end_flag = true;
|
poll_end_flag = true;
|
||||||
} else {
|
|
||||||
pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
|
if (poll_end_flag) {
|
||||||
|
napi_complete(napi);
|
||||||
|
if (adapter->rx_stop_flag) {
|
||||||
|
adapter->rx_stop_flag = false;
|
||||||
|
pch_gbe_start_receive(&adapter->hw);
|
||||||
|
}
|
||||||
|
pch_gbe_irq_enable(adapter);
|
||||||
|
} else
|
||||||
if (adapter->rx_stop_flag) {
|
if (adapter->rx_stop_flag) {
|
||||||
adapter->rx_stop_flag = false;
|
adapter->rx_stop_flag = false;
|
||||||
pch_gbe_start_receive(&adapter->hw);
|
pch_gbe_start_receive(&adapter->hw);
|
||||||
int_en = ioread32(&adapter->hw.reg->INT_EN);
|
int_en = ioread32(&adapter->hw.reg->INT_EN);
|
||||||
iowrite32((int_en | PCH_GBE_INT_RX_FIFO_ERR),
|
iowrite32((int_en | PCH_GBE_INT_RX_FIFO_ERR),
|
||||||
&adapter->hw.reg->INT_EN);
|
&adapter->hw.reg->INT_EN);
|
||||||
}
|
}
|
||||||
cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
|
|
||||||
|
|
||||||
if (cleaned)
|
|
||||||
work_done = budget;
|
|
||||||
/* If no Tx and not enough Rx work done,
|
|
||||||
* exit the polling mode
|
|
||||||
*/
|
|
||||||
if ((work_done < budget) || !netif_running(netdev))
|
|
||||||
poll_end_flag = true;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (poll_end_flag) {
|
|
||||||
napi_complete(napi);
|
|
||||||
pch_gbe_irq_enable(adapter);
|
|
||||||
}
|
|
||||||
|
|
||||||
pr_debug("poll_end_flag : %d work_done : %d budget : %d\n",
|
pr_debug("poll_end_flag : %d work_done : %d budget : %d\n",
|
||||||
poll_end_flag, work_done, budget);
|
poll_end_flag, work_done, budget);
|
||||||
|
|
|
@ -589,7 +589,7 @@ static void decode_rxts(struct dp83640_private *dp83640,
|
||||||
prune_rx_ts(dp83640);
|
prune_rx_ts(dp83640);
|
||||||
|
|
||||||
if (list_empty(&dp83640->rxpool)) {
|
if (list_empty(&dp83640->rxpool)) {
|
||||||
pr_warning("dp83640: rx timestamp pool is empty\n");
|
pr_debug("dp83640: rx timestamp pool is empty\n");
|
||||||
goto out;
|
goto out;
|
||||||
}
|
}
|
||||||
rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
|
rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
|
||||||
|
@ -612,7 +612,7 @@ static void decode_txts(struct dp83640_private *dp83640,
|
||||||
skb = skb_dequeue(&dp83640->tx_queue);
|
skb = skb_dequeue(&dp83640->tx_queue);
|
||||||
|
|
||||||
if (!skb) {
|
if (!skb) {
|
||||||
pr_warning("dp83640: have timestamp but tx_queue empty\n");
|
pr_debug("dp83640: have timestamp but tx_queue empty\n");
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
ns = phy2txts(phy_txts);
|
ns = phy2txts(phy_txts);
|
||||||
|
|
|
@ -1514,7 +1514,7 @@ static const u32 ar9300_2p2_mac_core[][2] = {
|
||||||
{0x00008258, 0x00000000},
|
{0x00008258, 0x00000000},
|
||||||
{0x0000825c, 0x40000000},
|
{0x0000825c, 0x40000000},
|
||||||
{0x00008260, 0x00080922},
|
{0x00008260, 0x00080922},
|
||||||
{0x00008264, 0x9bc00010},
|
{0x00008264, 0x9d400010},
|
||||||
{0x00008268, 0xffffffff},
|
{0x00008268, 0xffffffff},
|
||||||
{0x0000826c, 0x0000ffff},
|
{0x0000826c, 0x0000ffff},
|
||||||
{0x00008270, 0x00000000},
|
{0x00008270, 0x00000000},
|
||||||
|
|
|
@ -205,14 +205,22 @@ static void ath_rx_remove_buffer(struct ath_softc *sc,
|
||||||
|
|
||||||
static void ath_rx_edma_cleanup(struct ath_softc *sc)
|
static void ath_rx_edma_cleanup(struct ath_softc *sc)
|
||||||
{
|
{
|
||||||
|
struct ath_hw *ah = sc->sc_ah;
|
||||||
|
struct ath_common *common = ath9k_hw_common(ah);
|
||||||
struct ath_buf *bf;
|
struct ath_buf *bf;
|
||||||
|
|
||||||
ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
|
ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
|
||||||
ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
|
ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
|
||||||
|
|
||||||
list_for_each_entry(bf, &sc->rx.rxbuf, list) {
|
list_for_each_entry(bf, &sc->rx.rxbuf, list) {
|
||||||
if (bf->bf_mpdu)
|
if (bf->bf_mpdu) {
|
||||||
|
dma_unmap_single(sc->dev, bf->bf_buf_addr,
|
||||||
|
common->rx_bufsize,
|
||||||
|
DMA_BIDIRECTIONAL);
|
||||||
dev_kfree_skb_any(bf->bf_mpdu);
|
dev_kfree_skb_any(bf->bf_mpdu);
|
||||||
|
bf->bf_buf_addr = 0;
|
||||||
|
bf->bf_mpdu = NULL;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
INIT_LIST_HEAD(&sc->rx.rxbuf);
|
INIT_LIST_HEAD(&sc->rx.rxbuf);
|
||||||
|
|
|
@ -937,7 +937,7 @@ void iwl_legacy_irq_handle_error(struct iwl_priv *priv)
|
||||||
&priv->contexts[IWL_RXON_CTX_BSS]);
|
&priv->contexts[IWL_RXON_CTX_BSS]);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
wake_up_interruptible(&priv->wait_command_queue);
|
wake_up(&priv->wait_command_queue);
|
||||||
|
|
||||||
/* Keep the restart process from trying to send host
|
/* Keep the restart process from trying to send host
|
||||||
* commands by clearing the INIT status bit */
|
* commands by clearing the INIT status bit */
|
||||||
|
@ -1746,7 +1746,7 @@ int iwl_legacy_force_reset(struct iwl_priv *priv, bool external)
|
||||||
|
|
||||||
/* Set the FW error flag -- cleared on iwl_down */
|
/* Set the FW error flag -- cleared on iwl_down */
|
||||||
set_bit(STATUS_FW_ERROR, &priv->status);
|
set_bit(STATUS_FW_ERROR, &priv->status);
|
||||||
wake_up_interruptible(&priv->wait_command_queue);
|
wake_up(&priv->wait_command_queue);
|
||||||
/*
|
/*
|
||||||
* Keep the restart process from trying to send host
|
* Keep the restart process from trying to send host
|
||||||
* commands by clearing the INIT status bit
|
* commands by clearing the INIT status bit
|
||||||
|
|
|
@ -167,7 +167,7 @@ int iwl_legacy_send_cmd_sync(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
|
||||||
goto out;
|
goto out;
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = wait_event_interruptible_timeout(priv->wait_command_queue,
|
ret = wait_event_timeout(priv->wait_command_queue,
|
||||||
!test_bit(STATUS_HCMD_ACTIVE, &priv->status),
|
!test_bit(STATUS_HCMD_ACTIVE, &priv->status),
|
||||||
HOST_COMPLETE_TIMEOUT);
|
HOST_COMPLETE_TIMEOUT);
|
||||||
if (!ret) {
|
if (!ret) {
|
||||||
|
|
|
@ -625,6 +625,8 @@ iwl_legacy_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
|
||||||
cmd = txq->cmd[cmd_index];
|
cmd = txq->cmd[cmd_index];
|
||||||
meta = &txq->meta[cmd_index];
|
meta = &txq->meta[cmd_index];
|
||||||
|
|
||||||
|
txq->time_stamp = jiffies;
|
||||||
|
|
||||||
pci_unmap_single(priv->pci_dev,
|
pci_unmap_single(priv->pci_dev,
|
||||||
dma_unmap_addr(meta, mapping),
|
dma_unmap_addr(meta, mapping),
|
||||||
dma_unmap_len(meta, len),
|
dma_unmap_len(meta, len),
|
||||||
|
@ -645,7 +647,7 @@ iwl_legacy_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
|
||||||
clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
|
clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
|
||||||
IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
|
IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
|
||||||
iwl_legacy_get_cmd_string(cmd->hdr.cmd));
|
iwl_legacy_get_cmd_string(cmd->hdr.cmd));
|
||||||
wake_up_interruptible(&priv->wait_command_queue);
|
wake_up(&priv->wait_command_queue);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Mark as unmapped */
|
/* Mark as unmapped */
|
||||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue