mirrors
/
linux-stable
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
1
0
Fork 0
Code Issues Releases Wiki Activity

SoC: device tree updates for 6.9 

There is very little going on with new SoC support this time, all the
 new chips are variations of others that we already support, and they
 are all based on ARMv8 cores:
 
  - Mediatek MT7981B (Filogic 820) and MT7988A (Filogic 880) are
    networking SoCs designed to be used in wireless routers, similar
    to the already supported MT7986A (Filogic 830).
 
  - NXP i.MX8DXP is a variant of i.MX8QXP, with two CPU cores less.
    These are used in many embedded and industrial applications.
 
  - Renesas R8A779G2 (R-Car V4H ES2.0) and R8A779H0 (R-Car V4M)
    are automotive SoCs.
 
  - TI J722S is another automotive variant of its K3 family,
    related to the AM62 series.
 
 There are a total of 7 new arm32 machines and 45 arm64 ones, including
 
  - Two Android phones based on the old Tegra30 chip
 
  - Two machines using Cortex-A53 SoCs from Allwinner, a mini PC and
    a SoM development board
 
  - A set-top box using Amlogic Meson G12A S905X2
 
  - Eight embedded board using NXP i.MX6/8/9
 
  - Three machines using Mediatek network router chips
 
  - Ten Chromebooks, all based on Mediatek MT8186
 
  - One development board based on Mediatek MT8395 (Genio 1200)
 
  - Seven tablets and phones based on Qualcomm SoCs, most of them
    from Samsung.
 
  - A third development board for Qualcomm SM8550 (Snapdragon 8 Gen 2)
 
  - Three variants of the "White Hawk" board for Renesas
    automotive SoCs
 
  - Ten Rockchips RK35xx based machines, including NAS, Tablet,
    Game console and industrial form factors.
 
  - Three evaluation boards for TI K3 based SoCs
 
 The other changes are mainly the usual feature additions for existing hardware,
 cleanups, and dtc compile time fixes. One notable change is the inclusion
 of PowerVR SGX GPU nodes on TI SoCs.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXvLwQACgkQYKtH/8kJ
 Uidkhw/+LjDOIqF8f4+6TBCCS3pFAVSAZxKxlm7L4VhsVOOeGZdspOY57eKZJWqW
 bVqj+B22UjJSw/9LOrFBNApkV8vk+rR7UfJjzijXM34WB80DC8+s7DbenCHagqR8
 fsKCB4tHKTYbBk6EefzyWy7fSA1SFu7hpTg5qWK8XONbGdHnkhbj1aQDbUe7p961
 huKGM+2spO+bFs3ljHGymBWywFKtuMTmVzoq16mBZl/bnuIKobm7W2kF+n3NAo+h
 CMta6J9mBlinBT+VtIg2Xax+KvkjmoitevOmyURxp/33+14A64dafI+RLiSyeqb6
 DfeAp9ptrBbVGzYZq2r07WYX9AIBdD2hvdkrtrjOy6JPqtJpWdfA4slYzWCzZfOz
 O08sV3l7ERggpNkMcTWiwBiuB/y5Hci7SYVeQm8N8bp5PydgNpoo6kNVpnc1e6ri
 Ug8t/jQYvpkCVHT3ld8PmgpWoZRinKIe6PNmqdg5jUu8aH+m4TNNmHyA2IjBcovj
 006FBBGVKp4HlCrGz4t9/XsmKzt+cRxLaX06duoZ93FQknXSzs7j7UDkPhpR07kF
 yEHjETnfhziyONL2fHZ+ejBoK/9psTFtzbpgMreBJ0mFZM0yvL0c+gcMvDgDD8ho
 PCp2ohDYpKPoklrTqMLKM7Yjev5bTOdrAJeWoLDWCbgkzVDkyjw=
 =krkR
 -----END PGP SIGNATURE-----

Merge tag 'soc-dt-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC device tree updates from Arnd Bergmann:
 "There is very little going on with new SoC support this time, all the
  new chips are variations of others that we already support, and they
  are all based on ARMv8 cores:

   - Mediatek MT7981B (Filogic 820) and MT7988A (Filogic 880) are
     networking SoCs designed to be used in wireless routers, similar to
     the already supported MT7986A (Filogic 830).

   - NXP i.MX8DXP is a variant of i.MX8QXP, with two CPU cores less.
     These are used in many embedded and industrial applications.

   - Renesas R8A779G2 (R-Car V4H ES2.0) and R8A779H0 (R-Car V4M) are
     automotive SoCs.

   - TI J722S is another automotive variant of its K3 family, related to
     the AM62 series.

  There are a total of 7 new arm32 machines and 45 arm64 ones, including

   - Two Android phones based on the old Tegra30 chip

   - Two machines using Cortex-A53 SoCs from Allwinner, a mini PC and a
     SoM development board

   - A set-top box using Amlogic Meson G12A S905X2

   - Eight embedded board using NXP i.MX6/8/9

   - Three machines using Mediatek network router chips

   - Ten Chromebooks, all based on Mediatek MT8186

   - One development board based on Mediatek MT8395 (Genio 1200)

   - Seven tablets and phones based on Qualcomm SoCs, most of them from
     Samsung.

   - A third development board for Qualcomm SM8550 (Snapdragon 8 Gen 2)

   - Three variants of the "White Hawk" board for Renesas automotive
     SoCs

   - Ten Rockchips RK35xx based machines, including NAS, Tablet, Game
     console and industrial form factors.

   - Three evaluation boards for TI K3 based SoCs

  The other changes are mainly the usual feature additions for existing
  hardware, cleanups, and dtc compile time fixes. One notable change is
  the inclusion of PowerVR SGX GPU nodes on TI SoCs"

* tag 'soc-dt-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (824 commits)
  riscv: dts: Move BUILTIN_DTB_SOURCE to common Kconfig
  riscv: dts: starfive: jh7100: fix root clock names
  ARM: dts: samsung: exynos4412: decrease memory to account for unusable region
  arm64: dts: qcom: sm8250-xiaomi-elish: set rotation
  arm64: dts: qcom: sm8650: Fix SPMI channels size
  arm64: dts: qcom: sm8550: Fix SPMI channels size
  arm64: dts: rockchip: Fix name for UART pin header on qnap-ts433
  arm: dts: marvell: clearfog-gtr-l8: align port numbers with enclosure
  arm: dts: marvell: clearfog-gtr-l8: add support for second sfp connector
  dt-bindings: soc: renesas: renesas-soc: Add pattern for gray-hawk
  dtc: Enable dtc interrupt_provider check
  arm64: dts: st: add video encoder support to stm32mp255
  arm64: dts: st: add video decoder support to stm32mp255
  ARM: dts: stm32: enable crypto accelerator on stm32mp135f-dk
  ARM: dts: stm32: enable CRC on stm32mp135f-dk
  ARM: dts: stm32: add CRC on stm32mp131
  ARM: dts: add stm32f769-disco-mb1166-reva09
  ARM: dts: stm32: add display support on stm32f769-disco
  ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f769-disco
  ARM: dts: stm32: add DSI support on stm32f769
  ...
This commit is contained in:
Linus Torvalds 2024-03-12 10:29:57 -07:00
parent 508f34f238 59f33701fd
commit 306bee64b7
742 changed files with 40623 additions and 7996 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
Documentation/devicetree/bindings/arm/amlogic.yaml
View File

@ -7,19 +7,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic SoC based Platforms
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
- Jerome Brunet <jbrunet@baylibre.com>
- Kevin Hilman <khilman@baylibre.com>
description: |+
Work in progress statement:
Device tree files and bindings applying to Amlogic SoCs and boards are
considered "unstable". Any Amlogic device tree binding may change at
any time. Be sure to use a device tree binary and a kernel image
generated from the same source tree.
Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
stable binding/ABI.
properties:
$nodename:
const: '/'
@ -146,6 +138,7 @@ properties:
- enum:
- amediatech,x96-max
- amlogic,u200
- freebox,fbx8am
- radxa,zero
- seirobotics,sei510
- const: amlogic,g12a

6
Documentation/devicetree/bindings/arm/arm,realview.yaml
View File

@ -10,9 +10,9 @@ maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |+
The ARM RealView series of reference designs were built to explore the ARM
11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
the earlier CPUs such as TrustZone and multicore (MPCore).
The ARM RealView series of reference designs were built to explore the Arm11,
Cortex-A8, and Cortex-A9 CPUs. This included new features compared to the
earlier CPUs such as TrustZone and multicore (MPCore).
properties:
$nodename:

6
Documentation/devicetree/bindings/arm/atmel-at91.yaml
View File

@ -179,6 +179,12 @@ properties:
- const: microchip,sama7g5
- const: microchip,sama7
- description: Microchip SAMA7G54 Curiosity Board
items:
- const: microchip,sama7g54-curiosity
- const: microchip,sama7g5
- const: microchip,sama7
- description: Microchip LAN9662 Evaluation Boards.
items:
- enum:

41
Documentation/devicetree/bindings/arm/fsl.yaml
View File

@ -384,7 +384,8 @@ properties:
- toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board
- toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board
- toradex,apalis_imx6q-ixora-v1.2 # Apalis iMX6Q/D Module on Ixora V1.2 Carrier Board
- toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board
- toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board v1.0/v1.1
- toradex,apalis_imx6q-eval-v1.2 # Apalis iMX6Q/D Module on Apalis Evaluation Board v1.2
- const: toradex,apalis_imx6q
- const: fsl,imx6q
@ -469,6 +470,7 @@ properties:
- prt,prtvt7 # Protonic VT7 board
- rex,imx6dl-rex-basic # Rex Basic i.MX6 Dual Lite Board
- riot,imx6s-riotboard # RIoTboard i.MX6S
- sielaff,imx6dl-board # Sielaff i.MX6 Solo Board
- skov,imx6dl-skov-revc-lt2 # SKOV IMX6 CPU SoloCore lt2
- skov,imx6dl-skov-revc-lt6 # SKOV IMX6 CPU SoloCore lt6
- solidrun,cubox-i/dl # SolidRun Cubox-i Solo/DualLite
@ -708,6 +710,7 @@ properties:
- toradex,colibri-imx6ull # Colibri iMX6ULL Modules
- toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
- toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Modules
- uni-t,uti260b # UNI-T UTi260B Thermal Camera
- const: fsl,imx6ull
- description: i.MX6ULL Armadeus Systems OPOS6ULDev Board
@ -1026,7 +1029,7 @@ properties:
items:
- enum:
- dimonoff,gateway-evk # i.MX8MN Dimonoff Gateway EVK Board
- rve,rve-gateway # i.MX8MN RVE Gateway Board
- rve,gateway # i.MX8MN RVE Gateway Board
- variscite,var-som-mx8mn-symphony
- const: variscite,var-som-mx8mn
- const: fsl,imx8mn
@ -1194,7 +1197,8 @@ properties:
- description: i.MX8QM Boards with Toradex Apalis iMX8 Modules
items:
- enum:
- toradex,apalis-imx8-eval # Apalis iMX8 Module on Apalis Evaluation Board
- toradex,apalis-imx8-eval # Apalis iMX8 Module on Apalis Evaluation V1.0/V1.1 Board
- toradex,apalis-imx8-eval-v1.2 # Apalis iMX8 Module on Apalis Evaluation V1.2 Board
- toradex,apalis-imx8-ixora-v1.1 # Apalis iMX8 Module on Ixora V1.1 Carrier Board
- const: toradex,apalis-imx8
- const: fsl,imx8qm
@ -1202,7 +1206,8 @@ properties:
- description: i.MX8QM Boards with Toradex Apalis iMX8 V1.1 Modules
items:
- enum:
- toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. Board
- toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. V1.0/V1.1 Board
- toradex,apalis-imx8-v1.1-eval-v1.2 # Apalis iMX8 V1.1 Module on Apalis Eval. V1.2 Board
- toradex,apalis-imx8-v1.1-ixora-v1.1 # Apalis iMX8 V1.1 Module on Ixora V1.1 C. Board
- toradex,apalis-imx8-v1.1-ixora-v1.2 # Apalis iMX8 V1.1 Module on Ixora V1.2 C. Board
- const: toradex,apalis-imx8-v1.1
@ -1232,6 +1237,22 @@ properties:
- const: toradex,colibri-imx8x
- const: fsl,imx8qxp
- description:
TQMa8Xx is a series of SOM featuring NXP i.MX8X system-on-chip
variants. It is designed to be clicked on different carrier boards
MBa8Xx is the starterkit
oneOf:
- items:
- enum:
- tq,imx8dxp-tqma8xdp-mba8xx # TQ-Systems GmbH TQMa8XDP SOM on MBa8Xx
- const: tq,imx8dxp-tqma8xdp # TQ-Systems GmbH TQMa8XDP SOM (with i.MX8DXP)
- const: fsl,imx8dxp
- items:
- enum:
- tq,imx8qxp-tqma8xqp-mba8xx # TQ-Systems GmbH TQMa8XQP SOM on MBa8Xx
- const: tq,imx8qxp-tqma8xqp # TQ-Systems GmbH TQMa8XQP SOM (with i.MX8QXP)
- const: fsl,imx8qxp
- description: i.MX8ULP based Boards
items:
- enum:
@ -1275,6 +1296,18 @@ properties:
- const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM
- const: fsl,imx93
- description: PHYTEC phyCORE-i.MX93 SoM based boards
items:
- const: phytec,imx93-phyboard-segin # phyBOARD-Segin with i.MX93
- const: phytec,imx93-phycore-som # phyCORE-i.MX93 SoM
- const: fsl,imx93
- description: Variscite VAR-SOM-MX93 based boards
items:
- const: variscite,var-som-mx93-symphony
- const: variscite,var-som-mx93
- const: fsl,imx93
- description:
Freescale Vybrid Platform Device Tree Bindings

27
Documentation/devicetree/bindings/arm/marvell/armada-38x.txt
View File

@ -1,27 +0,0 @@
Marvell Armada 38x Platforms Device Tree Bindings
-------------------------------------------------
Boards with a SoC of the Marvell Armada 38x family shall have the
following property:
Required root node property:
- compatible: must contain "marvell,armada380"
In addition, boards using the Marvell Armada 385 SoC shall have the
following property before the previous one:
Required root node property:
compatible: must contain "marvell,armada385"
In addition, boards using the Marvell Armada 388 SoC shall have the
following property before the previous one:
Required root node property:
compatible: must contain "marvell,armada388"
Example:
compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380";

70
Documentation/devicetree/bindings/arm/marvell/armada-38x.yaml Normal file
View File

@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/marvell/armada-38x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada 38x Platforms
maintainers:
- Gregory CLEMENT <gregory.clement@bootlin.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description:
Netgear Armada 380 GS110EM Managed Switch.
items:
- const: netgear,gs110emx
- const: marvell,armada380
- description:
Marvell Armada 385 Development Boards.
items:
- enum:
- marvell,a385-db-amc
- marvell,a385-db-ap
- const: marvell,armada385
- const: marvell,armada380
- description:
SolidRun Armada 385 based single-board computers.
items:
- enum:
- solidrun,clearfog-gtr-l8
- solidrun,clearfog-gtr-s4
- const: marvell,armada385
- const: marvell,armada380
- description:
Kobol Armada 388 based Helios-4 NAS.
items:
- const: kobol,helios4
- const: marvell,armada388
- const: marvell,armada385
- const: marvell,armada380
- description:
Marvell Armada 388 Development Boards.
items:
- enum:
- marvell,a388-gp
- const: marvell,armada388
- const: marvell,armada385
- const: marvell,armada380
- description:
SolidRun Armada 388 clearfog family single-board computers.
items:
- enum:
- solidrun,clearfog-base-a1
- solidrun,clearfog-pro-a1
- const: solidrun,clearfog-a1
- const: marvell,armada388
- const: marvell,armada385
- const: marvell,armada380
additionalProperties: true

198
Documentation/devicetree/bindings/arm/mediatek.yaml
View File

@ -17,6 +17,7 @@ properties:
const: '/'
compatible:
oneOf:
# Sort by SoC (last) compatible, then board compatible
- items:
- enum:
- mediatek,mt2701-evb
@ -84,6 +85,11 @@ properties:
- const: mediatek,mt7629
- items:
- enum:
- xiaomi,ax3000t
- const: mediatek,mt7981b
- items:
- enum:
- acelink,ew-7886cax
- bananapi,bpi-r3
- mediatek,mt7986a-rfb
- const: mediatek,mt7986a
@ -91,6 +97,10 @@ properties:
- enum:
- mediatek,mt7986b-rfb
- const: mediatek,mt7986b
- items:
- enum:
- bananapi,bpi-r4
- const: mediatek,mt7988a
- items:
- enum:
- mediatek,mt8127-moose
@ -129,75 +139,10 @@ properties:
- enum:
- mediatek,mt8173-evb
- const: mediatek,mt8173
- items:
- enum:
- mediatek,mt8183-evb
- const: mediatek,mt8183
- description: Google Hayato rev5
items:
- const: google,hayato-rev5-sku2
- const: google,hayato-sku2
- const: google,hayato
- const: mediatek,mt8192
- description: Google Hayato
items:
- const: google,hayato-rev1
- const: google,hayato
- const: mediatek,mt8192
- description: Google Spherion rev4 (Acer Chromebook 514)
items:
- const: google,spherion-rev4
- const: google,spherion
- const: mediatek,mt8192
- description: Google Spherion (Acer Chromebook 514)
items:
- const: google,spherion-rev3
- const: google,spherion-rev2
- const: google,spherion-rev1
- const: google,spherion-rev0
- const: google,spherion
- const: mediatek,mt8192
- description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H)
items:
- enum:
- google,tomato-rev2
- google,tomato-rev1
- const: google,tomato
- const: mediatek,mt8195
- description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H)
items:
- const: google,tomato-rev4
- const: google,tomato-rev3
- const: google,tomato
- const: mediatek,mt8195
- items:
- enum:
- mediatek,mt8186-evb
- const: mediatek,mt8186
- items:
- enum:
- mediatek,mt8188-evb
- const: mediatek,mt8188
- items:
- enum:
- mediatek,mt8192-evb
- const: mediatek,mt8192
- items:
- enum:
- mediatek,mt8195-demo
- mediatek,mt8195-evb
- const: mediatek,mt8195
- description: Google Burnet (HP Chromebook x360 11MK G3 EE)
items:
- const: google,burnet
- const: mediatek,mt8183
- description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
items:
- enum:
- google,krane-sku0
- google,krane-sku176
- const: google,krane
- const: mediatek,mt8183
- description: Google Cozmo (Acer Chromebook 314)
items:
- const: google,cozmo
@ -255,6 +200,13 @@ properties:
- google,kodama-sku32
- const: google,kodama
- const: mediatek,mt8183
- description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
items:
- enum:
- google,krane-sku0
- google,krane-sku176
- const: google,krane
- const: mediatek,mt8183
- description: Google Makomo (Lenovo 100e Chromebook 2nd Gen MTK 2)
items:
- enum:
@ -276,10 +228,125 @@ properties:
- google,willow-sku1
- const: google,willow
- const: mediatek,mt8183
- items:
- enum:
- mediatek,mt8183-evb
- const: mediatek,mt8183
- items:
- enum:
- mediatek,mt8183-pumpkin
- const: mediatek,mt8183
- description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868))
items:
- const: google,steelix-sku393219
- const: google,steelix-sku393216
- const: google,steelix
- const: mediatek,mt8186
- description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868))
items:
- const: google,steelix-sku393220
- const: google,steelix-sku393217
- const: google,steelix
- const: mediatek,mt8186
- description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868))
items:
- const: google,steelix-sku393221
- const: google,steelix-sku393218
- const: google,steelix
- const: mediatek,mt8186
- description: Google Rusty (Lenovo 100e Chromebook Gen 4)
items:
- const: google,steelix-sku196609
- const: google,steelix-sku196608
- const: google,steelix
- const: mediatek,mt8186
- description: Google Steelix (Lenovo 300e Yoga Chromebook Gen 4)
items:
- enum:
- google,steelix-sku131072
- google,steelix-sku131073
- const: google,steelix
- const: mediatek,mt8186
- description: Google Tentacruel (ASUS Chromebook CM14 Flip CM1402F)
items:
- const: google,tentacruel-sku262147
- const: google,tentacruel-sku262146
- const: google,tentacruel-sku262145
- const: google,tentacruel-sku262144
- const: google,tentacruel
- const: mediatek,mt8186
- description: Google Tentacruel (ASUS Chromebook CM14 Flip CM1402F)
items:
- const: google,tentacruel-sku262151
- const: google,tentacruel-sku262150
- const: google,tentacruel-sku262149
- const: google,tentacruel-sku262148
- const: google,tentacruel
- const: mediatek,mt8186
- description: Google Tentacool (ASUS Chromebook CM14 CM1402C)
items:
- const: google,tentacruel-sku327681
- const: google,tentacruel
- const: mediatek,mt8186
- description: Google Tentacool (ASUS Chromebook CM14 CM1402C)
items:
- const: google,tentacruel-sku327683
- const: google,tentacruel
- const: mediatek,mt8186
- items:
- enum:
- mediatek,mt8186-evb
- const: mediatek,mt8186
- items:
- enum:
- mediatek,mt8188-evb
- const: mediatek,mt8188
- description: Google Hayato
items:
- const: google,hayato-rev1
- const: google,hayato
- const: mediatek,mt8192
- description: Google Hayato rev5
items:
- const: google,hayato-rev5-sku2
- const: google,hayato-sku2
- const: google,hayato
- const: mediatek,mt8192
- description: Google Spherion (Acer Chromebook 514)
items:
- const: google,spherion-rev3
- const: google,spherion-rev2
- const: google,spherion-rev1
- const: google,spherion-rev0
- const: google,spherion
- const: mediatek,mt8192
- description: Google Spherion rev4 (Acer Chromebook 514)
items:
- const: google,spherion-rev4
- const: google,spherion
- const: mediatek,mt8192
- items:
- enum:
- mediatek,mt8192-evb
- const: mediatek,mt8192
- description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H)
items:
- enum:
- google,tomato-rev2
- google,tomato-rev1
- const: google,tomato
- const: mediatek,mt8195
- description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H)
items:
- const: google,tomato-rev4
- const: google,tomato-rev3
- const: google,tomato
- const: mediatek,mt8195
- items:
- enum:
- mediatek,mt8195-demo
- mediatek,mt8195-evb
- const: mediatek,mt8195
- items:
- enum:
- mediatek,mt8365-evk
@ -287,6 +354,7 @@ properties:
- items:
- enum:
- mediatek,mt8395-evk
- radxa,nio-12l
- const: mediatek,mt8395
- const: mediatek,mt8195
- items:

58
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@ -10,17 +10,10 @@ maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Some qcom based bootloaders identify the dtb blob based on a set of
device properties like SoC and platform and revisions of those components.
To support this scheme, we encode this information into the board compatible
string.
Each board must specify a top-level board compatible string with the following
format:
compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]"
The 'SoC' and 'board' elements are required. All other elements are optional.
For devices using the Qualcomm SoC the "compatible" properties consists of
one or several "manufacturer,model" strings, describing the device itself,
followed by one or several "qcom,<SoC>" strings, describing the SoC used in
the device.
The 'SoC' element must be one of the following strings:
@ -90,43 +83,9 @@ description: |
sm8650
x1e80100
The 'board' element must be one of the following strings:
adp
cdp
dragonboard
idp
liquid
mtp
qcp
qrd
rb2
ride
sbc
x100
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
as v1. If all versions of the 'board_version' elements match, then a
wildcard '*' should be used, e.g. 'v*'.
The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9.
Examples:
"qcom,msm8916-v1-cdp-pm8916-v2.1"
A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version
2.1.
"qcom,apq8074-v2.0-2-dragonboard/1-v0.1"
A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in
foundry 2.
There are many devices in the list below that run the standard ChromeOS
bootloader setup and use the open source depthcharge bootloader to boot the
OS. These devices do not use the scheme described above. For details, see:
OS. These devices use the bootflow explained at
https://docs.kernel.org/arch/arm/google/chromebook-boot-flow.html
properties:
@ -187,6 +146,7 @@ properties:
- microsoft,superman-lte
- microsoft,tesla
- motorola,peregrine
- samsung,matisselte
- const: qcom,msm8926
- const: qcom,msm8226
@ -244,11 +204,15 @@ properties:
- samsung,a5u-eur
- samsung,e5
- samsung,e7
- samsung,fortuna3g
- samsung,gprimeltecan
- samsung,grandmax
- samsung,grandprimelte
- samsung,gt510
- samsung,gt58
- samsung,j5
- samsung,j5x
- samsung,rossa
- samsung,serranove
- thwc,uf896
- thwc,ufi001c
@ -988,6 +952,7 @@ properties:
- items:
- enum:
- xiaomi,curtana
- xiaomi,joyeuse
- const: qcom,sm7125
@ -1035,6 +1000,7 @@ properties:
- items:
- enum:
- qcom,sm8550-hdk
- qcom,sm8550-mtp
- qcom,sm8550-qrd
- const: qcom,sm8550

71
Documentation/devicetree/bindings/arm/rockchip.yaml
View File

@ -37,29 +37,16 @@ properties:
- anbernic,rg351v
- const: rockchip,rk3326
- description: Anbernic RG353P
- description: Anbernic RK3566 Handheld Gaming Console
items:
- const: anbernic,rg353p
- const: rockchip,rk3566
- description: Anbernic RG353PS
items:
- const: anbernic,rg353ps
- const: rockchip,rk3566
- description: Anbernic RG353V
items:
- const: anbernic,rg353v
- const: rockchip,rk3566
- description: Anbernic RG353VS
items:
- const: anbernic,rg353vs
- const: rockchip,rk3566
- description: Anbernic RG503
items:
- const: anbernic,rg503
- enum:
- anbernic,rg353p
- anbernic,rg353ps
- anbernic,rg353v
- anbernic,rg353vs
- anbernic,rg503
- anbernic,rg-arc-d
- anbernic,rg-arc-s
- const: rockchip,rk3566
- description: Asus Tinker board
@ -237,6 +224,13 @@ properties:
- friendlyarm,nanopi-r5s
- const: rockchip,rk3568
- description: FriendlyElec NanoPi R6 series boards
items:
- enum:
- friendlyarm,nanopi-r6c
- friendlyarm,nanopi-r6s
- const: rockchip,rk3588s
- description: FriendlyElec NanoPC T6
items:
- const: friendlyarm,nanopc-t6
@ -626,9 +620,9 @@ properties:
- const: openailab,eaidk-610
- const: rockchip,rk3399
- description: Orange Pi RK3399 board
- description: Xunlong Orange Pi RK3399 board
items:
- const: rockchip,rk3399-orangepi
- const: xunlong,rk3399-orangepi
- const: rockchip,rk3399
- description: Phytec phyCORE-RK3288 Rapid Development Kit
@ -655,6 +649,14 @@ properties:
- const: pine64,pinephone-pro
- const: rockchip,rk3399
- description: Pine64 PineTab2
items:
- enum:
- pine64,pinetab2-v0.1
- pine64,pinetab2-v2.0
- const: pine64,pinetab2
- const: rockchip,rk3566
- description: Pine64 Rock64
items:
- const: pine64,rock64
@ -692,11 +694,17 @@ properties:
- description: Powkiddy RK3566 Handheld Gaming Console
items:
- enum:
- powkiddy,rgb10max3
- powkiddy,rgb30
- powkiddy,rk2023
- powkiddy,x55
- const: rockchip,rk3566
- description: QNAP TS-433-4G 4-Bay NAS
items:
- const: qnap,ts433
- const: rockchip,rk3568
- description: Radxa Compute Module 3(CM3)
items:
- enum:
@ -878,6 +886,11 @@ properties:
- const: rockchip,rv1108-evb
- const: rockchip,rv1108
- description: Rockchip Toybrick TB-RK3588X board
items:
- const: rockchip,rk3588-toybrick-x0
- const: rockchip,rk3588
- description: Theobroma Systems PX30-uQ7 with Haikou baseboard
items:
- const: tsd,px30-ringneck-haikou
@ -898,6 +911,12 @@ properties:
- const: tsd,rk3588-jaguar
- const: rockchip,rk3588
- description: Theobroma Systems RK3588-Q7 with Haikou baseboard
items:
- const: tsd,rk3588-tiger-haikou
- const: tsd,rk3588-tiger
- const: rockchip,rk3588
- description: Tronsmart Orion R68 Meta
items:
- const: tronsmart,orion-r68-meta
@ -940,9 +959,9 @@ properties:
- const: rockchip,rk3568-evb1-v10
- const: rockchip,rk3568
- description: Rockchip RK3568 Banana Pi R2 Pro
- description: Sinovoip RK3568 Banana Pi R2 Pro
items:
- const: rockchip,rk3568-bpi-r2pro
- const: sinovoip,rk3568-bpi-r2pro
- const: rockchip,rk3568
- description: Sonoff iHost Smart Home Hub

12
Documentation/devicetree/bindings/arm/sunxi.yaml
View File

@ -815,6 +815,12 @@ properties:
- const: allwinner,r7-tv-dongle
- const: allwinner,sun5i-a10s
- description: Remix Mini PC
items:
- const: jide,remix-mini-pc
- const: allwinner,sun50i-h64
- const: allwinner,sun50i-a64
- description: RerVision H3-DVK
items:
- const: rervision,h3-dvk
@ -835,6 +841,12 @@ properties:
- const: sinlinx,sina33
- const: allwinner,sun8i-a33
- description: Sipeed Longan Pi 3H board for the Sipeed Longan Module 3H
items:
- const: sipeed,longan-pi-3h
- const: sipeed,longan-module-3h
- const: allwinner,sun50i-h618
- description: SourceParts PopStick v1.1
items:
- const: sourceparts,popstick-v1.1

8
Documentation/devicetree/bindings/arm/tegra.yaml
View File

@ -64,6 +64,14 @@ properties:
- items:
- const: asus,tf700t
- const: nvidia,tegra30
- description: LG Optimus 4X P880
items:
- const: lg,p880
- const: nvidia,tegra30
- description: LG Optimus Vu P895
items:
- const: lg,p895
- const: nvidia,tegra30
- items:
- const: toradex,apalis_t30-eval
- const: toradex,apalis_t30

54
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml
View File

@ -27,7 +27,7 @@ properties:
- const: pmc
- const: wake
- const: aotag
- const: scratch
- enum: [ scratch, misc ]
- const: misc
interrupt-controller: true
@ -41,25 +41,43 @@ properties:
description: If present, inverts the PMU interrupt signal.
$ref: /schemas/types.yaml#/definitions/flag
if:
properties:
compatible:
contains:
const: nvidia,tegra186-pmc
then:
properties:
reg:
maxItems: 4
allOf:
- if:
properties:
compatible:
contains:
const: nvidia,tegra186-pmc
then:
properties:
reg:
maxItems: 4
reg-names:
maxItems: 4
contains:
const: scratch
reg-names:
maxItems: 4
else:
properties:
reg:
minItems: 5
- if:
properties:
compatible:
contains:
const: nvidia,tegra194-pmc
then:
properties:
reg:
minItems: 5
reg-names:
minItems: 5
reg-names:
minItems: 5
- if:
properties:
compatible:
contains:
const: nvidia,tegra234-pmc
then:
properties:
reg-names:
contains:
const: misc
patternProperties:
"^[a-z0-9]+-[a-z0-9]+$":

14
Documentation/devicetree/bindings/arm/ti/k3.yaml
View File

@ -87,12 +87,20 @@ properties:
- const: tq,am642-tqma6442l
- const: ti,am642
- description: K3 AM642 SoC SolidRun SoM based boards
items:
- enum:
- solidrun,am642-hummingboard-t
- const: solidrun,am642-sr-som
- const: ti,am642
- description: K3 AM654 SoC
items:
- enum:
- siemens,iot2050-advanced
- siemens,iot2050-advanced-m2
- siemens,iot2050-advanced-pg2
- siemens,iot2050-advanced-sm
- siemens,iot2050-basic
- siemens,iot2050-basic-pg2
- ti,am654-evm
@ -123,6 +131,12 @@ properties:
- ti,j721s2-evm
- const: ti,j721s2
- description: K3 J722S SoC and Boards
items:
- enum:
- ti,j722s-evm
- const: ti,j722s
- description: K3 J784s4 SoC
items:
- enum:

28
Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
View File

@ -30,14 +30,16 @@ properties:
- google,gs101-cmu-top
- google,gs101-cmu-apm
- google,gs101-cmu-misc
- google,gs101-cmu-peric0
- google,gs101-cmu-peric1
clocks:
minItems: 1
maxItems: 2
maxItems: 3
clock-names:
minItems: 1
maxItems: 2
maxItems: 3
"#clock-cells":
const: 1
@ -88,6 +90,28 @@ allOf:
- const: bus
- const: sss
- if:
properties:
compatible:
contains:
enum:
- google,gs101-cmu-peric0
- google,gs101-cmu-peric1
then:
properties:
clocks:
items:
- description: External reference clock (24.576 MHz)
- description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
- description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- const: ip
additionalProperties: false
examples:

7
Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml
View File

@ -31,10 +31,15 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
power-domains:
items:
- description: CX domain
required:
- compatible
- clocks
- clock-names
- power-domains
allOf:
- $ref: qcom,gcc.yaml#
@ -44,6 +49,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@100000 {
compatible = "qcom,gcc-sc8180x";
reg = <0x00100000 0x1f0000>;
@ -51,6 +57,7 @@ examples:
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
power-domains = <&rpmhpd SC8180X_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

2
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
View File

@ -17,6 +17,7 @@ description: |
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
include/dt-bindings/clock/qcom,x1e80100-camcc.h
allOf:
- $ref: qcom,gcc.yaml#
@ -27,6 +28,7 @@ properties:
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
- qcom,x1e80100-camcc
clocks:
items:

2
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
View File

@ -18,6 +18,7 @@ description: |
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h
include/dt-bindings/reset/qcom,sm8650-gpucc.h
include/dt-bindings/reset/qcom,x1e80100-gpucc.h
properties:
compatible:
@ -25,6 +26,7 @@ properties:
- qcom,sm8450-gpucc
- qcom,sm8550-gpucc
- qcom,sm8650-gpucc
- qcom,x1e80100-gpucc
clocks:
items:

7
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
View File

@ -14,12 +14,17 @@ description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8550.
See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h
See also:
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
- include/dt-bindings/clock/qcom,x1e80100-dispcc.h
properties:
compatible:
enum:
- qcom,sm8550-dispcc
- qcom,sm8650-dispcc
- qcom,x1e80100-dispcc
clocks:
items:

1
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
View File

@ -23,6 +23,7 @@ properties:
- enum:
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
- qcom,x1e80100-tcsr
- const: syscon
clocks:

106
Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml
View File

@ -1,106 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller for SM8650
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8650.
See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h
properties:
compatible:
enum:
- qcom,sm8650-dispcc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
- description: Display's AHB clock
- description: sleep clock
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Byte clock from DSI PHY1
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY0
- description: VCO DIV clock from DP PHY0
- description: Link clock from DP PHY1
- description: VCO DIV clock from DP PHY1
- description: Link clock from DP PHY2
- description: VCO DIV clock from DP PHY2
- description: Link clock from DP PHY3
- description: VCO DIV clock from DP PHY3
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm8650-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,sm8650-dispcc";
reg = <0x0af00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
<&dsi1_phy 0>,
<&dsi1_phy 1>,
<&dp0_phy 0>,
<&dp0_phy 1>,
<&dp1_phy 0>,
<&dp1_phy 1>,
<&dp2_phy 0>,
<&dp2_phy 1>,
<&dp3_phy 0>,
<&dp3_phy 1>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

1
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
View File

@ -50,6 +50,7 @@ properties:
- renesas,r8a779a0-cpg-mssr # R-Car V3U
- renesas,r8a779f0-cpg-mssr # R-Car S4-8
- renesas,r8a779g0-cpg-mssr # R-Car V4H
- renesas,r8a779h0-cpg-mssr # R-Car V4M
reg:
maxItems: 1

1
Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml
View File

@ -29,6 +29,7 @@ properties:
vddi-supply:
description: regulator that supplies the vddi voltage
backlight: true
port: true
required:
- compatible

96
Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
View File

@ -26,6 +26,12 @@ properties:
- description: For implementations complying for Versal.
const: xlnx,versal-firmware
- description: For implementations complying for Versal NET.
items:
- enum:
- xlnx,versal-net-firmware
- const: xlnx,versal-firmware
method:
description: |
The method of calling the PM-API firmware layer.
@ -41,7 +47,53 @@ properties:
"#power-domain-cells":
const: 1
versal_fpga:
clock-controller:
$ref: /schemas/clock/xlnx,versal-clk.yaml#
description: The clock controller is a hardware block of Xilinx versal
clock tree. It reads required input clock frequencies from the devicetree
and acts as clock provider for all clock consumers of PS clocks.list of
clock specifiers which are external input clocks to the given clock
controller.
type: object
gpio:
$ref: /schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
description: The gpio node describes connect to PS_MODE pins via firmware
interface.
type: object
soc-nvmem:
$ref: /schemas/nvmem/xlnx,zynqmp-nvmem.yaml#
description: The ZynqMP MPSoC provides access to the hardware related data
like SOC revision, IDCODE and specific purpose efuses.
type: object
pcap:
$ref: /schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml
description: The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
configure the Programmable Logic (PL). The configuration uses the
firmware interface.
type: object
pinctrl:
$ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
description: The pinctrl node provides access to pinconfig and pincontrol
functionality available in firmware.
type: object
power-management:
$ref: /schemas/power/reset/xlnx,zynqmp-power.yaml#
description: The zynqmp-power node describes the power management
configurations. It will control remote suspend/shutdown interfaces.
type: object
reset-controller:
$ref: /schemas/reset/xlnx,zynqmp-reset.yaml#
description: The reset-controller node describes connection to the reset
functionality via firmware interface.
type: object
versal-fpga:
$ref: /schemas/fpga/xlnx,versal-fpga.yaml#
description: Compatible of the FPGA device.
type: object
@ -53,15 +105,6 @@ properties:
vector.
type: object
clock-controller:
$ref: /schemas/clock/xlnx,versal-clk.yaml#
description: The clock controller is a hardware block of Xilinx versal
clock tree. It reads required input clock frequencies from the devicetree
and acts as clock provider for all clock consumers of PS clocks.list of
clock specifiers which are external input clocks to the given clock
controller.
type: object
required:
- compatible
@ -73,7 +116,38 @@ examples:
firmware {
zynqmp_firmware: zynqmp-firmware {
#power-domain-cells = <1>;
soc-nvmem {
compatible = "xlnx,zynqmp-nvmem-fw";
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
soc_revision: soc-revision@0 {
reg = <0x0 0x4>;
};
};
};
gpio {
compatible = "xlnx,zynqmp-gpio-modepin";
gpio-controller;
#gpio-cells = <2>;
};
pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
pinctrl {
compatible = "xlnx,zynqmp-pinctrl";
};
power-management {
compatible = "xlnx,zynqmp-power";
interrupts = <0 35 4>;
};
reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
};
};
};
sata {
@ -84,7 +158,7 @@ examples:
compatible = "xlnx,versal-firmware";
method = "smc";
versal_fpga: versal_fpga {
versal_fpga: versal-fpga {
compatible = "xlnx,versal-fpga";
};

2
Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
View File

@ -26,7 +26,7 @@ additionalProperties: false
examples:
- |
versal_fpga: versal_fpga {
versal_fpga: versal-fpga {
compatible = "xlnx,versal-fpga";
};

4
Documentation/devicetree/bindings/gpu/img,powervr.yaml → Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
View File

@ -2,10 +2,10 @@
# Copyright (c) 2023 Imagination Technologies Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/img,powervr.yaml#
$id: http://devicetree.org/schemas/gpu/img,powervr-rogue.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Imagination Technologies PowerVR and IMG GPU
title: Imagination Technologies PowerVR and IMG Rogue GPUs
maintainers:
- Frank Binns <frank.binns@imgtec.com>

138
Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml Normal file
View File

@ -0,0 +1,138 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2023 Imagination Technologies Ltd.
# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/img,powervr-sgx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Imagination Technologies PowerVR SGX GPUs
maintainers:
- Frank Binns <frank.binns@imgtec.com>
properties:
compatible:
oneOf:
- items:
- enum:
- ti,omap3430-gpu # Rev 121
- ti,omap3630-gpu # Rev 125
- const: img,powervr-sgx530
- items:
- enum:
- ingenic,jz4780-gpu # Rev 130
- ti,omap4430-gpu # Rev 120
- const: img,powervr-sgx540
- items:
- enum:
- allwinner,sun6i-a31-gpu # MP2 Rev 115
- ti,omap4470-gpu # MP1 Rev 112
- ti,omap5432-gpu # MP2 Rev 105
- ti,am5728-gpu # MP2 Rev 116
- ti,am6548-gpu # MP1 Rev 117
- const: img,powervr-sgx544
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
maxItems: 3
clock-names:
minItems: 1
items:
- const: core
- const: mem
- const: sys
power-domains:
maxItems: 1
required:
- compatible
- reg
- interrupts
allOf:
- if:
properties:
compatible:
contains:
const: ti,am6548-gpu
then:
required:
- power-domains
else:
properties:
power-domains: false
- if:
properties:
compatible:
contains:
enum:
- allwinner,sun6i-a31-gpu
- ingenic,jz4780-gpu
then:
required:
- clocks
- clock-names
else:
properties:
clocks: false
clock-names: false
- if:
properties:
compatible:
contains:
const: allwinner,sun6i-a31-gpu
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
minItems: 2
maxItems: 2
- if:
properties:
compatible:
contains:
const: ingenic,jz4780-gpu
then:
properties:
clocks:
maxItems: 1
clock-names:
maxItems: 1
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
gpu@7000000 {
compatible = "ti,am6548-gpu", "img,powervr-sgx544";
reg = <0x7000000 0x10000>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
};
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpu: gpu@1c40000 {
compatible = "allwinner,sun6i-a31-gpu", "img,powervr-sgx544";
reg = <0x01c40000 0x10000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu 1>, <&ccu 2>;
clock-names = "core", "mem";
};

31
Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
View File

@ -16,14 +16,18 @@ description: |+
properties:
compatible:
enum:
- mediatek,mt8173-vcodec-enc-vp8
- mediatek,mt8173-vcodec-enc
- mediatek,mt8183-vcodec-enc
- mediatek,mt8188-vcodec-enc
- mediatek,mt8192-vcodec-enc
- mediatek,mt8195-vcodec-enc
oneOf:
- items:
- enum:
- mediatek,mt8173-vcodec-enc-vp8
- mediatek,mt8173-vcodec-enc
- mediatek,mt8183-vcodec-enc
- mediatek,mt8188-vcodec-enc
- mediatek,mt8192-vcodec-enc
- mediatek,mt8195-vcodec-enc
- items:
- const: mediatek,mt8186-vcodec-enc
- const: mediatek,mt8183-vcodec-enc
reg:
maxItems: 1
@ -109,10 +113,7 @@ allOf:
properties:
compatible:
enum:
- mediatek,mt8173-vcodec-enc
- mediatek,mt8188-vcodec-enc
- mediatek,mt8192-vcodec-enc
- mediatek,mt8195-vcodec-enc
- mediatek,mt8173-vcodec-enc-vp8
then:
properties:
@ -122,8 +123,8 @@ allOf:
maxItems: 1
clock-names:
items:
- const: venc_sel
else: # for vp8 hw encoder
- const: venc_lt_sel
else:
properties:
clock:
items:
@ -131,7 +132,7 @@ allOf:
maxItems: 1
clock-names:
items:
- const: venc_lt_sel
- const: venc_sel
additionalProperties: false

3
Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
View File

@ -38,7 +38,8 @@ properties:
maxItems: 1
iommus:
maxItems: 2
minItems: 2
maxItems: 4
description: |
Points to the respective IOMMU block with master port as argument, see
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.

1
Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
View File

@ -45,6 +45,7 @@ properties:
- renesas,r8a779a0-sysc # R-Car V3U
- renesas,r8a779f0-sysc # R-Car S4-8
- renesas,r8a779g0-sysc # R-Car V4H
- renesas,r8a779h0-sysc # R-Car V4M
reg:
maxItems: 1

1
Documentation/devicetree/bindings/reset/renesas,rst.yaml
View File

@ -50,6 +50,7 @@ properties:
- renesas,r8a779a0-rst # R-Car V3U
- renesas,r8a779f0-rst # R-Car S4-8
- renesas,r8a779g0-rst # R-Car V4H
- renesas,r8a779h0-rst # R-Car V4M
reg:
maxItems: 1

73
Documentation/devicetree/bindings/soc/renesas/renesas-soc.yaml Normal file
View File

@ -0,0 +1,73 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/renesas/renesas-soc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas SoC compatibles naming convention
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
- Niklas Söderlund <niklas.soderlund@ragnatech.se>
description: |
Guidelines for new compatibles for SoC blocks/components.
When adding new compatibles in new bindings, use the format::
renesas,SoC-IP
For example::
renesas,r8a77965-csi2
When adding new compatibles to existing bindings, use the format in the
existing binding, even if it contradicts the above.
select:
properties:
compatible:
contains:
pattern: "^renesas,.+-.+$"
required:
- compatible
properties:
compatible:
minItems: 1
maxItems: 4
items:
anyOf:
# Preferred naming style for compatibles of SoC components
- pattern: "^renesas,(emev2|r(7s|8a|9a)[a-z0-9]+|rcar|rmobile|rz[a-z0-9]*|sh(7[a-z0-9]+)?|mobile)-[a-z0-9-]+$"
- pattern: "^renesas,(condor|falcon|gr-peach|gray-hawk|salvator|sk-rz|smar(c(2)?)?|spider|white-hawk)(.*)?$"
# Legacy compatibles
#
# New compatibles are not allowed.
- pattern: "^renesas,(can|cpg|dmac|du|(g)?ether(avb)?|gpio|hscif|(r)?i[i2]c|imr|intc|ipmmu|irqc|jpu|mmcif|msiof|mtu2|pci(e)?|pfc|pwm|[rq]spi|rcar_sound|sata|scif[ab]*|sdhi|thermal|tmu|tpu|usb(2|hs)?|vin|xhci)-[a-z0-9-]+$"
- pattern: "^renesas,(d|s)?bsc(3)?-(r8a73a4|r8a7740|sh73a0)$"
- pattern: "^renesas,em-(gio|sti|uart)$"
- pattern: "^renesas,fsi2-(r8a7740|sh73a0)$"
- pattern: "^renesas,hspi-r8a777[89]$"
- pattern: "^renesas,sysc-(r8a73a4|r8a7740|rmobile|sh73a0)$"
- enum:
- renesas,imr-lx4
- renesas,mtu2-r7s72100
# None SoC component compatibles
#
# Compatibles with the Renesas vendor prefix that do not relate to any SoC
# component are OK. New compatibles are allowed.
- enum:
- renesas,smp-sram
# Do not fail compatibles not matching the select pattern
#
# Some SoC components in addition to a Renesas compatible list
# compatibles not related to Renesas. The select pattern for this
# schema hits all compatibles that have at lest one Renesas compatible
# and try to validate all values in that compatible array, allow all
# that don't match the schema select pattern. For example,
#
# compatible = "renesas,r9a07g044-mali", "arm,mali-bifrost";
- pattern: "^(?!renesas,.+-.+).+$"
additionalProperties: true

25
Documentation/devicetree/bindings/soc/renesas/renesas.yaml
View File

@ -348,12 +348,25 @@ properties:
- renesas,white-hawk-cpu # White Hawk CPU board (RTP8A779G0ASKB0FC0SA000)
- const: renesas,r8a779g0
- description: R-Car V4H (R8A779G2)
items:
- enum:
- renesas,white-hawk-single # White Hawk Single board (RTP8A779G2ASKB0F10SA001)
- const: renesas,r8a779g2
- const: renesas,r8a779g0
- items:
- enum:
- renesas,white-hawk-breakout # White Hawk BreakOut board (RTP8A779G0ASKB0SB0SA000)
- const: renesas,white-hawk-cpu
- const: renesas,r8a779g0
- description: R-Car V4M (R8A779H0)
items:
- enum:
- renesas,gray-hawk-single # Gray Hawk Single board (RTP8A779H0ASKB0F10S)
- const: renesas,r8a779h0
- description: R-Car H3e (R8A779M0)
items:
- enum:
@ -475,12 +488,6 @@ properties:
- renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L
- const: renesas,r9a07g054
- description: RZ/V2M (R9A09G011)
items:
- enum:
- renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
- const: renesas,r9a09g011
- description: RZ/G3S (R9A08G045)
items:
- enum:
@ -500,6 +507,12 @@ properties:
- const: renesas,r9a08g045s33 # PCIe support
- const: renesas,r9a08g045
- description: RZ/V2M (R9A09G011)
items:
- enum:
- renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
- const: renesas,r9a09g011
additionalProperties: true
...

22
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
View File

@ -22,12 +22,15 @@ properties:
- rockchip,rk3568-usb2phy-grf
- rockchip,rk3588-bigcore0-grf
- rockchip,rk3588-bigcore1-grf
- rockchip,rk3588-hdptxphy-grf
- rockchip,rk3588-ioc
- rockchip,rk3588-php-grf
- rockchip,rk3588-pipe-phy-grf
- rockchip,rk3588-sys-grf
- rockchip,rk3588-pcie3-phy-grf
- rockchip,rk3588-pcie3-pipe-grf
- rockchip,rk3588-usb-grf
- rockchip,rk3588-usbdpphy-grf
- rockchip,rk3588-vo-grf
- rockchip,rk3588-vop-grf
- rockchip,rv1108-usbgrf
@ -66,6 +69,9 @@ properties:
reg:
maxItems: 1
clocks:
maxItems: 1
"#address-cells":
const: 1
@ -248,6 +254,22 @@ allOf:
unevaluatedProperties: false
- if:
properties:
compatible:
contains:
enum:
- rockchip,rk3588-vo-grf
then:
required:
- clocks
else:
properties:
clocks: false
examples:
- |
#include <dt-bindings/clock/rk3399-cru.h>

70
Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
View File

@ -117,20 +117,70 @@ properties:
- const: xlnx,zynqmp
- description: Xilinx Kria SOMs
minItems: 3
items:
- const: xlnx,zynqmp-sm-k26-rev1
- const: xlnx,zynqmp-sm-k26-revB
- const: xlnx,zynqmp-sm-k26-revA
- const: xlnx,zynqmp-sm-k26
- const: xlnx,zynqmp
enum:
- xlnx,zynqmp-sm-k26-rev2
- xlnx,zynqmp-sm-k26-rev1
- xlnx,zynqmp-sm-k26-revB
- xlnx,zynqmp-sm-k26-revA
- xlnx,zynqmp-sm-k26
- xlnx,zynqmp
allOf:
- contains:
const: xlnx,zynqmp
- contains:
const: xlnx,zynqmp-sm-k26
- description: Xilinx Kria SOMs (starter)
minItems: 3
items:
- const: xlnx,zynqmp-smk-k26-rev1
- const: xlnx,zynqmp-smk-k26-revB
- const: xlnx,zynqmp-smk-k26-revA
- const: xlnx,zynqmp-smk-k26
- const: xlnx,zynqmp
enum:
- xlnx,zynqmp-smk-k26-rev2
- xlnx,zynqmp-smk-k26-rev1
- xlnx,zynqmp-smk-k26-revB
- xlnx,zynqmp-smk-k26-revA
- xlnx,zynqmp-smk-k26
- xlnx,zynqmp
allOf:
- contains:
const: xlnx,zynqmp
- contains:
const: xlnx,zynqmp-smk-k26
- description: Xilinx Kria SOM KV260 revA/Y/Z
minItems: 3
items:
enum:
- xlnx,zynqmp-sk-kv260-revA
- xlnx,zynqmp-sk-kv260-revY
- xlnx,zynqmp-sk-kv260-revZ
- xlnx,zynqmp-sk-kv260
- xlnx,zynqmp
allOf:
- contains:
const: xlnx,zynqmp-sk-kv260-revA
- contains:
const: xlnx,zynqmp-sk-kv260
- contains:
const: xlnx,zynqmp
- description: Xilinx Kria SOM KV260 rev2/1/B
minItems: 3
items:
enum:
- xlnx,zynqmp-sk-kv260-rev2
- xlnx,zynqmp-sk-kv260-rev1
- xlnx,zynqmp-sk-kv260-revB
- xlnx,zynqmp-sk-kv260
- xlnx,zynqmp
allOf:
- contains:
const: xlnx,zynqmp-sk-kv260-revB
- contains:
const: xlnx,zynqmp-sk-kv260
- contains:
const: xlnx,zynqmp
- description: AMD MicroBlaze V (QEMU)
items:

2
Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
View File

@ -56,7 +56,7 @@ properties:
ranges: true
patternProperties:
"^sram@[a-z0-9]+":
"^sram@[a-f0-9]+":
$ref: /schemas/sram/sram.yaml#
unevaluatedProperties: false

8
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -39,6 +39,8 @@ patternProperties:
description: ShenZhen Asia Better Technology Ltd.
"^acbel,.*":
description: Acbel Polytech Inc.
"^acelink,.*":
description: Acelink Technology Co., Ltd.
"^acer,.*":
description: Acer Inc.
"^acme,.*":
@ -500,6 +502,8 @@ patternProperties:
description: FocalTech Systems Co.,Ltd
"^forlinx,.*":
description: Baoding Forlinx Embedded Technology Co., Ltd.
"^freebox,.*":
description: Freebox SAS
"^freecom,.*":
description: Freecom Gmbh
"^frida,.*":
@ -719,6 +723,8 @@ patternProperties:
description: JetHome (IP Sokolov P.A.)
"^jianda,.*":
description: Jiandangjing Technology Co., Ltd.
"^jide,.*":
description: Jide Tech
"^joz,.*":
description: JOZ BV
"^kam,.*":
@ -1484,6 +1490,8 @@ patternProperties:
description: Ufi Space Co., Ltd.
"^ugoos,.*":
description: Ugoos Industrial Co., Ltd.
"^uni-t,.*":
description: Uni-Trend Technology (China) Co., Ltd.
"^uniwest,.*":
description: United Western Technologies Corp (UniWest)
"^upisemi,.*":

13
MAINTAINERS
View File

@ -10482,7 +10482,8 @@ M: Donald Robson <donald.robson@imgtec.com>
M: Matt Coster <matt.coster@imgtec.com>
S: Supported
T: git git://anongit.freedesktop.org/drm/drm-misc
F: Documentation/devicetree/bindings/gpu/img,powervr.yaml
F: Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
F: Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
F: Documentation/gpu/imagination/
F: drivers/gpu/drm/imagination/
F: include/uapi/drm/pvr_drm.h
@ -18884,6 +18885,7 @@ F: Documentation/devicetree/bindings/riscv/
F: arch/riscv/boot/dts/
X: arch/riscv/boot/dts/allwinner/
X: arch/riscv/boot/dts/renesas/
X: arch/riscv/boot/dts/sophgo/
RISC-V PMU DRIVERS
M: Atish Patra <atishp@atishpatra.org>
@ -20462,12 +20464,13 @@ F: drivers/char/sonypi.c
F: drivers/platform/x86/sony-laptop.c
F: include/linux/sony-laptop.h
SOPHGO DEVICETREES
M: Chao Wei <chao.wei@sophgo.com>
SOPHGO DEVICETREES and DRIVERS
M: Chen Wang <unicorn_wang@outlook.com>
M: Inochi Amaoto <inochiama@outlook.com>
T: git https://github.com/sophgo/linux.git
S: Maintained
F: arch/riscv/boot/dts/sophgo/
F: Documentation/devicetree/bindings/riscv/sophgo.yaml
N: sophgo
K: sophgo
SOUND
M: Jaroslav Kysela <perex@perex.cz>

4
arch/arm/Makefile
View File

@ -158,9 +158,7 @@ textofs-$(CONFIG_ARCH_REALTEK) := 0x00108000
ifeq ($(CONFIG_ARCH_SA1100),y)
textofs-$(CONFIG_SA1111) := 0x00208000
endif
textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
textofs-$(CONFIG_ARCH_QCOM_RESERVE_SMEM) := 0x00208000
textofs-$(CONFIG_ARCH_MESON) := 0x00208000
textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000

7
arch/arm/boot/dts/allwinner/sun8i-r40-feta40i.dtsi
View File

@ -42,6 +42,13 @@
vcc-pg-supply = <&reg_dldo1>;
};
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3-tv-usb";
};
&reg_aldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;

6
arch/arm/boot/dts/amlogic/meson.dtsi
View File

@ -23,7 +23,7 @@
#size-cells = <1>;
ranges;
cbus: cbus@c1100000 {
cbus: bus@c1100000 {
compatible = "simple-bus";
reg = <0xc1100000 0x200000>;
#address-cells = <1>;
@ -206,7 +206,7 @@
};
};
aobus: aobus@c8100000 {
aobus: bus@c8100000 {
compatible = "simple-bus";
reg = <0xc8100000 0x100000>;
#address-cells = <1>;
@ -302,7 +302,7 @@
reg = <0xd9040000 0x10000>;
};
secbus: secbus@da000000 {
secbus: bus@da000000 {
compatible = "simple-bus";
reg = <0xda000000 0x6000>;
#address-cells = <1>;

1
arch/arm/boot/dts/amlogic/meson8.dtsi
View File

@ -645,7 +645,6 @@
};
&hwrng {
compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
clocks = <&clkc CLKID_RNG0>;
clock-names = "core";
};

1
arch/arm/boot/dts/amlogic/meson8b.dtsi
View File

@ -620,7 +620,6 @@
};
&hwrng {
compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
clocks = <&clkc CLKID_RNG0>;
clock-names = "core";
};

2
arch/arm/boot/dts/arm/arm-realview-pb1176.dts
View File

@ -451,7 +451,7 @@
/* Direct-mapped development chip ROM */
pb1176_rom@10200000 {
compatible = "direct-mapped";
compatible = "mtd-rom";
reg = <0x10200000 0x4000>;
bank-width = <1>;
};

3
arch/arm/boot/dts/arm/integratorap-im-pd1.dts
View File

@ -129,8 +129,6 @@
bridge {
compatible = "ti,ths8134b", "ti,ths8134";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
@ -154,6 +152,7 @@
vga {
compatible = "vga-connector";
label = "J30";
port {
vga_con_in: endpoint {

3
arch/arm/boot/dts/arm/versatile-ab.dts
View File

@ -32,8 +32,6 @@
bridge {
compatible = "ti,ths8134b", "ti,ths8134";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
@ -59,6 +57,7 @@
vga {
compatible = "vga-connector";
label = "J1";
port {
vga_con_in: endpoint {

4
arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts
View File

@ -20,7 +20,9 @@
#address-cells = <1>;
#size-cells = <1>;
chosen { };
chosen {
stdout-path = &v2m_serial0;
};
aliases {
serial0 = &v2m_serial0;

30
arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts
View File

@ -27,10 +27,10 @@
gpio_keys {
compatible = "gpio-keys";
button-esc {
button-reset {
debounce-interval = <100>;
wakeup-source;
linux,code = <KEY_ESC>;
linux,code = <KEY_RESTART>;
label = "reset";
/* Collides with LPC_LAD[0], UART DCD, SSP 97RST */
gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
@ -187,7 +187,7 @@
};
/* This is a RealTek RTL8366RB switch and PHY using SMI over GPIO */
switch {
ethernet-switch {
compatible = "realtek,rtl8366rb";
/* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
@ -204,36 +204,36 @@
#interrupt-cells = <1>;
};
ports {
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
ethernet-port@0 {
reg = <0>;
label = "lan0";
phy-handle = <&phy0>;
};
port@1 {
ethernet-port@1 {
reg = <1>;
label = "lan1";
phy-handle = <&phy1>;
};
port@2 {
ethernet-port@2 {
reg = <2>;
label = "lan2";
phy-handle = <&phy2>;
};
port@3 {
ethernet-port@3 {
reg = <3>;
label = "lan3";
phy-handle = <&phy3>;
};
port@4 {
ethernet-port@4 {
reg = <4>;
label = "wan";
phy-handle = <&phy4>;
};
rtl8366rb_cpu_port: port@5 {
rtl8366rb_cpu_port: ethernet-port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
@ -252,27 +252,27 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@0 {
phy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&switch_intc>;
interrupts = <0>;
};
phy1: phy@1 {
phy1: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&switch_intc>;
interrupts = <1>;
};
phy2: phy@2 {
phy2: ethernet-phy@2 {
reg = <2>;
interrupt-parent = <&switch_intc>;
interrupts = <2>;
};
phy3: phy@3 {
phy3: ethernet-phy@3 {
reg = <3>;
interrupt-parent = <&switch_intc>;
interrupts = <3>;
};
phy4: phy@4 {
phy4: ethernet-phy@4 {
reg = <4>;
interrupt-parent = <&switch_intc>;
interrupts = <12>;

4
arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts
View File

@ -33,10 +33,10 @@
gpio_keys {
compatible = "gpio-keys";
button-esc {
button-reset {
debounce-interval = <100>;
wakeup-source;
linux,code = <KEY_ESC>;
linux,code = <KEY_RESTART>;
label = "reset";
gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
};

16
arch/arm/boot/dts/gemini/gemini-sl93512r.dts
View File

@ -43,7 +43,7 @@
button-setup {
debounce-interval = <50>;
wakeup-source;
linux,code = <KEY_SETUP>;
linux,code = <KEY_RESTART>;
label = "factory reset";
/* Conflict with NAND flash */
gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
@ -93,7 +93,7 @@
cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
switch@0 {
ethernet-switch@0 {
compatible = "vitesse,vsc7385";
reg = <0>;
/* Specified for 2.5 MHz or below */
@ -101,27 +101,27 @@
gpio-controller;
#gpio-cells = <2>;
ports {
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
ethernet-port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
ethernet-port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
ethernet-port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
ethernet-port@3 {
reg = <3>;
label = "lan4";
};
vsc: port@6 {
vsc: ethernet-port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac1>;

16
arch/arm/boot/dts/gemini/gemini-sq201.dts
View File

@ -30,7 +30,7 @@
button-setup {
debounce-interval = <100>;
wakeup-source;
linux,code = <KEY_SETUP>;
linux,code = <KEY_RESTART>;
label = "factory reset";
/* Conflict with NAND flash */
gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
@ -78,7 +78,7 @@
cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
switch@0 {
ethernet-switch@0 {
compatible = "vitesse,vsc7395";
reg = <0>;
/* Specified for 2.5 MHz or below */
@ -86,27 +86,27 @@
gpio-controller;
#gpio-cells = <2>;
ports {
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
ethernet-port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
ethernet-port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
ethernet-port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
ethernet-port@3 {
reg = <3>;
label = "lan4";
};
vsc: port@6 {
vsc: ethernet-port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac1>;

6
arch/arm/boot/dts/gemini/gemini-wbd111.dts
View File

@ -10,7 +10,7 @@
/ {
model = "Wiliboard WBD-111";
compatible = "wiliboard,wbd111", "cortina,gemini";
compatible = "wiligear,wiliboard-wbd111", "cortina,gemini";
#address-cells = <1>;
#size-cells = <1>;
@ -28,10 +28,10 @@
gpio_keys {
compatible = "gpio-keys";
button-setup {
button-reset {
debounce-interval = <100>;
wakeup-source;
linux,code = <KEY_SETUP>;
linux,code = <KEY_RESTART>;
label = "reset";
/* Conflict with ICE */
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;

6
arch/arm/boot/dts/gemini/gemini-wbd222.dts
View File

@ -10,7 +10,7 @@
/ {
model = "Wiliboard WBD-222";
compatible = "wiliboard,wbd222", "cortina,gemini";
compatible = "wiligear,wiliboard-wbd222", "cortina,gemini";
#address-cells = <1>;
#size-cells = <1>;
@ -27,10 +27,10 @@
gpio_keys {
compatible = "gpio-keys";
button-setup {
button-reset {
debounce-interval = <100>;
wakeup-source;
linux,code = <KEY_SETUP>;
linux,code = <KEY_RESTART>;
label = "reset";
/* Conflict with ICE */
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;

38
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts
View File

@ -4,6 +4,18 @@
/ {
model = "SolidRun Clearfog GTR L8";
compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385",
"marvell,armada380";
/* CON25 */
sfp1: sfp-1 {
compatible = "sff,sfp";
pinctrl-0 = <&cf_gtr_sfp1_pins>;
pinctrl-names = "default";
i2c-bus = <&i2c0>;
mod-def0-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
};
};
&mdio {
@ -20,57 +32,65 @@
ethernet-port@1 {
reg = <1>;
label = "lan8";
label = "lan1";
phy-handle = <&switch0phy0>;
};
ethernet-port@2 {
reg = <2>;
label = "lan7";
label = "lan2";
phy-handle = <&switch0phy1>;
};
ethernet-port@3 {
reg = <3>;
label = "lan6";
label = "lan3";
phy-handle = <&switch0phy2>;
};
ethernet-port@4 {
reg = <4>;
label = "lan5";
label = "lan4";
phy-handle = <&switch0phy3>;
};
ethernet-port@5 {
reg = <5>;
label = "lan4";
label = "lan5";
phy-handle = <&switch0phy4>;
};
ethernet-port@6 {
reg = <6>;
label = "lan3";
label = "lan6";
phy-handle = <&switch0phy5>;
};
ethernet-port@7 {
reg = <7>;
label = "lan2";
label = "lan7";
phy-handle = <&switch0phy6>;
};
ethernet-port@8 {
reg = <8>;
label = "lan1";
label = "lan8";
phy-handle = <&switch0phy7>;
};
ethernet-port@9 {
reg = <9>;
label = "lan-sfp";
phy-mode = "sgmii";
sfp = <&sfp1>;
managed = "in-band-status";
};
ethernet-port@10 {
reg = <10>;
phy-mode = "2500base-x";
ethernet = <&eth1>;
fixed-link {
speed = <2500>;
full-duplex;

2
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts
View File

@ -4,6 +4,8 @@
/ {
model = "SolidRun Clearfog GTR S4";
compatible = "solidrun,clearfog-gtr-s4", "marvell,armada385",
"marvell,armada380";
};
&sfp0 {

130
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi
View File

@ -141,6 +141,77 @@
};
pinctrl@18000 {
cf_gtr_fan_pwm: cf-gtr-fan-pwm {
marvell,pins = "mpp23";
marvell,function = "gpio";
};
cf_gtr_front_button_pins: cf-gtr-front-button-pins {
marvell,pins = "mpp53";
marvell,function = "gpio";
};
cf_gtr_i2c1_pins: i2c1-pins {
/* SFP */
marvell,pins = "mpp26", "mpp27";
marvell,function = "i2c1";
};
cf_gtr_isolation_pins: cf-gtr-isolation-pins {
marvell,pins = "mpp47";
marvell,function = "gpio";
};
cf_gtr_led_pins: led-pins {
marvell,pins = "mpp42", "mpp52";
marvell,function = "gpio";
};
cf_gtr_lte_disable_pins: lte-disable-pins {
marvell,pins = "mpp34";
marvell,function = "gpio";
};
cf_gtr_pci_pins: pci-pins {
// pci reset
marvell,pins = "mpp33", "mpp35", "mpp44";
marvell,function = "gpio";
};
cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
marvell,pins = "mpp48";
marvell,function = "gpio";
};
cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
marvell,pins = "mpp36";
marvell,function = "gpio";
};
cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
marvell,pins = "mpp21", "mpp28",
"mpp37", "mpp38",
"mpp39", "mpp40";
marvell,function = "sd0";
};
cf_gtr_sfp0_pins: sfp0-pins {
/* sfp modabs, txdisable */
marvell,pins = "mpp25", "mpp46";
marvell,function = "gpio";
};
cf_gtr_sfp1_pins: sfp1-pins {
/* sfp modabs, txdisable */
marvell,pins = "mpp24", "mpp54";
marvell,function = "gpio";
};
cf_gtr_spi1_cs_pins: spi1-cs-pins {
marvell,pins = "mpp59";
marvell,function = "spi1";
};
cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
marvell,pins = "mpp18";
marvell,function = "gpio";
@ -151,46 +222,8 @@
marvell,function = "gpio";
};
cf_gtr_fan_pwm: cf-gtr-fan-pwm {
marvell,pins = "mpp23";
marvell,function = "gpio";
};
cf_gtr_i2c1_pins: i2c1-pins {
/* SFP */
marvell,pins = "mpp26", "mpp27";
marvell,function = "i2c1";
};
cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
marvell,pins = "mpp21", "mpp28",
"mpp37", "mpp38",
"mpp39", "mpp40";
marvell,function = "sd0";
};
cf_gtr_isolation_pins: cf-gtr-isolation-pins {
marvell,pins = "mpp47";
marvell,function = "gpio";
};
cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
marvell,pins = "mpp48";
marvell,function = "gpio";
};
cf_gtr_spi1_cs_pins: spi1-cs-pins {
marvell,pins = "mpp59";
marvell,function = "spi1";
};
cf_gtr_front_button_pins: cf-gtr-front-button-pins {
marvell,pins = "mpp53";
marvell,function = "gpio";
};
cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
marvell,pins = "mpp36";
cf_gtr_wifi_disable_pins: wifi-disable-pins {
marvell,pins = "mpp30", "mpp31";
marvell,function = "gpio";
};
};
@ -221,21 +254,26 @@
};
pcie {
pinctrl-0 = <&cf_gtr_pci_pins>;
pinctrl-names = "default";
status = "okay";
/*
* The PCIe units are accessible through
* the mini-PCIe connectors on the board.
*/
/* CON3 - serdes 0 */
pcie@1,0 {
reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* CON4 - serdes 2 */
pcie@2,0 {
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* CON2 - serdes 4 */
pcie@3,0 {
reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
status = "okay";
@ -243,10 +281,12 @@
};
};
sfp0: sfp {
/* CON5 */
sfp0: sfp-0 {
compatible = "sff,sfp";
pinctrl-0 = <&cf_gtr_sfp0_pins>;
pinctrl-names = "default";
i2c-bus = <&i2c1>;
los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
};
@ -273,6 +313,8 @@
gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = <&cf_gtr_led_pins>;
pinctrl-names = "default";
led1 {
function = LED_FUNCTION_CPU;
@ -408,7 +450,7 @@
};
&gpio0 {
pinctrl-0 = <&cf_gtr_fan_pwm>;
pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>;
pinctrl-names = "default";
wifi-disable {
@ -420,7 +462,7 @@
};
&gpio1 {
pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>;
pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>;
pinctrl-names = "default";
lte-disable {

5
arch/arm/boot/dts/marvell/armada-388-clearfog.dts
View File

@ -10,8 +10,9 @@
/ {
model = "SolidRun Clearfog A1";
compatible = "solidrun,clearfog-a1", "marvell,armada388",
"marvell,armada385", "marvell,armada380";
compatible = "solidrun,clearfog-pro-a1", "solidrun,clearfog-a1",
"marvell,armada388", "marvell,armada385",
"marvell,armada380";
soc {
internal-regs {

4
arch/arm/boot/dts/marvell/dove-cubox.dts
View File

@ -101,7 +101,7 @@
/* connect xtal input as source of pll0 and pll1 */
silabs,pll-source = <0 0>, <1 0>;
clkout0 {
clkout@0 {
reg = <0>;
silabs,drive-strength = <8>;
silabs,multisynth-source = <0>;
@ -109,7 +109,7 @@
silabs,pll-master;
};
clkout2 {
clkout@2 {
reg = <2>;
silabs,drive-strength = <8>;
silabs,multisynth-source = <1>;

2
arch/arm/boot/dts/marvell/mmp2-brownstone.dts
View File

@ -28,7 +28,7 @@
&twsi1 {
status = "okay";
pmic: max8925@3c {
compatible = "maxium,max8925";
compatible = "maxim,max8925";
reg = <0x3c>;
interrupts = <1>;
interrupt-parent = <&intcmux4>;

2
arch/arm/boot/dts/microchip/Makefile
View File

@ -11,6 +11,7 @@ DTC_FLAGS_at91-sama5d2_xplained := -@
DTC_FLAGS_at91-sama5d3_eds := -@
DTC_FLAGS_at91-sama5d3_xplained := -@
DTC_FLAGS_at91-sama5d4_xplained := -@
DTC_FLAGS_at91-sama7g54_curiosity := -@
DTC_FLAGS_at91-sama7g5ek := -@
dtb-$(CONFIG_SOC_AT91RM9200) += \
at91rm9200ek.dtb \
@ -87,6 +88,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
at91-sama5d4ek.dtb \
at91-vinco.dtb
dtb-$(CONFIG_SOC_SAMA7G5) += \
at91-sama7g54_curiosity.dtb \
at91-sama7g5ek.dtb
dtb-$(CONFIG_SOC_LAN966) += \

482
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts Normal file
View File

@ -0,0 +1,482 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sama7g54_curiosity.dts - Device Tree file for SAMA7G54 Curiosity Board
*
* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
*
* Author: Mihai Sain <mihai.sain@microchip.com>
*
*/
/dts-v1/;
#include "sama7g5-pinfunc.h"
#include "sama7g5.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/pinctrl/at91.h>
/ {
model = "Microchip SAMA7G54 Curiosity";
compatible = "microchip,sama7g54-curiosity", "microchip,sama7g5", "microchip,sama7";
aliases {
serial0 = &uart3;
i2c0 = &i2c10;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
button-user {
label = "user-button";
gpios = <&pioA PIN_PD19 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROG1>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led_gpio_default>;
led-red {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_POWER;
gpios = <&pioA PIN_PD13 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-green {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_BOOT;
gpios = <&pioA PIN_PD14 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-blue {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_CPU;
gpios = <&pioA PIN_PB15 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x10000000>; /* 256 MiB DDR3L-1066 16-bit */
};
};
&adc {
vddana-supply = <&vddout25>;
vref-supply = <&vddout25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>;
status = "okay";
};
&cpu0 {
cpu-supply = <&vddcpu>;
};
&dma0 {
status = "okay";
};
&dma1 {
status = "okay";
};
&dma2 {
status = "okay";
};
&ebi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand_default>;
status = "okay";
nand_controller: nand-controller {
status = "okay";
nand@3 {
reg = <0x3 0x0 0x800000>;
atmel,rb = <0>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
at91bootstrap@0 {
label = "nand: at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "nand: u-boot";
reg = <0x40000 0x100000>;
};
bootloaderenv@140000 {
label = "nand: u-boot env";
reg = <0x140000 0x40000>;
};
dtb@180000 {
label = "nand: device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "nand: kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "nand: rootfs";
reg = <0x800000 0x1f800000>;
};
};
};
};
};
&flx3 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
status = "okay";
uart3: serial@200 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx3_default>;
status = "okay";
};
};
&flx10 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
i2c10: i2c@600 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx10_default>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
size = <256>;
vcc-supply = <&vdd_3v3>;
};
pmic@5b {
compatible = "microchip,mcp16502";
reg = <0x5b>;
regulators {
vdd_3v3: VDD_IO {
regulator-name = "VDD_IO";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-off-in-suspend;
regulator-mode = <4>;
};
};
vddioddr: VDD_DDR {
regulator-name = "VDD_DDR";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1350000>;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1350000>;
regulator-mode = <4>;
};
};
vddcore: VDD_CORE {
regulator-name = "VDD_CORE";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-voltage = <1150000>;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-off-in-suspend;
regulator-mode = <4>;
};
};
vddcpu: VDD_OTHER {
regulator-name = "VDD_OTHER";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1250000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-ramp-delay = <3125>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-voltage = <1050000>;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-off-in-suspend;
regulator-mode = <4>;
};
};
vldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-state-standby {
regulator-suspend-voltage = <1800000>;
regulator-on-in-suspend;
};
regulator-state-mem {
regulator-off-in-suspend;
};
};
vldo2: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-state-standby {
regulator-suspend-voltage = <3300000>;
regulator-on-in-suspend;
};
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
};
&main_xtal {
clock-frequency = <24000000>;
};
&qspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_default>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <100000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
m25p,fast-read;
};
};
&pioA {
pinctrl_flx3_default: flx3-default {
pinmux = <PIN_PD16__FLEXCOM3_IO0>,
<PIN_PD17__FLEXCOM3_IO1>;
bias-pull-up;
};
pinctrl_flx10_default: flx10-default {
pinmux = <PIN_PC30__FLEXCOM10_IO0>,
<PIN_PC31__FLEXCOM10_IO1>;
bias-pull-up;
};
pinctrl_key_gpio_default: key-gpio-default {
pinmux = <PIN_PD19__GPIO>;
bias-pull-up;
};
pinctrl_led_gpio_default: led-gpio-default {
pinmux = <PIN_PD13__GPIO>,
<PIN_PD14__GPIO>,
<PIN_PB15__GPIO>;
bias-pull-up;
};
pinctrl_mikrobus1_an_default: mikrobus1-an-default {
pinmux = <PIN_PC15__GPIO>;
bias-disable;
};
pinctrl_mikrobus2_an_default: mikrobus2-an-default {
pinmux = <PIN_PC13__GPIO>;
bias-disable;
};
pinctrl_nand_default: nand-default {
pinmux = <PIN_PD9__D0>,
<PIN_PD10__D1>,
<PIN_PD11__D2>,
<PIN_PC21__D3>,
<PIN_PC22__D4>,
<PIN_PC23__D5>,
<PIN_PC24__D6>,
<PIN_PD2__D7>,
<PIN_PD3__NANDRDY>,
<PIN_PD4__NCS3_NANDCS>,
<PIN_PD5__NWE_NWR0_NANDWE>,
<PIN_PD6__NRD_NANDOE>,
<PIN_PD7__A21_NANDALE>,
<PIN_PD8__A22_NANDCLE>;
bias-disable;
slew-rate = <0>;
};
pinctrl_qspi1_default: qspi1-default {
pinmux = <PIN_PB22__QSPI1_IO3>,
<PIN_PB23__QSPI1_IO2>,
<PIN_PB24__QSPI1_IO1>,
<PIN_PB25__QSPI1_IO0>,
<PIN_PB26__QSPI1_CS>,
<PIN_PB27__QSPI1_SCK>;
bias-pull-up;
slew-rate = <0>;
};
pinctrl_sdmmc0_default: sdmmc0-default {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_RSTN>,
<PIN_PA3__SDMMC0_DAT0>,
<PIN_PA4__SDMMC0_DAT1>,
<PIN_PA5__SDMMC0_DAT2>,
<PIN_PA6__SDMMC0_DAT3>;
bias-pull-up;
slew-rate = <0>;
};
pinctrl_sdmmc1_default: sdmmc1-default {
pinmux = <PIN_PB29__SDMMC1_CMD>,
<PIN_PB30__SDMMC1_CK>,
<PIN_PB31__SDMMC1_DAT0>,
<PIN_PC0__SDMMC1_DAT1>,
<PIN_PC1__SDMMC1_DAT2>,
<PIN_PC2__SDMMC1_DAT3>,
<PIN_PC4__SDMMC1_CD>;
bias-pull-up;
slew-rate = <0>;
};
};
&rtt {
atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
};
/* M.2 slot for wireless card */
&sdmmc0 {
bus-width = <4>;
cd-gpios = <&pioA 31 GPIO_ACTIVE_LOW>;
disable-wp;
sdhci-caps-mask = <0x0 0x00200000>;
vmmc-supply = <&vdd_3v3>;
vqmmc-supply = <&vdd_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
};
/* micro SD socket */
&sdmmc1 {
bus-width = <4>;
disable-wp;
sdhci-caps-mask = <0x0 0x00200000>;
vmmc-supply = <&vdd_3v3>;
vqmmc-supply = <&vdd_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_default>;
status = "okay";
};
&slow_xtal {
clock-frequency = <32768>;
};
&shdwc {
debounce-delay-us = <976>;
status = "okay";
input@0 {
reg = <0>;
};
};
&tcb0 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
&trng {
status = "okay";
};
&vddout25 {
vin-supply = <&vdd_3v3>;
status = "okay";
};

2
arch/arm/boot/dts/microchip/at91sam9g25-gardena-smart-gateway.dts
View File

@ -121,6 +121,8 @@
};
&usart3 {
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
pinctrl-0 = <&pinctrl_usart3

2
arch/arm/boot/dts/microchip/at91sam9x5ek.dtsi
View File

@ -39,6 +39,8 @@
};
&dbgu {
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};

64
arch/arm/boot/dts/microchip/sam9x60.dtsi
View File

@ -179,7 +179,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(8))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(9))>;
@ -202,7 +202,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(8))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(9))>;
@ -220,7 +220,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(8))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(9))>;
@ -248,7 +248,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(10))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(11))>;
@ -271,7 +271,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(10))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(11))>;
@ -289,7 +289,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(10))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(11))>;
@ -377,7 +377,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(22))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(23))>;
@ -399,7 +399,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(22))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(23))>;
@ -426,7 +426,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(24))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(25))>;
@ -448,7 +448,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(24))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(25))>;
@ -583,7 +583,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(12))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(13))>;
@ -605,7 +605,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(12))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(13))>;
@ -632,7 +632,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(14))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(15))>;
@ -654,7 +654,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(14))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(15))>;
@ -681,7 +681,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(16))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(17))>;
@ -703,7 +703,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(16))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(17))>;
@ -730,7 +730,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(0))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(1))>;
@ -753,7 +753,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(0))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(1))>;
@ -771,7 +771,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(0))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(1))>;
@ -798,7 +798,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(2))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(3))>;
@ -821,7 +821,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(2))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(3))>;
@ -839,7 +839,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(2))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(3))>;
@ -866,7 +866,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(4))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(5))>;
@ -889,7 +889,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(4))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(5))>;
@ -907,7 +907,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(4))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(5))>;
@ -934,7 +934,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(6))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(7))>;
@ -957,7 +957,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(6))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(7))>;
@ -975,7 +975,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(6))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(7))>;
@ -1057,7 +1057,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(18))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(19))>;
@ -1079,7 +1079,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(18))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(19))>;
@ -1106,7 +1106,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(20))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(21))>;
@ -1128,7 +1128,7 @@
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(20))>,
<&dma0
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) |
AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(21))>;

56
arch/arm/boot/dts/microchip/sama7g5.dtsi
View File

@ -698,7 +698,7 @@
};
flx0: flexcom@e1818000 {
compatible = "atmel,sama5d2-flexcom";
compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe1818000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
#address-cells = <1>;
@ -714,7 +714,7 @@
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
clock-names = "usart";
dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>,
<&dma1 AT91_XDMAC_DT_PERID(5)>;
<&dma1 AT91_XDMAC_DT_PERID(5)>;
dma-names = "tx", "rx";
atmel,use-dma-rx;
atmel,use-dma-tx;
@ -723,7 +723,7 @@
};
flx1: flexcom@e181c000 {
compatible = "atmel,sama5d2-flexcom";
compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe181c000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
#address-cells = <1>;
@ -740,14 +740,14 @@
clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
atmel,fifo-size = <32>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>,
<&dma0 AT91_XDMAC_DT_PERID(7)>;
<&dma0 AT91_XDMAC_DT_PERID(7)>;
dma-names = "tx", "rx";
status = "disabled";
};
};
flx3: flexcom@e1824000 {
compatible = "atmel,sama5d2-flexcom";
compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe1824000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
#address-cells = <1>;
@ -763,7 +763,7 @@
clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
clock-names = "usart";
dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>,
<&dma1 AT91_XDMAC_DT_PERID(11)>;
<&dma1 AT91_XDMAC_DT_PERID(11)>;
dma-names = "tx", "rx";
atmel,use-dma-rx;
atmel,use-dma-tx;
@ -791,7 +791,7 @@
};
flx4: flexcom@e2018000 {
compatible = "atmel,sama5d2-flexcom";
compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe2018000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
#address-cells = <1>;
@ -807,7 +807,7 @@
clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
clock-names = "usart";
dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>,
<&dma1 AT91_XDMAC_DT_PERID(13)>;
<&dma1 AT91_XDMAC_DT_PERID(13)>;
dma-names = "tx", "rx";
atmel,use-dma-rx;
atmel,use-dma-tx;
@ -817,7 +817,7 @@
};
flx7: flexcom@e2024000 {
compatible = "atmel,sama5d2-flexcom";
compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe2024000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
#address-cells = <1>;
@ -833,7 +833,7 @@
clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
clock-names = "usart";
dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>,
<&dma1 AT91_XDMAC_DT_PERID(19)>;
<&dma1 AT91_XDMAC_DT_PERID(19)>;
dma-names = "tx", "rx";
atmel,use-dma-rx;
atmel,use-dma-tx;
@ -911,7 +911,7 @@
};
flx8: flexcom@e2818000 {
compatible = "atmel,sama5d2-flexcom";
compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe2818000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
#address-cells = <1>;
@ -928,14 +928,14 @@
clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
atmel,fifo-size = <32>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>,
<&dma0 AT91_XDMAC_DT_PERID(21)>;
<&dma0 AT91_XDMAC_DT_PERID(21)>;
dma-names = "tx", "rx";
status = "disabled";
};
};
flx9: flexcom@e281c000 {
compatible = "atmel,sama5d2-flexcom";
compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe281c000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
#address-cells = <1>;
@ -952,14 +952,38 @@
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
atmel,fifo-size = <32>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>,
<&dma0 AT91_XDMAC_DT_PERID(23)>;
<&dma0 AT91_XDMAC_DT_PERID(23)>;
dma-names = "tx", "rx";
status = "disabled";
};
};
flx10: flexcom@e2820000 {
compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe2820000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 48>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xe2820000 0x800>;
status = "disabled";
i2c10: i2c@600 {
compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 48>;
atmel,fifo-size = <32>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>,
<&dma0 AT91_XDMAC_DT_PERID(25)>;
dma-names = "tx", "rx";
status = "disabled";
};
};
flx11: flexcom@e2824000 {
compatible = "atmel,sama5d2-flexcom";
compatible = "microchip,sama7g5-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe2824000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
#address-cells = <1>;
@ -977,7 +1001,7 @@
#size-cells = <0>;
atmel,fifo-size = <32>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>,
<&dma0 AT91_XDMAC_DT_PERID(27)>;
<&dma0 AT91_XDMAC_DT_PERID(27)>;
dma-names = "tx", "rx";
status = "disabled";
};

2
arch/arm/boot/dts/nvidia/Makefile
View File

@ -39,5 +39,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
tegra30-cardhu-a02.dtb \
tegra30-cardhu-a04.dtb \
tegra30-colibri-eval-v3.dtb \
tegra30-lg-p880.dtb \
tegra30-lg-p895.dtb \
tegra30-ouya.dtb \
tegra30-pegatron-chagall.dtb

1
arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi
View File

@ -338,6 +338,7 @@
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
reg = <0>;
wakeup-source;
google,cros-ec-spi-msg-delay = <2000>;

1
arch/arm/boot/dts/nvidia/tegra124-venice2.dts
View File

@ -857,6 +857,7 @@
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
reg = <0>;
wakeup-source;
google,cros-ec-spi-msg-delay = <2000>;

3
arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi
View File

@ -915,6 +915,9 @@
reg = <0x1c>;
realtek,dmic1-data-pin = <1>;
clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
clock-names = "mclk";
};
nct72: temperature-sensor@4c {

489
arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts Normal file
View File

@ -0,0 +1,489 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-lg-x3.dtsi"
/ {
model = "LG Optimus 4X HD P880";
compatible = "lg,p880", "nvidia,tegra30";
aliases {
mmc1 = &sdmmc3; /* uSD slot */
mmc2 = &sdmmc1; /* WiFi */
};
pinmux@70000868 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
/* WLAN SDIO pinmux */
host-wlan-wake {
nvidia,pins = "pu4";
nvidia,function = "pwm1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* GNSS UART-B pinmux */
uartb-rxd {
nvidia,pins = "uart2_rxd_pc3";
nvidia,function = "uartb";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
uartb-txd {
nvidia,pins = "uart2_txd_pc2";
nvidia,function = "uartb";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
gps-reset {
nvidia,pins = "kb_row7_pr7";
nvidia,function = "kbc";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
/* MicroSD pinmux */
sdmmc3-clk {
nvidia,pins = "sdmmc3_clk_pa6";
nvidia,function = "sdmmc3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
sdmmc3-data {
nvidia,pins = "sdmmc3_cmd_pa7",
"sdmmc3_dat0_pb7",
"sdmmc3_dat1_pb6",
"sdmmc3_dat2_pb5",
"sdmmc3_dat3_pb4";
nvidia,function = "sdmmc3";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
microsd-detect {
nvidia,pins = "clk2_out_pw5";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* GPIO keys pinmux */
volume-up {
nvidia,pins = "ulpi_data6_po7";
nvidia,function = "spi2";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* Sensors pinmux */
current-alert-irq {
nvidia,pins = "uart2_rts_n_pj6";
nvidia,function = "uartb";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* AUDIO pinmux */
sub-mic-ldo {
nvidia,pins = "gmi_cs7_n_pi6";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
};
};
i2c@7000c400 {
touchscreen@20 {
rmi4-f11@11 {
syna,clip-x-high = <1110>;
syna,clip-y-high = <1973>;
touchscreen-inverted-y;
};
};
};
memory-controller@7000f000 {
emc-timings-0 {
/* SAMSUNG 1GB K4P8G304EB FGC1 533MHz */
nvidia,ram-code = <0>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emem-configuration = < 0x00050001 0xc0000010
0x00000001 0x00000001 0x00000002 0x00000000
0x00000003 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000002 0x00000002
0x02020001 0x00060402 0x77230303 0x001f0000 >;
};
timing-25500000 {
clock-frequency = <25500000>;
nvidia,emem-configuration = < 0x00020001 0xc0000010
0x00000001 0x00000001 0x00000002 0x00000000
0x00000003 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000002 0x00000002
0x02020001 0x00060402 0x73e30303 0x001f0000 >;
};
timing-51000000 {
clock-frequency = <51000000>;
nvidia,emem-configuration = < 0x00010001 0xc0000010
0x00000001 0x00000001 0x00000002 0x00000000
0x00000003 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000002 0x00000002
0x02020001 0x00060402 0x72c30303 0x001f0000 >;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emem-configuration = < 0x00000001 0xc0000018
0x00000001 0x00000001 0x00000003 0x00000001
0x00000003 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000002 0x00000002
0x02020001 0x00060403 0x72430504 0x001f0000 >;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emem-configuration = < 0x00000003 0xc0000025
0x00000001 0x00000001 0x00000006 0x00000003
0x00000005 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000003 0x00000002
0x02030001 0x00070506 0x71e40a07 0x001f0000 >;
};
timing-266500000 {
clock-frequency = <266500000>;
nvidia,emem-configuration = < 0x00000004 0xC0000030
0x00000001 0x00000002 0x00000008 0x00000004
0x00000006 0x00000001 0x00000002 0x00000005
0x00000001 0x00000000 0x00000003 0x00000003
0x03030001 0x00090608 0x70040c09 0x001f0000 >;
};
timing-533000000 {
clock-frequency = <533000000>;
nvidia,emem-configuration = < 0x00000008 0xC0000060
0x00000003 0x00000004 0x00000010 0x0000000a
0x0000000d 0x00000002 0x00000002 0x00000008
0x00000002 0x00000000 0x00000004 0x00000005
0x05040002 0x00110b10 0x70281811 0x001f0000 >;
};
};
};
memory-controller@7000f400 {
emc-timings-0 {
/* SAMSUNG 1GB K4P8G304EB FGC1 533MHz */
nvidia,ram-code = <0>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010022>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000009>;
nvidia,emc-cfg-dyn-self-ref;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000000
0x00000001 0x00000002 0x00000002 0x00000004
0x00000004 0x00000001 0x00000005 0x00000002
0x00000002 0x00000001 0x00000001 0x00000000
0x00000001 0x00000003 0x00000001 0x0000000b
0x00000009 0x0000002f 0x00000000 0x0000000b
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000007 0x00000002 0x00000002
0x00000003 0x00000008 0x00000004 0x00000001
0x00000002 0x00000036 0x00000004 0x00000004
0x00000000 0x00000000 0x00004282 0x007800a4
0x00008000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00100220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x00000009 0x00090009 0xa0f10000 0x00000000
0x00000000 0x80000164 0xe0000000 0xff00ff00 >;
};
timing-25500000 {
clock-frequency = <25500000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010022>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000009>;
nvidia,emc-cfg-dyn-self-ref;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000001
0x00000003 0x00000002 0x00000002 0x00000004
0x00000004 0x00000001 0x00000005 0x00000002
0x00000002 0x00000001 0x00000001 0x00000000
0x00000001 0x00000003 0x00000001 0x0000000b
0x00000009 0x00000060 0x00000000 0x00000018
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000007 0x00000004 0x00000004
0x00000003 0x00000008 0x00000004 0x00000001
0x00000002 0x0000006b 0x00000004 0x00000004
0x00000000 0x00000000 0x00004282 0x007800a4
0x00008000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00100220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x0000000a 0x00090009 0xa0f10000 0x00000000
0x00000000 0x800001c5 0xe0000000 0xff00ff00 >;
};
timing-51000000 {
clock-frequency = <51000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010022>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000009>;
nvidia,emc-cfg-dyn-self-ref;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000003
0x00000006 0x00000002 0x00000002 0x00000004
0x00000004 0x00000001 0x00000005 0x00000002
0x00000002 0x00000001 0x00000001 0x00000000
0x00000001 0x00000003 0x00000001 0x0000000b
0x00000009 0x000000c0 0x00000000 0x00000030
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000007 0x00000008 0x00000008
0x00000003 0x00000008 0x00000004 0x00000001
0x00000002 0x000000d5 0x00000004 0x00000004
0x00000000 0x00000000 0x00004282 0x007800a4
0x00008000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00100220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x00000013 0x00090009 0xa0f10000 0x00000000
0x00000000 0x80000287 0xe0000000 0xff00ff00 >;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010022>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x0000000a>;
nvidia,emc-cfg-dyn-self-ref;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000006
0x0000000d 0x00000004 0x00000002 0x00000004
0x00000004 0x00000001 0x00000005 0x00000002
0x00000002 0x00000001 0x00000001 0x00000000
0x00000001 0x00000003 0x00000001 0x0000000b
0x00000009 0x00000181 0x00000000 0x00000060
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000007 0x0000000f 0x0000000f
0x00000003 0x00000008 0x00000004 0x00000001
0x00000002 0x000001a9 0x00000004 0x00000004
0x00000000 0x00000000 0x00004282 0x007800a4
0x00008000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00100220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x00000025 0x00090009 0xa0f10000 0x00000000
0x00000000 0x8000040b 0xe0000000 0xff00ff00 >;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010042>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000013>;
nvidia,emc-cfg-dyn-self-ref;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x0000000c
0x0000001a 0x00000008 0x00000003 0x00000005
0x00000004 0x00000001 0x00000006 0x00000003
0x00000003 0x00000002 0x00000002 0x00000000
0x00000001 0x00000003 0x00000001 0x0000000c
0x0000000a 0x00000303 0x00000000 0x000000c0
0x00000001 0x00000001 0x00000003 0x00000000
0x00000001 0x00000007 0x0000001d 0x0000001d
0x00000004 0x0000000b 0x00000005 0x00000001
0x00000002 0x00000351 0x00000004 0x00000006
0x00000000 0x00000000 0x00004282 0x004400a4
0x00008000 0x00070000 0x00070000 0x00070000
0x00070000 0x00070000 0x00070000 0x00070000
0x00070000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00080000 0x00080000 0x00080000
0x00080000 0x000e0220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x0000004a 0x00090009 0xa0f10000 0x00000000
0x00000000 0x80000713 0xe0000000 0xff00ff00 >;
};
timing-266500000 {
clock-frequency = <266500000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010042>;
nvidia,emc-mode-2 = <0x00020002>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000018>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x0000000f
0x00000022 0x0000000b 0x00000004 0x00000005
0x00000005 0x00000001 0x00000007 0x00000004
0x00000004 0x00000002 0x00000002 0x00000000
0x00000002 0x00000005 0x00000002 0x0000000c
0x0000000b 0x000003ef 0x00000000 0x000000fb
0x00000001 0x00000001 0x00000004 0x00000000
0x00000001 0x00000009 0x00000026 0x00000026
0x00000004 0x0000000e 0x00000006 0x00000001
0x00000002 0x00000455 0x00000000 0x00000004
0x00000000 0x00000000 0x00006282 0x003200a4
0x00008000 0x00050000 0x00050000 0x00050000
0x00050000 0x00050000 0x00050000 0x00050000
0x00050000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00060000 0x00060000 0x00060000
0x00060000 0x000b0220 0x0800003d 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x00000060 0x000a000a 0xa0f10000 0x00000000
0x00000000 0x800008ee 0xe0000000 0xff00ff00 >;
};
timing-533000000 {
clock-frequency = <533000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x000100c2>;
nvidia,emc-mode-2 = <0x00020006>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000030>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x0000001f
0x00000045 0x00000016 0x00000009 0x00000008
0x00000009 0x00000003 0x0000000d 0x00000009
0x00000009 0x00000005 0x00000003 0x00000000
0x00000004 0x00000009 0x00000006 0x0000000d
0x00000010 0x000007df 0x00000000 0x000001f7
0x00000003 0x00000003 0x00000009 0x00000000
0x00000001 0x0000000f 0x0000004b 0x0000004b
0x00000008 0x0000001b 0x0000000c 0x00000001
0x00000002 0x000008aa 0x00000000 0x00000006
0x00000000 0x00000000 0x00006282 0xf0120091
0x00008000 0x0000000a 0x0000000a 0x0000000a
0x0000000a 0x0000000a 0x0000000a 0x0000000a
0x0000000a 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x0000000a 0x0000000a 0x0000000a
0x0000000a 0x00090220 0x0800003d 0x00000000
0x77ffc004 0x01f1f408 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x000000c0 0x000e000e 0xa0f10000 0x00000000
0x00000000 0x800010d9 0xe0000000 0xff00ff88 >;
};
};
};
sdmmc3: mmc@78000400 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(W, 5) GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&vdd_usd>;
vqmmc-supply = <&vdd_1v8_vio>;
};
battery: battery-cell {
compatible = "simple-battery";
device-chemistry = "lithium-ion";
charge-full-design-microamp-hours = <2150000>;
energy-full-design-microwatt-hours = <8200000>;
operating-range-celsius = <0 45>;
};
gpio-keys {
key-volume-up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(O, 7) GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <10>;
wakeup-event-action = <EV_ACT_ASSERTED>;
wakeup-source;
};
};
sound {
compatible = "lg,tegra-audio-max98089-p880",
"nvidia,tegra-audio-max98089";
nvidia,model = "LG Optimus 4X HD MAX98089";
nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
};
};

496
arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts Normal file
View File

@ -0,0 +1,496 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-lg-x3.dtsi"
/ {
model = "LG Optimus Vu P895";
compatible = "lg,p895", "nvidia,tegra30";
pinmux@70000868 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
/* GNSS UART-B pinmux */
uartb-cts-rxd {
nvidia,pins = "uart2_cts_n_pj5",
"uart2_rxd_pc3";
nvidia,function = "uartb";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
uartb-rts-txd {
nvidia,pins = "uart2_rts_n_pj6",
"uart2_txd_pc2";
nvidia,function = "uartb";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
gps-reset {
nvidia,pins = "spdif_out_pk5";
nvidia,function = "spdif";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
/* GPIO keys pinmux */
memo-key {
nvidia,pins = "sdmmc3_dat1_pb6";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
volume-up {
nvidia,pins = "gmi_cs7_n_pi6";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* Sensors pinmux */
current-alert-irq {
nvidia,pins = "spi1_cs0_n_px6";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* Panel pinmux */
panel-vdd {
nvidia,pins = "pbb0";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
/* AUDIO pinmux */
sub-mic-ldo {
nvidia,pins = "gmi_dqs_pi2";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
/* Modem pinmux */
usim-detect {
nvidia,pins = "clk2_out_pw5";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* GPIO power/drive control */
drive-sdmmc4 {
nvidia,pins = "drive_gma",
"drive_gmb",
"drive_gmc",
"drive_gmd";
nvidia,pull-down-strength = <9>;
nvidia,pull-up-strength = <9>;
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
};
};
};
i2c@7000c400 {
touchscreen@20 {
rmi4-f11@11 {
syna,clip-x-high = <1535>;
syna,clip-y-high = <2047>;
};
};
};
memory-controller@7000f000 {
emc-timings-2 {
/* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */
nvidia,ram-code = <2>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emem-configuration = < 0x00020001 0xc0000010
0x00000001 0x00000001 0x00000002 0x00000000
0x00000003 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000002 0x00000002
0x02020001 0x00060402 0x77230303 0x001f0000 >;
};
timing-25500000 {
clock-frequency = <25500000>;
nvidia,emem-configuration = < 0x00030003 0xc0000010
0x00000001 0x00000001 0x00000002 0x00000000
0x00000003 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000002 0x00000002
0x02020001 0x00060402 0x73e30303 0x001f0000 >;
};
timing-51000000 {
clock-frequency = <51000000>;
nvidia,emem-configuration = < 0x00010003 0xc0000010
0x00000001 0x00000001 0x00000002 0x00000000
0x00000003 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000002 0x00000002
0x02020001 0x00060402 0x72c30303 0x001f0000 >;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emem-configuration = < 0x00000003 0xc0000018
0x00000001 0x00000001 0x00000003 0x00000001
0x00000003 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000002 0x00000002
0x02020001 0x00060403 0x72430504 0x001f0000 >;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emem-configuration = < 0x00000006 0xc0000025
0x00000001 0x00000001 0x00000006 0x00000003
0x00000005 0x00000001 0x00000002 0x00000004
0x00000001 0x00000000 0x00000003 0x00000002
0x02030001 0x00070506 0x71e40a07 0x001f0000 >;
};
timing-266500000 {
clock-frequency = <266500000>;
nvidia,emem-configuration = < 0x00000008 0xc0000030
0x00000001 0x00000002 0x00000008 0x00000004
0x00000006 0x00000001 0x00000002 0x00000005
0x00000001 0x00000000 0x00000003 0x00000003
0x03030001 0x00090608 0x70040c09 0x001f0000 >;
};
timing-533000000 {
clock-frequency = <533000000>;
nvidia,emem-configuration = < 0x0000000f 0xc0000060
0x00000003 0x00000004 0x00000010 0x0000000a
0x0000000d 0x00000002 0x00000002 0x00000008
0x00000002 0x00000000 0x00000004 0x00000005
0x05040002 0x00110b10 0x70281811 0x001f0000 >;
};
};
};
memory-controller@7000f400 {
emc-timings-2 {
/* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */
nvidia,ram-code = <2>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010022>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000009>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000000
0x00000001 0x00000002 0x00000002 0x00000004
0x00000004 0x00000001 0x00000005 0x00000002
0x00000002 0x00000001 0x00000001 0x00000000
0x00000001 0x00000003 0x00000001 0x0000000b
0x00000009 0x0000002f 0x00000000 0x0000000b
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000007 0x00000002 0x00000002
0x00000003 0x00000008 0x00000004 0x00000004
0x00000002 0x00000036 0x00000004 0x00000004
0x00000000 0x00000000 0x00004282 0x007800a4
0x00008000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00100220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x00000009 0x00090009 0xa0f10000 0x00000000
0x00000000 0x80000164 0xe0000000 0xff00ff00 >;
};
timing-25500000 {
clock-frequency = <25500000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010022>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000009>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000001
0x00000003 0x00000002 0x00000002 0x00000004
0x00000004 0x00000001 0x00000005 0x00000002
0x00000002 0x00000001 0x00000001 0x00000000
0x00000001 0x00000003 0x00000001 0x0000000b
0x00000009 0x00000060 0x00000000 0x00000018
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000007 0x00000004 0x00000004
0x00000003 0x00000008 0x00000004 0x00000004
0x00000002 0x0000006b 0x00000004 0x00000004
0x00000000 0x00000000 0x00004282 0x007800a4
0x00008000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00100220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x0000000a 0x00090009 0xa0f10000 0x00000000
0x00000000 0x800001c5 0xd0000000 0xff00ff00 >;
};
timing-51000000 {
clock-frequency = <51000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010022>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000009>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000003
0x00000006 0x00000002 0x00000002 0x00000004
0x00000004 0x00000001 0x00000005 0x00000002
0x00000002 0x00000001 0x00000001 0x00000000
0x00000001 0x00000003 0x00000001 0x0000000b
0x00000009 0x000000c0 0x00000000 0x00000030
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000007 0x00000008 0x00000008
0x00000003 0x00000008 0x00000004 0x00000004
0x00000002 0x000000d5 0x00000004 0x00000004
0x00000000 0x00000000 0x00004282 0x007800a4
0x00008000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00100220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x00000013 0x00090009 0xa0f10000 0x00000000
0x00000000 0x80000287 0xd0000000 0xff00ff00 >;
};
timing-102000000 {
clock-frequency = <102000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010022>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x0000000a>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x00000006
0x0000000d 0x00000004 0x00000002 0x00000004
0x00000004 0x00000001 0x00000005 0x00000002
0x00000002 0x00000001 0x00000001 0x00000000
0x00000001 0x00000003 0x00000001 0x0000000b
0x00000009 0x00000181 0x00000000 0x00000060
0x00000001 0x00000001 0x00000002 0x00000000
0x00000001 0x00000007 0x0000000f 0x0000000f
0x00000003 0x00000008 0x00000004 0x00000004
0x00000002 0x000001a9 0x00000004 0x00000006
0x00000000 0x00000000 0x00004282 0x007800a4
0x00008000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x000fc000 0x000fc000 0x000fc000
0x000fc000 0x00100220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x00000025 0x00090009 0xa0f10000 0x00000000
0x00000000 0x8000040b 0xd0000000 0xff00ff00 >;
};
timing-204000000 {
clock-frequency = <204000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010042>;
nvidia,emc-mode-2 = <0x00020001>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000013>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x0000000c
0x0000001a 0x00000008 0x00000003 0x00000005
0x00000004 0x00000001 0x00000006 0x00000003
0x00000003 0x00000002 0x00000002 0x00000000
0x00000001 0x00000004 0x00000001 0x0000000c
0x0000000a 0x00000303 0x00000000 0x000000c0
0x00000001 0x00000001 0x00000003 0x00000000
0x00000001 0x00000007 0x0000001d 0x0000001d
0x00000004 0x0000000b 0x00000005 0x00000004
0x00000002 0x00000351 0x00000005 0x00000004
0x00000000 0x00000000 0x00004282 0x004400a4
0x00008000 0x00080000 0x00080000 0x00080000
0x00080000 0x00072000 0x00072000 0x00072000
0x00072000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00080000 0x00080000 0x00080000
0x00080000 0x000e0220 0x0800201c 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x0000004a 0x00090009 0xa0f10000 0x00000000
0x00000000 0x80000713 0xe0000000 0xff00ff00 >;
};
timing-266500000 {
clock-frequency = <266500000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x00010042>;
nvidia,emc-mode-2 = <0x00020002>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000018>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x0000000f
0x00000022 0x0000000b 0x00000004 0x00000005
0x00000005 0x00000001 0x00000007 0x00000004
0x00000004 0x00000002 0x00000002 0x00000000
0x00000002 0x00000005 0x00000002 0x0000000c
0x0000000b 0x000003ef 0x00000000 0x000000fb
0x00000001 0x00000001 0x00000004 0x00000000
0x00000001 0x00000009 0x00000026 0x00000026
0x00000004 0x0000000e 0x00000006 0x00000004
0x00000002 0x00000455 0x00000000 0x00000004
0x00000000 0x00000000 0x00006282 0x003200a4
0x00008000 0x00070000 0x00070000 0x00070000
0x00070000 0x00072000 0x00072000 0x00072000
0x00072000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00080002 0x00080002 0x00080002
0x00080002 0x000e0220 0x0800003d 0x00000000
0x77ffc004 0x01f1f008 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x00000060 0x000a000a 0xa0f10000 0x00000000
0x00000000 0x800008ee 0xe0000000 0xff00ff00 >;
};
timing-533000000 {
clock-frequency = <533000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x000100c2>;
nvidia,emc-mode-2 = <0x00020006>;
nvidia,emc-mode-reset = <0x00000000>;
nvidia,emc-zcal-cnt-long = <0x00000030>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = < 0x0000001f
0x00000045 0x00000016 0x00000009 0x00000008
0x00000009 0x00000003 0x0000000d 0x00000009
0x00000009 0x00000005 0x00000003 0x00000000
0x00000004 0x0000000a 0x00000006 0x0000000d
0x00000010 0x000007df 0x00000000 0x000001f7
0x00000003 0x00000003 0x00000009 0x00000000
0x00000001 0x0000000f 0x0000004b 0x0000004b
0x00000008 0x0000001b 0x0000000c 0x00000004
0x00000002 0x000008aa 0x00000000 0x00000004
0x00000000 0x00000000 0x00006282 0xf0120091
0x00008000 0x0000000c 0x0000000c 0x0000000c
0x0000000c 0x0000000a 0x0000000a 0x0000000a
0x0000000a 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000
0x00000000 0x0000000c 0x0000000c 0x0000000c
0x0000000c 0x000c0220 0x0800003d 0x00000000
0x77ffc004 0x01f1f408 0x00000000 0x00000007
0x08000068 0x08000000 0x00000802 0x00064000
0x000000c0 0x000e000e 0xa0f10000 0x00000000
0x00000000 0x800010d9 0xe0000000 0xff00ff88 >;
};
};
};
battery: battery-cell {
compatible = "simple-battery";
device-chemistry = "lithium-ion";
charge-full-design-microamp-hours = <2080000>;
energy-full-design-microwatt-hours = <7700000>;
operating-range-celsius = <0 45>;
};
gpio-keys {
key-memo {
label = "Memo";
gpios = <&gpio TEGRA_GPIO(B, 6) GPIO_ACTIVE_LOW>;
linux,code = <KEY_MEMO>;
debounce-interval = <10>;
wakeup-event-action = <EV_ACT_ASSERTED>;
wakeup-source;
};
key-volume-up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <10>;
wakeup-event-action = <EV_ACT_ASSERTED>;
wakeup-source;
};
};
gpio-leds {
led-power {
label = "power::white";
gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
linux,default-trigger = "battery-charging";
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_CHARGING;
};
};
regulator-lcd3v {
gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound {
compatible = "lg,tegra-audio-max98089-p895",
"nvidia,tegra-audio-max98089";
nvidia,model = "LG Optimus Vu MAX98089";
nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(I, 2) GPIO_ACTIVE_HIGH>;
};
};

1812
arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

6
arch/arm/boot/dts/nxp/imx/Makefile
View File

@ -45,7 +45,9 @@ dtb-$(CONFIG_SOC_IMX53) += \
imx53-mba53.dtb \
imx53-ppd.dtb \
imx53-qsb.dtb \
imx53-qsb-hdmi.dtb \
imx53-qsrb.dtb \
imx53-qsrb-hdmi.dtb \
imx53-sk-imx53.dtb \
imx53-sk-imx53-atm0700d4-lvds.dtb \
imx53-sk-imx53-atm0700d4-rgb.dtb \
@ -54,6 +56,8 @@ dtb-$(CONFIG_SOC_IMX53) += \
imx53-tx53-x13x.dtb \
imx53-usbarmory.dtb \
imx53-voipac-bsb.dtb
imx53-qsb-hdmi-dtbs := imx53-qsb.dtb imx53-qsb-hdmi.dtbo
imx53-qsrb-hdmi-dtbs := imx53-qsrb.dtb imx53-qsb-hdmi.dtbo
dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-alti6p.dtb \
imx6dl-apf6dev.dtb \
@ -118,6 +122,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-sabrelite.dtb \
imx6dl-sabresd.dtb \
imx6dl-savageboard.dtb \
imx6dl-sielaff.dtb \
imx6dl-skov-revc-lt2.dtb \
imx6dl-skov-revc-lt6.dtb \
imx6dl-solidsense.dtb \
@ -147,6 +152,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-yapp4-phoenix.dtb \
imx6dl-yapp4-ursa.dtb \
imx6q-apalis-eval.dtb \
imx6q-apalis-eval-v1.2.dtb \
imx6q-apalis-ixora.dtb \
imx6q-apalis-ixora-v1.1.dtb \
imx6q-apalis-ixora-v1.2.dtb \

2
arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts
View File

@ -54,7 +54,7 @@
#size-cells = <1>;
};
eth: eth@4,c00000 {
eth: ethernet@4,c00000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eth>;
compatible = "davicom,dm9000";

2
arch/arm/boot/dts/nxp/imx/imx1.dtsi
View File

@ -251,7 +251,7 @@
};
};
weim: weim@220000 {
weim: memory-controller@220000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx1-weim";

2
arch/arm/boot/dts/nxp/imx/imx27.dtsi
View File

@ -568,7 +568,7 @@
status = "disabled";
};
weim: weim@d8002000 {
weim: memory-controller@d8002000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx27-weim";

2
arch/arm/boot/dts/nxp/imx/imx31.dtsi
View File

@ -352,7 +352,7 @@
status = "disabled";
};
weim: weim@b8002000 {
weim: memory-controller@b8002000 {
compatible = "fsl,imx31-weim", "fsl,imx27-weim";
reg = <0xb8002000 0x1000>;
clocks = <&clks 56>;

2
arch/arm/boot/dts/nxp/imx/imx35.dtsi
View File

@ -374,7 +374,7 @@
status = "disabled";
};
weim: weim@b8002000 {
weim: memory-controller@b8002000 {
#address-cells = <2>;
#size-cells = <1>;
clocks = <&clks 0>;

2
arch/arm/boot/dts/nxp/imx/imx51.dtsi
View File

@ -578,7 +578,7 @@
reg = <0x83fd8000 0x1000>;
};
weim: weim@83fda000 {
weim: memory-controller@83fda000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx51-weim";

87
arch/arm/boot/dts/nxp/imx/imx53-qsb-hdmi.dtso Normal file
View File

@ -0,0 +1,87 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* DT overlay for MCIMXHDMICARD as used with the iMX53 QSB or QSRB boards
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
/dts-v1/;
/plugin/;
&{/} {
/delete-node/ panel;
hdmi: connector-hdmi {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&sii9022_out>;
};
};
};
reg_1p2v: regulator-1p2v {
compatible = "regulator-fixed";
regulator-name = "1P2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
vin-supply = <&reg_3p2v>;
};
};
&display0 {
status = "okay";
};
&display0 {
port@1 {
display0_out: endpoint {
remote-endpoint = <&sii9022_in>;
};
};
};
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
sii9022: bridge-hdmi@39 {
compatible = "sil,sii9022";
reg = <0x39>;
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
interrupts-extended = <&gpio3 31 IRQ_TYPE_LEVEL_LOW>;
iovcc-supply = <&reg_3p2v>;
#sound-dai-cells = <0>;
sil,i2s-data-lanes = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sii9022_in: endpoint {
remote-endpoint = <&display0_out>;
};
};
port@1 {
reg = <1>;
sii9022_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
&tve {
status = "disabled";
};

533
arch/arm/boot/dts/nxp/imx/imx6dl-sielaff.dts Normal file
View File

@ -0,0 +1,533 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2022 Kontron Electronics GmbH
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Sielaff i.MX6 Solo";
compatible = "sielaff,imx6dl-board", "fsl,imx6dl";
chosen {
stdout-path = &uart2;
};
backlight: pwm-backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
pwms = <&pwm3 0 50000 0>;
brightness-levels = <0 0 64 88 112 136 184 232 255>;
default-brightness-level = <4>;
enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_backlight>;
};
cec {
compatible = "cec-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_cec>;
cec-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
hdmi-phandle = <&hdmi>;
};
enet_ref: clock-enet-ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "enet-ref";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
key-0 {
gpios = <&gpio2 16 0>;
debounce-interval = <10>;
linux,code = <1>;
};
key-1 {
gpios = <&gpio3 27 0>;
debounce-interval = <10>;
linux,code = <2>;
};
key-2 {
gpios = <&gpio5 4 0>;
debounce-interval = <10>;
linux,code = <3>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-debug {
label = "debug-led";
gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
};
memory@80000000 {
reg = <0x80000000 0x20000000>;
device_type = "memory";
};
osc_eth_phy: clock-osc-eth-phy {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "osc-eth-phy";
};
panel {
compatible = "lg,lb070wv8";
backlight = <&backlight>;
power-supply = <&reg_3v3>;
port {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out>;
};
};
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_backlight: regulator-backlight {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_backlight>;
enable-active-high;
gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
regulator-name = "backlight";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
enable-active-high;
gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
};
};
&fec {
/*
* Set PTP clock to external instead of internal reference, as the
* REF_CLK from the PHY is fed back into the i.MX6 and the GPR
* register needs to be set accordingly (see mach-imx6q.c).
*/
clocks = <&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>,
<&enet_ref>,
<&clks IMX6QDL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "ptp", "enet_out";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-connection-type = "rmii";
phy-handle = <&ethphy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@1 {
reg = <1>;
clocks = <&osc_eth_phy>;
clock-names = "rmii-ref";
micrel,led-mode = <1>;
reset-assert-us = <500>;
reset-deassert-us = <100>;
reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
};
};
};
&gpio1 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "key-out", "key-in",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio2 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"lan9500a-rst", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c4>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <100000>;
status = "okay";
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clock-frequency = <100000>;
status = "okay";
touchscreen@55 {
compatible = "sitronix,st1633";
reg = <0x55>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&gpio5>;
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
status = "disabled";
};
touchscreen@5d {
compatible = "goodix,gt928";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio5>;
irq-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clock-frequency = <100000>;
status = "okay";
};
&ldb {
status = "okay";
lvds: lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
status = "okay";
port@4 {
reg = <4>;
lvds_out: endpoint {
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
disable-over-current;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
usb1@1 {
compatible = "usb4b4,6570";
reg = <1>;
clocks = <&clks IMX6QDL_CLK_CKO>;
assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
<&clks IMX6QDL_CLK_CKO2_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>,
<&clks IMX6QDL_CLK_OSC>;
assigned-clock-rates = <12000000 0>;
};
};
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
dr_mode = "host";
over-current-active-low;
vbus-supply = <&reg_usb_otg_vbus>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
no-1-8-v;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x1b0b0 /* PMIC_IRQ */
MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
>;
};
pinctrl_backlight: backlightgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b1
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b080
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b080
MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b080
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_hdmi_cec: hdmicecgrp {
fsl,pins = <
MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_reg_backlight: regbacklightgrp {
fsl,pins = <
MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b1
>;
};
pinctrl_reg_usbotg_vbus: regusbotgvbusgrp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1
>;
};
pinctrl_touch: touchgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b1
MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b1
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x100b1
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
>;
};
};

25
arch/arm/boot/dts/nxp/imx/imx6dl-yapp4-common.dtsi
View File

@ -117,17 +117,9 @@
#address-cells = <1>;
#size-cells = <0>;
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
switch@10 {
compatible = "qca,qca8334";
reg = <10>;
reg = <0x10>;
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
switch_ports: ports {
@ -149,15 +141,30 @@
eth2: port@2 {
reg = <2>;
label = "eth2";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
eth1: port@3 {
reg = <3>;
label = "eth1";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port2: ethernet-phy@1 {
reg = <1>;
};
phy_port3: ethernet-phy@2 {
reg = <2>;
};
};
};
};
};

200
arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval-v1.2.dts Normal file
View File

@ -0,0 +1,200 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2024 Toradex
*/
/dts-v1/;
#include "imx6q-apalis-eval.dtsi"
/ {
model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board v1.2";
compatible = "toradex,apalis_imx6q-eval-v1.2", "toradex,apalis_imx6q",
"fsl,imx6q";
reg_3v3_mmc: regulator-3v3-mmc {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_3v3_mmc>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "3.3V_MMC";
startup-delay-us = <10000>;
};
reg_3v3_sd: regulator-3v3-sd {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_3v3_sd>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "3.3V_SD";
startup-delay-us = <10000>;
};
reg_can1: regulator-can1 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_can1_power>;
regulator-name = "5V_SW_CAN1";
startup-delay-us = <10000>;
};
reg_can2: regulator-can2 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_can2_power>;
regulator-name = "5V_SW_CAN2";
startup-delay-us = <10000>;
};
sound-carrier {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,name = "apalis-nau8822";
simple-audio-card,routing =
"Headphones", "LHP",
"Headphones", "RHP",
"Speaker", "LSPK",
"Speaker", "RSPK",
"Line Out", "AUXOUT1",
"Line Out", "AUXOUT2",
"LAUX", "Line In",
"RAUX", "Line In",
"LMICP", "Mic In",
"RMICP", "Mic In";
simple-audio-card,widgets =
"Headphones", "Headphones",
"Line Out", "Line Out",
"Speaker", "Speaker",
"Microphone", "Mic In",
"Line", "Line In";
codec_dai: simple-audio-card,codec {
sound-dai = <&nau8822_1a>;
system-clock-frequency = <12288000>;
};
simple-audio-card,cpu {
sound-dai = <&ssi2>;
};
};
};
&can1 {
xceiver-supply = <&reg_can1>;
status = "okay";
};
&can2 {
xceiver-supply = <&reg_can2>;
status = "okay";
};
/* I2C1_SDA/SCL on MXM3 209/211 */
&i2c1 {
/* Audio Codec */
nau8822_1a: audio-codec@1a {
compatible = "nuvoton,nau8822";
reg = <0x1a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nau8822>;
#sound-dai-cells = <0>;
};
/* Current measurement into module VCC */
hwmon@40 {
compatible = "ti,ina219";
reg = <0x40>;
shunt-resistor = <5000>;
};
/* Temperature Sensor */
temperature-sensor@4f {
compatible = "ti,tmp75c";
reg = <0x4f>;
};
/* EEPROM */
eeprom@57 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x57>;
pagesize = <16>;
size = <256>;
};
};
&pcie {
status = "okay";
};
&ssi2 {
status = "okay";
};
/* MMC1 */
&usdhc1 {
bus-width = <4>;
pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>;
vmmc-supply = <&reg_3v3_mmc>;
status = "okay";
};
/* SD1 */
&usdhc2 {
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
vmmc-supply = <&reg_3v3_sd>;
status = "okay";
};
&iomuxc {
pinctrl_enable_3v3_mmc: enable3v3mmcgrp {
fsl,pins = <
/* MMC1_PWR_CTRL */
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
>;
};
pinctrl_enable_3v3_sd: enable3v3sdgrp {
fsl,pins = <
/* SD1_PWR_CTRL */
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
>;
};
pinctrl_enable_can1_power: enablecan1powergrp {
fsl,pins = <
/* CAN1_PWR_EN */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
>;
};
pinctrl_enable_can2_power: enablecan2powergrp {
fsl,pins = <
/* CAN2_PWR_EN */
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
>;
};
pinctrl_nau8822: nau8822grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x130b0
MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
>;
};
};

108
arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts
View File

@ -7,29 +7,13 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6q.dtsi"
#include "imx6qdl-apalis.dtsi"
#include "imx6q-apalis-eval.dtsi"
/ {
model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board";
compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q",
"fsl,imx6q";
aliases {
i2c0 = &i2c1;
i2c1 = &i2c3;
i2c2 = &i2c2;
rtc0 = &rtc_i2c;
rtc1 = &snvs_rtc;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_pcie_switch: regulator-pcie-switch {
compatible = "regulator-fixed";
enable-active-high;
@ -40,14 +24,6 @@
startup-delay-us = <100000>;
status = "okay";
};
reg_3v3_sw: regulator-3v3-sw {
compatible = "regulator-fixed";
regulator-always-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "3.3V_SW";
};
};
&can1 {
@ -62,102 +38,22 @@
/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
&i2c1 {
status = "okay";
/* PCIe Switch */
pcie-switch@58 {
compatible = "plx,pex8605";
reg = <0x58>;
};
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
reg = <0x68>;
};
};
/*
* I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
* board)
*/
&i2c3 {
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_moci>;
/* active-high meaning opposite of regular PERST# active-low polarity */
reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
reset-gpio-active-high;
vpcie-supply = <&reg_pcie_switch>;
status = "okay";
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&pwm3 {
status = "okay";
};
&pwm4 {
status = "okay";
};
&reg_usb_host_vbus {
status = "okay";
};
&reg_usb_otg_vbus {
status = "okay";
};
&sata {
status = "okay";
};
&sound_spdif {
status = "okay";
};
&spdif {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart4 {
status = "okay";
};
&uart5 {
status = "okay";
};
&usbh1 {
disable-over-current;
vbus-supply = <&reg_usb_host_vbus>;
status = "okay";
};
&usbotg {
disable-over-current;
vbus-supply = <&reg_usb_otg_vbus>;
status = "okay";
};
/* MMC1 */
&usdhc1 {
status = "okay";

120
arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dtsi Normal file
View File

@ -0,0 +1,120 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2014-2024 Toradex
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6q.dtsi"
#include "imx6qdl-apalis.dtsi"
/ {
aliases {
i2c0 = &i2c1;
i2c1 = &i2c3;
i2c2 = &i2c2;
rtc0 = &rtc_i2c;
rtc1 = &snvs_rtc;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_3v3_sw: regulator-3v3-sw {
compatible = "regulator-fixed";
regulator-always-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "3.3V_SW";
};
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
reg = <0x68>;
};
};
/*
* I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
* board)
*/
&i2c3 {
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_moci>;
/* active-high meaning opposite of regular PERST# active-low polarity */
reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
reset-gpio-active-high;
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&pwm3 {
status = "okay";
};
&pwm4 {
status = "okay";
};
&reg_usb_host_vbus {
status = "okay";
};
&reg_usb_otg_vbus {
status = "okay";
};
&sata {
status = "okay";
};
&spdif {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart4 {
status = "okay";
};
&uart5 {
status = "okay";
};
&usbh1 {
disable-over-current;
vbus-supply = <&reg_usb_host_vbus>;
status = "okay";
};
&usbotg {
disable-over-current;
vbus-supply = <&reg_usb_otg_vbus>;
status = "okay";
};

7
arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi
View File

@ -41,6 +41,11 @@
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
aliases {
rtc0 = &carrier_rtc;
rtc1 = &snvs_rtc;
};
/* Will be filled by the bootloader */
memory@10000000 {
device_type = "memory";
@ -187,7 +192,7 @@
status = "okay";
/* Pro baseboard model */
rtc@68 {
carrier_rtc: rtc@68 {
compatible = "nxp,pcf8523";
reg = <0x68>;
};

5
arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard2.dtsi
View File

@ -41,6 +41,11 @@
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
aliases {
rtc0 = &pcf8523;
rtc1 = &snvs_rtc;
};
/* Will be filled by the bootloader */
memory@10000000 {
device_type = "memory";

10
arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi
View File

@ -13,10 +13,14 @@
aliases {
can0 = &can1;
can1 = &can2;
ethernet0 = &fec;
ethernet1 = &lan1;
ethernet2 = &lan2;
mdio-gpio0 = &mdio;
nand = &gpmi;
rtc0 = &i2c_rtc;
rtc1 = &snvs;
switch0 = &switch;
usb0 = &usbh1;
usb1 = &usbotg;
};
@ -60,7 +64,7 @@
gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>,
<&gpio1 22 GPIO_ACTIVE_HIGH>;
switch@0 {
switch: switch@0 {
compatible = "microchip,ksz8873";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_switch>;
@ -73,13 +77,13 @@
#address-cells = <1>;
#size-cells = <0>;
ports@0 {
lan1: ports@0 {
reg = <0>;
phy-mode = "internal";
label = "lan1";
};
ports@1 {
lan2: ports@1 {
reg = <1>;
phy-mode = "internal";
label = "lan2";

2
arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
View File

@ -1158,7 +1158,7 @@
status = "disabled";
};
weim: weim@21b8000 {
weim: memory-controller@21b8000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx6q-weim";

6
arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts
View File

@ -141,8 +141,10 @@
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
vdd-supply = <&ldo1_reg>;
reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
x-size = <1072>;
y-size = <1448>;
touchscreen-size-x = <1072>;
touchscreen-size-y = <1448>;
touchscreen-swapped-x-y;
touchscreen-inverted-x;
};
/* TODO: TPS65185 PMIC for E Ink at 0x68 */

2
arch/arm/boot/dts/nxp/imx/imx6sl.dtsi
View File

@ -949,7 +949,7 @@
clocks = <&clks IMX6SL_CLK_DUMMY>;
};
weim: weim@21b8000 {
weim: memory-controller@21b8000 {
#address-cells = <2>;
#size-cells = <1>;
reg = <0x021b8000 0x4000>;

2
arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
View File

@ -1107,7 +1107,7 @@
status = "disabled";
};
weim: weim@21b8000 {
weim: memory-controller@21b8000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";

2
arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi
View File

@ -321,7 +321,7 @@
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure-delay-time = <0xffff>;
pre-charge-time = <0xfff>;
status = "okay";

2
arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts
View File

@ -203,7 +203,7 @@
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
};
&sai2 {

2
arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi
View File

@ -156,7 +156,7 @@
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure-delay-time = <0xffff>;
pre-charge-time = <0xffff>;
status = "okay";

18
arch/arm/boot/dts/nxp/imx/imx6ul.dtsi
View File

@ -370,7 +370,7 @@
};
};
tsc: tsc@2040000 {
tsc: touchscreen@2040000 {
compatible = "fsl,imx6ul-tsc";
reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
@ -538,6 +538,8 @@
fsl,num-rx-queues = <1>;
fsl,stop-mode = <&gpr 0x10 4>;
fsl,magic-packet;
nvmem-cells = <&fec2_mac_addr>;
nvmem-cell-names = "mac-address";
status = "disabled";
};
@ -638,6 +640,7 @@
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
#thermal-sensor-cells = <0>;
};
};
@ -855,7 +858,6 @@
clocks = <&clks IMX6UL_CLK_USBOH3>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc 0>;
fsl,anatop = <&anatop>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x10>;
rx-burst-size-dword = <0x10>;
@ -897,6 +899,8 @@
fsl,num-rx-queues = <1>;
fsl,stop-mode = <&gpr 0x10 3>;
fsl,magic-packet;
nvmem-cells = <&fec1_mac_addr>;
nvmem-cell-names = "mac-address";
status = "disabled";
};
@ -975,7 +979,7 @@
clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
};
weim: weim@21b8000 {
weim: memory-controller@21b8000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
@ -1004,6 +1008,14 @@
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
fec1_mac_addr: mac-addr@88 {
reg = <0x88 6>;
};
fec2_mac_addr: mac-addr@8e {
reg = <0x8e 6>;
};
};
csi: csi@21c4000 {

4
arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som-cfg-sdcard.dtsi
View File

@ -14,10 +14,12 @@
*/
/*
* To use usdhc1 as SD card, the WiFi node must be deleted.
* To use usdhc1 as SD card, the WiFi node must be deleted. The associated
* pwrseq node is also deleted in order to ensure that GPIO H is released.
* BT is also not available, so remove BT from the UART node.
*/
/delete-node/ &brcmf;
/delete-node/ &usdhc1_pwrseq;
/delete-node/ &bluetooth;
/ {

4
arch/arm/boot/dts/nxp/imx/imx6ull-dhcom-som.dtsi
View File

@ -52,7 +52,7 @@
};
/* SoM with WiFi/BT: WiFi pin WL_REG_ON is connected to a DHCOM GPIO */
/omit-if-no-ref/ usdhc1_pwrseq: usdhc1-pwrseq {
usdhc1_pwrseq: usdhc1-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; /* GPIO H */
};
@ -273,7 +273,7 @@
pinctrl-names = "default";
pre-charge-time = <0xfff>;
touchscreen-average-samples = <32>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
};
/* DHCOM UART1 */

7
arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi
View File

@ -28,10 +28,14 @@
/*
* Due to the design as a solderable SOM, there are no capacitors
* below the SoC, therefore higher voltages are required.
* Due to CPU lifetime consideration of the SoC manufacturer and
* the preferred area of operation in the industrial related
* environment, set the maximum frequency for each DHCOM i.MX6ULL
* to 792MHz, as with the industrial type.
*/
clock-frequency = <792000000>;
operating-points = <
/* kHz uV */
900000 1275000
792000 1250000 /* Voltage increased */
528000 1175000
396000 1025000
@ -39,7 +43,6 @@
>;
fsl,soc-operating-points = <
/* KHz uV */
900000 1250000
792000 1250000 /* Voltage increased */
528000 1175000
396000 1175000

2
arch/arm/boot/dts/nxp/imx/imx6ull.dtsi
View File

@ -75,7 +75,7 @@
clocks = <&clks IMX6UL_CLK_DUMMY>;
};
iomuxc_snvs: iomuxc-snvs@2290000 {
iomuxc_snvs: pinctrl@2290000 {
compatible = "fsl,imx6ull-iomuxc-snvs";
reg = <0x02290000 0x4000>;
};

315
arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi
View File

@ -18,6 +18,8 @@
mmc0 = &usdhc3;
mmc1 = &usdhc1;
/delete-property/ mmc2;
rtc0 = &ds1339;
rtc1 = &snvs_rtc;
};
beeper {
@ -32,11 +34,18 @@
gpio_buttons: gpio-keys {
compatible = "gpio-keys";
/*
* NOTE: These buttons are attached to a GPIO-expander.
* Enabling wakeup-source, enables wakeup on all inputs.
* If PE_GPIO[3..6] are used as inputs, they cause a
* wakeup as well.
*/
button-0 {
/* #SWITCH_A */
label = "S11";
linux,code = <KEY_1>;
gpios = <&pca9555 13 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-1 {
@ -44,6 +53,7 @@
label = "S12";
linux,code = <KEY_2>;
gpios = <&pca9555 14 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-2 {
@ -51,6 +61,7 @@
label = "S13";
linux,code = <KEY_3>;
gpios = <&pca9555 15 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
@ -171,6 +182,14 @@
regulator-always-on;
};
reg_vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sound {
compatible = "fsl,imx-audio-tlv320aic32x4";
model = "imx-audio-tlv320aic32x4";
@ -198,9 +217,9 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_ss0>;
cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
<&gpio4 2 GPIO_ACTIVE_LOW>;
<&gpio4 2 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -214,8 +233,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-supply = <&reg_fec1_pwdn>;
phy-handle = <&ethphy1_0>;
fsl,magic-packet;
@ -228,10 +245,15 @@
ethphy1_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1_phy>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <500>;
};
};
};
@ -290,13 +312,17 @@
lm75: temperature-sensor@49 {
compatible = "national,lm75";
reg = <0x49>;
vs-supply = <&reg_vcc_3v3>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_recovery>;
scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio4 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
tlv320aic32x4: audio-codec@18 {
@ -319,13 +345,17 @@
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
vcc-supply = <&reg_vcc_3v3>;
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_recovery>;
scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@ -334,213 +364,213 @@
pinctrl-0 = <&pinctrl_hog_mba7_1>;
pinctrl_ecspi1: ecspi1grp {
fsl,pins =
<MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c>,
<MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74>,
<MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74>,
<MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74>,
<MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74>,
<MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74>;
};
pinctrl_ecspi1_ss0: ecspi1ss0grp {
fsl,pins = <
MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c
MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74
MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74
MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74
MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74
MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74
MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x74
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c
MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74
MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74
MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74
>;
fsl,pins =
<MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c>,
<MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74>,
<MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74>,
<MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02
MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79
fsl,pins =
<MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02>,
<MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00>,
<MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71>,
<MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71>,
<MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71>,
<MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71>,
<MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71>,
<MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71>,
<MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79>,
<MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79>,
<MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79>,
<MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79>,
<MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79>,
<MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79>;
};
pinctrl_enet1_phy: enet1phygrp {
fsl,pins =
/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070
<MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070>,
/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078
>;
<MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a
MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52
>;
fsl,pins =
<MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a>,
<MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a
MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52
>;
fsl,pins =
<MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a>,
<MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52>;
};
pinctrl_hog_mba7_1: hogmba71grp {
fsl,pins = <
fsl,pins =
/* Limitation: WDOG2_B / WDOG2_RESET not usable */
MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c
MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074
<MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c>,
<MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074>,
/* #BOOT_EN */
MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010
>;
<MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078
>;
fsl,pins =
<MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078>,
<MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078>;
};
pinctrl_i2c2_recovery: i2c2recoverygrp {
fsl,pins =
<MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x40000078>,
<MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x40000078>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078
MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078
>;
fsl,pins =
<MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078>,
<MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078>;
};
pinctrl_i2c3_recovery: i2c3recoverygrp {
fsl,pins =
<MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x40000078>,
<MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x40000078>;
};
pinctrl_pca9555: pca95550grp {
fsl,pins = <
MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78
>;
fsl,pins =
<MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11
MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c
MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c
MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c
fsl,pins =
<MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11>,
<MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c>,
<MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c>,
<MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c>,
MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c
MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14
MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14
>;
<MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c>,
<MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14>,
<MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e
MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76
MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76
MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e
>;
fsl,pins =
<MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e>,
<MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76>,
<MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76>,
<MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e
MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76
MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76
MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e
>;
fsl,pins =
<MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e>,
<MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76>,
<MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76>,
<MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e
MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76
>;
fsl,pins =
<MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e>,
<MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76>;
};
pinctrl_uart6: uart6grp {
fsl,pins = <
MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d
MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75
MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75
MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d
>;
fsl,pins =
<MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d>,
<MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75>,
<MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75>,
<MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d>;
};
pinctrl_uart7: uart7grp {
fsl,pins = <
MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e
MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76
MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76
fsl,pins =
<MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e>,
<MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76>,
<MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76>,
/* Limitation: RTS is not connected */
MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e
>;
<MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e>;
};
pinctrl_usdhc1_gpio: usdhc1grp_gpio {
fsl,pins = <
pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
fsl,pins =
/* WP */
MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c
<MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c>,
/* CD */
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c
<MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c>,
/* VSELECT */
MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59
>;
<MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5e
MX7D_PAD_SD1_CLK__SD1_CLK 0x57
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e
>;
fsl,pins =
<MX7D_PAD_SD1_CMD__SD1_CMD 0x5e>,
<MX7D_PAD_SD1_CLK__SD1_CLK 0x57>,
<MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e>,
<MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e>,
<MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e>,
<MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e>;
};
pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
MX7D_PAD_SD1_CLK__SD1_CLK 0x57
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
>;
pinctrl_usdhc1_100mhz: usdhc1_100mhzgrp {
fsl,pins =
<MX7D_PAD_SD1_CMD__SD1_CMD 0x5a>,
<MX7D_PAD_SD1_CLK__SD1_CLK 0x57>,
<MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a>,
<MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a>,
<MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a>,
<MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a>;
};
pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
MX7D_PAD_SD1_CLK__SD1_CLK 0x57
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
>;
pinctrl_usdhc1_200mhz: usdhc1_200mhzgrp {
fsl,pins =
<MX7D_PAD_SD1_CMD__SD1_CMD 0x5b>,
<MX7D_PAD_SD1_CLK__SD1_CLK 0x57>,
<MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b>,
<MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b>,
<MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b>,
<MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b>;
};
};
&iomuxc_lpsr {
pinctrl_pwm1: pwm1grp {
fsl,pins = <
fsl,pins =
/* LCD_CONTRAST */
MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50
>;
<MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59
>;
fsl,pins =
<MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c>,
<MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59>;
};
pinctrl_wdog1: wdog1grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30
>;
fsl,pins =
<MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30>;
};
};
@ -560,6 +590,10 @@
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
@ -605,6 +639,7 @@
};
&usbh {
disable-over-current;
status = "okay";
};
@ -630,6 +665,8 @@
vmmc-supply = <&reg_sd1_vmmc>;
bus-width = <4>;
no-1-8-v;
no-sdio;
no-emmc;
status = "okay";
};

Some files were not shown because too many files have changed in this diff Show More