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drm/amd/display: Add otg vertical interrupt0 support in DCN1.0
[Why & How] On DCN1.0, need otg vertical line interrupt to get appropriate timing to achieve specific feature request. Add otg vertical interrupt0 support for registers which operation is vertical sensitive. Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
11f1a5538b
commit
320eca62fe
3 changed files with 54 additions and 0 deletions
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@ -662,6 +662,20 @@ static int amdgpu_dm_set_crtc_irq_state(struct amdgpu_device *adev,
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__func__);
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}
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static int amdgpu_dm_set_vline0_irq_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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unsigned int crtc_id,
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enum amdgpu_interrupt_state state)
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{
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return dm_irq_state(
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adev,
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source,
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crtc_id,
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state,
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IRQ_TYPE_VLINE0,
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__func__);
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}
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static int amdgpu_dm_set_vupdate_irq_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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unsigned int crtc_id,
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@ -681,6 +695,11 @@ static const struct amdgpu_irq_src_funcs dm_crtc_irq_funcs = {
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.process = amdgpu_dm_irq_handler,
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};
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static const struct amdgpu_irq_src_funcs dm_vline0_irq_funcs = {
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.set = amdgpu_dm_set_vline0_irq_state,
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.process = amdgpu_dm_irq_handler,
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};
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static const struct amdgpu_irq_src_funcs dm_vupdate_irq_funcs = {
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.set = amdgpu_dm_set_vupdate_irq_state,
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.process = amdgpu_dm_irq_handler,
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@ -702,6 +721,9 @@ void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev)
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adev->crtc_irq.num_types = adev->mode_info.num_crtc;
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adev->crtc_irq.funcs = &dm_crtc_irq_funcs;
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adev->vline0_irq.num_types = adev->mode_info.num_crtc;
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adev->vline0_irq.funcs = &dm_vline0_irq_funcs;
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adev->vupdate_irq.num_types = adev->mode_info.num_crtc;
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adev->vupdate_irq.funcs = &dm_vupdate_irq_funcs;
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@ -58,6 +58,18 @@ enum dc_irq_source to_dal_irq_source_dcn10(
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return DC_IRQ_SOURCE_VBLANK5;
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case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
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return DC_IRQ_SOURCE_VBLANK6;
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case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
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return DC_IRQ_SOURCE_DC1_VLINE0;
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case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
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return DC_IRQ_SOURCE_DC2_VLINE0;
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case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
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return DC_IRQ_SOURCE_DC3_VLINE0;
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case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
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return DC_IRQ_SOURCE_DC4_VLINE0;
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case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
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return DC_IRQ_SOURCE_DC5_VLINE0;
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case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
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return DC_IRQ_SOURCE_DC6_VLINE0;
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case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
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return DC_IRQ_SOURCE_VUPDATE1;
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case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
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@ -167,6 +179,11 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
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.ack = NULL
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};
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static const struct irq_source_info_funcs vline0_irq_info_funcs = {
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.set = NULL,
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.ack = NULL
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};
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static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
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.set = NULL,
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.ack = NULL
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@ -241,6 +258,14 @@ static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
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.funcs = &vblank_irq_info_funcs\
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}
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#define vline0_int_entry(reg_num)\
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[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
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IRQ_REG_ENTRY(OTG, reg_num,\
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OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
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OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
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.funcs = &vline0_irq_info_funcs\
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}
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#define dummy_irq_entry() \
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{\
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.funcs = &dummy_irq_info_funcs\
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@ -349,6 +374,12 @@ irq_source_info_dcn10[DAL_IRQ_SOURCES_NUMBER] = {
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vblank_int_entry(3),
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vblank_int_entry(4),
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vblank_int_entry(5),
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vline0_int_entry(0),
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vline0_int_entry(1),
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vline0_int_entry(2),
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vline0_int_entry(3),
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vline0_int_entry(4),
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vline0_int_entry(5),
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};
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static const struct irq_service_funcs irq_service_funcs_dcn10 = {
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@ -160,6 +160,7 @@ enum irq_type
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IRQ_TYPE_PFLIP = DC_IRQ_SOURCE_PFLIP1,
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IRQ_TYPE_VUPDATE = DC_IRQ_SOURCE_VUPDATE1,
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IRQ_TYPE_VBLANK = DC_IRQ_SOURCE_VBLANK1,
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IRQ_TYPE_VLINE0 = DC_IRQ_SOURCE_DC1_VLINE0,
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};
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#define DAL_VALID_IRQ_SRC_NUM(src) \
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