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ARM: S5PC100: Modified files for SPI consolidation work
As SPI platform devices are consolidated to plat-samsung, some corresponding changes are required in the respective machine folder. Added SPI Setup file for GPIO configurations and platform data initialization. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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6 changed files with 79 additions and 0 deletions
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@ -45,6 +45,11 @@ config S5PC100_SETUP_SDHCI_GPIO
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help
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Common setup code for SDHCI gpio.
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config S5PC100_SETUP_SPI
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bool
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help
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Common setup code for SPI GPIO configurations.
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config MACH_SMDKC100
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bool "SMDKC100"
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select CPU_S5PC100
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@ -22,6 +22,7 @@ obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
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obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o
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obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o
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obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
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obj-$(CONFIG_S5PC100_SETUP_SPI) += setup-spi.o
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# device support
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obj-y += dev-audio.o
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@ -100,6 +100,9 @@
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#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
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#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
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#define S3C_PA_WDT S5PC100_PA_WATCHDOG
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#define S3C_PA_SPI0 S5PC100_PA_SPI0
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#define S3C_PA_SPI1 S5PC100_PA_SPI1
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#define S3C_PA_SPI2 S5PC100_PA_SPI2
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#define S5P_PA_CHIPID S5PC100_PA_CHIPID
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#define S5P_PA_FIMC0 S5PC100_PA_FIMC0
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65
arch/arm/mach-s5pc100/setup-spi.c
Normal file
65
arch/arm/mach-s5pc100/setup-spi.c
Normal file
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@ -0,0 +1,65 @@
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/* linux/arch/arm/mach-s5pc100/setup-spi.c
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*
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* Copyright (C) 2011 Samsung Electronics Ltd.
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* http://www.samsung.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <plat/gpio-cfg.h>
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#include <plat/s3c64xx-spi.h>
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#ifdef CONFIG_S3C64XX_DEV_SPI0
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struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 13,
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.high_speed = 1,
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.tx_st_done = 21,
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};
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int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
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{
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s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
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S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
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return 0;
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}
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#endif
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#ifdef CONFIG_S3C64XX_DEV_SPI1
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struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 13,
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.high_speed = 1,
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.tx_st_done = 21,
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};
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int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
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{
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s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
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S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
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return 0;
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}
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#endif
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#ifdef CONFIG_S3C64XX_DEV_SPI2
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struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
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.fifo_lvl_mask = 0x7f,
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.rx_lvl_offset = 13,
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.high_speed = 1,
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.tx_st_done = 21,
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};
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int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
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{
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s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
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s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
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s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
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S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
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return 0;
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}
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#endif
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@ -1582,6 +1582,9 @@ void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
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pd->num_cs = num_cs;
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pd->src_clk_nr = src_clk_nr;
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if (!pd->cfg_gpio)
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pd->cfg_gpio = s3c64xx_spi2_cfg_gpio;
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s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2);
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}
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#endif /* CONFIG_S3C64XX_DEV_SPI2 */
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@ -75,7 +75,9 @@ extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
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/* defined by architecture to configure gpio */
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extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev);
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extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev);
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extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev);
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extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
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extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
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extern struct s3c64xx_spi_info s3c64xx_spi2_pdata;
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#endif /* __S3C64XX_PLAT_SPI_H */
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