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clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
CLK_SET_RATE_GATE means that the clock must be gated when being reclocked. This is not the case for the PLLs in Ingenic SoCs. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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21534fe39c
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1 changed files with 7 additions and 2 deletions
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@ -182,6 +182,7 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate,
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const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
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unsigned long rate, flags;
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unsigned int m, n, od;
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int ret = 0;
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u32 ctl;
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rate = ingenic_pll_calc(clk_info, req_rate, parent_rate,
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@ -203,9 +204,14 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate,
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ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift;
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writel(ctl, cgu->base + pll_info->reg);
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/* If the PLL is enabled, verify that it's stable */
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if (ctl & BIT(pll_info->enable_bit))
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ret = ingenic_pll_check_stable(cgu, pll_info);
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spin_unlock_irqrestore(&cgu->lock, flags);
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return 0;
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return ret;
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}
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static int ingenic_pll_enable(struct clk_hw *hw)
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@ -662,7 +668,6 @@ static int ingenic_register_clock(struct ingenic_cgu *cgu, unsigned idx)
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}
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} else if (caps & CGU_CLK_PLL) {
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clk_init.ops = &ingenic_pll_ops;
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clk_init.flags |= CLK_SET_RATE_GATE;
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caps &= ~CGU_CLK_PLL;
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